WO2022248570A1 - Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements - Google Patents
Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements Download PDFInfo
- Publication number
- WO2022248570A1 WO2022248570A1 PCT/EP2022/064244 EP2022064244W WO2022248570A1 WO 2022248570 A1 WO2022248570 A1 WO 2022248570A1 EP 2022064244 W EP2022064244 W EP 2022064244W WO 2022248570 A1 WO2022248570 A1 WO 2022248570A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor chip
- semiconductor
- carrier
- plastic material
- cavity
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 233
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 270
- 239000004033 plastic Substances 0.000 claims abstract description 73
- 229920003023 plastic Polymers 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims description 37
- 229920001296 polysiloxane Polymers 0.000 claims description 29
- 239000004593 Epoxy Substances 0.000 claims description 22
- 230000005693 optoelectronics Effects 0.000 claims description 17
- 238000001746 injection moulding Methods 0.000 claims description 15
- 238000000465 moulding Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000005507 spraying Methods 0.000 claims description 5
- 238000005266 casting Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- 229910000831 Steel Inorganic materials 0.000 claims description 3
- 239000010959 steel Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 20
- 230000035882 stress Effects 0.000 description 10
- 239000002356 single layer Substances 0.000 description 7
- 238000001721 transfer moulding Methods 0.000 description 6
- 238000005476 soldering Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000012876 carrier material Substances 0.000 description 4
- 150000002118 epoxides Chemical class 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000032683 aging Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000007779 soft material Substances 0.000 description 2
- 229920000965 Duroplast Polymers 0.000 description 1
- 239000004638 Duroplast Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
Definitions
- a semiconductor component and a method for producing a semiconductor component are specified.
- a soft case material can help avoid this problem.
- this also means that the package as a whole mechanically offers little resistance to deformation and can therefore be damaged during testing or when handling the component.
- forms of housing are known in which the chip is mounted in a cavity on a first level, while bonding wires are connected to a second level of the housing that is different from the first level. With such a stepped cavity, it may be possible that a possible partial lifting of the chip does not directly affect the bonding wires.
- a disadvantage of this structure is the extremely high cost of the housing, for which a multi-layer printed circuit board with a stepped cavity is usually used, which costs many times more than a flat printed circuit board.
- the cavity is usually filled with a soft material.
- a soft material is used, the different thermal expansions of the chip, filling material and substrate lead to strong stresses in the package. If, for example, the usual transfer molding is used for production, this effect is intensified.
- At least one object of certain embodiments is to provide a semiconductor device. At least one further object of specific embodiments is to specify a method for producing a semiconductor component.
- a semiconductor device has a carrier with a main surface on which a semiconductor chip element is mounted.
- a carrier having a main surface is provided, on which a semiconductor chip element is mounted.
- the support is particularly preferably a planar support.
- a planar carrier is thus particularly preferably provided for mounting the semiconductor chip element on the carrier. This can mean in particular that the carrier has no cavity, ie no depression, in which the semiconductor chip element can be mounted.
- the main surface of the carrier on which the Semiconductor chip element is mounted is particularly preferably flat or substantially flat. In this case, even can mean in particular that height variations of the main surface are smaller than a height of the
- the carrier can thus be designed in the form of a plate, in which case the underside of the carrier opposite the main surface can be provided and set up for mounting and for making electrical contact with the semiconductor component.
- the support can be a monolayer support or a multilayer support, ie a support which has a layer of one support material or a plurality of layers of one or more support materials.
- the carrier material can be a plastic or a ceramic material, for example.
- the carrier can be, for example, a ceramic carrier or a plastic carrier such as a single-layer or multi-layer circuit board, for example a single-layer or multi-layer PCB ("printed circuit board").
- electrical connection points, Conductor tracks and electrical vias must be present.
- the semiconductor chip element has at least one semiconductor chip.
- the at least one semiconductor chip has an upper side which faces away from the carrier after the semiconductor chip element has been mounted on the main surface of the carrier.
- the at least one semiconductor chip can be an electronic semiconductor chip, for example an integrated circuit (IC: "integrated circuit") or an optoelectronic semiconductor chip, for example a light-emitting diode chip or laser diode chip.
- the semiconductor chip element can particularly preferably have an electronic semiconductor chip with the upper side as at least one semiconductor chip, on which an optoelectronic semiconductor chip is mounted.
- the electronic semiconductor chip can be, for example, an integrated circuit, for example based on a silicon chip, which is provided and set up for driving the optoelectronic semiconductor chip.
- the optoelectronic semiconductor chip can be a pixelated light-emitting diode chip, i.e a light-emitting diode chip which has a plurality of emitter regions which can be driven independently of one another and which are arranged in a matrix-like manner be attached to the main surface of the carrier by means of soldering or gluing and optionally, depending on the configuration of the at least one semiconductor chip, also be electrically connected from the underside of the semiconductor chip element.
- a pixelated light-emitting diode chip i.e a light-emitting diode chip which has a plurality of emitter regions which can be driven independently of one another and which are arranged in a matrix-like manner be attached to the main surface of the carrier by means of soldering or gluing and optionally, depending on the configuration of the at least one semiconductor chip, also be electrically connected from the underside of the semiconductor chip element.
- the at least one wire connection which in particular can have or be a bonding wire or a plurality of bonding wires.
- an electrical connection point can be present on the main surface of the carrier which the bonding wire or wires of the wire connection is bonded.
- a corresponding electrical connection point can also be present on the upper side of the at least one semiconductor chip.
- the semiconductor chip element with the at least one semiconductor chip is thus mounted on the carrier and electrically contacted at least with the at least one wire connection between the main surface of the carrier and the top side of the semiconductor chip.
- the semiconductor component furthermore has a first material and a second material.
- the first material and the second material are different from one another and are applied, in particular one after the other, to the carrier, ie to the main surface of the carrier.
- the first and second material are provided and set up in particular to form a housing body together with the carrier, in which the semiconductor chip element remains at least partially free.
- the first and second materials are particularly preferably applied to the carrier after the semiconductor chip element has been mounted.
- the first material completely encloses the at least one wire connection.
- the at least one wire connection is encased with the first material after the main surface of the carrier has been electrically connected to the top side of the at least one semiconductor chip of the semiconductor chip element, so that the wire connection, i.e. preferably the one or more bonding wires including the electrical connection points on the main surface of the carrier and on the upper side of the at least one semiconductor chip, with the first material are covered. If several wire connections are present, these are all completely enveloped by the first material, it being possible for the first material to be applied to the carrier in a continuous manner or in regions which are separate from one another.
- the second material forms a frame.
- the frame can be formed on the main surface of the carrier.
- the second material may surround a cavity such that a depression is formed by the second material.
- the top side of the at least one semiconductor chip has an area which is free from the first and second material and which is arranged in the cavity. Particularly preferably, only that part of the top side of the semiconductor chip that is in the region of the at least one wire connection is covered with the first material in order to completely encapsulate the at least one wire connection with the first material.
- This part can particularly preferably be in an edge area of the upper side of the at least one semiconductor chip, so that only the edge area or even only one or more parts of the edge area are covered with the first material.
- no part of the upper side or only the part that is covered by the first material is covered with the second material.
- the entire area of the upper side of the at least one semiconductor chip that is free of the first material is therefore preferably also free of the second material.
- the top side of the semiconductor chip can have an area that is free of any material. In other words, this can mean in particular that the semiconductor chip is not finished with any solid material in the region that is free of any material Asked semiconductor device is covered.
- the area that is free of any material can be in direct contact with the atmosphere of the environment in which the semiconductor device is arranged, which can be air, for example.
- the semiconductor chip element has an electronic semiconductor chip as at least one semiconductor chip with the upper side on which an optoelectronic semiconductor chip is mounted
- the optoelectronic semiconductor chip is particularly preferably arranged in the cavity at a distance from the first and second material.
- the optoelectronic semiconductor chip is particularly preferably arranged on that region of the upper side of the electronic semiconductor chip which is free from the first and second material.
- the first material has or consists of a first plastic material.
- the first material that is to say in particular the first plastic material, is particularly preferably applied using a method which exerts as little or as little force as possible on the at least one wire connection.
- the first material is particularly preferably applied by means of vacuum injection molding (VIM: "vacuum injection molding”).
- VIP vacuum injection molding
- at least the first plastic material is molded onto the at least one wire connection using a vacuum, with the at least one wire connection being completely encased.
- vacuum injection molding the sealing forces are significantly smaller than with the commonly used transfer molding. Furthermore, the forces acting on the semiconductor chip element are lower than when Transfer molding and the stress on the carrier and the compression of an adhesive, if used, for mounting the semiconductor chip element are reduced.
- a film-assisted molding process FAM: "foil-assisted molding”
- a casting process casting
- a spraying process "spraying”
- a sacrificial layer method a combination of the methods mentioned
- the first material is particularly preferably at least partially soft and/or elastic. Accordingly, at least the first plastic material is soft and/or elastic. In other words, the first material, ie at least the first plastic material, is not rigid but plastically and/or elastically deformable even under the action of smaller forces, so that in the case of stresses, for example due to different
- a material designated as soft and/or elastic can particularly preferably have a modulus of elasticity of less than 1 GPa or less than 500 MPa or even less than 100 MPa.
- the first plastic material can include or be made of silicone.
- the silicone can have a modulus of elasticity greater than or equal to 1 MPa and less than or equal to 50 MPa.
- it can also be a black silicone that can serve as protection against radiation.
- the first Plastic material for example, an epoxy, particularly preferably with a plasticizer, have or be made of it.
- the first material may have a second plastic material, which from the first
- the second plastic material can be arranged on the first plastic material and, together with the first plastic material, completely envelop the at least one wire connection.
- the second plastic material can preferably be soft and/or elastic.
- the second plastic material can include or be made of silicone.
- the second plastic material can also include or be made of an epoxy, for example.
- the epoxy may have a Young's modulus greater than or equal to 1 GPa and less than or equal to 10 GPa.
- Materials that have an epoxy also include, in particular, silicone-epoxy hybrid materials.
- two different silicones or a silicone and an epoxy or a silicone and a silicone-epoxy hybrid material can be used for the first and second plastic material.
- the second plastic material can in particular be applied using a method previously described for the first plastic material.
- the second material has one or more materials selected from a third plastic material, a semiconductor material and a metal material.
- the second material is particularly preferably rigid. Silicon, for example, can be used as the semiconductor material for the second material. In the case of a metal material, for example, steel can be used will.
- a rigid second material can be used to form a rigid and therefore non-elastic frame on the carrier, which can be advantageous for the stability of the semiconductor component. Because the at least one wire connection is encased in the first material, which is preferably at least partially soft and/or elastic, the at least one wire connection can be protected from stresses, as described above, even if such stresses are between the wearer and occur with the second material.
- the third plastic material can preferably include or be a duroplast.
- the third plastic material can include or be made of an epoxide, in particular a rigid epoxide.
- Highly filled epoxy materials through which the mechanical properties such as hardness, the thermal expansion coefficient, the modulus of elasticity, etc. can be optimized and adapted to the joining partners, can be particularly preferred.
- the second material can, for example, also include or be made of a silicone, for example a black silicone. If only plastic materials are used for the first and second material, it can be particularly advantageous if the first and second material are applied using the same mold.
- the carrier with the mounted and electrically contacted semiconductor chip element can be placed in a mold in which the first material is first molded onto the at least one wire connection and the second material is then molded on the carrier.
- the third plastic material can, for example, by means of transfer molding or another, in conjunction with the method mentioned in the first plastic material.
- the at least one wire connection i.e. at least one bonding wire including the connection points
- the soft first material for example silicone
- the harder second material for example epoxy
- the first material can be applied at least partially on and/or under the second material.
- the first material can be arranged at least partially in the cavity formed by the second material.
- the first material can partially or completely cover the second material.
- the second material can also partially or completely cover the first material.
- the first and second material can in particular be formed in such a way that the semiconductor component has a top side facing away from the carrier, which is flat and has an opening, at least partially formed by the cavity, through which part of the semiconductor chip is exposed.
- a cover element having a wavelength conversion material and/or a window element and/or a protective film can be arranged in or on the cavity above the semiconductor chip element. Particularly preferably, the cover element can be spaced apart from the semiconductor chip element.
- the problems of hard or soft packages described above can be significantly reduced.
- a carrier with a stepped cavity i.e. a stepped main surface, in which the at least one semiconductor chip is mounted on a first level and the connection point or points for the at least one wire connection are arranged on a second level that differs from the first level.
- first and second material can result in increased mechanical stability and cycle strength with a flat package design.
- Figures 1A and 1B show schematic representations of a
- FIGS. 2A to 3B show schematic representations of a semiconductor component according to further exemplary embodiments
- FIGS. 4A and 4B show schematic representations of a semiconductor component according to a further exemplary embodiment
- FIGS. 5A to 5D show schematic representations of
- FIGS. 6A and 6B show schematic representations of a semiconductor component according to a further exemplary embodiment
- FIGS 7A to 7D show schematic representations of
- FIGS. 8A and 8B show schematic representations of a semiconductor component according to a further exemplary embodiment
- FIGS 9A to 9D show schematic representations of
- FIGS. 10A to 10D show schematic illustrations of a semiconductor component according to further exemplary embodiments.
- elements which are the same, of the same type or have the same effect can each be provided with the same reference symbols.
- the elements shown and their proportions to one another are not to be regarded as true to scale; instead, individual elements, such as layers, components, components and areas, may be shown in an exaggerated size for better representation and/or better understanding.
- FIGS. 1A and 1B A semiconductor component 100 according to an exemplary embodiment is shown in FIGS. 1A and 1B in a sectional view (FIG. 1A) and in a top view (FIG. 1B).
- the semiconductor component 100 has a carrier 1 with a main surface 10 on which a semiconductor chip element 2 is mounted, which has at least one semiconductor chip 21, for example an electronic semiconductor chip such as an integrated circuit or an optoelectronic semiconductor chip such as a light-emitting diode chip or laser diode chip.
- the semiconductor chip element 2 has, purely by way of example, an electronic semiconductor chip as at least one semiconductor chip 21, on which a further semiconductor chip 22, formed by an optoelectronic semiconductor chip, is mounted and electrically connected.
- the electronic semiconductor chip 21 is, for example, an integrated circuit, for example based on a silicon chip, which is provided and set up for driving the optoelectronic semiconductor chip.
- the at least one semiconductor chip 21 has an upper side 23, which faces away from the carrier 1 and on which the optoelectronic semiconductor chip 22 is mounted in the exemplary embodiment shown. for example by soldering.
- the optoelectronic semiconductor chip 22 can be a pixelated light-emitting diode chip, that is to say a light-emitting diode chip which has a plurality of emitter regions which can be driven independently of one another and are arranged in a matrix.
- the optoelectronic semiconductor chip 22 can have a matrix of 10 ⁇ 10 emitter regions.
- Such a semiconductor chip can be advantageous, for example, for adaptive lighting, for example in the automotive sector.
- the carrier 1 is preferably a flat carrier which has no cavity, ie no depression, in which the semiconductor chip element 2 can be mounted.
- the main surface 10 of the carrier 1, on which the semiconductor chip element 2 is mounted, is particularly preferably flat or essentially flat.
- the carrier 1 can thus be plate-shaped, with the underside of the carrier 1 opposite the main surface 10 being provided and set up for mounting and for making electrical contact with the semiconductor component 100 .
- the carrier 1 can be a single-layer carrier or a multi-layer carrier, ie a carrier that has a layer made of one carrier material or a plurality of layers made of one or more carrier materials.
- the carrier material can be a plastic or a ceramic material, for example.
- the carrier can be, for example, a ceramic carrier or a plastic carrier such as a single-layer or multi-layer printed circuit board, for example a single-layer or multi-layer PCB (“printed circuit board”)
- a single-layer PCB is shown as the carrier 1 purely by way of example. Electrical connection points 11, conductor tracks 12 and electrical vias 13 are present for contacting the semiconductor component 100 and for electrically connecting the semiconductor chip element 2 .
- the semiconductor chip element 2 can be attached to the main surface 10 of the carrier 1, for example by soldering or gluing, and optionally also electrically connected from the underside of the semiconductor chip element 2.
- the semiconductor chip element 2 is attached to the at least one semiconductor chip 2 on a mounting pad 14 which is connected via a multiplicity of vias 13 to a connection point 11 for dissipating heat from the semiconductor chip element 2 .
- At least one wire connection 3 is present between the main surface 10 of the carrier 1 and the upper side 23 of the at least one semiconductor chip 21 .
- a number of wire connections 3 are present, as shown.
- That Semiconductor chip element 2 with the at least one semiconductor chip 21 is thus mounted on the carrier 1 and electrically contacted at least with one or, as shown, several wire connections 3 between the main surface 10 of the carrier 1 and the upper side 23 of the at least one semiconductor chip 2.
- the semiconductor component 100 also has a first material 4 and a second material 5 which are applied to the main surface 10 of the carrier 1 .
- the first material 4 and the second material 5 are different from one another and are applied, in particular one after the other, to the carrier 1, ie to the main surface 10 of the carrier 1.
- the first and second material 4, 5 are intended and set up in particular to form a housing body together with the carrier 1, in which the semiconductor chip element 2 remains at least partially free.
- the first and second material 4, 5 are particularly preferred after the semiconductor chip element 2 has been mounted on the carrier
- the first material 4 completely encloses the wire connections 3 . This means in particular that the wire connections 3 after the main surface 10 of the carrier 1 has been electrically connected to the top side 23 of the at least one semiconductor chip 21 of the semiconductor chip element
- the wire connections 3 are covered with the first material 4, so that the wire connections 3, so the bonding wires including the electrical connection points 11, 24 on the main surface 10 of the carrier 1 and on the upper side 24 of the at least one semiconductor chip 21 are covered with the first material 4.
- the second material 5 forms a frame on the main surface 10 of the carrier 1.
- the second material 5 surrounds a cavity 50, so that the second material 5 forms a depression.
- the semiconductor chip element 2 is arranged in the cavity 50 and is spaced apart from the second material 5 in the exemplary embodiment shown.
- the wire connections 3 are arranged, encased by the first material 4 .
- the upper side 23 of the at least one semiconductor chip 21 of the semiconductor chip element 2 has an area which is free from the first and second material 4, 5 and which is arranged in the cavity 50.
- only that part of the top side 23 of the semiconductor chip 21 that lies in the area of the wire connections 3 is covered with the first material 4 in order to completely encapsulate the wire connections 3 with the first material 4 .
- this part is in an edge area of the top 23 of the at least one semiconductor chip 21, so that only the edge area of the top 23, in which the connection points 24 are arranged, is covered with the first material 4 .
- the semiconductor component 100 has an opening 6 on its upper side.
- the further semiconductor chip 22, ie the optoelectronic semiconductor chip, is completely free of the first and second material 4, 5 and is thus exposed and accessible from the top side of the semiconductor component 100 in the opening 6.
- the semiconductor chip 21 has an area that is free of any material of the semiconductor component 100 and thus also is exposed and accessible.
- the further semiconductor chip 22 also has an area that is free of any material of the semiconductor component 100 .
- the first material 4 has a first plastic material 41 .
- the first material 4 can consist of the first plastic material 41 .
- the first plastic material 41 includes silicone or is particularly preferably a silicone. This can also be a black silicone, which can serve as protection against radiation.
- the first plastic material 41 and thus the first material 4 is soft and/or elastic and thus plastically and/or elastically deformable, so that the wire connections 3 encased by the first material 4 can be protected from mechanical loads and stresses in the semiconductor component 100.
- the first material 4 that is to say the first plastic material 41, is particularly preferably applied using a method which exerts as few forces as possible on the wire connections 3, or at least as little as possible.
- the first material 4 is particularly preferably applied by means of vacuum injection molding.
- the first plastic material 41 is molded onto the wire connections using a vacuum, with the wire connections 3 being completely encased.
- vacuum injection molding can achieve good sealing on the semiconductor chip 21 using a small sealing force.
- the wire bonds 3 are encased, there is only a small risk of deformation of the wire bonds 3 and a small risk of chip lifting.
- a film-assisted molding method ie at least the first plastic material 41, and thus for encasing the Wire connections 3 also a film-assisted molding method, a casting method, a spraying method, a sacrificial layer method or a combination of the above methods can be used.
- the first material 4 can, for example, also have at least one further plastic material, which is referred to here and below as the second plastic material and which forms the first material together with the first plastic material 41 .
- the first material 4 completely covers the second material 5 and can therefore also serve as protection for the second material 5, for example as protection against radiation in the case of black silicone.
- the second material 5 comprises a rigid material and serves as a rigid stiffening frame.
- the second material 5 can include or be a third plastic material 53, which preferably includes or can be an epoxide, in particular a highly filled epoxide.
- a silicone-epoxy hybrid material can also be used.
- Liquid crystal material (LCP: "liquid-crystal polymer”) or a semiconductor material such as silicon or a metal material such as steel or a combination thereof is possible.
- the second material 5 can preferably be molded onto the frame, for example by means of a transfer molding process.
- the second material 5 can form, for example, a prefabricated frame which is glued onto the main surface 10 of the support.
- the semiconductor chip element 2 ie in particular the semiconductor chips 21, 22, sits in the cavity 50 formed by the rigid second material 5, while the
- Wire connections 3 and the edge area of the upper side 23 of the semiconductor chip 21 are formed by the first material 4 and are thus protected.
- the upper side of the semiconductor component 100, which is formed by the first material 4, is flat and without an undefined sub-encapsulation, for example.
- the semiconductor component 100 offers defined surfaces and in particular a smooth and large surface for handling, for example by means of vacuum pickups. Due to the second material 5 and the resulting stiffening, the semiconductor component 5 nevertheless has good dimensional stability.
- FIGS. 2A and 2B A semiconductor component 100 according to a further exemplary embodiment is shown in FIGS. 2A and 2B in a sectional view and a top view of the upper side, which additionally has a viewing window 7 in the first material 4 .
- the first material 4 covers the second material 5 completely except for the viewing window 7.
- a part of a surface of the second material 5 can be visible through the viewing window 7.
- An inscription for example a laser inscription, or another identifier can be applied to the second material 5, ie to the stiffening frame of the semiconductor component 100.
- FIG. 2C A further exemplary embodiment is shown in FIG. 2C in a sectional illustration, in which the viewing window 7 is filled with a filling material 8 .
- the filling material 8 can, for example, be white or whitish or particularly preferably transparent and, for example, have or be a silicone.
- a covering element 9 can be arranged in or on the cavity 50 and thus in or on the opening 6 above the semiconductor chip element 2 .
- the covering element 9 can have or be a wavelength conversion material and/or a window element and/or a protective film.
- the cover element 9 can be spaced apart from the semiconductor chip element 2, as indicated in FIG. 2C.
- a viewing window and/or one or more covering elements can be present as described above.
- Exemplary embodiment of the semiconductor component 100 is shown, in which the first material 4 is arranged only in the cavity 50 of the second material 5 .
- the upper side of the second material 5 facing away from the carrier 1 is thus free from the first material 4 and thus forms part of the upper side of the semiconductor component 100.
- the stiffening frame formed by the second material 5 thus remains largely free at the top in this exemplary embodiment.
- a channel (not shown) for the molding compound can be on top of or below the second material 5 .
- a marking is shown on the upper side of the second material 5 purely by way of example.
- Exemplary embodiment of the semiconductor component 100 is shown, in which the first material 4 is arranged only in the region of the single wire connection 3 in this exemplary embodiment.
- the second material 5, which particularly preferably can have a third plastic material 53 formed by a black epoxy in this exemplary embodiment, can adjoin the semiconductor chip element 2 except for the area of the wire connection 3 and can be molded onto the main surface 10 of the carrier, for example by a molding process .
- the entire housing part can be produced on the carrier 1 by molding processes.
- FIGS. 5A to 5D Method steps of a method for producing the semiconductor component 100 of FIGS. 4A and 4B are shown in FIGS. 5A to 5D.
- a first method step the semiconductor chip element 2 is mounted on the carrier 1 and electrically contacted via the wire connection 3 .
- the first material 4 formed by the first plastic material 41 for encasing the wire connection 3 is applied.
- a kind of dome made of the soft and/or elastic first material 4 can be formed over the wire connection 3, which completely encloses the wire connection 3, but is only arranged in the area of the wire connection 3 .
- an optional further mold part 92 which can be moved separately, the top of the
- Semiconductor chip element 2 in particular the optoelectronic semiconductor chip, are protected.
- the second material 5 can be formed on the carrier 1 around the semiconductor chip element 2 with the first material 4 using the same molding tool 90 in a further method step.
- part of the upper side of the electronic semiconductor chip of the semiconductor chip element 2 can also be overmolded with the second material 5 .
- the semiconductor device 100 can be completed, as shown in Figure 5D.
- FIGS. 5A to 5D Even if methods for producing a single semiconductor component 100 are shown in FIGS. 5A to 5D and in other figures, a Production of a plurality of semiconductor components in the composite may be possible, which can be isolated after curing into separate semiconductor components.
- Semiconductor component 100 and a method for producing this are shown, in which two opposing wire connections 3 are present, which are encased by separate parts made of the first material 4.
- FIGS. 8A and 8B show an exemplary embodiment in which wire connections 3 are present around the semiconductor chip element 2, that is to say on all four sides.
- the first material 4 can be designed in the form of a frame, for example as shown, by means of the method described above, or it can also be applied to the wire connections 3 in separate parts. By simply adapting the mold 90, any number of wire contacts 3 can be encapsulated using the method described.
- Figures 9A to 9D show method steps for a method for producing a semiconductor component 100 according to a further exemplary embodiment, in which the molding tool for forming the second material 5 is shaped in such a way that the second material 5 is formed thicker and thus forms a more stable frame can.
- the second material 5 thus forms a molded body with a deeper cavity in which the semiconductor chip element is arranged.
- a cover element for example, can be placed in the cavity spaced from the semiconductor chip element 3 or are arranged directly on this.
- a wavelength conversion substance can be poured into the cavity, a glass window can be introduced, or, due to the depth of the cavity, a protective film can be kept at a distance over it.
- Exemplary embodiments and process steps can also be used, for example, to carry out and combine several vacuum injection molding steps or combinations of vacuum injection molding with other molding processes such as transfer molding in succession.
- FIG. 10A shows an exemplary embodiment of the semiconductor component 100 in which a radiation-insensitive protective layer formed from the second material 5 is applied over the first material 4.
- FIG. 10A shows an exemplary embodiment of the semiconductor component 100 in which a radiation-insensitive protective layer formed from the second material 5 is applied over the first material 4.
- 5 vacuum injection molding can be used for production.
- the first material 4 can form a mechanically stable molded body, for example made of a first plastic material 41 which has a preferably soft epoxy, while the second material 5 has a third plastic material 53 made of black silicone. Since both materials are produced in an injection molding process, the surfaces and layer thicknesses are well defined.
- the exemplary embodiment shown advantageously has high rigidity over a large component area, in particular over the wire connections 3 . There is also the benefit of protecting the epoxy to avoid UV light or blue light induced aging.
- FIG. 10A shows an exemplary embodiment of the semiconductor component 100 in which a radiation-insensitive protective layer formed from the second material 5 is applied over the first material 4.
- FIG. 10B shows an exemplary embodiment in which the first material has a first plastic material 41 formed by a silicone, while the second material 5 has a third plastic material 53 formed by a preferably rigid epoxy.
- the first material has a first plastic material 41 formed by a silicone
- the second material 5 has a third plastic material 53 formed by a preferably rigid epoxy.
- Both the first and the second material can comprise more than one plastic material, as shown in the exemplary embodiments below. In this way, for example, sequences of soft, hard and soft layers can be generated.
- FIG. 10C A further exemplary embodiment is shown in FIG. 10C, in which the first material 4 has, in addition to the first plastic material 41, a second plastic material 42 which is applied over the first plastic material 41.
- the plastic materials 41, 42 can be the same or preferably different from one another and can be applied using the same or different methods.
- the first plastic material 41 can be a silicone applied by means of vacuum injection molding or by means of mask-supported spraying
- the second plastic material 42 can be an epoxy applied by means of vacuum injection molding or else a silicone.
- a second material 5 comprising a third plastic material 53 formed from black silicone is applied, preferably by means of vacuum injection molding.
- the semiconductor component 100 shown has in particular a high rigidity over a large component area and a high rigidity in the area over the wire connections 3. Furthermore, a voltage reduction can be achieved in particular by the soft silicone layer between the carrier 1 and the epoxy layer, protection of the wire connections 3 by the epoxy layer, protection against light aging of the epoxy by the black silicone and a large light emission area.
- FIG. 10D shows a further exemplary embodiment in which the first material 4, as in the exemplary embodiment in FIG. 10A, is formed by a first plastic material 41 which has or is silicone applied by means of vacuum injection molding and which can be optically clear, for example.
- the second material 5 comprises a third plastic material 53 of optically clear or black rigid epoxy and overlying a fourth plastic material 54 of black silicone.
- the semiconductor component 100 shown has, in particular, a high level of rigidity over a large component area and a high level of rigidity in the area above the wire connections 3 .
- a stress reduction can be achieved in particular by the soft silicone layer between the carrier 1 and the epoxy layer and protection against light aging of the epoxy can be achieved by the black silicone.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202280038178.8A CN117397047A (zh) | 2021-05-27 | 2022-05-25 | 半导体元件和用于制造半导体元件的方法 |
DE112022002802.5T DE112022002802A5 (de) | 2021-05-27 | 2022-05-25 | Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102021113715.2A DE102021113715A1 (de) | 2021-05-27 | 2021-05-27 | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements |
DE102021113715.2 | 2021-05-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022248570A1 true WO2022248570A1 (de) | 2022-12-01 |
Family
ID=82218429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2022/064244 WO2022248570A1 (de) | 2021-05-27 | 2022-05-25 | Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN117397047A (de) |
DE (2) | DE102021113715A1 (de) |
WO (1) | WO2022248570A1 (de) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080164413A1 (en) * | 2004-11-24 | 2008-07-10 | Katsumi Shibayama | Infrared Sensor |
US20090127690A1 (en) * | 2005-07-28 | 2009-05-21 | Nxp B.V. | Package and Manufacturing Method for a Microelectronic Component |
US20160093761A1 (en) * | 2014-09-26 | 2016-03-31 | Texas Instruments Incorporated | Optoelectronic packages having through-channels for routing and vacuum |
WO2016193098A1 (de) * | 2015-06-02 | 2016-12-08 | Osram Opto Semiconductors Gmbh | Optoelektronisches bauelement und verfahren zur herstellung eines optoelektronischen bauelements |
US20170288108A1 (en) * | 2014-09-01 | 2017-10-05 | Osram Opto Semiconductors Gmbh | Light-emitting diode device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006269986A (ja) | 2005-03-25 | 2006-10-05 | Matsushita Electric Ind Co Ltd | 発光装置 |
US20190206752A1 (en) | 2017-12-29 | 2019-07-04 | Texas Instruments Incorporated | Integrated circuit packages with cavities and methods of manufacturing the same |
-
2021
- 2021-05-27 DE DE102021113715.2A patent/DE102021113715A1/de not_active Withdrawn
-
2022
- 2022-05-25 CN CN202280038178.8A patent/CN117397047A/zh active Pending
- 2022-05-25 DE DE112022002802.5T patent/DE112022002802A5/de active Pending
- 2022-05-25 WO PCT/EP2022/064244 patent/WO2022248570A1/de active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080164413A1 (en) * | 2004-11-24 | 2008-07-10 | Katsumi Shibayama | Infrared Sensor |
US20090127690A1 (en) * | 2005-07-28 | 2009-05-21 | Nxp B.V. | Package and Manufacturing Method for a Microelectronic Component |
US20170288108A1 (en) * | 2014-09-01 | 2017-10-05 | Osram Opto Semiconductors Gmbh | Light-emitting diode device |
US20160093761A1 (en) * | 2014-09-26 | 2016-03-31 | Texas Instruments Incorporated | Optoelectronic packages having through-channels for routing and vacuum |
WO2016193098A1 (de) * | 2015-06-02 | 2016-12-08 | Osram Opto Semiconductors Gmbh | Optoelektronisches bauelement und verfahren zur herstellung eines optoelektronischen bauelements |
Also Published As
Publication number | Publication date |
---|---|
CN117397047A (zh) | 2024-01-12 |
DE112022002802A5 (de) | 2024-03-21 |
DE102021113715A1 (de) | 2022-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1380056B2 (de) | Optoelektronische bauelementanordnung und verfahren zur herstellung einer optoelektronischen bauelementanordnung | |
DE102011053871B4 (de) | Multichip-Halbleitergehäuse und deren Zusammenbau | |
EP2215657B1 (de) | Anordnung mit mindestens zwei lichtemittierenden halbleiterbauelementen und herstellungsverfahren dafür | |
EP2345074B1 (de) | Trägerkörper für ein halbleiterbauelement, halbleiterbauelement und verfahren zur herstellung eines trägerkörpers | |
EP1622237A1 (de) | Optisches oder elektronisches Modul und Verfahren zu dessen Herstellung | |
WO2014060355A2 (de) | Verfahren zur herstellung einer vielzahl von optoelektronischen halbleiterbauteilen | |
EP1602625A1 (de) | Halbleitermodul mit einem Halbleiter-Sensorchip und einem Kunststoffgehäuse sowie Verfahren zu dessen Herstellung | |
DE102012102420B4 (de) | Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils | |
WO2016202917A1 (de) | Verfahren zum herstellen eines optoelektronischen bauelements und optoelektronisches bauelement | |
WO2015040107A1 (de) | Optoelektronisches bauelement und verfahren zu seiner herstellung | |
DE102016124270A1 (de) | Halbleiter-package und verfahren zum fertigen eines halbleiter-package | |
DE10124970B4 (de) | Elektronisches Bauteil mit einem Halbleiterchip auf einer Halbleiterchip-Anschlußplatte, Systemträger und Verfahren zu deren Herstellung | |
DE102018104382A1 (de) | Optoelektronisches bauelement und herstellungsverfahren | |
DE10234978A1 (de) | Oberflächenmontierbares Halbleiterbauelement und Verfahren zu dessen Herstellung | |
WO2022248570A1 (de) | Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements | |
DE102016108931A1 (de) | Optoelektronisches Bauteil und Verfahren zur Herstellung eines optoelektronischen Bauteils | |
DE102013207111B4 (de) | Optoelektronisches Bauelement | |
WO2020052973A1 (de) | Optoelektronisches bauteil und verfahren zur herstellung eines optoelektronischen bauteils | |
WO2019141435A1 (de) | Bauteil und verfahren zur herstellung eines bauteils | |
WO2018172276A1 (de) | Verfahren zur herstellung von optoelektronischen halbleiterbauteilen | |
WO2020169448A1 (de) | Optoelektronisches bauteil und verfahren zur herstellung eines optoelektronischen bauteils | |
DE102015115900A1 (de) | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements | |
DE102008043773A1 (de) | Elektrisches und/oder mikromechanisches Bauelement und Verfahren zur Herstellung eines elektrischen und/oder mikromechanischen Bauelements | |
DE102019112733A1 (de) | Lichtemittierendes Bauelement und Anzeigevorrichtung | |
DE102014116080A1 (de) | Optoelektronisches Bauelement und Verfahren zu seiner Herstellung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 22733865 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 202280038178.8 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112022002802 Country of ref document: DE |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: R225 Ref document number: 112022002802 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 22733865 Country of ref document: EP Kind code of ref document: A1 |