WO2022247742A1

WO2022247742A1 - Led chip and fabrication method therefor

Info

Publication number: WO2022247742A1
Application number: PCT/CN2022/094089
Authority: WO
Inventors: 曲晓东; 陈凯轩; 崔恒平; 蔡海防; 蔡玉梅; 林志伟; 杨克伟; 赵斌; 江土堆; 李艳
Original assignee: 厦门乾照光电股份有限公司
Priority date: 2021-05-24
Filing date: 2022-05-20
Publication date: 2022-12-01

Abstract

An LED chip and a fabrication method therefor, which implements a fabrication means of integrating a current spreading layer and a PAD metal layer, that is, forming an integrated metal layer and replacing a current spreading layer with the integrated metal layer; by using a metal material containing Au when fabricating the integrated metal layer, better current spreading capability is achieved due to the low resistivity of the Au-containing metal material. In addition, during the fabrication of the PAD, a part of the surface of the integrated metal layer is exposed by means of etching, and the exposed part acts as a PAD and can be electrically connected externally. By means of the described means, the process of separately fabricating the PAD metal layer is eliminated, saving costs. In addition, unlike a conventionally fabricated PAD metal layer, a side wall of the integrated metal layer is coated in an insulating layer, enabling relatively good resistance to erosion by external water vapor, an acid/base, salt mist and so on, and improving the reliability of a chip.

Description

A kind of LED chip and manufacturing method thereof

This application claims three priority rights: 1) A Chinese patent application submitted to the China Patent Office on May 24, 2021, with the application number 202110562795.5, and the invention titled "A through-hole vertical structure LED chip and its manufacturing method"; 2) On April 25, 2022, the Chinese patent application with the application number 202210442069.4 and the invention name "A Vertical Structure LED Chip and Its Manufacturing Method" was submitted to the China Patent Office; 3) On April 25, 2022, the Chinese patent application was submitted Bureau, the application number is 202220968167.7, and the Chinese patent application with the title of invention and creation is "a vertical structure LED chip".

The entire content of this application is quoted from the above three priority documents.

technical field

The present application relates to the field of light emitting diodes, in particular to an LED chip and a manufacturing method thereof.

Background technique

With the development of LED chip technology, great progress has been made in both vertical structure chips and flip chip structures, especially through-hole design, which can greatly improve the luminous efficiency of vertical chips and flip chips.

The so-called through-hole type is to open a hole on the epitaxial surface to the N-type semiconductor, and lead the N-type contact to the chip surface through electrical connection, so as to facilitate bonding or solid crystal; the chip structure can refer to Figure 1 of the accompanying drawing. As shown, in order to conduct the second-type semiconductor layer 33 during the fabrication process, an ohmic reflective layer 4 needs to be formed on the surface of the second-type semiconductor layer 33, and the ohmic reflective layer 4 and the PAD metal layer 9 are connected through the current spreading layer 8. connect. The better the expansion ability of the current expansion layer, the lower the voltage, the more uniform the current distribution, and the higher the light efficiency. In order to increase the expansion capability, the current spreading layer is usually realized by using high-conductivity metal or increasing the thickness. However, the chemical properties of high-conductivity metals are usually active (such as Ag, Cu, Al, Ca, Mg, etc.) or expensive (such as Au, etc.); Make a balance and compromise between product costs; for example, choose metals with relatively high resistivity such as Ti, W, Pt, Cr, etc., and achieve current expansion by increasing the thickness.

In view of this, the applicant specially designed an LED chip and its manufacturing method, and this case arose from it.

Contents of the invention

The purpose of this application is to provide an LED chip and a manufacturing method thereof, so as to solve the technical problem of balancing and compromising between current expansion performance and product cost when designing the product of the existing LED chip.

In order to achieve the above object, the technical scheme adopted by the application is as follows:

A LED chip, comprising:

A substrate, and a first metal layer, an insulating layer, an integrated metal layer, and an epitaxial stack disposed above the substrate; the epitaxial stack at least includes a second-type semiconductor layer stacked in sequence along a first direction, an active region, and A first-type semiconductor layer, and the epitaxial stack has a through hole exposing part of the surface of the first-type semiconductor layer; the first direction is perpendicular to the substrate, and is directed from the substrate to the epitaxial stack;

Wherein, the integrated metal layer is stacked on the surface of the second-type semiconductor layer away from the active region, and the integrated metal layer is provided with an electrical connection on the side facing the second-type semiconductor layer. bare face;

The insulating layer is arranged on a side of the epitaxial stack facing the substrate, and covers the integrated metal layer, the exposed surface of the epitaxial stack, and extends to the sidewall of the through hole;

The first metal layer is stacked on the surface of the insulation layer facing away from the integrated metal layer, and embedded in the through hole to form contact with the first-type semiconductor layer; and the substrate is stacked on the first The metal layer faces away from the surface of one side of the epitaxial stack.

Preferably, the integrated metal layer includes one or more of gold, copper, palladium and aluminum.

Preferably, the sidewall of the integrated metal layer is covered by the insulating layer.

Preferably, an ohmic reflective layer capable of ohmic contact and realizing light reflection is provided on the surface of the integrated metal layer facing the second type semiconductor layer.

Preferably, the ohmic reflective layer includes indium tin oxide, zinc tin oxide, indium zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrOx, RuOx, indium, One or more of tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium, molybdenum.

Preferably, the substrate comprises a conductive substrate.

Preferably, a passivation layer is provided on the sidewall of the epitaxial stack.

The application provides a method for manufacturing an LED chip, comprising the following steps:

S01, providing a growth substrate;

S02. Lay an epitaxial stack on the surface of the growth substrate, the epitaxial stack includes sequentially stacking a first-type semiconductor layer, an active region, and a second-type semiconductor layer along a first direction, and the first direction is perpendicular to the growth substrate, and directed from the growth substrate to the epitaxial stack;

S03, forming a through hole and a light-emitting mesa in the epitaxial stack by an etching process, the through hole exposing a part of the surface of the first type semiconductor layer;

S04, forming an ohmic reflective layer on the light-emitting mesa, the ohmic reflective layer is used for ohmic contact and realizes light reflection;

S05. Depositing an insulating layer, the insulating layer fills the through hole and extends to the periphery of the ohmic reflective layer;

S06, making an integrated metal layer, the integrated metal layer is stacked on the surface of the ohmic reflective layer and the insulating layer;

S07, depositing an insulating layer again, making the insulating layer cover the integrated metal layer, and forming a plane on the surface of the epitaxial stack;

S08, forming a through hole with an insulating layer on the side wall through an etching process;

S09, making a first metal layer, where the first metal layer is stacked on the surface of the insulating layer, and embedded in the through hole to form contact with the first type semiconductor layer;

S10, fixing the chip structure formed in step S09 on a conductive substrate through a bonding process, and the substrate is formed on the surface of the first metal layer;

S11. Peeling off the growth substrate;

S12. Etching part of the epitaxial stack to the insulating layer, so that the integrated metal layer has an exposed surface for electrical connection.

Preferably, the step S12 includes making the sidewall of the integrated metal layer covered by the insulating layer through an etching process.

The present application also provides a method for manufacturing an LED chip, comprising the following steps:

S01, providing a growth substrate;

S04. Deposit an insulating layer, the insulating layer covers the surface of the epitaxial stack, the sidewall and the bottom surface of the through hole, and pattern the insulating layer to expose part of the surface of the light-emitting mesa;

S05, forming an ohmic reflective layer on the exposed surface of the light-emitting mesa, the ohmic reflective layer is used for ohmic contact and realizes light reflection;

S07, depositing an insulating layer again, so that the insulating layer covers the integrated metal layer;

S11. Peeling off the growth substrate;

S12. Etching part of the epitaxial stack, so that the insulating layer has an exposed surface;

S13. Depositing a passivation layer, the passivation layer covering the exposed surfaces of the epitaxial stack and the insulating layer;

S14 , patterning the passivation layer and the insulating layer by photolithography and etching, so that part of the surface of the first-type semiconductor layer and part of the surface of the integrated metal layer are exposed.

Preferably, in the step S14, the pattern of the passivation layer and the exposed surface of the integrated metal layer are formed by the same photolithography.

Preferably, the step S14 includes making the sidewall of the integrated metal layer covered by the insulating layer through an etching process.

Preferably, the ohmic reflective layer includes indium tin oxide, zinc tin oxide, indium zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrO _x , RuO _x , One or more of indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium, and molybdenum.

It can be seen from the above-mentioned technical solutions that the LED chip provided by the present application is provided with an integrated metal layer on the surface of the second-type semiconductor layer away from the active region, and the integrated metal layer faces the first One side of the type II semiconductor layer is provided with an exposed surface for electrical connection; the insulating layer is arranged on the side of the epitaxial stack facing the substrate, and covers the integrated metal layer, the exposed surface of the epitaxial stack and extends to the sidewall of the through hole. The method of integrating the current spreading layer and the PAD metal layer is realized, that is, forming an integrated metal layer, replacing the current spreading layer with an integrated metal layer, and using Au-containing metal materials in the process of making the integrated metal layer, because the Au metal material The resistivity is low, which can achieve better current spreading ability; in addition, when the PAD is manufactured, part of the surface of the integrated metal layer is exposed by etching, and the material of the exposed part is easy to wire on it. The metal material of the material assumes the function of the PAD and can realize electrical connection with the outside. In this way, the process of separately manufacturing the PAD metal layer is saved, and the cost is saved. In addition, different from the traditional PAD metal layer, the side wall of the integrated metal layer is covered in the insulating layer, which can better withstand the erosion of external water vapor, acid and alkali, salt spray, etc., and improves the reliability of the chip.

At the same time, a passivation layer for protecting the LED chip is provided on the sidewall of the epitaxial stack, and based on this structure, the passivation layer and the insulating layer can be patterned in the same photolithography and etching process By exposing the surface of the first-type semiconductor layer and part of the surface of the integrated metal layer, the passivation of the side wall of the LED chip and the fabrication of the PAD can be realized simultaneously.

The manufacturing method of the LED chip provided by the application, while realizing the above-mentioned beneficial effects of the LED chip, its process is simple and convenient, saves the process of making a PAD metal layer separately, and the passivation layer and the insulating layer can be separated. Patterning in the same lithography and etching process saves costs and facilitates production.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present application, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

FIG. 1 is a schematic structural view of a through-hole LED chip provided in the background art;

FIG. 2 is a schematic structural view of a first implementation of an LED chip provided in an embodiment of the present application;

Figures 2.1 to 2.12 are structural schematic diagrams corresponding to the steps of the manufacturing method of the LED chip provided in Figure 2 in the embodiment of the present application;

FIG. 3 is a schematic structural diagram of a second implementation of the LED chip provided in the embodiment of the present application;

Fig. 3.1 to Fig. 3.14 are structural schematic diagrams corresponding to the steps of the manufacturing method of the LED chip provided in Fig. 3 in the embodiment of the present application.

Explanation of symbols in the figure: 1. Substrate, 2. Growth substrate, 3. Epitaxial stack, 31. First-type semiconductor layer, 32. Active region, 33. Second-type semiconductor layer, 34. Through hole, 35. Light-emitting mesa, 4. Ohmic reflection layer, 5. Insulation layer, 6. Integrated metal layer, 7. First metal layer, 8. Current spreading layer, 9. PAD metal layer, 10. Passivation layer.

Detailed ways

In order to make the content of this application clearer, the content of this application will be further described below in conjunction with the accompanying drawings. The application is not limited to this specific example. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

Embodiment one

As shown in Figure 2, an LED chip includes:

The substrate 1, and the first metal layer 7, the insulating layer 5, the integrated metal layer 6 and the epitaxial stack 3 disposed above the substrate 1; the epitaxial stack 3 at least includes a second-type semiconductor layer 33 stacked in sequence along the first direction, The active region 32 and the first-type semiconductor layer 31, and the epitaxial stack 3 has a through hole 34 exposing part of the surface of the first-type semiconductor layer 31; the first direction is perpendicular to the substrate 1, and is directed from the substrate 1 to the epitaxial stack 3;

Wherein, the integrated metal layer 6 is stacked on the side surface of the second-type semiconductor layer 33 away from the active region 32, and the side of the integrated metal layer 6 facing the second-type semiconductor layer 33 is provided with an exposed surface for electrical connection;

The insulating layer 5 is provided on the side of the epitaxial stack 3 facing the substrate 1, and covers the integrated metal layer 6, the exposed surface of the epitaxial stack 3, and extends to the side wall of the through hole 34;

The first metal layer 7 is stacked on the side surface of the insulating layer 5 away from the integrated metal layer 6, and embedded in the through hole 34 to form contact with the first type semiconductor layer 31; and the substrate 1 is stacked on the first metal layer 7 away from the epitaxial stack 3 side surface.

It is worth mentioning that, in addition, the types of the first-type semiconductor layer 31, the active region 32, and the second-type semiconductor layer 33 of the epitaxial stack are not limited in this embodiment, for example, the first-type semiconductor layer 31 may be but not limited to a gallium nitride layer, and correspondingly, the second-type semiconductor layer 33 may be but not limited to a gallium nitride layer;

Meanwhile, this embodiment does not limit the specific types of the insulating layer 5 and the first metal layer 7 , as long as the above requirements are met.

In this embodiment, the integrated metal layer 6 includes Au metal material.

In this embodiment, the sidewall of the integrated metal layer 6 is covered by the insulating layer 5 .

In this embodiment, an ohmic reflective layer 4 capable of ohmic contact and light reflection is provided on the surface of the integrated metal layer 6 facing the second-type semiconductor layer 33 .

In this embodiment, the ohmic reflective layer 4 includes one or more of indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, and nickel.

In this embodiment, the substrate 1 includes a conductive substrate 1 .

S01, as shown in Figure 2.1, provide a growth substrate 2;

S02, as shown in Figure 2.2, stack an epitaxial stack 3 on the surface of the growth substrate 2, the epitaxial stack 3 includes stacking the first type semiconductor layer 31, the active region 32 and the second type semiconductor layer 33 in sequence along the first direction , the first direction is perpendicular to the growth substrate 2, and is directed from the growth substrate 2 to the epitaxial stack 3;

S03, as shown in FIG. 2.3, form a through hole 34 and a light-emitting mesa 35 in the epitaxial stack 3 through an etching process, and the through hole 34 exposes part of the surface of the first-type semiconductor layer 31;

S04, as shown in Figure 2.4, form an ohmic reflective layer 4 on the light-emitting table 35, and the ohmic reflective layer 4 is used for ohmic contact and realizes light reflection;

S05, as shown in Figure 2.5, deposit an insulating layer 5, the insulating layer 5 fills the through hole 34 and extends to the periphery of the ohmic reflective layer 4;

S06, as shown in Figure 2.6, fabricate the integrated metal layer 6, and the integrated metal layer 6 is stacked on the surface of the ohmic reflective layer 4 and the insulating layer 5;

S07, as shown in Figure 2.7, deposit an insulating layer 5 again, so that the insulating layer 5 covers the integrated metal layer 6, and make the surface of the epitaxial stack 3 form a plane;

S08. As shown in FIG. 2.8, through an etching process, a through hole 34 having an insulating layer 5 on the side wall is formed;

S09, as shown in Figure 2.9, fabricate the first metal layer 7, the first metal layer 7 is stacked on the surface of the insulating layer 5, and embedded in the through hole 34 to form contact with the first type semiconductor layer 31;

S10. As shown in FIG. 2.10, the chip structure formed in step S09 is fixed on the conductive substrate 1 through a bonding process, and the substrate 1 is formed on the surface of the first metal layer 7;

S11, as shown in Figure 2.11, peel off the growth substrate 2;

S12. As shown in FIG. 2.12, etch part of the epitaxial stack 3 to the insulating layer 5, so that the integrated metal layer 6 has an exposed surface for electrical connection.

In this embodiment, step S12 includes making the sidewall of the integrated metal layer 6 covered by the insulating layer 5 through an etching process.

In this embodiment, the integrated metal layer 6 includes Au metal material.

It can be known from the above technical solutions that the LED chip provided by the present application is provided with an integrated metal layer 6 on the surface of the second-type semiconductor layer 33 facing away from the active region 32, and the integrated metal layer 6 faces the second-type semiconductor layer One side of 33 is provided with an exposed surface for electrical connection; the insulating layer 5 is provided on the side of the epitaxial stack 3 facing the substrate, and covers the integrated metal layer 6 , the exposed surface of the epitaxial stack 3 and extends to the sidewall of the through hole 34 . The method of integrating the current spreading layer and the PAD metal layer is realized, that is, the integrated metal layer 6 is formed, and the current spreading layer is replaced by the integrated metal layer 6. Au-containing metal materials are used in the process of making the integrated metal layer 6, because The resistivity of the Au metal material is low, which can achieve better current expansion capability; in addition, when the PAD is made, a part of the surface in the integrated metal layer 6 is exposed by etching, and the exposed part undertakes the PAD function, which can realize with external electrical connection. In this way, the process of separately manufacturing the PAD metal layer is saved, and the cost is saved. In addition, different from the traditional PAD metal layer, the side wall of the integrated metal layer 6 is covered in the insulating layer 5, which can better withstand the erosion of external water vapor, acid and alkali, salt spray, etc., and improves the reliability of the chip. sex.

The manufacturing method of the LED chip provided by the present application realizes the above-mentioned beneficial effect of the through hole 34 filled LED chip, and at the same time, its process is simple and convenient to manufacture, saves the process of separately manufacturing the PAD metal layer, saves the cost, and is convenient for production. .

Embodiment two

As shown in Figure 3, an LED chip includes:

Wherein, the integrated metal layer 6 is stacked on the surface of the second-type semiconductor layer 33 facing away from the active region 32, and the integrated metal layer 6 is provided with an exposed surface for electrical connection on the side facing the second-type semiconductor layer 33; and, On the surface of the integrated metal layer 6 facing the second-type semiconductor layer 33, an ohmic reflective layer 4 capable of ohmic contact and light reflection is provided;

The first metal layer 7 is stacked on the side surface of the insulating layer 5 away from the integrated metal layer 6, and embedded in the through hole 34 to form contact with the first type semiconductor layer 31; and the substrate 1 is stacked on the first metal layer 7 away from the epitaxial stack 3 one side of the surface;

A passivation layer 10 is provided on the sidewall of the epitaxial stack 3 . It can be seen from the comparison that, compared with the first embodiment, the passivation layer 10 is added in the embodiment of the present application.

In this embodiment, the integrated metal layer 6 includes but not limited to one or more of gold, copper, palladium, and aluminum.

In this embodiment, the ohmic reflective layer 4 includes but not limited to indium tin oxide, zinc tin oxide, indium zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrOx, One or more of RuOx, indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium, molybdenum.

In this embodiment, the substrate 1 includes a conductive substrate.

In this embodiment, the passivation layer 10 includes but is not limited to one or more stacks of SiOxNy passivation layer, Al2O3 passivation layer, MgF passivation layer, TiOx passivation layer, wherein, x≥0, y≥0 .

In this embodiment, the epitaxial stack 3 has at least one exposed surface of the insulating layer, which extends from the first-type semiconductor layer 31 to the insulating layer 5 through the active region 32 and the second-type semiconductor layer 33, wherein , the passivation layer 10 is attached to the sidewalls of the epitaxial stack 3 in such a manner that it remains on the exposed surface of the insulating layer.

In this embodiment, the exposed surface of the lining insulating layer surrounds the periphery of the epitaxial stack 3; wall.

S01, as shown in Figure 3.1, provide a growth substrate 2;

S02, as shown in Figure 3.2, stack an epitaxial stack 3 on the surface of the growth substrate 2, the epitaxial stack 3 includes stacking the first type semiconductor layer 31, the active region 32 and the second type semiconductor layer 33 in sequence along the first direction , the first direction is perpendicular to the growth substrate 2, and is directed from the growth substrate 2 to the epitaxial stack 3;

S03, as shown in FIG. 3.3, form a through hole 34 and a light-emitting mesa 35 in the epitaxial stack 3 through an etching process, and the through hole 34 exposes part of the surface of the first-type semiconductor layer 31;

S04, as shown in Figure 3.4, deposit an insulating layer 5, the insulating layer 5 covers the surface of the epitaxial stack 3, the side wall and the bottom surface of the through hole 34, and pattern the insulating layer 5 to expose the light-emitting mesa part of the surface;

S05, as shown in Figure 3.5, form an ohmic reflective layer 4 on the exposed surface of the light-emitting table 35, and the ohmic reflective layer 4 is used for ohmic contact and realizes light reflection;

S06, as shown in Figure 3.6, fabricate the integrated metal layer 6, and the integrated metal layer 6 is stacked on the surface of the ohmic reflective layer 4 and the insulating layer 5;

S07, as shown in Figure 3.7, deposit an insulating layer 5 again, so that the insulating layer 5 covers the integrated metal layer 6;

S08, as shown in Figure 3.8, through an etching process, form a through hole 34 with an insulating layer 5 on the side wall;

S09, as shown in Figure 3.9, fabricate the first metal layer 7, the first metal layer 7 is stacked on the surface of the insulating layer 5, and embedded in the through hole 34 to form contact with the first type semiconductor layer 31;

S10, as shown in Figure 3.10, fix the chip structure formed in step S09 on the conductive substrate 1 through a bonding process, and the substrate 1 is formed on the surface of the first metal layer 7;

S11, as shown in Figure 3.11, peel off the growth substrate 2;

S12. As shown in FIG. 3.12, etching part of the epitaxial stack 3 so that the insulating layer 5 has an exposed surface;

S13. As shown in FIG. 3.13, deposit a passivation layer 10, the passivation layer 10 covering the exposed surfaces of the epitaxial stack 3 and the insulating layer 5;

S14, as shown in Figure 3.14, pattern the passivation layer 10 and the insulating layer 5 by photolithography and etching, so that part of the surface of the first-type semiconductor layer 31 and part of the surface of the integrated metal layer 6 exposed.

In this embodiment, in the step S14, the pattern of the passivation layer 10 and the exposed surface of the integrated metal layer 6 are formed by the same photolithography.

In this embodiment, step S14 includes making the sidewall of the integrated metal layer 6 covered by the insulating layer 5 through an etching process.

In this embodiment, the integrated metal layer 6 includes but not limited to one or more of gold, copper, palladium, and aluminum. In this embodiment, the ohmic reflective layer 4 includes indium tin oxide, zinc tin oxide, indium zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrOx, RuOx, indium , tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium, molybdenum in one or more. Further, in this embodiment, the exposed surface of the insulating layer surrounds the periphery of the epitaxial stack 3; and the passivation layer 10 is arranged around the epitaxial stack 3 in a manner of being kept on the exposed surface of the insulating layer. side wall.

It can be known from the above technical solutions that the LED chip provided by the present application is provided with an integrated metal layer 6 on the surface of the second-type semiconductor layer 33 facing away from the active region 32, and the integrated metal layer 6 faces the second-type semiconductor layer One side of 33 is provided with an exposed surface for electrical connection; the insulating layer 5 is provided on the side of the epitaxial stack 3 facing the substrate, and covers the integrated metal layer 6 , the exposed surface of the epitaxial stack 3 and extends to the sidewall of the through hole 34 . The method of integrating the current spreading layer and the PAD metal layer is realized, that is, the integrated metal layer 6 is formed, and the current spreading layer is replaced by the integrated metal layer 6. Au-containing metal materials are used in the process of making the integrated metal layer 6, because The resistivity of Au metal material is low, can realize better electric current spreading ability; In addition, when PAD is made, by the mode of etching, expose the partial surface in integrated metal layer 6, the material of this bare part is easy to be in its The metal material of the upper wire bonding material undertakes the PAD function and can realize electrical connection with the outside. In this way, the process of separately manufacturing the PAD metal layer is saved, and the cost is saved. In addition, different from the traditional PAD metal layer, the side wall of the integrated metal layer 6 is covered in the insulating layer 5, which can better withstand the erosion of external water vapor, acid and alkali, salt spray, etc., and improves the reliability of the chip. sex.

At the same time, a passivation layer 10 for protecting the LED chip is provided on the sidewall of the epitaxial stack 3, and based on this structure, the passivation layer 10 and the insulating layer 5 can be etched and etched in the same process. Patterning in the etching process, so that the surface of the first-type semiconductor layer and part of the surface of the integrated metal layer are exposed, so that the passivation of the side wall of the LED chip and the manufacture of the PAD can be realized.

The manufacturing method of the LED chip provided by the application realizes the above-mentioned beneficial effect of the through-hole 34-filled LED chip, and its process is simple and convenient, saves the process of separately manufacturing the PAD metal layer, and the passivation layer and The insulating layer can be patterned in the same photolithography and etching process, which saves cost and facilitates production.

The implementation principles and technical effects of the device provided by the embodiment of the present application are the same as those of the aforementioned method embodiment. For brief description, for the parts not mentioned in the device embodiment, reference may be made to the corresponding content in the aforementioned method embodiment. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the above-mentioned method embodiments, and will not be repeated here.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

It should also be noted that in this article, relational terms such as first and second etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations Any such actual relationship or order exists between. Moreover, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that an article or device comprising a set of elements includes not only those elements but also other elements not expressly listed, Or also include elements inherent in the article or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in an article or device comprising the aforementioned element.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

A kind of LED chip is characterized in that, comprises:

A substrate, and a first metal layer, an insulating layer, an integrated metal layer, and an epitaxial stack disposed above the substrate; the epitaxial stack at least includes a second-type semiconductor layer stacked in sequence along a first direction, an active region, and A first-type semiconductor layer, and the epitaxial stack has a through hole exposing part of the surface of the first-type semiconductor layer; the first direction is perpendicular to the substrate, and is directed from the substrate to the epitaxial stack;

Wherein, the integrated metal layer is stacked on the surface of the second-type semiconductor layer away from the active region, and the integrated metal layer is provided with an electrical connection on the side facing the second-type semiconductor layer. bare face;

The insulating layer is arranged on a side of the epitaxial stack facing the substrate, and covers the integrated metal layer, the exposed surface of the epitaxial stack, and extends to the sidewall of the through hole;

The first metal layer is stacked on the surface of the insulation layer facing away from the integrated metal layer, and embedded in the through hole to form contact with the first-type semiconductor layer; and the substrate is stacked on the first The metal layer faces away from the surface of one side of the epitaxial stack.
The LED chip according to claim 1, wherein the integrated metal layer comprises one or more of gold, copper, palladium and aluminum.
The LED chip according to claim 1, wherein the sidewall of the integrated metal layer is covered by the insulating layer.
The LED chip according to claim 1, wherein an ohmic reflective layer capable of ohmic contact and realizing light reflection is provided on the surface of the integrated metal layer facing the second type semiconductor layer.
The LED chip according to claim 4, wherein the ohmic reflective layer comprises indium tin oxide, zinc tin oxide, indium zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide , gallium zinc oxide, IrOx, RuOx, indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium, molybdenum in one or more.
The LED chip according to claim 1, wherein the substrate comprises a conductive substrate.
The LED chip according to any one of claims 1-6, characterized in that a passivation layer is provided on the sidewall of the epitaxial stack.
A method for manufacturing an LED chip, characterized in that it comprises the steps of:

S01, providing a growth substrate;

S02. Lay an epitaxial stack on the surface of the growth substrate, the epitaxial stack includes a first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked in sequence along a first direction, and the first direction is vertical on the growth substrate, and directed from the growth substrate to the epitaxial stack;

S03, forming a through hole and a light-emitting mesa in the epitaxial stack by an etching process, the through hole exposing a part of the surface of the first type semiconductor layer;

S04, forming an ohmic reflective layer on the light-emitting mesa, the ohmic reflective layer is used for ohmic contact and realizes light reflection;

S05. Depositing an insulating layer, the insulating layer fills the through hole and extends to the periphery of the ohmic reflective layer;

S06, making an integrated metal layer, the integrated metal layer is stacked on the surface of the ohmic reflective layer and the insulating layer;

S07, depositing an insulating layer again, making the insulating layer cover the integrated metal layer, and forming a plane on the surface of the epitaxial stack;

S08, forming a through hole with an insulating layer on the side wall through an etching process;

S09, making a first metal layer, where the first metal layer is stacked on the surface of the insulating layer, and embedded in the through hole to form contact with the first type semiconductor layer;

S10, fixing the chip structure formed in step S09 on a conductive substrate through a bonding process, and the substrate is formed on the surface of the first metal layer;

S11. Peeling off the growth substrate;

S12. Etching part of the epitaxial stack to the insulating layer, so that the integrated metal layer has an exposed surface for electrical connection.
The method for manufacturing an LED chip according to claim 8, wherein the step S12 comprises: making the sidewall of the integrated metal layer covered by the insulating layer through an etching process.
A method for manufacturing an LED chip, characterized in that it comprises the steps of:

S01, providing a growth substrate;

S02. Lay an epitaxial stack on the surface of the growth substrate, the epitaxial stack includes sequentially stacking a first-type semiconductor layer, an active region, and a second-type semiconductor layer along a first direction, and the first direction is perpendicular to the growth substrate, and directed from the growth substrate to the epitaxial stack;

S03, forming a through hole and a light-emitting mesa in the epitaxial stack by an etching process, the through hole exposing a part of the surface of the first type semiconductor layer;

S04. Deposit an insulating layer, the insulating layer covers the surface of the epitaxial stack, the sidewall and the bottom surface of the through hole, and pattern the insulating layer to expose part of the surface of the light-emitting mesa;

S05, forming an ohmic reflective layer on the exposed surface of the light-emitting mesa, the ohmic reflective layer is used for ohmic contact and realizes light reflection;

S06, making an integrated metal layer, the integrated metal layer is stacked on the surface of the ohmic reflective layer and the insulating layer;

S07, depositing an insulating layer again, so that the insulating layer covers the integrated metal layer;

S08, forming a through hole with an insulating layer on the side wall through an etching process;

S09, making a first metal layer, where the first metal layer is stacked on the surface of the insulating layer, and embedded in the through hole to form contact with the first type semiconductor layer;

S10, fixing the chip structure formed in step S09 on a conductive substrate through a bonding process, and the substrate is formed on the surface of the first metal layer;

S11. Peeling off the growth substrate;

S12. Etching part of the epitaxial stack, so that the insulating layer has an exposed surface;

S13. Depositing a passivation layer, the passivation layer covering the exposed surfaces of the epitaxial stack and the insulating layer;

S14 , patterning the passivation layer and the insulating layer by photolithography and etching, so that part of the surface of the first-type semiconductor layer and part of the surface of the integrated metal layer are exposed.
The method for manufacturing an LED chip according to claim 10, wherein in the step S14, the pattern of the passivation layer and the exposed surface of the integrated metal layer are formed by the same photolithography.
The method for manufacturing an LED chip according to claim 10, wherein the step S14 includes encapsulating the sidewall of the integrated metal layer by the insulating layer through an etching process.
The method for manufacturing an LED chip according to any one of claims 8-12, wherein the integrated metal layer includes one or more of gold, copper, palladium, and aluminum.
The manufacturing method of an LED chip according to any one of claims 8-12, wherein the ohmic reflective layer comprises indium tin oxide, zinc tin oxide, indium zinc tin oxide, indium aluminum tin oxide, indium gallium oxide One or more of tin, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrO x , RuO x , indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium, molybdenum .