CN106159045A - Flip LED chips and manufacture method thereof - Google Patents
Flip LED chips and manufacture method thereof Download PDFInfo
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- CN106159045A CN106159045A CN201510173371.4A CN201510173371A CN106159045A CN 106159045 A CN106159045 A CN 106159045A CN 201510173371 A CN201510173371 A CN 201510173371A CN 106159045 A CN106159045 A CN 106159045A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
A kind of flip LED chips and manufacture method thereof.Wherein, described manufacture method includes: depositing extension lamination on substrate, extension lamination includes the first semiconductor layer, quantum well layer and the second semiconductor layer；Etching extension lamination, until forming the groove of bottom-exposed the first semiconductor layer, residue extension lamination is Mesa platform；Deposition of first electrode on the first semiconductor layer of channel bottom, has gap between the first electrode and Mesa platform；Form insulating barrier cover the first electrode and fill full gap；Mesa platform and insulating barrier are formed electrode extension layer；Electrode extension layer connects electrically-conductive backing plate；Substrate is peeled off with extension lamination, to expose the exiting surface of the first semiconductor layer；Etch the exiting surface of the first semiconductor layer, until exposing at least part of first electrode.The flip LED chips encapsulation yield that described manufacture method is formed improves.
Description
Technical field
The present invention relates to LED and manufacture field, particularly relate to a kind of flip LED chips and manufacture method thereof.
Background technology
Light emitting diode (Light Emitting Diode, LED) chip, also referred to as LED (luminous) chip,
It it is the semiconductor device of solid-state.Light emitting diode in LED chip utilizes semiconductor PN as luminescence
Material, can convert the electricity into light.Time luminous, the two ends of semiconductor PN add forward voltage, inject
Electronics and hole in PN junction occur compound, are discharged with the form of photon by superfluous energy.And light
Wavelength i.e. the color of light, be by formed PN junction material determine.
LED chip has that energy consumption is low, volume is little, life-span length, good stability, response are fast and emission wavelength
The photoelectric properties feature such as stable, the most has extensively in fields such as illumination, household electrical appliances, display screen and display lamps
General application.
In order to improve quality of lighting and the integrated level of LED product, unit are light efficiency be [unit are light efficiency
Unit is: lm/ (W cm2)] become the important indicator weighing LED chip.
Flip LED chips has low-voltage, specular removal and high stability, owing to flip LED chips is outstanding
Heat-sinking capability and current expansion ability, become meet LED chip development trend require focus product.
The manufacture method of existing flip LED chips structure is generally as follows: preparation LED chip；Prepare simultaneously
The heat-radiating substrate of corresponding LED chip size, and on heat-radiating substrate, make the conductive layer of electrode and extraction is led
Electric layer；LED chip is welded together with heat-radiating substrate.
But, the P of existing flip-chip, N electrode are generally at the homonymy of LED chip, and it is to encapsulation skill
The requirement of art is of a relatively high, easily causes the loss of encapsulation yield, and more difficult welds, unit plane
Long-pending light efficiency also has much room for improvement.
More contents about existing flip LED chips structure and manufacture method thereof are referred to Publication No.
The Chinese invention patent application of CN103078050A.
Summary of the invention
The problem that the present invention solves is to provide a kind of flip LED chips and manufacture method thereof, to improve encapsulation
Yield.
For solving the problems referred to above, the present invention provides the manufacture method of a kind of flip LED chips, including:
Substrate is provided；
Depositing extension lamination over the substrate, described extension lamination includes the first semiconductor layer, SQW
Layer and the second semiconductor layer, described quantum well layer is positioned at described first semiconductor layer and described second quasiconductor
Between Ceng；
Etch described extension lamination, until forming the groove of the first semiconductor layer described in bottom-exposed, residue
Described extension lamination is left Mesa platform；
Deposition of first electrode on the first semiconductor layer of described channel bottom, described first electrode is with described
Between Mesa platform, there is gap；
Form insulating barrier cover described first electrode and fill full described gap；
Described Mesa platform and described insulating barrier are formed electrode extension layer；
Described electrode extension layer connects electrically-conductive backing plate as the second electrode；
Described substrate is peeled off with described extension lamination, to expose the exiting surface of described first semiconductor layer；
Etch the exiting surface of described first semiconductor layer, until exposing the most described first electrode.
Optionally, described manufacture method also includes: form the collets covering described Mesa platform surface,
Described insulating barrier and described collets expose at least part of described Mesa platform surface, described electrode extension layer
Cover the described Mesa platform surface exposed by described insulating barrier and described collets, and described electrode expands
Exhibition layer covers described insulating barrier and described collets.
Optionally, described manufacture method also includes: after the exiting surface exposing described first semiconductor layer,
And before the exiting surface etching described first semiconductor layer, the exiting surface of described first semiconductor layer is carried out
At least one process that cleaning processes and rough surface processes.
Optionally, described substrate is included with the stripping of described extension lamination: use chemical method or laser
Described substrate is peeled off by method with described extension lamination.
Optionally, described manufacture method also includes: after exposing the most described first electrode, in institute
The 3rd electrode is formed on described first electrode exposed.
Optionally, described first semiconductor layer is n type nitride semiconductor layer and described second semiconductor layer
For P-type nitride semiconductor, or described first semiconductor layer is P-type nitride semiconductor and institute
Stating the second semiconductor layer is n type nitride semiconductor layer.
Optionally, the material of described first electrode be Cr, Ni, Ti, Pt, Ag, Al, Rh, Au and
One or more in Sn；The material of described 3rd electrode is Cr, Ni, Ti, Pt, Ag, Al, Rh,
One or more in Au and Sn.
Optionally, described insulating barrier is single layer structure or multiple structure.
Optionally, the material of described insulating barrier is SiO2、SiN、SiON、Al2O3And TiO2In one
Or it is multiple.
For solving the problems referred to above, present invention also offers a kind of flip LED chips, including:
Mesa platform, described Mesa platform includes the first semiconductor layer, quantum well layer and the second quasiconductor
Layer, described quantum well layer between described first semiconductor layer and described second semiconductor layer, Mei Gesuo
The described Mesa stating chip unit region has groove；
Described channel bottom has the first electrode, between having between described first electrode and described Mesa platform
Gap；
Insulating barrier, described insulating barrier covers described first electrode and fills described gap；
Electrode extension layer, described electrode extension layer covers described Mesa platform and described insulating barrier；
Electrically-conductive backing plate, described electrically-conductive backing plate covers described electrode extension layer.
Optionally, described flip LED chips also includes the collets covering described Mesa platform surface,
Described insulating barrier and described collets expose at least part of described Mesa platform surface, described electrode extension layer
Cover the described Mesa platform surface exposed by described insulating barrier and described collets, and described electrode expands
Exhibition layer covers described insulating barrier and described collets.
Optionally, described flip LED chips also includes the 3rd electrode being positioned at described first electrode surface.
Optionally, the exiting surface of described first semiconductor layer is rough surface.
Optionally, described first semiconductor layer is n type nitride semiconductor layer and described second semiconductor layer
For P-type nitride semiconductor, or described first semiconductor layer is P-type nitride semiconductor and institute
Stating the second semiconductor layer is n type nitride semiconductor layer.
Optionally, described insulating barrier is single layer structure or multiple structure.
Optionally, during the material of described insulating barrier is SiO2, SiN, SiON, Al2O3 and TiO2
Plant or multiple.
Compared with prior art, technical scheme has the advantage that
In technical scheme, by by LED chip using electrically-conductive backing plate as one of them electrode
(the i.e. second electrode), and another electrode (the i.e. first electrode) is arranged on relative with electrically-conductive backing plate the first half
The exiting surface of conductor layer, thus by the upper and lower surface of the two of LED chip electrode separation to LED chip,
Improve the ease of the encapsulation of LED chip, improve encapsulation yield.
Further, arrange and cover the collets of described Mesa platform surface.Arranging of collets can cover
Described Mesa platform surface is to realize reducing between the second semiconductor layer and the electrode extension layer being subsequently formed
Electric current.First, due to the obstructed electric current of collets, therefore, it can arrange control electric current by collets
Distribution, the CURRENT DISTRIBUTION making LED chip is more reasonable；Second, due to the existence of collets, LED core
Reflectance within sheet can become more preferable, and particularly collets can be (follow-up with follow-up metal level
Electrode extension layer use metal level formed) cooperatively form full-shape reflecting mirror (Omni-Directional
Reflector, ODR), thus increase the average reflectance of whole electrode extension layer plane.
Accompanying drawing explanation
Fig. 1 to Figure 12 is each step of manufacture method of the flip LED chips that the embodiment of the present invention is provided
Counter structure schematic diagram；
Figure 13 to Figure 20 is that the manufacture method of the flip LED chips that another embodiment of the present invention is provided is each
Step counter structure schematic diagram.
Detailed description of the invention
From background technology, the P of existing flip LED chips structure, N electrode generally same at chip
Side, therefore the requirement to encapsulation technology is of a relatively high, easily causes the loss of encapsulation yield.
Although the upside-down mounting product design having fewer companies can realize P, N electrode is distributed in the both sides of chip,
But their N electrode that is designed with is interconnected with substrate by the method for through hole, causes encapsulating yield still
Relatively low.And also causing the lighting area that LED chip loses relatively big, high reflecting mirror surface area is less, leads
Cause unit are light efficiency to reduce.Therefore, the encapsulation yield of existing flip LED chips is relatively low, and unit plane
Long-pending light efficiency still has room for promotion.
To this end, the present invention provides a kind of new flip LED chips and manufacture method thereof.Described flip LED
Chip is by using electrically-conductive backing plate as an electrode of chip, and another electrode uses at exiting surface routing
Method, such that it is able to by the upper and lower surface of the two of chip electrode separation to chip, improve encapsulation good
Rate.Further, described flip LED chips can also keep the outstanding current expansion of conventional flip chip and dissipate
Heat energy power, and there is the advantage more easily welding encapsulation., designed by rational chip, institute meanwhile
State flip LED chips and there is the advantage that processing technology is simple, unit are light efficiency is high.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
One embodiment of the invention provide a kind of flip LED chips manufacture method, incorporated by reference to referring to figs. 1 to
Figure 12.
With reference to Fig. 1, it is provided that substrate 100.
In the present embodiment, substrate 100 can be sapphire (Al2O3) substrate.Other reality in the present invention
Execute in example, according to technique needs, it is also possible to select other to be applicable to the substrate that LED chip manufactures, such as
With spinelle (MgAl2O4), the substrate that SiC, ZnS, ZnO or GaAs etc. manufacture.
With continued reference to Fig. 1, deposit extension lamination (mark), described extension lamination bag on the substrate 100
Include the first semiconductor layer 110, quantum well layer 120 and the second semiconductor layer 130, the first semiconductor layer 110,
Quantum well layer 120 and the second semiconductor layer 130 stacking from top to bottom.
In the present embodiment, the first semiconductor layer 110 is n type nitride semiconductor layer and the second semiconductor layer
130 is P-type nitride semiconductor.First semiconductor layer 110 can be the GaN film of n-type doping.
The n-type doping concentration of GaN film can be 5E17cm-3～1E19cm-3.Second semiconductor layer 130 can be
The GaN film of p-type doping.Second semiconductor layer 130 is grown on quantum well layer 120.Can be by right
Semiconductor layer is doped, to form the second semiconductor layer 130.And it is possible to improve hole by doping
Concentration, improves the electric conductivity of the second semiconductor layer 130, thus obtains high-quality second semiconductor layer
130, improve LED chip structure quality.
It should be noted that in other embodiments of the invention, the first semiconductor layer 110 can also be P
Type nitride semiconductor layer, the such as GaN film of p-type doping.Now the second semiconductor layer 130 is N-type
The GaN film of nitride semiconductor layer, such as n-type doping.When the first semiconductor layer 110 nitrogenizes for p-type
When thing semiconductor layer and the second semiconductor layer 130 are n type nitride semiconductor layer, substrate 100 can select
Make of the material being suitable to the first semiconductor layer 110 growth.
In the present embodiment, quantum well layer 120 generally can be expressed as again MQW (multiple quantum
Well) active layer, also referred to as multiple quantum well layer.Quantum well layer 120 can be by generating the low energy gap containing In
Width nitride film (not shown) and the nitride film (not shown) of broad stopband width, and allow low energy gap width
The nitride film of degree and the nitride film of broad stopband width are alternately arranged, form quantum well layer 120.Wherein,
Low energy gap width nitride film containing In can be InGaN film, and forming temperature can be 700 DEG C～900 DEG C.
The nitride film of broad stopband width can be GaN film, and forming temperature can be 700 DEG C～900 DEG C.
Fig. 2 with Fig. 3 is shown that mutually isostructural different views.Wherein, Fig. 2 is top view, Fig. 3
For sectional view.
In conjunction with referring to figs. 2 and 3, etch described extension lamination, until formed bottom-exposed the first quasiconductor
The groove 140 of layer 110, remains described extension lamination and is left Mesa platform (mark).
Fig. 2 shows groove 140 and the plan structure of described Mesa platform.Described Mesa platform is institute
Stating extension lamination to be etched and form the remainder after groove 140, groove 140 bottom-exposed goes out the simultaneously
Semi-conductor layer 110.
In the present embodiment, groove 140 is in being similar to the plan view shape of a spoon, and described shape has one
Spoon head part that individual area is bigger and the kettleholder part of a uniform elongate.The benefit of this shape is: after
The continuous electrode formed also can be this spoon shape, and so, described electrode just can only utilize spoon head part
Reduce connection area for electrically connecting with follow-up electrode or contact conductor, and utilize kettleholder partially ON
Electric current and increase described electrode electric current transmission scope.
Fig. 3 shows that groove 140 runs through quantum well layer 120 and the second semiconductor layer 130, but does not runs through
Semi-conductor layer 110.It is internal and only need to expose that groove 140 needs not extend to the first semiconductor layer 110
Semi-conductor layer 110 surface, but due to over etching effect, being usually formed groove 140 can extend partially into
First semiconductor layer 110 is internal.
In the present embodiment, groove 140 can use BCl3、Cl2Or the gas such as Ar is in plasmoid
Under, selective etch quantum well layer 120 and the second semiconductor layer 130, until exposing the first semiconductor layer
110, thus form described Mesa platform and groove 140.
In the present embodiment, generally by above-mentioned selective etch effect, the described Mesa platform of formation has
The sidewall tilted, the i.e. base angle of sidewall are acute angle and drift angle is that obtuse angle is (it should be noted that be in Fig. 3
Convenient, base angle and the drift angle of display sidewall are illustrated as right angle).This sloped sidewall utilizes follow-up insulation
The filling of layer (refer to Fig. 6 and Fig. 7 and the content of their correspondences).
Fig. 4 with Fig. 5 is shown that mutually isostructural different views, and wherein, Fig. 4 is top view, Fig. 5
For sectional view.
In conjunction with reference to Fig. 4 and Fig. 5, the first semiconductor layer 110 bottom groove 140 deposits the first electricity
Pole 150, has gap (mark) between the first electrode 150 and described Mesa platform.
From fig. 4 it can be seen that define the first electrode 150 in groove 140, but the first electrode 150 with
Whole groove 140 sidewall (groove 140 sidewall is quantum well layer 120 and the second semiconductor layer 130) it
Between there is described gap.The existence in described gap ensure that the first electrode 150 and quantum well layer 120 and the
Two semiconductor layers 130 keep insulation between the two.(please subsequently through filling insulating barrier in described gap
With reference to Fig. 6 and Fig. 7 and the content of their correspondences), to be further ensured that above-mentioned dielectric relationship, and protect the
One electrode 150.
In the present embodiment, as previously described, owing to groove 140 is in the vertical view shape being similar to a spoon
Shape, therefore the first electrode 150 is also in being similar to the plan view shape of a spoon, i.e. both plan view shapes
Similar.But the plan view shape being smaller in size than groove 140 of the plan view shape of the first electrode 150, thus protect
Demonstrate,prove described gap and be present in the whole periphery of the first electrode 150 top plan view.
In the present embodiment, the width in described gap can be more than 1 μm.The width in described gap is first
Electrode 150 arrives the distance between described Mesa platform, owing to described Mesa mesa sidewalls tilts, therefore
The width of described gap diverse location may be different.But, when the width in described gap can be 1 μm with
On ensure that follow-up insulating barrier be easier to fill, and fill after insulation effect preferable.But, other
In various different concrete chip designs, various factors can be considered by the size in described gap,
Select corresponding size range.
It should be noted that Fig. 5 also show the thickness degree of depth less than groove 140 of the first electrode 150.
This set contributes to follow-up insulating barrier and preferably protects the first electrode 150, and prevents insulating barrier and first
The gross thickness of electrode 150 is too big and affects the size of whole bankruptcy LED chip.
In the present embodiment, evaporation coating method (such as chemical vapor coating method) can be used to form the first electricity
Pole 150, and use methods such as using negative glue stripping (lift-off) to prepare the concrete big of the first electrode 150
Little and shape, to ensure that the first electrode 150 is preferably formed in groove 140, and ensure described between
Gap is uniformly around at the first electrode 150 periphery.
In the present embodiment, the material of the first electrode 150 can be Cr, Ni, Ti, Pt, Ag, Al, Rh,
One or more in Au and Sn.Concrete, the first electrode 150 can be Cr, Ni, Ti, Pt,
The single layer structure of Ag, Al, Rh, Au, Sn, or be the compound laminating structure based on them.
In the present embodiment, the first electrode 150 can be 200nm～4 μm.Concrete thickness can be according to whole
The structure of body and performance requirement are arranged.
Fig. 6 with Fig. 7 is shown that mutually isostructural different views, and wherein, Fig. 6 is top view, Fig. 7
For sectional view.
In conjunction with reference Fig. 6 and Fig. 7, between formation insulating barrier 160 covers described in the first electrode 150 filling completely
Gap.
Fig. 6 shows the described gap and the first electrode 150 that groove 140 remains by insulating barrier 160
All it is completely covered.Being previously noted described Mesa platform and have the sidewall of inclination, this sloped sidewall is conducive to
Insulating barrier 160 is complete by filling complete for described gap uniformity, so that the first electrode 150 and SQW
Layer 120 and the second semiconductor layer 130 keep good insulating effect between the two.
Fig. 7 demonstrates, described gap is filled by insulating barrier 160, and insulating barrier 160 is higher than original ditch
The degree of depth of groove 140, i.e. insulating barrier 160 cover the first electrode 150 and fill full described gap.
In the present embodiment, the process forming insulating barrier 160 can be, first uses depositing operation to form insulation
Material layer, described insulation material layer is uniform and progressively cover on each face, may then pass through and adopts
Remove the described insulation material layer of other position with anisotropic etching method, remain described insulation material layer
It is left corresponding insulating barrier 160.
In the present embodiment, insulating barrier 160 can be single layer structure or multiple structure.
In the present embodiment, in the above-mentioned single layer structure of insulating barrier 160 or multiple structure, the material used
Material can be SiO2、SiN、SiON、Al2O3And TiO2In one or more.
In the present embodiment, if insulating barrier 160 is multiple structure, then can be by selecting different reflectivity
Layers of material so that this multiple structure formed can become distributing Bragg mirror
(distributed bragg reflectors, DBR).Insulating barrier 160 now can preferably reflect light.
When using this multiple structure, each layer of insulating barrier 160 suitably selects the material that reflectance is higher to make,
And SiO2、SiN、SiON、Al2O3、TiO2Or the laminating structure based on them meets corresponding making
Requirement.
In the present embodiment, although insulating barrier 160 covers on first each surface of electrode 150 for overall structure,
But the part edge of insulating barrier 160 covers at least part of described Mesa platform upper surface, with more preferably the most simultaneously
Realize insulation barrier effect.
It should be noted that Fig. 7 show insulating barrier 160 upper surface smooth be the optimization of a kind of figure, actual
In structure, owing to insulating barrier is that (each surface includes side and the bottom surface in described gap, institute along each surface
State the upper surface of the first electrode 150) uniform deposition, therefore, insulating barrier 160 is frequently not flat
Smooth.It is therefore to be understood that Fig. 7 is only a kind of Utopian structural representation.
With reference to Fig. 8, described Mesa platform and insulating barrier 160 form electrode extension layer 170.
In the present embodiment, the material of electrode extension layer 170 can be transparent metal oxide, such as ITO,
AZO or ZnO, it is also possible to for metal, such as Ag, Al, Rh, Ru, TiW, Ti, Pt, Ni, Cr,
Au, S or combinations thereof, it is also possible to for aforementioned transparent metal-oxide and the combination of metal.
In the present embodiment, the formation process of electrode extension layer 170 can be divided into multiple step, such as 1～5
Individual step.When electrode extension layer 170 makes nesa coating, it is possible to better ensure that follow-up LED core
The luminescence of sheet.
With reference to Fig. 9, electrode extension layer 170 connects electrically-conductive backing plate 180 as the second electrode.
In the present embodiment, it is possible to use electrode extension layer 170 is connected to conductive base by bonding or other technology
On plate 180, electrically-conductive backing plate 180 can be the conductive material of metallic plate etc, and electrically-conductive backing plate 180 can
Think conductive and heat-conductive type substrate.After electrode extension layer 170 connects electrically-conductive backing plate 180, electrically-conductive backing plate 180
To turn on electrode extension layer 170, the most now electrically-conductive backing plate 180 can be as the P of flip LED chips
Electrode tip.
In the present embodiment, electrically-conductive backing plate 180 can be specially conductive and heat-conductive type substrate, can be silicon, gold
Belong to the conductive material of plate etc.
With reference to Figure 10, substrate 100 is peeled off with described extension lamination, to expose the first semiconductor layer 110
Exiting surface.
In the present embodiment, substrate 100 and extension lamination are peeled off and may include that employing chemical etching, machine
Substrate 100 is peeled off, to expose the first semiconductor layer 110 by tool segmentation or laser means with extension lamination
Exiting surface.Wherein, the face exposed after the first semiconductor layer 110 separates with substrate 100 is exiting surface.
With reference to Figure 11, after the exiting surface exposing the first semiconductor layer 110, and at etching the first quasiconductor
Before the exiting surface of layer 110, it is cleaned processing to the exiting surface of the first semiconductor layer 110, and carries out table
The coarse process in face (Surface roughing).
Cleaning processes the method that can use dry etching, wet etching or a combination thereof, to the first semiconductor layer 110 table
Face is cleaned.
Rough surface processes, and can make and have the little matte surface finish of protruding 111.And it is thick on surface
After rough process, then exiting surface is cleaned.Described rough surface processing intent is to destroy light at exiting surface
With the total reflection of Air Interface, increase the outgoing efficiency of light, improve the light extraction efficiency of chip.Improve and
The method of light efficiency is that LED chip is made reverse pyramid or taper etc..When being fabricated to inverted pyramid
During (Truncated Inverted Pyramid, TIP) shape (side is with a vertical certain angle),
Four sides of chip are no longer parallel to each other, so that be mapped to the light of chip sides, and anti-through side
It is mapped to end face, with the angle outgoing less than the cirtical angle of total reflection；Meanwhile, it is mapped to end face face more than total reflection
The light at angle, boundary from side outgoing, thus can substantially increase the light extraction efficiency of chip.Therefore, Tu11Zhong
It is processed into little protruding the 111 of inverted pyramid shape by coarse for chip surface.
It should be noted that described cleaning processes and rough surface processes and can improve flip LED chips
Performance, such as, improve the performances such as light extraction efficiency.But in other embodiments of the invention, can select right
The exiting surface of the first semiconductor layer 110 is cleaned a kind of process processed and rough surface processes, it is possible to
Need not be cleaned processing and rough surface process.
With reference to Figure 12, etch the exiting surface of the first semiconductor layer 110, until exposing at least part of first electricity
Pole 150.
In the present embodiment, it is possible to use mask (not shown) carries out selectivity to the first semiconductor layer 110
Etching, until exposing the first electrode 150.
After exposing at least part of first electrode 150, the first electrode 150 exposed forms the 3rd
Electrode.And form the 3rd electrode 190 on the first electrode 150 surface exposed.
The forming process of the 3rd electrode 190 can be: carries out new electrode material in the first electrode 150 position
Material evaporation, to form the 3rd electrode 190 on the first electrode 150.
The material of the 3rd electrode be the one in Cr, Ni, Ti, Pt, Ag, Al, Rh, Au and Sn or
Multiple.The material of the i.e. the 3rd electrode 190 can also be Cr, Ni, Ti, Pt, Ag, Al, Rh, Au,
Sn or the laminating structure based on them.
After forming the 3rd electrode 190, routing method can be used to be welded by the 3rd electrode 190 and to lead accordingly
Line.
It should be noted that in other embodiments of the present invention, after forming the 3rd electrode and being formed, also
One layer of passivating film can be optionally made in LED chip light extraction face.
It should be noted that in other embodiments of the present invention, it is also possible to it is not necessarily forming the 3rd electrode, and
Directly after exposing the first electrode, follow-up encapsulation process use routing method by corresponding for the first electrode welding
Wire.
Through above-mentioned steps, the present embodiment is manufactured that flip LED chips.In described flip LED chips,
Utilize electrically-conductive backing plate 180 as chip P electrode (owing to electrically-conductive backing plate 180 contacts the second semiconductor layer,
And in the present embodiment, the second semiconductor layer is P-type nitride semiconductor, it is specifically as follows P-GaN half
Conductor layer, therefore electrically-conductive backing plate 180 as chip as P electrode), exiting surface design N electrode (institute
State N electrode that is first electrode 150) mode, it is achieved P electrode, N electrode are located away from LED chip
Two sides.
In the present embodiment, N-GaN part (the i.e. first semiconductor layer 110) of flip LED chips passes through
Metal (the i.e. first electrode 150) contacts, and P-GaN part (the i.e. second semiconductor layer 130) is by having
The metal of high reflectance or conducting metal oxide lamination (i.e. electrode extension layer 170) form contact, upside-down mounting
The metal (the i.e. first electrode 150) of P-GaN and the N-GaN contact of LED chip is by insulating barrier 160
Isolation, thus form complete structure.Wherein, electrode extension layer 170 can cover whole flip LED core
Sheet surface, and engage with electrically-conductive backing plate 180.
In the present embodiment, flip LED chips is by by N electrode (the i.e. first electrode 150) and thereon
Insulating barrier 160 all covers high reflecting material (i.e. electrode extension layer 170 uses high reflecting material to make)
Design, increases the reflectance of flip LED chips, reduces the flip LED chips absorption loss water to light.
Wherein, insulating barrier 160 can pass through monolayer non-conducting material or have high reflectance, non-conductive multilamellar
Material realizes.The figure of insulating barrier 160 can appropriate design according to demand, in addition to reaching the effect of insulation,
Can be with flexible design to optimize current expansion and the reflectance of chip.
In the present embodiment, flip LED chips and leading that P-GaN (the i.e. second semiconductor layer 130) contacts
Electric layer (i.e. electrode extension layer 170) can use high reflecting material, and is covered in whole flip LED core
Sheet surface, to maximize reflective surface area.Flip LED chips can pass through N electrode (the i.e. first electrode
150) flexible design, to optimize current expansion distribution, improves luminous efficiency.
In the manufacture method of the flip LED chips that the present embodiment is provided, by will lead LED chip
Electric substrate 180 is as one of them electrode (the i.e. second electrode), and another electrode (the i.e. first electrode 150)
At exiting surface, (the first semiconductor layer 110 belongs to phase with electrically-conductive backing plate 180 in whole LED chip in employing
To position, between them, include multiple quantum well layer the 120, second semiconductor layer 130 and electrode extension layer
The structures such as 170) method of routing, thus by upper to LED chip of the two of LED chip electrode separation
Lower two sides, improves the ease of the encapsulation of LED chip.
Owing to electrode extension layer 170 can use high reflecting metal layer, and flood covers whole LED chip,
Improving reflective surface area substantially, the specular removal for LED chip provides safeguard.
Owing to the edition type design of groove 140 and the first electrode 150 is flexible, can be by rational first electricity
Pole 150 is distributed, and optimizes the current expansion distribution situation of LED chip.Due to groove 140 and the first electrode
150 can design neatly, and therefore, its their shape and position can be entered according to actual needs
Row sum-equal matrix.Therefore, being designed by rational chip, described flip LED chips can also have technique letter
Single and that unit are light efficiency is high advantage.Owing to edition type design is flexible, what therefore the present embodiment was provided falls
Dress LED chip also has outstanding ductility, can realize LED by simply increasing base unit
The conversion of chip operating voltage.
Compared to P, N at the flip-chip design of homonymy, the flip LED chips that the present embodiment is provided
In, electrode extension layer 170 is bigger with the contact area of electrically-conductive backing plate 180, and heat-sinking capability is higher.Therefore,
Described flip LED chips keeps and improves the outstanding current expansion of conventional flip chip and heat-sinking capability,
And there is the advantage more easily welding encapsulation simultaneously.
Another embodiment of the present invention additionally provides a kind of flip LED chips, and described flip LED chips is permissible
The manufacture method using previous embodiment is formed, and therefore, structure and the character of described flip LED chips can
With with reference to previous embodiment corresponding contents.
Concrete, refer to Figure 12, described flip LED chips includes electrically-conductive backing plate 180, is positioned at conduction
Electrode extension layer 170 under substrate 180, the Mesa platform being positioned under electrode extension layer 170, Mesa
Platform includes the second semiconductor layer 130, quantum well layer 120 and at least part of first semiconductor layer 110.The
Two semiconductor layers 130, quantum well layer 120 are together with the first semiconductor layer 110 stacked above one another.Mesa
There is in platform groove 140.Groove 140 (refer to Fig. 2 and Fig. 3) bottom has the first electrode 150.
Between first electrode 150 and electrode extension layer 170 and Mesa platform, there is insulating barrier 160.
In other words, in described flip LED chips, described Mesa platform include the first semiconductor layer 110,
Quantum well layer 120 and the second semiconductor layer 130, the described Mesa in each described chip unit region has
Groove 140 (refer to Fig. 2 and Fig. 3), has the first electrode 150, the first electrode bottom groove 140
There is between 150 and described Mesa platform gap (not marking, refer to Fig. 5).Described flip LED
Chip also includes insulating barrier 160, electrode extension layer 170 and electrically-conductive backing plate 180.Insulating barrier 160 covers
One electrode 150 and fill described gap, electrode extension layer 170 covers described Mesa platform and insulating barrier
160, electrically-conductive backing plate 180 covers electrode extension layer 170.
In the present embodiment, also include the 3rd electrode 190 being positioned at the first electrode 150 surface.
In the present embodiment, the exiting surface of the first semiconductor layer 110 is rough surface, and rough surface has little
Protruding 111.
In the present embodiment, the first semiconductor layer 110 is n type nitride semiconductor layer and the second semiconductor layer
130 is P-type nitride semiconductor.
It should be noted that in other embodiments of the invention, the first semiconductor layer 110 can also be P
Type nitride semiconductor layer, now the second semiconductor layer 130 is n type nitride semiconductor layer.
In the present embodiment, insulating barrier 160 can be single layer structure or multiple structure.Insulating barrier 160
Material can be SiO2、SiN、SiON、Al2O3And TiO2In one or more.
In the flip LED chips that the present embodiment is provided, utilize electrode extension layer 170 and electrically-conductive backing plate 180
Contact, design is simple, and lighting area loss is less, electrode extension layer 170 and electrically-conductive backing plate 180
Contact makes high reflection mirror area maximize the most simultaneously, and the light efficiency lifting to LED chip has positive role,
Meanwhile, described LED chip also has an advantage of easily encapsulation, and keeps the outstanding electricity of conventional flip chip
Stream extension and heat-sinking capability.
Another embodiment of the present invention provides the manufacture method of another flip LED chips, incorporated by reference to reference
Figure 13 to Figure 20.
With reference to Figure 13, it is provided that substrate 200.Deposit extension lamination (mark) on the substrate 200, described
Extension lamination includes the first semiconductor layer 210, quantum well layer 220 and the second semiconductor layer 230.
In the present embodiment, substrate 200 can be Sapphire Substrate.In other embodiments of the invention,
According to technique needs, it is also possible to select other be applicable to LED chip manufacture substrate, such as with spinelle,
The substrate that SiC, ZnS, ZnO or GaAs etc. manufacture.
With continued reference to Figure 13, deposit extension lamination (mark), described extension lamination bag on the substrate 200
Include the first semiconductor layer 210, quantum well layer 220 and the second semiconductor layer 230.
In the present embodiment, the first semiconductor layer 210 is n type nitride semiconductor layer and the second semiconductor layer
230 is P-type nitride semiconductor.
Concrete, the first semiconductor layer 210 can be the GaN film of n-type doping.The N-type of GaN film
Doping content can be 5E17cm-3～1E19cm-3。
Concrete, quantum well layer 220 generally can be expressed as again MQW active layer, also referred to as MQW
Layer.Quantum well layer 220 can be by generating the low energy gap width nitride film (not shown) containing In and width
The nitride film (not shown) of energy gap, and allow the nitride film of low energy gap width and broad stopband width
Nitride film is alternately arranged, forms quantum well layer 220.Wherein, the low energy gap width nitride film containing In
Can be InGaN film, forming temperature can be 700 DEG C～900 DEG C.The nitride film of broad stopband width can
Thinking GaN film, forming temperature can be 700 DEG C～900 DEG C.
Concrete, the second semiconductor layer 230 can be the GaN film of p-type doping.Second semiconductor layer 230
It is grown on quantum well layer 220.Can be by semiconductor layer be doped, to form the second quasiconductor
Layer 230.And it is possible to improve hole concentration by doping, improve the electric conductivity of the second semiconductor layer 230,
Thus obtain high-quality second semiconductor layer 230, improve LED chip structure quality.
It should be noted that in other embodiments of the invention, the first semiconductor layer 210 can also be P
Type nitride semiconductor layer, now the second semiconductor layer 230 is n type nitride semiconductor layer.Further,
When the first semiconductor layer 210 is also P-type nitride semiconductor and the second semiconductor layer 230 is N-type nitrogen
During compound semiconductor layer, substrate 200 can select the material system being suitable to the first semiconductor layer 210 growth
Make.
Figure 14 with Figure 15 is shown that mutually isostructural different views, and wherein, Figure 14 is top view, figure
15 is sectional view.
In conjunction with reference to Figure 14 and Figure 15, etching described extension lamination, leading until forming bottom-exposed the first half
The groove 240 of body layer 210, remains described extension lamination and is left Mesa platform (mark).
Figure 14 shows groove 240 and the plan structure of described Mesa platform.Described Mesa platform is institute
Stating extension lamination to be etched and form the remainder after groove 240, groove 240 bottom-exposed goes out the simultaneously
Semi-conductor layer 210.
In the present embodiment, groove 240 is in being similar to the plan view shape of a spoon, and described shape has one
Spoon head part that individual area is bigger and the kettleholder part of a uniform elongate.The benefit of this shape is: after
The continuous electrode formed also can be this spoon shape, and so, described electrode just can only utilize spoon head part
Reduce connection area for electrically connecting with follow-up electrode or contact conductor, and utilize kettleholder partially ON
Electric current and increase described electrode electric current transmission scope.
Figure 15 shows that groove 240 runs through quantum well layer 220 and the second semiconductor layer 230, but does not runs through
First semiconductor layer 210.Groove 240 needs not extend to the first semiconductor layer 210 inside and only needs to expose
First semiconductor layer 210 surface, but due to over etching effect, being usually formed groove 240 can part extend
Internal to the first semiconductor layer 210.
In the present embodiment, groove 240 can use BCl3、Cl2Or the gas such as Ar is in plasmoid
Under, selective etch quantum well layer 220 and the second semiconductor layer 230, until exposing the first semiconductor layer
210, thus form described Mesa platform and groove 240.
In the present embodiment, generally by above-mentioned selective etch effect, the described Mesa platform of formation has
The sidewall tilted, the i.e. base angle of sidewall are acute angle and drift angle is that obtuse angle is (it should be noted that be in Figure 15
Convenient, base angle and the drift angle of display sidewall are illustrated as right angle).This sloped sidewall utilizes follow-up insulation
The filling of layer.
Figure 16 with Figure 17 is shown that mutually isostructural different views, and wherein, Figure 16 is top view, figure
17 is sectional view.
In conjunction with reference to Figure 16 and Figure 17, the first semiconductor layer 210 bottom groove 240 deposits first
Electrode 250, has gap (mark) between the first electrode 250 and described Mesa platform.
As seen from Figure 16, in groove 240, define the first electrode 250, but the first electrode 250
With whole groove 240 sidewall (groove 240 sidewall is quantum well layer 220 and the second semiconductor layer 230)
Between there is described gap.The existence in described gap ensure that the first electrode 250 and quantum well layer 220 and
Second semiconductor layer 230 keeps insulation between the two.(please subsequently through filling insulating barrier in described gap
With reference to Figure 18 and Figure 19 and the content of their correspondences), to be further ensured that above-mentioned dielectric relationship, and protect
First electrode 250.
In the present embodiment, as previously described, owing to groove 240 is in the vertical view shape being similar to a spoon
Shape, therefore the first electrode 250 is also in being similar to the plan view shape of a spoon, i.e. both plan view shapes
Similar.But the plan view shape being smaller in size than groove 240 of the plan view shape of the first electrode 250, thus protect
Demonstrate,prove described gap and be present in the whole periphery of the first electrode 250 top plan view.
In the present embodiment, the width in described gap can be more than 1 μm.The width in described gap is first
Electrode 250 arrives the distance between described Mesa platform, owing to described Mesa mesa sidewalls tilts, therefore
The width of described gap diverse location may be different.But, when the width in described gap can be 1 μm with
On ensure that follow-up insulating barrier be easier to fill, and fill after insulation effect preferable.But, other
In various different concrete chip designs, various factors can be considered by the size in described gap,
Select corresponding size range.
It should be noted that Figure 17 also show the thickness degree of depth less than groove 240 of the first electrode 250.
This set contributes to follow-up insulating barrier and preferably protects the first electrode 250, and prevents insulating barrier and first
The gross thickness of electrode 250 is too big and affects the size of whole bankruptcy LED chip.
In the present embodiment, the methods such as negative glue stripping can be used to prepare the first electrode 250, to ensure the first electricity
Pole 250 is preferably formed in groove 240, and ensures that described gap uniformity is distributed.
In the present embodiment, the material of the first electrode 250 can be Cr, Ni, Ti, Pt, Ag, Al, Rh,
One or more in Au and Sn.Concrete, the first electrode 250 can be Cr, Ni, Ti, Pt,
The single layer structure of Ag, Al, Rh, Au, Sn, or be the compound laminating structure based on them.
In the present embodiment, the first electrode 250 can be 200nm～4 μm.Concrete thickness can be according to whole
The structure of body and performance requirement are arranged.
Figure 18 with Figure 19 is shown that mutually isostructural different views, and wherein, Figure 18 is top view, figure
19 is sectional view.
In conjunction with reference to Figure 18 and Figure 19, form insulating barrier 260 and cover the first electrode 250 and fill full described
Gap.Further, the present embodiment concurrently forms the collets covering described Mesa platform surface, collets
261 are specifically distributed on the second semiconductor layer 230.
In the present embodiment, collets 261 are in a discrete distribution, insulating barrier 260 and collets 261 expose to
Mesa platform surface described in small part (the i.e. second semiconductor layer 230 surface), thus ensure subsequent electrode
Extension layer can cover the described Mesa platform surface exposed by described insulating barrier and described collets, and
Follow-up described electrode extension layer covers insulating barrier 260 and collets 261 simultaneously.
In the present embodiment, the plan view shape of collets 261 is rounded, in other embodiments, and collets
The plan view shape of 261 can also be other shape.The distribution mode of collets 261 can also be alternate manner,
Specifically can need to arrange according to LED chip.
Figure 18 shows the described gap and the first electrode 250 that groove 240 remains by insulating barrier 260
All it is completely covered.Being previously noted described Mesa platform and have the sidewall of inclination, this sloped sidewall is conducive to
Insulating barrier 260 is complete by filling complete for described gap uniformity, so that the first electrode 250 and SQW
Layer 220 and the second semiconductor layer 230 keep good insulating effect between the two.
Figure 19 demonstrates, described gap is filled by insulating barrier 260, and insulating barrier 260 is higher than original ditch
The degree of depth of groove 240, i.e. insulating barrier 260 cover the first electrode 250 and fill full described gap.
In the present embodiment, same technique can be used to form insulating barrier 260 and collets 261, thus save
Processing step, cost-effective.Now, the process forming insulating barrier 260 and collets 261 can be,
First using depositing operation to form insulation material layer, insulation material layer is uniform and progressively cover on each face
, may then pass through the insulation material layer using anisotropic etching method to remove other position, residue
Insulation material layer is left corresponding insulating barrier 260 and collets 261.
It should be noted that in other embodiments, insulating barrier 260 and collets 261 can also be distinguished
It is fabricated separately.
In the present embodiment, insulating barrier 260 and collets 261 can be single layer structure or multiple structure.
In the present embodiment, in insulating barrier 260 and the above-mentioned single layer structure of collets 261 or multiple structure,
The material used can be SiO2、SiN、SiON、Al2O3And TiO2In one or more.
In the present embodiment, if insulating barrier 260 and collets 261 are multiple structure, then can be by choosing
Select the layers of material of different reflectivity so that this multiple structure formed can become distributing Prague
Reflecting mirror.Insulating barrier 260 now can preferably reflect light.When using this multiple structure, absolutely
Each layer of edge layer 260 and collets 261 suitably selects the material that reflectance is higher to make, and SiO2、SiN、
SiON、Al2O3、TiO2Or laminating structure based on them meets and makes requirement accordingly.
In the present embodiment, although all overall structures of insulating barrier 260 cover the first electrode 250 each
Surface, but insulating barrier 260 covers at least part of described Mesa platform upper surface the most simultaneously, with the most real
Existing insulation barrier effect.
In the present embodiment, arranging of collets 261 can cover described Mesa platform surface to realize reducing
Electric current between second semiconductor layer 230 and the electrode extension layer being subsequently formed.Specifically, collets
261 have the most two-part effect: first, due to the obstructed electric current of collets 261, therefore, it can lead to
That crosses collets 261 arranges control CURRENT DISTRIBUTION, and the CURRENT DISTRIBUTION making LED chip is more reasonable；Second,
Due to the existence of collets 261, the reflectance within LED chip can become more preferable, particularly, absolutely
Edge block 261 can coordinate with follow-up metal level (follow-up electrode extension layer uses metal level to be formed)
Form full-shape reflecting mirror, thus increase the average reflectance of whole electrode extension layer plane.
It should be noted that Figure 19 show insulating barrier 260 and collets 261 upper surface smooth be a kind of figure
Optimization, in practical structures, owing to above-mentioned insulation material layer is that (each surface includes described along each surface
The side in gap and bottom surface, the upper surface of described first electrode 250) uniform deposition, therefore,
Insulating barrier 260 is frequently not smooth.It is therefore to be understood that Figure 19 is only a kind of Utopian structural representation
Figure.
With reference to Figure 20, described Mesa platform and insulating barrier 260 and collets 261 form electrode
Extension layer 270.
In the present embodiment, the material of electrode extension layer 270 can be metal, such as Ag, Al, Rh, Ru,
TiW, Ti, Pt, Ni, Cr, Au, S or combinations thereof.In other embodiments, electrode extension layer
Material can also be transparent metal oxide, such as ITO, AZO or ZnO, it is also possible to for aforementioned
Bright metal-oxide and the combination of metal.
In the present embodiment, the formation process of electrode extension layer 270 can be divided into multiple step, such as 1～5
Individual step.When electrode extension layer 270 makes nesa coating, it is possible to better ensure that follow-up LED core
The luminescence of sheet.
With continued reference to Figure 20, electrode extension layer 270 connects electrically-conductive backing plate 280 as the second electrode (not
Mark).
In the present embodiment, it is possible to use bonding or other technology will be connected to, on electrically-conductive backing plate 280, lead
Electric substrate 280 can be the conductive material of metallic plate etc, and electrically-conductive backing plate 280 can be conductive and heat-conductive type
Substrate.After electrode extension layer 270 connects electrically-conductive backing plate 280, electrically-conductive backing plate 280 will be with electrode extension layer
270 conductings, the most now electrically-conductive backing plate 280 can be as the P electrode end of flip LED chips.
With continued reference to Figure 20, substrate 200 is peeled off with described extension lamination, to expose the first semiconductor layer
The exiting surface of 210.
In the present embodiment, substrate 200 is peeled off with extension lamination and includes: use chemical etching, machinery point
Cut or substrate 200 is peeled off with extension lamination by laser means, expose the first semiconductor layer 210.Wherein,
The face that first semiconductor layer 210 exposes after separating with substrate 200 is exiting surface.
With continued reference to Figure 20, after the exiting surface exposing the first semiconductor layer 210, and in etching the first half
Before the exiting surface of conductor layer 210, it is cleaned processing to the exiting surface of the first semiconductor layer 210, goes forward side by side
Row rough surface processes.
Described cleaning processes the method that can use dry etching, wet etching or a combination thereof, to the first semiconductor layer 210
Surface is cleaned.
Described rough surface processes to make has the little matte surface finish of protruding 211.And on surface
After coarse process, then exiting surface is cleaned.Described rough surface processing intent is to destroy light to go out light
Face and the total reflection of Air Interface, increase the outgoing efficiency of light, improve the light extraction efficiency of chip.Improve
The method of light extraction efficiency is that LED chip is made reverse pyramid or taper etc..When being fabricated to inverted pyramid
During shape (side is with a vertical certain angle), four sides of chip are no longer parallel to each other,
So that be mapped to the light of chip sides, reflex to end face, with less than the cirtical angle of total reflection through side
Angle outgoing；Meanwhile, being mapped to end face can be from side outgoing more than the light of the cirtical angle of total reflection, thus greatly
Improve greatly the light extraction efficiency of chip.Therefore, Figure 20 is processed into reverse pyramid by coarse for chip surface
Little protruding the 211 of shape.
It should be noted that described cleaning processes and rough surface processes and can improve flip LED chips
Performance, such as, improve the performances such as light extraction efficiency.But in other embodiments of the invention, can select right
The exiting surface of the first semiconductor layer 210 is cleaned a kind of process processed and rough surface processes, it is possible to
Need not be cleaned processing and rough surface process.
With continued reference to Figure 20, etch the exiting surface of the first semiconductor layer 210, until exposing at least part of
One electrode 250.
In the present embodiment, it is possible to use mask (not shown) carries out selectivity to the first semiconductor layer 210
Etching, until exposing the first electrode 250.
After exposing at least part of first electrode 250, the first electrode 250 exposed forms the 3rd
Electrode.And form the 3rd electrode 290 on the first electrode 250 surface exposed.
The forming process of the 3rd electrode 290 can be: carries out new electrode material in the first electrode 250 position
Material evaporation, to form the 3rd electrode 290 on the first electrode 250.
The material of the 3rd electrode be the one in Cr, Ni, Ti, Pt, Ag, Al, Rh, Au and Sn or
Multiple.The material of the i.e. the 3rd electrode 290 can be Cr, Ni, Ti, Pt, Ag, Al, Rh, Au, Sn
Or the laminating structure based on them.
After forming the 3rd electrode 290, routing method can be used to be welded by the 3rd electrode 290 and to lead accordingly
Line.
It should be noted that in other embodiments of the present invention, after forming the 3rd electrode and being formed, also
One layer of passivating film can be optionally made in LED chip light extraction face.
It should be noted that in other embodiments of the present invention, it is also possible to it is not necessarily forming the 3rd electrode, and
Directly after exposing the first electrode, follow-up encapsulation process use routing method by corresponding for the first electrode welding
Wire.
Through above-mentioned steps, the present embodiment is manufactured that flip LED chips.And the present embodiment is provided
Flip LED chips manufacture method in, by by LED chip using electrically-conductive backing plate 280 as wherein
One electrode (the i.e. second electrode), and another electrode (the i.e. first electrode 250) uses at exiting surface routing
Method, thus by the upper and lower surface of the two of LED chip electrode separation to LED chip.Therefore, institute
State flip LED chips and can keep the outstanding current expansion of conventional flip chip and heat-sinking capability, and simultaneously
There is the advantage more easily welding encapsulation.
Additionally, due in the present embodiment, groove 240 can design neatly, therefore, its shape
Can be adjusted according to actual needs with position.Therefore, designed by rational chip, described fall
Dress LED chip can also have the advantage that technique is simple and unit are light efficiency is high.
Another embodiment of the present invention additionally provides a kind of flip LED chips, and described flip LED chips is permissible
The manufacture method using previous embodiment is formed, and therefore, structure and the character of described flip LED chips can
With with reference to previous embodiment corresponding contents.
Concrete, with reference to Figure 20, described flip LED chips includes electrically-conductive backing plate 280, is positioned at conductive base
Electrode extension layer 270 on plate 280, the Mesa platform being positioned on electrode extension layer 270, Mesa platform
Including the second semiconductor layer 230, quantum well layer 220 and at least part of first semiconductor layer 210.Mesa
There is in platform groove 240.There is bottom groove 240 first electrode 250.First electrode 250 and electrode
Between extension layer 270 and Mesa platform, there are insulating barrier 260 and collets 261.
In other words, in described flip LED chips, described Mesa platform include the first semiconductor layer 210,
Quantum well layer 220 and the second semiconductor layer 230, the described Mesa in each described chip unit region has
Groove 240 (refer to Fig. 2 and Fig. 3), has the first electrode 250, the first electrode bottom groove 240
There is between 250 and described Mesa platform gap (not marking, refer to Fig. 5).Described flip LED
Chip also includes insulating barrier 260, collets 261, electrode extension layer 270 and electrically-conductive backing plate 280.Insulation
Layer 260 covers described first electrode 250 and fills described gap, and electrode extension layer 270 covers described Mesa
Platform, insulating barrier 260 and collets 261, electrically-conductive backing plate 280 covers electrode extension layer 270.
In the present embodiment, electrode extension layer 270 covers the institute exposed by insulating barrier 260 and collets 261
State Mesa platform surface, and electrode extension layer 270 covers insulating barrier 260 and collets 261.
In the present embodiment, also include the 3rd electrode 290 being positioned at the first electrode 250 surface.
In the present embodiment, the exiting surface of the first semiconductor layer 210 is rough surface, and rough surface has little
Protruding 211.
In the present embodiment, the first semiconductor layer 210 is n type nitride semiconductor layer and the second semiconductor layer
230 is P-type nitride semiconductor.
It should be noted that in other embodiments of the invention, the first semiconductor layer 210 can also be P
Type nitride semiconductor layer, now the second semiconductor layer 230 is n type nitride semiconductor layer.
In the present embodiment, insulating barrier 260 and collets 261 can be single layer structure or multiple structure.
The material of insulating barrier 260 and collets 261 can be SiO2、SiN、SiON、Al2O3And TiO2In
One or more.
Flip LED chips that the present embodiment is provided keeps the outstanding current expansion of conventional flip chip and dissipates
Heat energy power, and simultaneously have the advantage more easily welding encapsulation, the most also has that technique is simple and unit
The advantage that area light efficiency is high.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (16)
1. the manufacture method of a flip LED chips, it is characterised in that including:
Substrate is provided；
Depositing extension lamination over the substrate, described extension lamination includes the first semiconductor layer, SQW
Layer and the second semiconductor layer, described quantum well layer is positioned at described first semiconductor layer and described second quasiconductor
Between Ceng；
Etch described extension lamination, until forming the groove of the first semiconductor layer described in bottom-exposed, residue
Described extension lamination is left Mesa platform；
Deposition of first electrode on the first semiconductor layer of described channel bottom, described first electrode is with described
Between Mesa platform, there is gap；
Form insulating barrier cover described first electrode and fill full described gap；
Described Mesa platform and described insulating barrier are formed electrode extension layer；
Described electrode extension layer connects electrically-conductive backing plate as the second electrode；
Described substrate is peeled off with described extension lamination, to expose the exiting surface of described first semiconductor layer；
Etch the exiting surface of described first semiconductor layer, until exposing the most described first electrode.
2. the manufacture method of flip LED chips as claimed in claim 1, it is characterised in that also include: shape
Becoming to cover the collets of described Mesa platform surface, described insulating barrier and described collets expose at least
Part described Mesa platform surface, described electrode extension layer covers by described insulating barrier and described insulation
The described Mesa platform surface that block exposes, and described electrode extension layer covers described insulating barrier and institute
State collets.
3. the manufacture method of flip LED chips as claimed in claim 1, it is characterised in that also include:
After exposing the exiting surface of described first semiconductor layer, and etching the exiting surface of described first semiconductor layer
Before, the exiting surface of described first semiconductor layer is cleaned process and at least the one of rough surface process
Plant and process.
4. the manufacture method of flip LED chips as claimed in claim 1, it is characterised in that by described substrate
Peel off with described extension lamination and include: use chemical method or laser means by described substrate with described
Extension lamination is peeled off.
5. the manufacture method of flip LED chips as claimed in claim 1, it is characterised in that also include:
After exposing the most described first electrode, described first electrode exposed forms the 3rd electrode.
6. the manufacture method of flip LED chips as claimed in claim 1, it is characterised in that described the first half
Conductor layer is n type nitride semiconductor layer and described second semiconductor layer is p-type nitride-based semiconductor
Layer, or described first semiconductor layer is P-type nitride semiconductor and described second semiconductor layer is
N type nitride semiconductor layer.
7. the manufacture method of flip LED chips as claimed in claim 3, it is characterised in that described first electricity
The material of pole is one or more in Cr, Ni, Ti, Pt, Ag, Al, Rh, Au and Sn；Institute
State the material of the 3rd electrode be the one in Cr, Ni, Ti, Pt, Ag, Al, Rh, Au and Sn or
Multiple.
8. the manufacture method of the flip LED chips as described in any one of claim 1 to 7, it is characterised in that
Described insulating barrier is single layer structure or multiple structure.
9. the manufacture method of flip LED chips as claimed in claim 8, it is characterised in that described insulating barrier
Material be SiO2、SiN、SiON、Al2O3And TiO2In one or more.
10. a flip LED chips, it is characterised in that including:
Mesa platform, described Mesa platform includes the first semiconductor layer, quantum well layer and the second quasiconductor
Layer, described quantum well layer between described first semiconductor layer and described second semiconductor layer, Mei Gesuo
The described Mesa stating chip unit region has groove；
Described channel bottom has the first electrode, between having between described first electrode and described Mesa platform
Gap；
Insulating barrier, described insulating barrier covers described first electrode and fills described gap；
Electrode extension layer, described electrode extension layer covers described Mesa platform and described insulating barrier；
Electrically-conductive backing plate, described electrically-conductive backing plate covers described electrode extension layer.
11. flip LED chips as claimed in claim 10, it is characterised in that it is characterized in that, also include
Cover the collets of described Mesa platform surface, described insulating barrier and described collets and expose at least portion
Dividing described Mesa platform surface, described electrode extension layer covers by described insulating barrier and described collets
The described Mesa platform surface exposed, and described electrode extension layer covers described insulating barrier and described
Collets.
12. flip LED chips as claimed in claim 10, it is characterised in that also include being positioned at described first
3rd electrode of electrode surface.
13. flip LED chips as claimed in claim 10, it is characterised in that described first semiconductor layer
Exiting surface is rough surface.
14. flip LED chips as claimed in claim 10, it is characterised in that described first semiconductor layer is
N type nitride semiconductor layer and described second semiconductor layer are P-type nitride semiconductor, or institute
State the first semiconductor layer and be P-type nitride semiconductor and described second semiconductor layer is N-type nitride
Semiconductor layer.
15. flip LED chips as described in any one of claim 10 to 14, it is characterised in that described insulation
Layer is single layer structure or multiple structure.
16. flip LED chips as claimed in claim 15, it is characterised in that the material of described insulating barrier is
SiO2、SiN、SiON、Al2O3And TiO2In one or more.
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| CN201510173371.4A CN106159045A (en) | 2015-04-13 | 2015-04-13 | Flip LED chips and manufacture method thereof |
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| CN201510173371.4A CN106159045A (en) | 2015-04-13 | 2015-04-13 | Flip LED chips and manufacture method thereof |
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Application publication date: 20161123 |