CN114628561A - LED chip with vertical structure and manufacturing method thereof - Google Patents
LED chip with vertical structure and manufacturing method thereof Download PDFInfo
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- CN114628561A CN114628561A CN202210442069.4A CN202210442069A CN114628561A CN 114628561 A CN114628561 A CN 114628561A CN 202210442069 A CN202210442069 A CN 202210442069A CN 114628561 A CN114628561 A CN 114628561A
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- 238000002161 passivation Methods 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000003475 lamination Methods 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 55
- 239000000758 substrate Substances 0.000 claims description 49
- 239000010931 gold Substances 0.000 claims description 15
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 13
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
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- 229910052737 gold Inorganic materials 0.000 claims description 12
- 229910052738 indium Inorganic materials 0.000 claims description 12
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 7
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- 239000010936 titanium Substances 0.000 claims description 7
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 6
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 claims description 6
- -1 indium aluminum tin oxide Chemical compound 0.000 claims description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 6
- VRIVJOXICYMTAG-IYEMJOQQSA-L iron(ii) gluconate Chemical compound [Fe+2].OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O.OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O VRIVJOXICYMTAG-IYEMJOQQSA-L 0.000 claims description 6
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- 229910052763 palladium Inorganic materials 0.000 claims description 6
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- 239000010948 rhodium Substances 0.000 claims description 6
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- SKRWFPLZQAAQSU-UHFFFAOYSA-N stibanylidynetin;hydrate Chemical compound O.[Sn].[Sb] SKRWFPLZQAAQSU-UHFFFAOYSA-N 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910001887 tin oxide Inorganic materials 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- 239000011701 zinc Substances 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- 230000010354 integration Effects 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 description 5
- 238000003892 spreading Methods 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 229910020286 SiOxNy Inorganic materials 0.000 description 2
- 229910003087 TiOx Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
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Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention provides a vertical-structure LED chip and a manufacturing method thereof, which realize the manufacturing mode of integrating a current expansion layer and a PAD metal layer together, namely forming an integrated metal layer, and replacing the current expansion layer with the integrated metal layer; in addition, when the PAD is manufactured, part of the surface of the integrated metal layer is exposed in an etching mode, and the exposed part plays the function of the PAD and can realize the electric connection with the outside. By the method, the process of independently manufacturing the PAD metal layer is omitted, and the cost is saved. Meanwhile, a passivation layer used for protecting the LED chip is arranged on the side wall of the epitaxial lamination layer, and based on the structure, the passivation layer and the insulating layer can be patterned in the same photoetching and etching process, so that the side wall passivation of the LED chip and the PAD manufacturing can be synchronously realized.
Description
Technical Field
The invention relates to the field of light emitting diodes, in particular to a vertical-structure LED chip and a manufacturing method thereof.
Background
With the development of the LED chip technology, the vertical structure chip, the flip chip and the like make great progress, and especially by adopting a through hole type design, the luminous efficiency of the vertical chip and the flip chip can be greatly improved.
The through hole type is that an N-type contact is led to the surface of a chip through electric connection by opening a hole on an epitaxial surface to an N-type semiconductor so as to bond or fix the crystal; referring to fig. 1 of the drawings, in order to turn on the second type semiconductor layer 33 during the manufacturing process, it is necessary to form an ohmic reflective layer 4 on the surface of the second type semiconductor layer 33, and connect the ohmic reflective layer 4 with the PAD metal layer 9 through the current spreading layer 8. The better the expansion capability of the current expansion layer, the lower the voltage, the more uniform the current distribution and the higher the luminous efficiency. In order to increase the spreading capability, the current spreading layer is usually implemented with a high conductivity metal or with an increased thickness. However, the chemical properties of metals with high conductivity are usually relatively active (e.g., Ag, Cu, Al, Ca, Mg, etc.) or relatively expensive (e.g., Au, etc.); therefore, in product design, a balance and compromise between current spreading performance and product cost is usually required; for example, a metal having a relatively high resistivity such as Ti, W, Pt, or Cr is selected, and current spreading is achieved by increasing the thickness.
In view of the above, the present inventors have specially designed a vertical structure LED chip and a method for manufacturing the same.
Disclosure of Invention
The invention aims to provide a vertical structure LED chip and a manufacturing method thereof, which aim to solve the technical problem that the balance and compromise between current expansion performance and product cost are generally required when the product design of the conventional vertical structure LED chip is carried out.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a vertical structure LED chip, comprising:
the device comprises a substrate, a first metal layer, an insulating layer, an integrated metal layer and an epitaxial lamination layer, wherein the first metal layer, the insulating layer, the integrated metal layer and the epitaxial lamination layer are arranged above the substrate; the epitaxial lamination at least comprises a second type semiconductor layer, an active region and a first type semiconductor layer which are sequentially stacked along a first direction, and the epitaxial lamination is provided with a through hole which exposes part of the surface of the first type semiconductor layer; the first direction is perpendicular to the substrate and is directed to the epitaxial stacked layer by the substrate;
the integrated metal layer is laminated on the surface of one side, away from the active region, of the second type semiconductor layer, and a bare surface for electric connection is arranged on one side, facing the second type semiconductor layer, of the integrated metal layer; an ohmic reflecting layer which can be in ohmic contact and can realize light reflection is arranged on the surface of one side, facing the second type semiconductor layer, of the integrated metal layer;
the insulating layer is arranged on one side, facing the substrate, of the epitaxial lamination layer, covers the integrated metal layer and the exposed surface of the epitaxial lamination layer and extends to the side wall of the through hole;
the first metal layer is stacked on the surface of one side, away from the integrated metal layer, of the insulating layer, and is embedded into the through hole to be in contact with the first type semiconductor layer; the substrate is stacked on the surface of one side, away from the epitaxial stacked layer, of the first metal layer;
and a passivation layer is arranged on the side wall of the epitaxial lamination layer.
Preferably, the integrated metal layer comprises one or more of gold, copper, palladium, and aluminum.
Preferably, the sidewalls of the integrated metal layer are covered by the insulating layer.
Preferably, the ohmic reflective layer comprises indium tin oxide, zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrOx、RuOxOne or more of indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium and molybdenum.
Preferably, the substrate comprises an electrically conductive substrate.
Preferably, the passivation layer comprises SiOxNyPassivation layer, Al2O3Passivation layer, MgF passivation layer, TiOxOne or more stacks of passivation layers, wherein x ≧ 0 and y ≧ 0.
Preferably, the epitaxial stack has at least one insulating layer exposed surface extending from the first type semiconductor layer to the insulating layer through the active region and the second type semiconductor layer, wherein the passivation layer is attached to the sidewall of the epitaxial stack in such a manner as to be maintained at the insulating layer exposed surface.
Preferably, the exposed surface of the insulating layer surrounds the periphery of the epitaxial lamination; and the passivation layer is arranged on the side wall of the epitaxial lamination layer in a surrounding mode in a mode of being kept on the exposed surface of the insulating layer.
The invention provides a method for manufacturing an LED chip with a vertical structure, which comprises the following steps:
s01, providing a growth substrate;
s02, stacking an epitaxial lamination layer on the surface of the growth substrate, wherein the epitaxial lamination layer comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially stacked along a first direction, and the first direction is perpendicular to the growth substrate and points to the epitaxial lamination layer from the growth substrate;
s03, forming a through hole and a light-emitting table surface on the epitaxial lamination layer through an etching process, wherein the through hole exposes part of the surface of the first type semiconductor layer;
s04, depositing an insulating layer, wherein the insulating layer covers the surface of the epitaxial lamination, the side wall and the bottom surface of the through hole, and the insulating layer is patterned to expose partial surface of the light-emitting table top;
s05, forming an ohmic reflecting layer on the exposed surface of the light-emitting table top, wherein the ohmic reflecting layer is used for ohmic contact and realizing light reflection;
s06, manufacturing an integrated metal layer, wherein the integrated metal layer is laminated on the surfaces of the ohmic reflecting layer and the insulating layer;
s07, depositing an insulating layer again to enable the insulating layer to wrap the integrated metal layer; s08, forming a through hole with an insulating layer on the side wall through an etching process;
s09, manufacturing a first metal layer, wherein the first metal layer is laminated on the surface of the insulating layer and is embedded into the through hole to be in contact with the first type semiconductor layer;
s10, fixing the chip structure formed in the step S09 on a conductive substrate through a bonding process, wherein the substrate is formed on the surface of the first metal layer;
s11, stripping the growth substrate;
s12, etching part of the epitaxial lamination layer to enable the insulating layer to have an exposed surface;
s13, depositing a passivation layer, wherein the passivation layer covers the exposed surfaces of the epitaxial lamination layer and the insulating layer;
and S14, patterning the passivation layer and the insulating layer through photoetching and etching to expose partial surface of the first type semiconductor layer and partial surface of the integrated metal layer.
Preferably, in step S14, the pattern of the passivation layer and the exposed surface of the integration metal layer are formed by the same photolithography.
Preferably, the step S14 includes coating the sidewalls of the integration metal layer with the insulating layer through an etching process.
Preferably, the integrated metal layer comprises one or more of gold, copper, palladium, and aluminum.
Preferably, the ohmic reflective layer comprises indium tin oxide, zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrOx、RuOxOne or more of indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium and molybdenum.
Preferably, the exposed surface of the insulating layer surrounds the periphery of the epitaxial stack; and the passivation layer is arranged on the side wall of the epitaxial lamination layer in a surrounding mode in a mode of being kept on the exposed surface of the insulating layer.
According to the technical scheme, the LED chip with the vertical structure provided by the invention comprises the following components in parts by weight: an integrated metal layer is arranged on the surface of one side, away from the active region, of the second type semiconductor layer, and an exposed surface for electric connection is arranged on one side, facing the second type semiconductor layer, of the integrated metal layer; the insulating layer is arranged on one side, facing the substrate, of the epitaxial lamination layer, covers the integrated metal layer and the exposed surface of the epitaxial lamination layer and extends to the side wall of the through hole. The manufacturing method of integrating the current expansion layer and the PAD metal layer is realized, namely, the integrated metal layer is formed, the integrated metal layer is used for replacing the current expansion layer, and the Au-containing metal material is adopted in the process of manufacturing the integrated metal layer; in addition, when the PAD is manufactured, part of the surface in the integrated metal layer is exposed in an etching mode, the exposed part is made of a metal material which is easy to wire on the integrated metal layer, the PAD function is carried out, and the PAD can be electrically connected with the outside. By the method, the process of independently manufacturing the PAD metal layer is omitted, and the cost is saved. In addition, different from the PAD metal layer manufactured in the traditional mode, the side wall of the integrated metal layer is coated in the insulating layer, so that the integrated metal layer can better resist the erosion of external water vapor, acid and alkali, salt mist and the like, and the reliability of the chip is improved.
Meanwhile, a passivation layer for protecting the LED chip is arranged on the side wall of the epitaxial lamination layer, and based on the structure, the passivation layer and the insulating layer can be patterned in the same photoetching and etching process, so that the surface of the first type semiconductor layer and part of the surface of the integrated metal layer are exposed, and the side wall passivation of the LED chip and the manufacturing of the PAD can be synchronously realized.
The manufacturing method of the LED chip with the vertical structure provided by the invention has the beneficial effects that the manufacturing process is simple and convenient while the through hole filling type LED chip is realized, the process of independently manufacturing the PAD metal layer is saved, the passivation layer and the insulating layer can be patterned in the same photoetching and etching process, the cost is saved, and the production is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural view of a through hole type LED chip provided in the background art;
fig. 2 is a schematic structural diagram of an LED chip with a vertical structure according to an embodiment of the present invention;
fig. 2.1 to fig. 2.14 are schematic structural diagrams corresponding to steps of a method for manufacturing the vertical LED chip provided in fig. 2 according to an embodiment of the present invention;
the symbols in the figures illustrate: 1. the light-emitting diode comprises a substrate, 2, a growth substrate, 3, an epitaxial lamination layer, 31, a first type semiconductor layer, 32, an active region, 33, a second type semiconductor layer, 34, a through hole, 35, a light-emitting table surface, 4, an ohmic reflection layer, 5, an insulating layer, 6, an integrated metal layer, 7, a first metal layer, 8, a current expansion layer, 9, a PAD metal layer, 10 and a passivation layer.
Detailed Description
In order to make the content of the present invention clearer, the content of the present invention is further explained below with reference to the attached drawings. The invention is not limited to this specific embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, a vertical structure LED chip includes:
a substrate 1, and a first metal layer 7, an insulating layer 5, an integrated metal layer 6 and an epitaxial stack 3 disposed over the substrate 1; the epitaxial stack 3 at least comprises a second type semiconductor layer 33, an active region 32 and a first type semiconductor layer 31 which are stacked in sequence along a first direction, and the epitaxial stack 3 is provided with a through hole 34 exposing a part of the surface of the first type semiconductor layer 31; the first direction is perpendicular to the substrate 1 and directed from the substrate 1 to the epitaxial stack 3;
the integrated metal layer 6 is stacked on a surface of the second type semiconductor layer 33, which is away from the active region 32, and a bare surface for electrical connection is arranged on a side of the integrated metal layer 6, which faces the second type semiconductor layer 33; an ohmic reflecting layer 4 which can make ohmic contact and realize light reflection is arranged on the surface of one side of the integrated metal layer 6 facing the second type semiconductor layer 33;
the insulating layer 5 is arranged on one side of the epitaxial lamination layer 3 facing the substrate 1, covers the integrated metal layer 6, and extends to the side wall of the through hole 34 on the exposed surface of the epitaxial lamination layer 3;
the first metal layer 7 is laminated on the surface of the insulating layer 5, which is far away from the integrated metal layer 6, and is embedded into the through hole 34 to be in contact with the first-type semiconductor layer 31; the substrate 1 is laminated on the surface of one side of the first metal layer 7, which is far away from the epitaxial lamination layer 3;
a passivation layer 10 is provided on the sidewalls of the epitaxial stack 3.
It should be noted that, in addition, the types of the first-type semiconductor layer 31, the active region 32 and the second-type semiconductor layer 33 of the epitaxial stack may also be not limited in the present embodiment, for example, the first-type semiconductor layer 31 may be, but is not limited to, a gallium nitride layer, and correspondingly, the second-type semiconductor layer 33 may be, but is not limited to, a gallium nitride layer;
meanwhile, the present embodiment does not limit the specific types of the insulating layer 5 and the first metal layer 7 as long as the above requirements are satisfied.
In the present embodiment, the integrated metal layer 6 includes, but is not limited to, one or more of gold, copper, palladium, and aluminum.
In this embodiment, the sidewalls of the integrated metal layer 6 are covered with the insulating layer 5.
In this embodiment, the ohmic reflective layer 4 includes, but is not limited to, indium tin oxide, zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrOx、RuOxOne or more of indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium and molybdenum.
In the present embodiment, the substrate 1 includes a conductive substrate.
In the present embodiment, the passivation layer 10 includes, but is not limited to, SiOxNyPassivation layer, Al2O3Passivation layer, MgF passivation layer, TiOxOne or more of the passivation layersAnd (3) stacking, wherein x is more than or equal to 0, and y is more than or equal to 0.
In the present embodiment, the epitaxial stack 3 has at least one insulating layer exposed surface, which extends from the first type semiconductor layer 31 to the insulating layer 5 through the active region 32 and the second type semiconductor layer 33, wherein the passivation layer 10 is attached to the sidewall of the epitaxial stack 3 in such a way as to be maintained on the insulating layer exposed surface.
In this embodiment, the exposed surface of the liner insulating layer surrounds the periphery of the epitaxial stacked layer 3; and a passivation layer 10 is disposed around the sidewall of the epitaxial stack 3 in such a manner as to be maintained on the exposed surface of the insulating layer.
The invention provides a method for manufacturing an LED chip with a vertical structure, which comprises the following steps:
s01, as shown in fig. 2.1, providing a growth substrate 2;
s02, as shown in fig. 2.2, stacking an epitaxial stack 3 on the surface of the growth substrate 2, where the epitaxial stack 3 includes a first type semiconductor layer 31, an active region 32, and a second type semiconductor layer 33 stacked in sequence along a first direction, the first direction being perpendicular to the growth substrate 2 and directed from the growth substrate 2 to the epitaxial stack 3;
s03, as shown in fig. 2.3, forming a via hole 34 and a light emitting mesa 35 on the epitaxial stacked layer 3 by an etching process, wherein the via hole 34 exposes a portion of the surface of the first type semiconductor layer 31;
s04, as shown in fig. 2.4, depositing an insulating layer 5, wherein the insulating layer 5 covers the surface of the epitaxial stack 3, the sidewall of the via 34 and the bottom surface thereof, and patterning the insulating layer 5 to expose a portion of the surface of the light emitting mesa;
s05, as shown in fig. 2.5, forming an ohmic reflective layer 4 on the exposed surface of the light emitting mesa 35, wherein the ohmic reflective layer 4 is used for ohmic contact and realizes light reflection;
s06, as shown in fig. 2.6, fabricating an integrated metal layer 6, wherein the integrated metal layer 6 is stacked on the surfaces of the ohmic reflective layer 4 and the insulating layer 5;
s07, as shown in fig. 2.7, depositing an insulating layer 5 again, so that the insulating layer 5 covers the integrated metal layer 6;
s08, as shown in fig. 2.8, forming the via hole 34 with the insulating layer 5 on the sidewall by the etching process;
s09, as shown in fig. 2.9, fabricating a first metal layer 7, wherein the first metal layer 7 is stacked on the surface of the insulating layer 5, and is embedded in the via hole 34 to contact with the first-type semiconductor layer 31;
s10, as shown in fig. 2.10, fixing the chip structure formed in step S09 on the conductive substrate 1 through a bonding process, wherein the substrate 1 is formed on the surface of the first metal layer 7;
s11, as shown in fig. 2.11, peeling the growth substrate 2;
s12, as shown in fig. 2.12, etching a part of the epitaxial stack 3 to make the insulating layer 5 have an exposed surface;
s13, as shown in fig. 2.13, depositing a passivation layer 10, wherein the passivation layer 10 covers the exposed surfaces of the epitaxial stack 3 and the insulating layer 5;
s14, as shown in fig. 2.14, the passivation layer 10 and the insulating layer 5 are patterned by photolithography and etching to expose a portion of the surface of the first type semiconductor layer 31 and a portion of the surface of the integration metal layer 6.
In this embodiment, in the step S14, the pattern of the passivation layer 10 and the exposed surface of the integration metal layer 6 are formed by the same photolithography.
In this embodiment, step S14 includes covering the sidewalls of the integrated metal layer 6 with the insulating layer 5 by an etching process.
In the present embodiment, the integrated metal layer 6 includes, but is not limited to, one or more of gold, copper, palladium, and aluminum. In this embodiment, the ohmic reflective layer 4 comprises indium tin oxide, zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, and IrOx、RuOxOne or more of indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium and molybdenum. Further, in this embodiment, the exposed surface of the insulating layer surrounds the periphery of the epitaxial stacked layer 3; and a passivation layer 10 is disposed around the sidewall of the epitaxial stack 3 in such a manner as to be maintained on the exposed surface of the insulating layer.
According to the technical scheme, the LED chip with the vertical structure provided by the invention comprises the following components in parts by weight: an integrated metal layer 6 is arranged on the surface of one side of the second type semiconductor layer 33, which is far away from the active region 32, and an exposed surface for electric connection is arranged on one side of the integrated metal layer 6, which faces the second type semiconductor layer 33; the insulating layer 5 is disposed on the side of the epitaxial stack 3 facing the substrate, and covers the integrated metal layer 6, the exposed surface of the epitaxial stack 3, and extends to the sidewall of the via 34. The manufacturing method of integrating the current expansion layer and the PAD metal layer is realized, namely the integrated metal layer 6 is formed, the integrated metal layer 6 is used for replacing the current expansion layer, and an Au-containing metal material is adopted in the process of manufacturing the integrated metal layer 6; in addition, when the PAD is manufactured, part of the surface in the integrated metal layer 6 is exposed in an etching mode, the exposed part is made of a metal material which is easy to wire on the metal material, the PAD is used, and the PAD can be electrically connected with the outside. By the method, the process of independently manufacturing the PAD metal layer is omitted, and the cost is saved. In addition, different from the PAD metal layer manufactured in the traditional mode, the side wall of the integrated metal layer 6 is wrapped in the insulating layer 5, so that the integrated metal layer can well resist the erosion of external water vapor, acid and alkali, salt mist and the like, and the reliability of the chip is improved.
Meanwhile, a passivation layer 10 for protecting the LED chip is disposed on the sidewall of the epitaxial stack 3, and based on this structure, the passivation layer 10 and the insulating layer 5 may be patterned in the same photolithography and etching process, so that the surface of the first type semiconductor layer and a part of the surface of the integrated metal layer are exposed, and then the sidewall passivation of the LED chip and the fabrication of the PAD may be achieved.
According to the manufacturing method of the LED chip with the vertical structure, the beneficial effects of the through hole 34 filling type LED chip are achieved, meanwhile, the process is simple and convenient to manufacture, the process of independently manufacturing the PAD metal layer is omitted, the passivation layer and the insulating layer can be patterned in the same photoetching and etching process, the cost is saved, and the manufacturing method is convenient to produce.
The device provided by the embodiment of the present invention has the same implementation principle and the same technical effects as those of the foregoing method embodiments, and for the sake of brief description, reference may be made to corresponding contents in the foregoing method embodiments for the parts of the device embodiments that are not mentioned. It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the foregoing systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A vertical structure LED chip, comprising:
the device comprises a substrate, a first metal layer, an insulating layer, an integrated metal layer and an epitaxial lamination layer, wherein the first metal layer, the insulating layer, the integrated metal layer and the epitaxial lamination layer are arranged above the substrate; the epitaxial lamination at least comprises a second type semiconductor layer, an active region and a first type semiconductor layer which are sequentially stacked along a first direction, and the epitaxial lamination is provided with a through hole which exposes part of the surface of the first type semiconductor layer; the first direction is perpendicular to the substrate and is directed to the epitaxial stacked layer by the substrate;
the integrated metal layer is laminated on the surface of one side, away from the active region, of the second type semiconductor layer, and a bare surface for electric connection is arranged on one side, facing the second type semiconductor layer, of the integrated metal layer; an ohmic reflecting layer which can be in ohmic contact and can realize light reflection is arranged on the surface of one side, facing the second type semiconductor layer, of the integrated metal layer;
the insulating layer is arranged on one side, facing the substrate, of the epitaxial lamination layer, covers the integrated metal layer and the exposed surface of the epitaxial lamination layer and extends to the side wall of the through hole;
the first metal layer is laminated on the surface of one side, away from the integrated metal layer, of the insulating layer, and is embedded into the through hole to be in contact with the first type semiconductor layer; the substrate is stacked on the surface of one side, away from the epitaxial stacked layer, of the first metal layer;
and a passivation layer is arranged on the side wall of the epitaxial lamination layer.
2. The vertical geometry LED chip of claim 1 wherein the integrated metal layer comprises one or more of gold, copper, palladium, aluminum.
3. The vertical geometry LED chip of claim 1 wherein the sidewalls of the integrated metal layer are encapsulated by the insulating layer.
4. The vertical structure LED chip of claim 1, wherein the ohmic reflective layer comprises indium tin oxide, zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrOx、RuOxOne or more of indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium and molybdenum.
5. The vertical geometry LED chip of claim 1 wherein the substrate comprises an electrically conductive substrate.
6. A manufacturing method of an LED chip with a vertical structure is characterized by comprising the following steps:
s01, providing a growth substrate;
s02, stacking an epitaxial lamination layer on the surface of the growth substrate, wherein the epitaxial lamination layer comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially stacked along a first direction, and the first direction is perpendicular to the growth substrate and points to the epitaxial lamination layer from the growth substrate;
s03, forming a through hole and a light-emitting table surface on the epitaxial lamination layer through an etching process, wherein the through hole exposes part of the surface of the first type semiconductor layer;
s04, depositing an insulating layer, wherein the insulating layer covers the surface of the epitaxial lamination, the side wall and the bottom surface of the through hole, and the insulating layer is patterned to expose partial surface of the light-emitting table top;
s05, forming an ohmic reflecting layer on the exposed surface of the light-emitting table top, wherein the ohmic reflecting layer is used for ohmic contact and realizing light reflection;
s06, manufacturing an integrated metal layer, wherein the integrated metal layer is laminated on the surfaces of the ohmic reflecting layer and the insulating layer;
s07, depositing an insulating layer again to enable the insulating layer to wrap the integrated metal layer;
s08, forming a through hole with an insulating layer on the side wall through an etching process;
s09, manufacturing a first metal layer, wherein the first metal layer is laminated on the surface of the insulating layer and is embedded into the through hole to be in contact with the first type semiconductor layer;
s10, fixing the chip structure formed in the step S09 on a conductive substrate through a bonding process, wherein the substrate is formed on the surface of the first metal layer;
s11, stripping the growth substrate;
s12, etching part of the epitaxial lamination layer to enable the insulating layer to have an exposed surface;
s13, depositing a passivation layer, wherein the passivation layer covers the exposed surfaces of the epitaxial lamination layer and the insulating layer;
and S14, patterning the passivation layer and the insulating layer through photoetching and etching to expose partial surface of the first type semiconductor layer and partial surface of the integrated metal layer.
7. The method of claim 6, wherein in step S14, the passivation layer pattern and the exposed surface of the integration metal layer are formed by the same photolithography.
8. The method for manufacturing the vertical structure LED chip according to claim 6, wherein the step S14 includes coating the sidewalls of the integrated metal layer with the insulating layer by an etching process.
9. The method of claim 6, wherein the integrated metal layer comprises one or more of gold, copper, palladium, and aluminum.
10. The method according to claim 6, wherein the ohmic reflective layer comprises indium tin oxide, zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrOx、RuOxOne or more of indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, nickel, rhodium and molybdenum.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210442069.4A CN114628561A (en) | 2022-04-25 | 2022-04-25 | LED chip with vertical structure and manufacturing method thereof |
| PCT/CN2022/094089 WO2022247742A1 (en) | 2021-05-24 | 2022-05-20 | Led chip and fabrication method therefor |
| US18/380,139 US20240038938A1 (en) | 2021-05-24 | 2023-10-13 | Light-emitting structure, manufacturing method thereof, and light-emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210442069.4A CN114628561A (en) | 2022-04-25 | 2022-04-25 | LED chip with vertical structure and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN114628561A true CN114628561A (en) | 2022-06-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210442069.4A Pending CN114628561A (en) | 2021-05-24 | 2022-04-25 | LED chip with vertical structure and manufacturing method thereof |
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| Country | Link |
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| CN (1) | CN114628561A (en) |
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- 2022-04-25 CN CN202210442069.4A patent/CN114628561A/en active Pending
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