CN117153985A - LED chip with vertical structure and manufacturing method thereof - Google Patents
LED chip with vertical structure and manufacturing method thereof Download PDFInfo
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- CN117153985A CN117153985A CN202310469186.4A CN202310469186A CN117153985A CN 117153985 A CN117153985 A CN 117153985A CN 202310469186 A CN202310469186 A CN 202310469186A CN 117153985 A CN117153985 A CN 117153985A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 153
- 239000002184 metal Substances 0.000 claims abstract description 153
- 238000003475 lamination Methods 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 23
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- 239000011810 insulating material Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 4
- ORUIBWPALBXDOA-UHFFFAOYSA-L magnesium fluoride Chemical compound [F-].[F-].[Mg+2] ORUIBWPALBXDOA-UHFFFAOYSA-L 0.000 claims description 4
- 229910001635 magnesium fluoride Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052758 niobium Inorganic materials 0.000 claims description 4
- 239000010955 niobium Substances 0.000 claims description 4
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052703 rhodium Inorganic materials 0.000 claims description 4
- 239000010948 rhodium Substances 0.000 claims description 4
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- 238000002310 reflectometry Methods 0.000 abstract description 5
- 238000000605 extraction Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 349
- 238000002347 injection Methods 0.000 description 12
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- 150000002739 metals Chemical class 0.000 description 6
- 230000007480 spreading Effects 0.000 description 5
- 238000003892 spreading Methods 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 2
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 1
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/641—Heat extraction or cooling elements characterized by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The application provides a vertical structure LED chip and a manufacturing method thereof, wherein an ODR omnidirectional reflector is formed on the surface of an epitaxial lamination through the cooperation of a dielectric layer and a metal reflecting layer, so that light rays are taken out from the upper surface of the LED chip after being reflected, the overall reflectivity of the chip is effectively improved, and the light extraction efficiency is increased; meanwhile, through embedding the integrated metal layer, au-containing metal materials are adopted in the process of manufacturing the integrated metal layer, and part of the surface in the integrated metal layer is exposed in an etching mode, and the exposed part bears the PAD function, so that the electric connection with the outside can be realized.
Description
Technical Field
The application relates to the field of light emitting diodes, in particular to a vertical structure LED chip and a manufacturing method thereof.
Background
With the development of the LED chip technology, the vertical structure chip, the flip chip and the like are greatly improved, and especially, the through hole type design is adopted, so that the luminous efficiency of the vertical chip and the flip chip can be greatly improved. The through hole type semiconductor is formed by opening a hole in the epitaxial surface to an N-type semiconductor, and the N-type contact is led to the surface of the chip through electrical connection so as to facilitate bonding or die bonding. The chip structure can be shown in fig. 1 of the drawings, and in order to conduct the second type semiconductor layer 33 in the manufacturing process, the ohmic reflection layer 10 needs to be manufactured on the surface of the second type semiconductor layer 33, and the ohmic reflection layer 10 is connected with the PAD metal layer 12 through the current expansion layer 11.
For an LED light emitting device, the improvement of the quantum efficiency of an LED is a permanent subject pursued by research and development workers. The design of the current expansion and the reflector is taken as a key attack object of the structural layer of the LED chip with the vertical structure. To increase the spreading capability, current spreading layers are typically implemented with high conductivity metals or increased thickness. However, the chemistry of high conductivity metals is generally relatively reactive (e.g., ag, cu, al, ca, mg, etc.) or relatively expensive (e.g., au, etc.); therefore, in product design, a balance and compromise is typically made between current spreading performance and product cost; for example, a metal having a relatively high resistivity such as Ti, W, pt, cr is selected, while current spreading is achieved by increasing the thickness. To increase reflectivity, highly reflective metals are typically employed as mirrors, the metals comprising one or more of Ag, au, al, mg, ni, ti, etc.; however, the reflectivity distance of the reflective metal is still a certain difference of 100%.
In view of this, the present inventors have specifically devised a vertical structure LED chip and a method for manufacturing the same, which results from this.
Disclosure of Invention
The application aims to provide a vertical structure LED chip and a manufacturing method thereof, which are used for solving the technical problems that the reflection effect is poor in the conventional vertical structure LED chip, and balance and compromise are required to be made between the current expansion performance and the product cost.
In order to achieve the above purpose, the technical scheme adopted by the application is as follows:
a vertical structure LED chip comprising:
the substrate, and the conductive bonding layer, the insulating layer, the integrated metal layer, the dielectric layer, the metal reflecting layer and the epitaxial lamination which are arranged above the substrate; the epitaxial lamination at least comprises a second type semiconductor layer, an active region and a first type semiconductor layer which are sequentially stacked along a first direction, and the epitaxial lamination is provided with a through hole exposing part of the surface of the first type semiconductor layer; a first direction perpendicular to the substrate and directed from the substrate to the epitaxial stack;
the dielectric layer is laminated on the surface of one side of the second type semiconductor layer, which is away from the active region, and the metal reflecting layer is in contact with the second type semiconductor layer in a mode of embedding the dielectric layer into the opening;
the integrated metal layer is laminated on the surface of one side of the metal reflecting layer, which is away from the epitaxial lamination, and a bare surface for electrical connection is arranged on one side of the integrated metal layer, which is towards the second semiconductor layer;
the insulating layer is arranged on one side of the epitaxial lamination towards the substrate and covers the integrated metal layer;
the conductive bonding layer is laminated on the surface of one side of the insulating layer, which is away from the integrated metal layer, and is embedded into the through hole to form contact with the first semiconductor layer; wherein the conductive bonding layer is arranged in an insulating manner with the side wall of the through hole; and the substrate is laminated on one side surface of the conductive bonding layer, which is away from the epitaxial lamination.
Preferably, the insulating layer extends to the via sidewall, so that the conductive bonding layer is insulated from the via sidewall.
Preferably, the dielectric layer has m openings, where m is a positive integer not less than 2.
Preferably, the vertical structure LED chip has n through holes, where n is a positive integer not less than 2.
Preferably, a filling structure may be further disposed in the through hole, the filling structure including a separate epitaxial pillar formed in the epitaxial stack by etching, or the filling structure including at least one or more of an insulating material and a metal.
Preferably, the dielectric layer includes any one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, an aluminum oxide layer, a magnesium fluoride layer, and a hafnium oxide layer.
Preferably, the metal reflective layer includes any one or more of an aluminum metal layer, a silver metal layer, a gold metal layer, a platinum metal layer, a lead metal layer, a nickel metal layer, an indium metal layer, a zinc metal layer, a chromium metal layer, a niobium metal layer, a titanium metal layer, a tin metal layer, and a rhodium metal layer.
Preferably, a roughened surface is provided on a side of the first semiconductor layer facing away from the active region.
Preferably, an ohmic contact layer is disposed on a surface of the second semiconductor layer, which faces away from the active region, the dielectric layer is stacked on a surface of the ohmic contact layer, and the metal reflection layer is in contact with the ohmic contact layer.
Preferably, a passivation protection layer is arranged on the side wall of the epitaxial lamination.
Preferably, the integrated metal layer includes Au metal material.
Preferably, the sidewall of the integrated metal layer is covered by the insulating layer.
Preferably, the substrate comprises a conductive substrate.
Preferably, the dielectric layer extends to the via sidewall.
Preferably, the metal reflective layer extends to the via sidewall by being attached to the dielectric layer, and the insulating layer covers the surface of the metal reflective layer.
The application also provides a manufacturing method of the LED chip with the vertical structure, which comprises the following steps:
s01, providing a growth substrate;
s02, stacking an epitaxial lamination on the surface of the growth substrate, wherein the epitaxial lamination comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially stacked along a first direction, and the first direction is perpendicular to the growth substrate and points to the epitaxial lamination from the growth substrate;
s03, forming a through hole and a light emitting table top in the epitaxial lamination through an etching process, wherein the through hole exposes part of the surface of the first semiconductor layer;
s04, forming an ohmic contact layer on the light-emitting table surface;
s05, forming a dielectric layer on the surface of the ohmic contact layer, wherein the dielectric layer is provided with an opening exposing the ohmic contact layer;
s06, manufacturing a metal reflecting layer, wherein the metal reflecting layer is in contact with the second semiconductor layer in a mode of embedding the opening into the dielectric layer;
s07, manufacturing an integrated metal layer, wherein the integrated metal layer is laminated on the surface of the metal reflecting layer;
s08, manufacturing an insulating layer, enabling the insulating layer to cover the integrated metal layer, and enabling the surface of the epitaxial lamination to form a plane;
s09, forming a through hole with an insulating layer on the side wall through an etching process;
s10, manufacturing a conductive bonding layer, wherein the conductive bonding layer is stacked on the surface of the insulating layer and is embedded into the through hole to form contact with the first type semiconductor layer;
s11, providing a substrate, and bonding the substrate and the conductive bonding layer through a bonding process;
s12, stripping the growth substrate;
and S13, etching part of the epitaxial lamination to the insulating layer so that the integrated metal layer has an exposed surface for electric connection.
Preferably, the dielectric layer has m openings, where m is a positive integer not less than 2.
Preferably, the vertical structure LED chip has n through holes, where n is a positive integer not less than 2.
Preferably, the integrated metal layer includes Au metal material.
According to the technical scheme, the LED chip with the vertical structure provided by the application is characterized in that: a dielectric layer is arranged on the surface of one side of the second type semiconductor layer, which is away from the active region, and the metal reflecting layer is in contact with the second type semiconductor layer in a mode of embedding the opening into the dielectric layer; the integrated metal layer is laminated on the surface of one side of the metal reflecting layer, which is away from the epitaxial lamination, and a bare surface for electrical connection is arranged on one side of the integrated metal layer, which is towards the second semiconductor layer; the insulating layer is arranged on one side of the epitaxial lamination towards the substrate and covers the integrated metal layer. Therefore, an ODR omnidirectional reflector is formed on the surface of the epitaxial lamination through the cooperation of the dielectric layer and the metal reflecting layer, so that light rays are taken out from the upper surface of the LED chip after being reflected, the overall reflectivity of the chip is effectively improved, and the light extraction efficiency is increased; meanwhile, through embedding the integrated metal layer, au-containing metal materials are adopted in the process of manufacturing the integrated metal layer, and part of the surface in the integrated metal layer is exposed in an etching mode, and the exposed part bears the PAD function, so that the electric connection with the outside can be realized. The contact electrode does not need to be manufactured independently, and can be directly wired on the integrated metal layer during packaging, so that the cost is saved, and meanwhile, the Au layer has lower resistivity and higher heat conductivity, so that the integrated metal layer has good current expansion capability and lower heat resistance. In addition, unlike the PAD metal layer produced in traditional way, the side wall of the integrated metal layer is coated in the insulating layer, so that the integrated metal layer can better resist the corrosion of external water vapor, acid and alkali, salt mist and the like, and the reliability of the chip is improved.
Further, the epitaxial lamination is provided with n through holes exposing part of the surface of the first type semiconductor layer; the conductive bonding layer is laminated on the surface of one side of the insulating layer, which is away from the integrated metal layer, and is embedded into the through hole to be in contact with the first type semiconductor layer, so that a first carrier injection lattice is formed. Based on this, when backside electrons are injected through the entire surface of the conductive substrate, the respective through holes in the first carrier injection lattice have the same electric potential, so that uniform injection of electrons can be achieved.
Further, by setting the dielectric layer to have m openings, where m is a positive integer not less than 2, the metal reflecting layer is embedded through the openings, so as to form a second carrier lattice injection point; the situation that electrons and holes are excessively concentrated on the periphery of the first carrier injection lattice is avoided, and the current can be uniformly distributed in the epitaxial stacked layer through the regulation and control of the second carrier lattice injection points, so that current congestion is effectively relieved, auger recombination is reduced, and internal quantum efficiency is further increased.
The manufacturing method of the LED chip with the vertical structure has the advantages of realizing the beneficial effects of the LED chip with the vertical structure, along with simple and convenient process manufacturing, saving the cost and facilitating the production.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a through hole type LED chip provided in the background art;
fig. 2 is a schematic structural diagram of an LED chip with a vertical structure according to an embodiment of the present application;
FIG. 3 is a cross-sectional view along the AA' direction of the LED chip with the vertical structure shown in FIG. 2 according to an embodiment of the present application;
fig. 4.1 to fig. 4.16 are schematic structural diagrams corresponding to steps of a method for manufacturing a vertical structure LED chip according to an embodiment of the present application;
the symbols in the drawings illustrate:
1. a substrate;
2. a growth substrate;
3. epitaxial lamination, 31, a first semiconductor layer, 32, an active region, 33, a second semiconductor layer, 34, a through hole, 35 and a light emitting mesa;
4. an ohmic contact layer;
5. a dielectric layer 51 and an opening;
6. a metal reflective layer;
7. the metal layer is integrated with the metal layer,
8. an insulating layer;
9. a conductive bonding layer;
10. an ohmic reflective layer;
11. a current spreading layer;
12. a PAD metal layer;
13. and passivating the protective layer.
Detailed Description
In order to make the contents of the present application more clear, the contents of the present application will be further described with reference to the accompanying drawings. The present application is not limited to this specific embodiment. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
As shown in fig. 2 and 3, a vertical structure LED chip includes:
a substrate 1, and a conductive bonding layer 9, an insulating layer 8, an integrated metal layer 7, a dielectric layer 5, a metal reflecting layer 6 and an epitaxial stack 3 which are arranged above the substrate 1; the epitaxial stack 3 includes at least a second type semiconductor layer 33, an active region 32, and a first type semiconductor layer 31 stacked in this order along a first direction, and the epitaxial stack 3 has a via 34 exposing a part of the surface of the first type semiconductor layer 31; a first direction is perpendicular to the substrate 1 and directed from the substrate 1 towards the epitaxial stack 3;
wherein the dielectric layer 5 is laminated on a surface of the second type semiconductor layer 33 facing away from the active region 32, and the metal reflective layer 6 is in contact with the second type semiconductor layer 33 by embedding the opening 51 into the dielectric layer 5;
the integrated metal layer 7 is laminated on the surface of one side of the metal reflecting layer 6 facing away from the epitaxial lamination layer 3, and a bare surface for electrical connection is arranged on one side of the integrated metal layer 7 facing the second type semiconductor layer 33;
the insulating layer 8 is arranged on the side of the epitaxial stack 3 facing the substrate 1 and covers the integrated metal layer 7;
the conductive bonding layer 9 is laminated on the surface of one side of the insulating layer 8, which is away from the integrated metal layer 7, and is embedded in the through hole 34 to form contact with the first type semiconductor layer 31; wherein the conductive bonding layer 9 is arranged in an insulating manner with the side wall of the through hole 34; and the substrate 1 is laminated on a surface of the conductive bonding layer 9 facing away from the epitaxial layer stack 3.
It should be noted that the types of the first type semiconductor layer 31, the active region 32 and the second type semiconductor layer 33 of the epitaxial stack 3 may also be not limited in the present embodiment, for example, the first type semiconductor layer 31 may be, but not limited to, an N type gallium nitride layer, and correspondingly, the second type semiconductor layer 33 may be, but not limited to, a P type gallium nitride layer.
Meanwhile, the present embodiment is not limited to the specific types of the insulating layer 8, the conductive type bonding layer 9, as long as the above requirements are satisfied. In one embodiment of the present application, the conductive bonding layer 9 includes, but is not limited to, an alloy of one or at least two metals of Au, in, ni, sn, ag, cu. Accordingly, the insulating layer 8 includes, but is not limited to, a silicon oxide layer.
Based on the above embodiment, in one embodiment of the present application, the insulating layer 8 extends to the sidewall of the via 34, so that the conductive bonding layer 9 is disposed insulated from the sidewall of the via 34.
Based on the above embodiment, in one embodiment of the present application, the dielectric layer 5 has m of the openings 51, where m is a positive integer not less than 2. It should be emphasized that, in the embodiment of the present application, in order to highlight the technical application point, fig. 2 and fig. 3 only illustrate a part of openings of the dielectric layer, and in actual use, the dielectric layer contains a plurality of openings, and the present application is not limited thereto as the case may be.
Based on the above embodiments, in one embodiment of the present application, the vertical structure LED chip has n of the through holes 34, n being a positive integer not less than 2. It should be emphasized that, in the embodiment of the present application, in order to highlight the technical application point, fig. 2 and fig. 3 only illustrate a part of through holes of the LED chip with a vertical structure, and in the actual use process, the LED chip with a vertical structure contains a plurality of through holes, which is not limited in the present application according to the situation.
Based on the above embodiments, in one embodiment of the present application, a filling structure may be further provided in the through hole, the filling structure including a separate epitaxial pillar formed by etching in the epitaxial stack, or the filling structure including at least one or more of an insulating material and a metal. The filling structure reduces the surface height difference caused by the open pores and the cavities generated by the surface height difference on the premise of ensuring that the conductive bonding layer and the first type semiconductor layer are in contact, thereby solving the technical problems of stress mismatch, heat aggregation and uneven current distribution caused by the surface height difference.
Based on the above embodiment, in one embodiment of the present application, the dielectric layer 5 includes any one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, an aluminum oxide layer, a magnesium fluoride layer, and a hafnium oxide layer.
Based on the above-described embodiments, in one embodiment of the present application, the metal reflective layer 6 includes any one or more of an aluminum metal layer, a silver metal layer, a gold metal layer, a platinum metal layer, a lead metal layer, a nickel metal layer, an indium metal layer, a zinc metal layer, a chromium metal layer, a niobium metal layer, a titanium metal layer, a tin metal layer, and a rhodium metal layer.
Based on the above-described embodiments, in one embodiment of the present application, a roughened surface is provided on the side of the first-type semiconductor layer 31 facing away from the active region 32.
Based on the above embodiment, in one embodiment of the present application, an ohmic contact layer 4 is disposed on a surface of the second type semiconductor layer 33 on a side facing away from the active region 32, the dielectric layer 5 is stacked on a surface of the ohmic contact layer 4, and the metal reflective layer 6 is in contact with the ohmic contact layer 4; the ohmic contact layer 4 is used for promoting ohmic contact of metal and semiconductor layers.
Based on the above embodiments, the ohmic contact layer 4 includes a metal ohmic contact layer 4 or a transparent conductive layer; in one embodiment of the present application, the ohmic contact layer 4 is a transparent conductive layer in order to avoid the problem of metal absorption.
Based on the above embodiments, in one embodiment of the present application, a passivation layer 13 is provided on the sidewall of the epitaxial stack 3, and the passivation layer 13 is a layer of insulating material. Alternatively, the passivation protection layer 13 includes an insulating material layer having a reflection effect; as a preferred embodiment, the passivation layer 13 comprises a DBR mirror.
Based on the above embodiment, in one embodiment of the present application, the integrated metal layer 7 includes Au metal material.
Based on the above embodiment, in one embodiment of the present application, the sidewall of the integrated metal layer 7 is covered by the insulating layer 8.
Based on the above embodiments, in one embodiment of the present application, the substrate 1 includes a conductive substrate 1.
Based on the above embodiments, in one embodiment of the present application, the dielectric layer 5 extends to the sidewall of the via 34.
Based on the above embodiment, in one embodiment of the present application, the metal reflective layer 6 extends to the sidewall of the via 34 by being attached to the dielectric layer 5, and the insulating layer 8 covers the surface of the metal reflective layer 6.
The embodiment of the application also provides a manufacturing method of the LED chip with the vertical structure, which comprises the following steps:
s01, as shown in fig. 4.1, providing a growth substrate 2;
based on the above-mentioned real matterIn one embodiment of the present application, the growth substrate 2 is made of sapphire (Al 2 O 3 ) SiC, gaAs, gaN, znO, si, gaP, inP, ge and Ga 2 O 3 But is not limited thereto.
S02, as shown in fig. 4.2, stacking an epitaxial stack 3 on the surface of the growth substrate 2, where the epitaxial stack 3 includes a first type semiconductor layer 31, an active region 32, and a second type semiconductor layer 33 stacked in sequence along a first direction, and the first direction is perpendicular to the growth substrate 2 and is directed from the growth substrate 2 to the epitaxial stack 3;
it should be noted that the types of the first type semiconductor layer 31, the active region 32 and the second type semiconductor layer 33 of the epitaxial stack 3 may also be not limited in the present embodiment, for example, the first type semiconductor layer 31 may be, but not limited to, an N type gallium nitride layer, and correspondingly, the second type semiconductor layer 33 may be, but not limited to, a P type gallium nitride layer.
S03, as shown in fig. 4.3, forming a through hole 34 and a light emitting mesa 35 in the epitaxial lamination 3 by an etching process, wherein the through hole 34 exposes a part of the surface of the first type semiconductor layer 31;
based on the above embodiments, in one embodiment of the present application, the vertical structure LED chip has n of the through holes 34, n being a positive integer not less than 2. It should be emphasized that, in the embodiment of the present application, in order to highlight the technical application point, fig. 4.3 only illustrates that two through holes 34 are provided in the LED chip with a vertical structure, and in actual use, the LED chip with a vertical structure includes a plurality of through holes, and the present application is not limited thereto as the case may be.
S04, as shown in fig. 4.4, forming an ohmic contact layer 4 on the light emitting mesa 35, where the ohmic contact layer 4 is used to promote ohmic contact between metal and semiconductor materials;
based on the above embodiments, in one embodiment of the present application, the ohmic contact layer 4 includes a metal ohmic contact layer or a transparent conductive layer; in one embodiment of the present application, the ohmic contact layer 4 is a transparent conductive layer in order to avoid the problem of metal absorption.
S05, as shown in fig. 4.5, forming a dielectric layer 5 on the surface of the ohmic contact layer 4, wherein the dielectric layer 5 is provided with an opening 51 exposing the ohmic contact layer 4;
based on the above embodiment, in one embodiment of the present application, the dielectric layer 5 covers the ohmic contact layer 4 and extends to the sidewall of the via 34;
based on the above embodiment, in one embodiment of the present application, the dielectric layer 5 includes any one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, an aluminum oxide layer, a magnesium fluoride layer, and a hafnium oxide layer.
Based on the above embodiment, in one embodiment of the present application, the dielectric layer 5 has m of the openings 51, where m is a positive integer not less than 2. It should be emphasized that, in the embodiment of the present application, in order to highlight the technical application point, fig. 4.5 only illustrates a part of the openings of the dielectric layer, and in the actual use process, the dielectric layer includes a plurality of openings, and the present application is not limited thereto as the case may be.
S06, as shown in fig. 4.6, manufacturing a metal reflecting layer 6, wherein the metal reflecting layer 6 is in contact with the second type semiconductor layer 33 in a manner of embedding the opening 51 into the dielectric layer 5;
based on the above-described embodiments, in one embodiment of the present application, the metal reflective layer 6 includes any one or more of an aluminum metal layer, a silver metal layer, a gold metal layer, a platinum metal layer, a lead metal layer, a nickel metal layer, an indium metal layer, a zinc metal layer, a chromium metal layer, a niobium metal layer, a titanium metal layer, a tin metal layer, and a rhodium metal layer.
S07, as shown in fig. 4.7, manufacturing an integrated metal layer 7, wherein the integrated metal layer 7 is laminated on the surface of the metal reflection layer 6;
based on the above embodiment, in one embodiment of the present application, the integrated metal layer 7 includes Au metal material.
S08, as shown in fig. 4.8, manufacturing an insulating layer 8, enabling the insulating layer 8 to cover the integrated metal layer 7, and enabling the surface of the epitaxial lamination layer 3 to form a plane; based on the above embodiment, in one embodiment of the present application, the insulating layer 8 includes, but is not limited to, a silicon dioxide layer
S09, as shown in fig. 4.9, through-holes 34 with insulating layers 8 on the sidewalls are formed by etching process;
s10, as shown in FIG. 4.10, manufacturing a conductive bonding layer 9, wherein the conductive bonding layer 9 is laminated on the surface of the insulating layer 8 and is embedded in the through hole 34 to form contact with the first semiconductor layer 31;
based on the above embodiments, in one embodiment of the present application, the conductive type bonding layer 9 includes, but is not limited to, one of Au, in, ni, sn, ag, cu or an alloy formed of at least two metals.
S11, as shown in FIG. 4.11, providing a substrate 1; and bonding the substrate 1 and the conductive bonding layer 9 into a whole through a bonding process, as shown in fig. 4.12;
based on the above embodiments, in one embodiment of the present application, the substrate 1 includes a conductive substrate 1.
S12, as shown in FIG. 4.13, stripping the growth substrate 2;
further, in one embodiment of the present application, after the growth substrate 2 is peeled to expose the first type semiconductor layer 31, a roughened surface is formed on a side of the first type semiconductor layer 31 facing away from the active region 32 through a photolithography process, as shown in fig. 4.14.
S13, as shown in fig. 4.15, etching a part of the epitaxial stack 3 to the insulating layer 8 to make the integrated metal layer 7 have an exposed surface for electrical connection.
Further, based on the above embodiment, in one embodiment of the present application, as shown in fig. 4.16, a passivation layer 13 is provided on a sidewall of the epitaxial stack 3, and the passivation layer 13 is an insulating material layer. Alternatively, the passivation protection layer 13 includes an insulating material layer having a reflection effect; as a preferred embodiment, the passivation layer 13 comprises a DBR mirror.
According to the technical scheme, the LED chip with the vertical structure provided by the application is characterized in that: a dielectric layer 5 is arranged on the surface of one side of the second type semiconductor layer 33, which is away from the active region 32, and the metal reflecting layer 6 is in contact with the second type semiconductor layer 33 in a manner of embedding the dielectric layer 5 through an opening 51; the integrated metal layer 7 is laminated on the surface of one side of the metal reflecting layer 6 facing away from the epitaxial lamination layer 3, and a bare surface for electrical connection is arranged on one side of the integrated metal layer 7 facing the second type semiconductor layer 33; the insulating layer 8 is arranged on the side of the epitaxial stack 3 facing the substrate 1 and covers the integrated metal layer 7. Therefore, an ODR omnidirectional reflector is formed on the surface of the epitaxial lamination 3 through the cooperation of the dielectric layer 5 and the metal reflecting layer 6, so that light rays are taken out from the upper surface of the LED chip after being reflected, the overall reflectivity of the chip is effectively improved, and the light extraction efficiency is increased; meanwhile, through embedding the integrated metal layer 7, an Au-containing metal material is adopted in the process of manufacturing the integrated metal layer 7, and part of the surface in the integrated metal layer 7 is exposed in an etching mode, and the exposed part bears the PAD function, so that the electric connection with the outside can be realized. The contact electrode does not need to be manufactured independently, and can be directly wired on the integrated metal layer 7 during packaging, so that the cost is saved, and meanwhile, the Au layer has lower resistivity and higher heat conductivity, so that the integrated metal layer 7 has good current expansion capability and lower heat resistance. In addition, unlike the PAD metal layer manufactured in the prior art, the side wall of the integrated metal layer 7 is coated in the insulating layer 8, so that the integrated metal layer can better resist the corrosion of external water vapor, acid and alkali, salt mist and the like, and the reliability of the chip is improved.
Further, the epitaxial stack 3 has n through holes 34 exposing a part of the surface of the first type semiconductor layer 31; the conductive bonding layer 9 is laminated on a surface of the insulating layer 8, which is away from the integrated metal layer 7, and is embedded in the through hole 34 to contact the first type semiconductor layer 31, so as to form a first carrier injection lattice. Based on this, when backside electrons are injected through the entire surface of the conductive substrate 1, the respective through holes 34 in the first carrier injection lattice have the same electric potential, so that uniform injection of electrons can be achieved.
Further, by providing the dielectric layer 5 with m openings 51, where m is a positive integer not less than 2, the metal reflection layer 6 is embedded through the openings 51, so as to form a second carrier lattice injection point; the situation that electrons and holes are excessively concentrated on the periphery of the first carrier injection lattice is avoided, and the current can be uniformly distributed in the epitaxial lamination 3 through the regulation and control of the second carrier lattice injection points, so that current congestion is effectively relieved, auger recombination is reduced, and internal quantum efficiency is further increased.
The manufacturing method of the LED chip with the vertical structure has the advantages of realizing the beneficial effects of the LED chip with the vertical structure, along with simple and convenient process manufacturing, saving the cost and facilitating the production.
The device provided by the embodiment of the present application has the same implementation principle and technical effects as those of the foregoing method embodiment, and for the sake of brevity, reference may be made to the corresponding content in the foregoing method embodiment where the device embodiment is not mentioned. It will be clear to those skilled in the art that, for convenience and brevity, the specific operation of the system, apparatus and unit described above may refer to the corresponding process in the above method embodiment, which is not described in detail herein.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (14)
1. A vertical structure LED chip, comprising:
the substrate, and the conductive bonding layer, the insulating layer, the integrated metal layer, the dielectric layer, the metal reflecting layer and the epitaxial lamination which are arranged above the substrate; the epitaxial lamination at least comprises a second type semiconductor layer, an active region and a first type semiconductor layer which are sequentially stacked along a first direction, and the epitaxial lamination is provided with a through hole exposing part of the surface of the first type semiconductor layer; a first direction perpendicular to the substrate and directed from the substrate to the epitaxial stack;
the dielectric layer is laminated on the surface of one side of the second type semiconductor layer, which is away from the active region, and the metal reflecting layer is in contact with the second type semiconductor layer in a mode of embedding the dielectric layer into the opening;
the integrated metal layer is laminated on the surface of one side of the metal reflecting layer, which is away from the epitaxial lamination, and a bare surface for electrical connection is arranged on one side of the integrated metal layer, which is towards the second semiconductor layer;
the insulating layer is arranged on one side of the epitaxial lamination towards the substrate and covers the integrated metal layer;
the conductive bonding layer is laminated on the surface of one side of the insulating layer, which is away from the integrated metal layer, and is embedded into the through hole to form contact with the first semiconductor layer; wherein the conductive bonding layer is arranged in an insulating manner with the side wall of the through hole; and the substrate is laminated on one side surface of the conductive bonding layer, which is away from the epitaxial lamination.
2. The LED chip of claim 1, wherein said insulating layer extends to said via sidewall, such that said conductive bonding layer is disposed insulated from said via sidewall.
3. The LED chip of claim 1, wherein said dielectric layer has m said openings, m being a positive integer not less than 2.
4. The vertical structure LED chip of claim 1, wherein said vertical structure LED chip has n of said through holes, n being a positive integer not less than 2.
5. The LED chip of claim 1, wherein a filling structure is further provided in the via hole, the filling structure comprising a separate epitaxial pillar formed by etching in the epitaxial stack, or the filling structure comprising at least one or more of an insulating material, a metal.
6. The vertical structure LED chip of claim 1, wherein said dielectric layer comprises any one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, an aluminum oxide layer, a magnesium fluoride layer, and a hafnium oxide layer.
7. The vertical structure LED chip of claim 1, wherein said metal reflective layer comprises any one or more of an aluminum metal layer, a silver metal layer, a gold metal layer, a platinum metal layer, a lead metal layer, a nickel metal layer, an indium metal layer, a zinc metal layer, a chromium metal layer, a niobium metal layer, a titanium metal layer, a tin metal layer, and a rhodium metal layer.
8. The vertical structure LED chip of claim 1, wherein said first type semiconductor layer has a roughened surface on a side facing away from said active region.
9. The LED chip of claim 1, wherein an ohmic contact layer is disposed on a surface of said second semiconductor layer facing away from said active region, said dielectric layer is laminated on a surface of said ohmic contact layer, and said metal reflective layer is in contact with said ohmic contact layer.
10. The LED chip of claim 1, wherein a passivation layer is provided on the sidewall of said epitaxial stack.
11. The vertical structure LED chip of claim 1, wherein said integrated metal layer comprises Au metal material.
12. The manufacturing method of the LED chip with the vertical structure is characterized by comprising the following steps of:
s01, providing a growth substrate;
s02, stacking an epitaxial lamination on the surface of the growth substrate, wherein the epitaxial lamination comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially stacked along a first direction, and the first direction is perpendicular to the growth substrate and points to the epitaxial lamination from the growth substrate;
s03, forming a through hole and a light emitting table top in the epitaxial lamination through an etching process, wherein the through hole exposes part of the surface of the first semiconductor layer;
s04, forming an ohmic contact layer on the light-emitting table surface;
s05, forming a dielectric layer on the surface of the ohmic contact layer, wherein the dielectric layer is provided with an opening exposing the ohmic contact layer;
s06, manufacturing a metal reflecting layer, wherein the metal reflecting layer is in contact with the second semiconductor layer in a mode of embedding the opening into the dielectric layer;
s07, manufacturing an integrated metal layer, wherein the integrated metal layer is laminated on the surface of the metal reflecting layer;
s08, manufacturing an insulating layer, enabling the insulating layer to cover the integrated metal layer, and enabling the surface of the epitaxial lamination to form a plane;
s09, forming a through hole with an insulating layer on the side wall through an etching process;
s10, manufacturing a conductive bonding layer, wherein the conductive bonding layer is stacked on the surface of the insulating layer and is embedded into the through hole to form contact with the first type semiconductor layer;
s10, providing a substrate, and bonding the substrate and the conductive bonding layer through a bonding process;
s12, stripping the growth substrate;
and S13, etching part of the epitaxial lamination to the insulating layer so that the integrated metal layer has an exposed surface for electric connection.
13. The method of manufacturing a vertical structure LED chip of claim 12, wherein said dielectric layer has m said openings, m being a positive integer not less than 2.
14. The method of manufacturing a vertical structure LED chip of claim 12, wherein said vertical structure LED chip has n of said through holes, n being a positive integer not less than 2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310469186.4A CN117153985A (en) | 2023-04-27 | 2023-04-27 | LED chip with vertical structure and manufacturing method thereof |
| US18/380,139 US20240038938A1 (en) | 2021-05-24 | 2023-10-13 | Light-emitting structure, manufacturing method thereof, and light-emitting device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310469186.4A CN117153985A (en) | 2023-04-27 | 2023-04-27 | LED chip with vertical structure and manufacturing method thereof |
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| CN117153985A true CN117153985A (en) | 2023-12-01 |
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