WO2022242000A1 - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
WO2022242000A1
WO2022242000A1 PCT/CN2021/120350 CN2021120350W WO2022242000A1 WO 2022242000 A1 WO2022242000 A1 WO 2022242000A1 CN 2021120350 W CN2021120350 W CN 2021120350W WO 2022242000 A1 WO2022242000 A1 WO 2022242000A1
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Prior art keywords
metal
metal layer
signal line
blocks
dummy
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PCT/CN2021/120350
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English (en)
French (fr)
Inventor
翁坤
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/650,122 priority Critical patent/US12341094B2/en
Publication of WO2022242000A1 publication Critical patent/WO2022242000A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Definitions

  • the present application relates to, but is not limited to, a semiconductor structure.
  • a semiconductor integrated circuit device includes a metal layer on which patterned metal is deployed, and part of the metal on the metal layer is used to transmit signals, such as clock signals, control terminal signals of transistors, and the like.
  • the present application provides a semiconductor structure, including: a multilayer metal layer and a substrate, where the multilayer metal layer includes a first metal layer, a second metal layer and a third metal layer;
  • a plurality of dummy metal blocks and at least one signal line are arranged on the metal layer;
  • the virtual metal blocks on the metal layer are staggered from each other in the direction perpendicular to the substrate;
  • the second distance between the projection of the target signal line on the substrate and the projection of the second virtual metal block on the substrate is greater than the projection of the target signal line on the substrate to the projection of the first virtual metal block on the substrate.
  • the first distance between; the target signal line is located on the first metal layer;
  • the third distance between the projection of the target signal line on the substrate and the projection of the third virtual metal block on the substrate is greater than the first distance
  • the first virtual metal block is the virtual metal block closest to the target signal line in the first metal layer
  • the second virtual metal block is the virtual metal block closest to the target signal line in the second metal layer
  • the third virtual metal block is the closest virtual metal block to the target signal line in the second metal layer.
  • the block is the virtual metal block closest to the target signal line in the third metal layer.
  • FIG. 1 is a front view of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 2 is a schematic layout diagram of a signal line provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of making a metal layer in a semiconductor structure provided by an embodiment of the present application.
  • FIG. 4 is a schematic layout diagram of a signal line and a virtual metal block provided by an embodiment of the present application
  • FIG. 5 is a schematic layout diagram of a virtual metal block in a semiconductor structure provided by an embodiment of the present application.
  • FIG. 6 is a schematic layout diagram of a virtual metal block in the semiconductor structure provided by the embodiment shown in FIG. 5;
  • FIG. 7 is a schematic diagram of a parasitic capacitance between a signal line and a virtual metal block provided by an embodiment of the present application.
  • FIG. 8 is a schematic layout diagram of virtual metal blocks in each metal layer provided by an embodiment of the present application.
  • the semiconductor structure includes a substrate 30 , electronic components 20 and multiple metal layers 10 , and electronic components 20 such as transistors are arranged on the substrate 30 .
  • a multi-layer metal layer 10 is arranged on the electronic component 20, for example: the metal layer M0, the metal layer Mn, the metal layer Mn+1 and the metal layer Mn+2 with successively increasing heights, n is a natural number, that is, the height of the metal layer Mn is In the metal layer M0, the metal layer Mn+1 is higher than the metal layer Mn, and the metal layer Mn+2 is higher than the metal layer Mn+1.
  • the various metal layers are electrically connected through conductive plugs 40 .
  • Signal lines are arranged on part of the metal layer 10 for interconnection of various electronic components, and for connecting the electronic components to ground pads or power supply pads.
  • the dry etching process is usually used when making the signal lines of integrated circuits.
  • the typical manufacturing process includes the following steps: first, draw the layout pattern of the signal lines, and then use the photolithography process to transfer the layout pattern of the signal lines to the semiconductor substrate.
  • the semiconductor The substrate refers to the semiconductor structure to be dry etched. Then, dry etching is performed on the semiconductor structure, and the metal layer or dielectric layer not covered by the photolithographic medium is removed to form the required semiconductor structure.
  • each layer can be divided into a signal line dense area 103 and a signal line sparse area 104 according to the distribution area of signal lines.
  • the uneven distribution of the metal wires will affect the fabrication process of the semiconductor structure.
  • FIG. 3 especially when the distance between the two layers exceeds a certain value, when a layer of dielectric layer 105 is covered on the current layer 106, the dielectric layer 105 will be dish-shaped in the sparse area 104 of the signal line. , resulting in a significant difference in thickness of the dielectric layer between the signal line dense area 103 and the signal line sparse area 104 .
  • the dry etching process is a chemical or chemical and mechanical process whose etching rate is related to the density of components on the semiconductor substrate. Due to the uneven density of signal lines on the semiconductor substrate, the etching rate of the place with high signal line density and the place with low density is significantly different, resulting in difficulties in etching, which is the so-called loading effect.
  • the thickness of the subsequently formed dielectric layer 105 is another factor affecting the etching process. Due to the different densities of the signal lines on the semiconductor substrate, a dish shape will be formed in the area where the signal lines are sparse, making it difficult to detect the etching end point during the dielectric layer etching process, resulting in over-etching or stopping the etching before reaching the etching end point occur. This further affects the yield rate in the process of fabricating the semiconductor structure.
  • dummy metal blocks are usually arranged in the signal line sparse area of each layer, so that the density of the signal line dense area is the same as that of the signal line sparse area.
  • virtual metal slugs do not carry signals.
  • the virtual metal block can be grounded, connected to a power source, or left floating. Since the parasitic capacitance value will increase when the virtual metal block is grounded or connected to a power supply, the virtual metal block is usually in a floating state. It should be noted that the connection state of the virtual metal block is not limited here.
  • An embodiment of the present application provides a semiconductor structure, including a substrate 30 and a multi-layer metal layer 10, wherein signal lines are provided on each metal layer, and dummy metal blocks are provided on the metal layer with uneven distribution of signal lines. In order to make the wiring on the metal layer uniform.
  • each layer has a dense area of signal lines and a sparse area of signal lines.
  • Fig. 5 and Fig. 6 are top views of the same semiconductor structure
  • Fig. 5 is a layout diagram of virtual metal blocks of metal layer Mn and metal layer Mn+1
  • Fig. 6 is a virtual metal block of metal layer Mn+1 and metal layer Mn+2 layout diagram.
  • dummy metal blocks arranged in an array are deployed on the metal layer Mn. And each virtual metal block on the metal layer Mn is deployed along a first direction, for example: the first direction is deployed from top to bottom.
  • Dummy metal blocks arranged in an array are deployed on the metal layer Mn+1. And each virtual metal block on the metal layer Mn+1 is deployed along a second direction, and the first direction is different from the second direction, for example: the second direction is deployed from left to right.
  • the projection of the dummy metal block of the metal layer Mn on the substrate partially overlaps with the projection of the dummy metal block of the metal layer Mn+1 on the substrate.
  • dummy metal blocks arranged in an array are deployed on the metal layer Mn+1. And each dummy metal block on the metal layer Mn+1 is deployed along the second direction. Dummy metal blocks arranged in an array are deployed on the metal layer Mn+2. And each virtual metal block on the metal layer Mn+2 is deployed along the first direction, the projection of the virtual metal block of the metal layer Mn on the substrate completely overlaps with the projection of the virtual metal block of the metal layer Mn+2 on the substrate .
  • the wiring density of the metal layer Mn, the metal layer Mn+1 and the metal layer Mn+2 can be effectively compensated, so that the wiring of each metal layer is more uniform.
  • the semiconductor structures shown in FIGS. 5 and 6 introduce relatively large parasitic capacitances on the signal lines.
  • the parasitic capacitance C1 generated by the signal line 102 and the dummy metal block 101 on the same layer the parasitic capacitance C2 generated by the signal line 102 and the dummy metal block 101 directly above the Mn+1 layer, and the parasitic capacitance C2 generated by the signal line 102 and the The parasitic capacitance C3 generated by the dummy metal block 101 on the upper right of the Mn+1 layer, the parasitic capacitance C4 generated by the signal line 102 and the dummy metal block 101 directly above the Mn+2 layer, the signal line 102 and the dummy metal block 101 located on the Mn+2 layer
  • parasitic capacitances are also generated between the virtual metal blocks. Especially when the projections of the virtual metal blocks on the substrate overlap each other, the parasitic capacitance is relatively large. When the parasitic capacitance between the dummy metal blocks is large, it is easy to collect charges on the dummy metal blocks during the manufacturing process, thereby affecting the yield rate of semiconductor structure manufacturing.
  • an embodiment of the present application provides a semiconductor structure, which includes multiple metal layers 10 and a substrate 30 . Signal lines are arranged on each metal layer, and dummy metal blocks are arranged on the metal layer where the signal lines are unevenly distributed.
  • the dummy metal blocks on the metal layer are staggered in a direction perpendicular to the substrate, that is, the dummy metal blocks on all metal layers on which the dummy metal blocks are deployed are staggered in a direction perpendicular to the substrate.
  • the semiconductor structure is provided with L layers of metal layers, and dummy metal blocks are arranged on the metal layer Mn to the metal layer Mn+2, and the dummy metal blocks on the metal layer Mn and the dummy metal blocks on the metal layer Mn+1 are staggered from each other, The dummy metal blocks on the metal layer Mn are staggered from the dummy metal blocks on the metal layer Mn+2, and the dummy metal blocks on the metal layer Mn+1 are staggered from the dummy metal blocks on the metal layer Mn+2.
  • n+2 ⁇ L, and both n and L are positive integers.
  • the effective area of the parasitic capacitance generated between the virtual metal blocks can be reduced, thereby reducing the parasitic capacitance between the virtual metal blocks, reducing the charge collected on the virtual metal blocks during the manufacturing process, and improving semiconductor performance. Yield of structure fabrication.
  • the multi-layer metal layer includes a first metal layer, a second metal layer and a third metal layer.
  • the height relationship of the three metal layers may be arbitrary, that is, the first metal layer may be higher than the second metal layer, and the second metal layer may be higher than the third metal layer. It may also be that the first metal layer is lower than the second metal layer, and the second metal layer is lower than the third metal layer. It may also be that the second metal layer is higher than the first metal layer, and the first metal layer is higher than the third metal layer. There are no restrictions here.
  • the first metal layer is the metal layer Mn
  • the second metal layer is the metal layer Mn+1
  • the third metal layer is the metal layer Mn+2.
  • the geometric center of the projection of the virtual metal block on the substrate to the geometric center of the projection of the target signal line 107 on the substrate can be calculated the distance.
  • the second distance between the projection of the target signal line on the substrate and the projection of the second dummy metal block on the substrate is greater than the projection of the target signal line on the substrate to the first dummy metal block on the substrate
  • the first distance between the projections of the target signal line on the substrate and the third distance between the projection of the target signal line on the substrate and the projection of the third virtual metal block on the substrate are greater than the first distance.
  • the distance from the second virtual metal block to the target signal line and the distance from the third virtual metal block to the target signal line are farther, which can reduce the target signal line and the second layer
  • the parasitic capacitance between the dummy metal blocks on the metal layer can also reduce the parasitic capacitance between the target signal line and the dummy metal block on the third metal layer, and the distance between the first dummy metal block 108 and the target signal line 107 More recently, the wiring uniformity on the first metal layer can be guaranteed.
  • the parasitic capacitance between the virtual metal blocks can be effectively reduced, while ensuring that the virtual metal blocks in each metal layer are vertically Under the premise of staggering the direction of the substrate, the dummy metal blocks on the second and third metal layers are farther away from the target signal line, and the dummy metal blocks on the first metal layer are further away from the target signal line.
  • ensuring the uniformity of wiring on the first metal layer can also reduce the parasitic capacitance between the target signal line and the virtual metal blocks on the second and third metal layers, thereby improving the transmission of the target signal line. the quality of the signal.
  • the projections of the dummy metal blocks on the multi-layer metal layers on the substrate do not overlap, that is, the projections of the dummy metal blocks on all the metal layers on which the dummy metal blocks are deployed do not overlap on the substrate.
  • the effective area of parasitic capacitance generated between any two virtual metal blocks can be further reduced, thereby reducing the parasitic capacitance between any two virtual metal blocks.
  • the dummy metal blocks on each metal layer are distributed in an array, which can improve the uniformity of wiring on each metal layer, avoid dish-shaped metal layers when manufacturing the semiconductor structure, and improve the yield of the semiconductor structure.
  • the projection matrix of the virtual metal blocks on the first metal layer on the substrate and the projection matrix of the virtual metal blocks on the other metal layers on the substrate are arranged to cross each other, wherein the other metal layers are the first A metal layer other than a metal layer. That is, the projections of some or all of the virtual metal blocks on the other metal layers on the substrate are located between the projections of the two virtual metal blocks on the first layer of metal layer on the substrate, or the first layer of metal The projections of part or all of the virtual metal blocks on the layer on the substrate are located between the projections of two virtual metal blocks on the other metal layers on the substrate.
  • the third virtual metal block on the third metal layer The distance of the target signal line is greater than the distance from the first dummy metal block on the first metal layer to the target signal line, reducing the parasitic capacitance between the target signal line and the dummy metal block on the third metal layer, which can further reduce the
  • the staggered setting of the dummy metal blocks affects the wiring uniformity of the first metal layer and the third metal layer, so that the wiring of the first metal layer and the third metal layer is more uniform.
  • the projections of two adjacent dummy metal blocks on the first metal layer and the projections of the dummy metal blocks on the third metal layer are in contact with each other.
  • the same dummy metal block on the metal layer Mn The projections of the adjacent dummy metal blocks of the row and the projections of the dummy metal blocks on the metal layer Mn+2 are in contact with each other.
  • the distance from the second dummy metal block on the second metal layer to the target signal line is greater than the distance from the first dummy metal block on the first metal layer to the target signal line, and also ensure that the third dummy metal block on the third metal layer
  • the distance from the metal block to the target signal line is greater than the distance from the first dummy metal block to the target signal line on the first metal layer, reducing the distance between the target signal line and the virtual metal block on the second metal layer, and on the third metal layer.
  • the parasitic capacitance between the virtual metal blocks can further reduce the influence on the wiring uniformity of the first metal layer, the second metal layer, and the third metal layer due to the staggered setting of the virtual metal blocks, so that the first metal layer to The third metal layer is routed more uniformly.
  • the projections of two adjacent dummy metal blocks on the third metal layer and the projections of the dummy metal blocks on the second metal layer are in contact with each other.
  • the projections of the adjacent virtual metal blocks located in the same column and the projections of the virtual metal blocks on the metal layer Mn+1 are in contact with each other.
  • the third distance between the projection on the substrate and the second distance between the projection of the target signal line on the substrate and the projection of the second virtual metal block on the substrate are equal, reducing the distance between the target signal line and the second metal layer.
  • the parasitic capacitance between the dummy metal blocks on the third metal layer and the dummy metal blocks on the third metal layer can also make the wiring from the first metal layer to the third metal layer more uniform.
  • the second metal layer is higher than the first metal layer
  • the third metal layer is higher than the second metal layer, and two adjacent dummy metal layers in the same row on the first metal layer
  • the dummy metal block on the first metal layer and the dummy metal on the second metal layer The parasitic capacitance between blocks is larger.
  • the projection of the virtual metal block on the third metal layer lie between the projections of two adjacent virtual metal blocks on the same row on the first metal layer
  • the projection of the virtual metal block on the second metal layer The projection is located between the projections of two adjacent virtual metal blocks in the same column on the third metal layer, reducing the generation between the virtual metal blocks on the first metal layer and the virtual metal blocks on the second metal layer
  • the effective area of the parasitic capacitance thereby reducing the parasitic capacitance between the dummy metal block on the first metal layer and the dummy metal block on the second metal layer.
  • the target signal line 107 is selected from at least one signal line according to the layout of at least one signal line, and the signal line closest to the boundary of the signal line sparse area in the signal line dense area can be selected as the target signal line 107.
  • the distance to the boundary of the signal line sparse area and the selection of the wiring direction of the signal line can also be combined, and the distance to the boundary of the signal line sparse area, the wiring direction of the signal line, and the selection of the signal type transmitted by the signal line can also be combined. There is no limit.
  • the projection of the dummy metal block on the substrate is in the shape of a quadrilateral.
  • the target signal line 107 is used to transmit the clock signal, and the clock signal has relatively high requirements on the rising/falling edge, and the signal line used to transmit the clock signal is used as the target signal line 107, which can reduce the time required for transmitting the clock signal.
  • the parasitic capacitance of the signal line ensures that the rising/falling edge of the clock signal is relatively steep.
  • Another embodiment of the present application provides a semiconductor structure, which includes a substrate, a first metal layer, a second metal layer, and a third metal layer.
  • the first metal layer is the bottom metal layer
  • the second metal layer is higher than the first metal layer
  • the third metal layer is higher than the second metal layer.
  • the first metal layer to the third metal layer are all provided with signal lines, and the first metal layer, the second metal layer and the third metal layer are all provided with a plurality of dummy metal blocks distributed in an array. Select the signal line on the first metal layer as the target signal line.
  • the first dummy metal block is located on the first metal layer, the second dummy metal block is located on the second metal layer, and the third dummy metal block is located on the third metal layer.
  • a projection of a virtual metal block on the third metal layer between the projections of two adjacent virtual metal blocks in the same row on the first metal layer, and two adjacent virtual metal blocks in the same column on the third metal layer
  • a projection of a virtual metal block on the second metal layer between the projections of adjacent virtual metal blocks, and the projection of the target signal line on the substrate is to the projection of the third virtual metal block on the substrate.
  • the third distance is equal to the second distance between the projection of the target signal line on the substrate and the projection of the second virtual metal block on the substrate.
  • the virtual metal blocks in the first metal layer to the third metal layer can be staggered in the direction perpendicular to the substrate, which can effectively reduce the parasitic capacitance between the virtual metal blocks.
  • the virtual metal blocks on the second and third metal layers are farther away from the target signal line, while the first layer The dummy metal block on the metal layer is closer to the target signal line, which ensures the uniformity of wiring on the target metal layer, and can also reduce the parasitic capacitance between the target signal line and the dummy metal blocks on other metal layers.
  • the dummy metal blocks on the third metal layer be located between the dummy metal blocks on the first metal layer, and let the dummy metal blocks on the second metal layer be located between the dummy metal blocks on the third metal layer,
  • the effective area of the parasitic capacitance between the dummy metal block on the first metal layer and the dummy metal block on the second metal layer can be reduced, thereby reducing the parasitic capacitance.

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Abstract

本申请提供一种半导体结构，包括：多层金属层和衬底，多层金属层包括第一层金属层，第二层金属层以及第三层金属层；金属层上设有多个虚拟金属块和至少一个信号线；金属层上的虚拟金属块在垂直于衬底的方向上相互错开；目标信号线在衬底上的投影到第二虚拟金属块在衬底上的投影之间的第二距离，大于目标信号线在衬底上的投影到第一虚拟金属块在衬底上的投影之间的第一距离；目标信号线位于第一层金属层；目标信号线在衬底上的投影到第三虚拟金属块在衬底上的投影之间的第三距离大于第一距离。本方案可减少虚拟金属块之间的寄生电容以及目标信号线上的寄生电容。

Description

半导体结构
本申请要求于2021年05月19日提交中国专利局、申请号为202110547455.5、申请名称为“半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限定于一种半导体结构。
背景技术
半导体集成电路器件包括部署有图形化金属的金属层，金属层上部分金属用于传输信号，例如：时钟信号、晶体管的控制端信号等。
随着半导体集成电路器件集成密度的增加，特别是在一些复杂的集成电路中，由于金属层上图形化金属产生的寄生效应，对金属层上的信号传输产生了延迟，从而导致半导体集成电路的性能降低。如何降低图形化金属上的寄生效应的影响成为亟待解决的问题。
发明内容
本申请提供一种半导体结构，包括：多层金属层和衬底，多层金属层包括第一层金属层，第二层金属层以及第三层金属层；
金属层上设有多个虚拟金属块和至少一个信号线；
金属层上的虚拟金属块在垂直于衬底的方向上相互错开；
目标信号线在衬底上的投影到第二虚拟金属块在衬底上的投影之间的第二距离，大于目标信号线在衬底上的投影到第一虚拟金属块在衬底上的投影之间的第一距离；目标信号线位于第一层金属层；
目标信号线在衬底上的投影到第三虚拟金属块在衬底上的投影之间的第三距离大于第一距离；
其中，第一虚拟金属块是第一层金属层中距离目标信号线最近的虚拟金属块，第二虚拟金属块是第二层金属层中距离目标信号线最近的虚拟金属块，第三虚拟金属块是第三层金属层中距离目标信号线最近的虚拟金属块。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
图1为本申请一实施例提供的半导体结构的主视图；
图2为本申请一实施例提供的信号线的布局示意图；
图3为本申请一实施例提供的半导体结构中金属层的制作示意图；
图4为本申请一实施例提供的信号线和虚拟金属块的布局示意图；
图5为本申请一实施例提供的半导体结构中虚拟金属块的布局示意图；
图6为图5所示实施例提供的半导体结构中虚拟金属块的布局示意图；
图7为本申请一实施例提供的信号线和虚拟金属块之间寄生电容的示意图；
图8为本申请一实施例提供的各层金属层中虚拟金属块的布局示意图。
通过上述附图，已示出本申请明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本申请构思的范围，而是通过参考特定实施例为本领域技术人员说明本申请的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
如图1所示，半导体结构包括衬底30、电子元器件20和多层金属层10，在衬底30上设有晶体管等电子元器件20。在电子元器件20的上面设置有多层金属层10，例如：高度依次递增的金属层M0、金属层Mn、金属层Mn+1以及金属层Mn+2，n为自然数，即金属层Mn高于金属层M0，金属层Mn+1高于金属层Mn，金属层Mn+2高于金属层Mn+1。各层金属层通过导电插塞40电连接。在部分金属层10上布置有信号线，用于实现各个电子元器件的相互连接，还用于将电子元器件与接地焊盘或者电源焊盘连接。
制作集成电路的信号线时通常采用干蚀刻工艺，典型的制作过程包括如下步骤：首先，绘制信号线的布局图案，再使用光刻工艺将信号线的布局图案转移到半导体基底上，其中，半导体基底是指待进行干蚀刻的半导体结构。然后，对半导体结构进行干蚀刻，将没有光刻介质覆盖的金属层或者介电层去除，即可形成所需半导体结构。
如图2所示，通常情况下每层信号线的分布是不均匀的，根据信号线的分布区域可以将每层分成信号线密集区103和信号线稀疏区104。金属线的分布不均匀会影响到半导体结构的制作过程。如图3所示，尤其是两层之间距离超过某一特定值时，在当前层106上再覆盖一层介电层105时，介电层105在信号线的稀疏区104会呈碟形，造成于信号线密集区103与信号线稀疏区104的介电层厚度明显不同。
干蚀刻工艺为一种化学或化学和机械混合的工艺，其蚀刻速率与半导体基底上组件的密度有关。由于半导体基底上信号线的密度不均匀，导致信号线密度高的地方与密度低的地方的蚀刻率显著不同，造成蚀刻上的困难，此即所谓的负载效应。
而且，影响蚀刻工艺的另一个因素为后续形成的介电层105的厚度。由于半导体基底上的信号线的密度不同，会在信号线稀疏的区域形成碟形形状，使得进行介电层蚀刻工艺时蚀刻终点不易探测，从而导致过度蚀刻或未达蚀刻终点就停止蚀刻的现象发生。进而影响制作半导体结构过程中的良率。
如图4所示，为了克服由于信号线不均匀而引起的问题，通常会在每层的信号线稀疏区布置虚拟金属块，以使信号线密集区域的密度与信号线稀疏区域的密度相同。与信号线不同的是，虚拟金属块不传输信号。
虚拟金属块可以接地、连接电源或为浮空状态。由于虚拟金属块接地、或连接电源时会增加寄生电容值，通常情况下虚拟金属块处于浮空状态。需要说明地是，此处不限制虚拟金属块的连接状态。
本申请一实施例提供一种半导体结构，包括衬底30和多层金属层10，其中，每层金属层上设有信号线，在信号线分布不均匀的金属层上设有虚拟金属块，以使金属层上布线均匀。
以相邻的三个金属层，金属层Mn，金属层Mn+1和金属层Mn+2为 例说明。金属层Mn，金属层Mn+1和金属层Mn+2上均部署有信号线，且三个金属层上的信号线的分布不均匀。也就是每层上有信号线密集区和信号线稀疏区。
图5和图6为同一半导体结构的俯视图，图5为金属层Mn和金属层Mn+1的虚拟金属块的布局图，图6为金属层Mn+1和金属层Mn+2的虚拟金属块的布局图。
如图5所示，在金属层Mn上部署呈阵列布置的虚拟金属块。且金属层Mn上每个虚拟金属块沿着第一方向部署，例如：第一方向为从上到下的方向部署。
在金属层Mn+1上部署呈阵列布置的虚拟金属块。且金属层Mn+1上每个虚拟金属块沿着第二方向部署，第一方向与第二方向不同，例如：第二方向为从左到右的方向部署。金属层Mn的虚拟金属块在衬底上的投影与金属层Mn+1的虚拟金属块在衬底上的投影部分重叠。
如图6所示，在金属层Mn+1上部署呈阵列布置的虚拟金属块。且金属层Mn+1上每个虚拟金属块沿着第二方向部署。在金属层Mn+2上部署呈阵列布置的虚拟金属块。且金属层Mn+2上每个虚拟金属块沿着第一方向部署，金属层Mn的虚拟金属块在衬底上的投影与金属层Mn+2的虚拟金属块在衬底上的投影完全重叠。
通过上述布置可以有效补偿金属层Mn，金属层Mn+1和金属层Mn+2的布线密度，使得各层金属层布线更加均匀。
然而，图5和图6所示的半导体结构在信号线上引入比较大的寄生电容。如图7所示，信号线102与同层虚拟金属块101产生的寄生电容C1，信号线102与位于Mn+1层的正上方的虚拟金属块101产生的寄生电容C2，信号线102与位于Mn+1层的右上方的虚拟金属块101产生的寄生电容C3，信号线102与位于Mn+2层的正上方的虚拟金属块101产生的寄生电容C4，信号线102与位于Mn+2层的右上方的虚拟金属块101产生的寄生电容C5。
还需要说明的是，除了金属信号线上产生的寄生电容，虚拟金属块之间也会产生寄生电容。尤其是在虚拟金属块在衬底上的投影相互重叠时，寄生电容比较大。当虚拟金属块之间的寄生电容较大时，虚拟金属块上容易在制造过程中收集电荷，从而影响半导体结构制造的良率。
如图8所示，本申请一实施例提供一种半导体结构，该半导体结构包括多层金属层10和衬底30。每个金属层上设置有信号线，在信号线分布不均匀的金属层上部署有虚拟金属块。
其中，金属层上的虚拟金属块在垂直于衬底的方向上相互错开，也就是部署有虚拟金属块的所有金属层上的虚拟金属块在垂直于衬底的方向上相互错开。例如：半导体结构设有L层金属层，在金属层Mn至金属层Mn+2上部署有虚拟金属块，金属层Mn上的虚拟金属块与金属层Mn+1上的虚拟金属块相互错开，金属层Mn上的虚拟金属块与金属层Mn+2上的虚拟金属块相互错开，金属层Mn+1上的虚拟金属块与金属层Mn+2上的虚拟金属块相互错开。其中，n+2≤L，n和L均为正整数。由于虚拟金属块的相互错开，可以减少虚拟金属块之间产生寄生电容的有效面积，从而可以减少虚拟金属块之间的寄生电容，减少在制造过程中虚拟金属块上收集的电荷，进而提升半导体结构制造的良率。
其中，多层金属层包括第一层金属层，第二层金属层以及第三层金属层。三个金属层的高度关系可以是任意的，也就是，可以是第一层金属层高于第二层金属层，第二层金属层高于第三层金属层。也可以是第一层金属层低于第二层金属层，第二层金属层低于第三层金属层。也可以是第二层金属层高于第一层金属层，第一层金属层高于第三层金属层。此处不做限制。
例如：第一层金属层为金属层Mn，第二层金属层为金属层Mn+1，第三层金属层为金属层Mn+2。
从位于第一层金属层上的至少一个信号线中选择一个信号线作为目标信号线107，并将第一层金属层中距离目标信号线107最近的虚拟金属块标记为第一虚拟金属块108。将第二金属层上的中距离目标信号线107最近的虚拟金属块标记为第二虚拟金属块109，将第三金属层上的中距离目标信号线107最近的虚拟金属块标记为第三虚拟金属块110。
需要说明的是，在计算各个虚拟金属块到目标信号线107之间的距离时，可以计算虚拟金属块在衬底上的投影的几何中心到目标信号线107在衬底上的投影的几何中心的距离。
其中，目标信号线在衬底上的投影到第二虚拟金属块在衬底上的投影 之间的第二距离，大于目标信号线在衬底上的投影到第一虚拟金属块在衬底上的投影之间的第一距离，目标信号线在衬底上的投影到第三虚拟金属块在衬底上的投影之间的第三距离大于第一距离。相较于第一虚拟金属块到目标信号线的距离，第二虚拟金属块到目标信号线的距离和第三虚拟金属块到目标信号线的距离更远，可以减少目标信号线和第二层金属层上虚拟金属块之间的寄生电容，也可以减少目标信号线和第三层金属层上虚拟金属块之间的寄生电容，又第一虚拟金属块108到目标信号线107之间的距离更近，可以保证第一层金属层上布线均匀性。
在上述技术方案中，通过让各层金属层中虚拟金属块在垂直于衬底方向上错开，可以有效减少虚拟金属块之间的寄生电容，在保证让各层金属层中虚拟金属块在垂直于衬底方向上错开前提下，让第二层金属层和第三层金属层上的虚拟金属块距离目标信号线更远，而让第一层金属层上的虚拟金属块距离目标信号线更近，保证第一层金属层上布线均匀性，也可以减少目标信号线和第二层金属层、第三层金属层上的虚拟金属块之间的寄生电容，从而提高了目标信号线上传输的信号的质量。
在一实施例中，多层金属层上的虚拟金属块在衬底的投影不重叠，也就是部署有虚拟金属块的所有金属层上的虚拟金属块在衬底的投影不重叠。可以更进一步的减少任意两个虚拟金属块之间产生寄生电容的有效面积，从而减少任意两个虚拟金属块之间的寄生电容。
在一实施例中，每层金属层上的虚拟金属块呈阵列分布，可以提升每层金属层上布线均匀性，避免在制作半导体结构时产生碟形的金属层，提升半导体结构的良率。
在一实施例中，第一层金属层上的虚拟金属块在衬底上的投影矩阵和其他金属层上的虚拟金属块在衬底上的投影矩阵相互交叉布置，其中，其他金属层是第一层金属层以外的金属层。也就是，其他金属层上的部分或者全部的虚拟金属块在衬底上的投影位于第一层金属层上的两个虚拟金属块在衬底上的投影之间，也可以是第一层金属层上的部分或者全部的虚拟金属块在衬底上的投影位于其他金属层上的两个虚拟金属块在衬底上的投影之间。通过如此设置，保证各层金属层上的虚拟金属块在衬底上的投影不会重叠，减少虚拟金属块之间的寄生电容，也可以使每层金属层中 布线均匀，提升半导体结构的良率。
在一实施例中，第一层金属层上的虚拟金属块的投影之间有一个第三层金属层上的虚拟金属块的投影，一方面保证第三层金属层上第三虚拟金属块到目标信号线的距离大于第一层金属层上第一虚拟金属块到目标信号线的距离，减少目标信号线和第三层金属层上的虚拟金属块之间的寄生电容，可以进一步减少由于让虚拟金属块错开设置而影响第一层金属层和第三层金属层布线均匀性，使得第一层金属层和第三层金属层布线更加均匀。
在一实施例中，第一层金属层上的位于同一行的相邻虚拟金属块的投影之间有一个第三层金属层上的虚拟金属块的投影。继续参考图8，金属层Mn上的同一行的相邻虚拟金属块的投影之间有一个金属层Mn+2上的虚拟金属块的投影。通过如此设置，可以充分利用第一层金属层上两个相邻虚拟金属块之间的间隙，在保证各层虚拟金属块错开的前提下使得每层金属层布线均匀。
在一实施例中，第一层金属层上的两个相邻的虚拟金属块的投影和第三层金属层上的虚拟金属块的投影相互接触，继续参考图8，金属层Mn上的同一行的相邻虚拟金属块的投影和金属层Mn+2上的虚拟金属块的投影相互接触。通过如此设置，可以提升每层金属层上虚拟金属块的密度，从而在信号线的密集区和稀疏区差异较大时，可以有效平衡密集区和稀疏区的密度，保证各层金属层的布线均匀性。
在一实施例中，第三层金属层上的两个相邻的虚拟金属块的投影之间有一个第二层金属层上的虚拟金属块的投影。一方面保证第二层金属层上第二虚拟金属块到目标信号线的距离大于第一层金属层上第一虚拟金属块到目标信号线的距离，也保证第三层金属层上第三虚拟金属块到目标信号线的距离大于第一层金属层上第一虚拟金属块到目标信号线的距离，减少目标信号线和第二层金属层上的虚拟金属块、第三层金属层上的虚拟金属块之间的寄生电容，还可以进一步减少由于让虚拟金属块错开设置而影响第一层金属层、第二层金属层、第三层金属层布线均匀性，使得第一层金属层至第三层金属层布线更加均匀。
在一实施例中，第三层金属层上的位于同一列的相邻虚拟金属块的投 影之间有一个第二层金属层上的虚拟金属块的投影。继续参考图8，金属层Mn+2上的同一列的相邻虚拟金属块的投影之间有一个金属层Mn+1上的虚拟金属块的投影。通过如此设置，可以充分利用第三层金属层上两个相邻虚拟金属块之间的间隙，在保证各层虚拟金属块错开的前提下使得每层金属层布线均匀。
在一实施例中，第三层金属层上的两个相邻的虚拟金属块的投影和第二层金属层上的虚拟金属块的投影相互接触，继续参考图8，金属层Mn+2上的位于同一列的相邻虚拟金属块的投影和金属层Mn+1上的虚拟金属块的投影相互接触。通过如此设置，可以提升每层金属层上虚拟金属块的密度，从而在信号线的密集区和稀疏区差异较大时，可以有效平衡密集区和稀疏区的密度，保证各层金属层的布线均匀性。
在一实施例中，第一层金属层上的两个位于同一行的相邻虚拟金属块的投影之间有一个第三层金属层上的虚拟金属块的投影，第三层金属层上的两个位于同一列的相邻虚拟金属块的投影之间有一个第二层金属层上的虚拟金属块的投影，并使目标信号线在衬底上的投影到第三虚拟金属块在衬底上的投影之间的第三距离和目标信号线在衬底上的投影到第二虚拟金属块在衬底上的投影之间的第二距离相等，减少目标信号线和第二层金属层上的虚拟金属块、第三层金属层上的虚拟金属块之间的寄生电容，还可以使第一层金属层至第三层金属层布线更加均匀。
在一实施例中，第二层金属层高于第一层金属层，且第三层金属层高于第二层金属层，第一层金属层上的两个位于同一行的相邻虚拟金属块的投影之间有一个第三层金属层上的虚拟金属块的投影，第三层金属层上的两个位于同一列的相邻虚拟金属块的投影之间有一个第二层金属层上的虚拟金属块的投影。相较于第一层金属层上的虚拟金属块与第三层金属层上的虚拟金属块之间的寄生电容，第一层金属层上的虚拟金属块与第二层金属层上的虚拟金属块之间的寄生电容更大。通过让第三层金属层上的虚拟金属块的投影位于第一层金属层上的两个位于同一行的相邻虚拟金属块的投影之间，让第二层金属层上的虚拟金属块的投影位于第三层金属层上的两个位于同一列的相邻虚拟金属块的投影之间，减少第一层金属层上的虚拟金属块和第二层金属层上的虚拟金属块之间产生寄生电容的有效 面积，从而减少第一层金属层上的虚拟金属块与第二层金属层上的虚拟金属块之间的寄生电容。
在一实施例中，目标信号线107是根据至少一个信号线的布局，从至少一个信号线中选择的，可以选择信号线密集区中距离信号线稀疏区的边界最近的信号线为目标信号线107，还可以结合到信号线稀疏区的边界的距离和信号线的布线方向选择，还可以结合到信号线稀疏区的边界的距离、信号线的布线方向以及信号线所传输信号类型选择，此处不做限定。
在一实施例中，虚拟金属块在衬底的投影呈四边形，通过如此设置，在虚拟金属块呈阵列排布时可以充分利用信号线稀疏区的空间，从而平衡信号线稀疏区和信号线密集区的布线密度，使各层金属层上布线均匀，提升半导体结构的良率。
在一实施例中，目标信号线107用于传输时钟信号，时钟信号对于上升/下降沿要求比较高，将用于传输时钟信号的信号线作为目标信号线107，可以减少用于传输时钟信号的信号线的寄生电容，保证时钟信号的上升/下降沿比较陡。
本申请另一实施例提供一种半导体结构，该半导体结构包括衬底、第一层金属层，第二层金属层以及第三层金属层。其中，第一层金属层为底层金属层，第二层金属层高于第一层金属层，第三层金属层高于第二层金属层。
第一层金属层至第三层金属层上均设有信号线，第一层金属层、第二层金属层以及第三层金属层上均设有多个呈阵列分布的虚拟金属块。选择第一层金属层上的信号线作为目标信号线。第一虚拟金属块位于第一层金属层上，第二虚拟金属块位于第二层金属层上，第三虚拟金属块位于第三层金属层上。
第一层金属层上的位于同一行的两个相邻的虚拟金属块的投影之间有一个第三金属层上的虚拟金属块的投影，第三层金属层上的位于同一列的两个相邻的虚拟金属块的投影之间有一个第二金属层上的虚拟金属块的投影，并使目标信号线在衬底上的投影到第三虚拟金属块在衬底上的投影之间的第三距离等于目标信号线在衬底上的投影到第二虚拟金属块在衬底上的投影之间的第二距离。
在上述技术方案中，通过上述布局方式，可以使得第一层金属层至第三层金属层中虚拟金属块在垂直于衬底方向上错开，可以有效减少虚拟金属块之间的寄生电容，在保证让各层金属层中虚拟金属块在垂直于衬底方向上错开前提下，让第二层金属层和第三层金属层上的虚拟金属块距离目标信号线更远，而让第一层金属层上的虚拟金属块距离目标信号线更近，保证目标金属层上布线均匀性，也可以减少目标信号线和其他金属层上的虚拟金属块之间的寄生电容。让第三层金属层上的虚拟金属块位于第一层金属层的虚拟金属块之间，而让第二层金属层上的虚拟金属块位于第三层金属层上的虚拟金属块之间，可以减少第一层金属层上的虚拟金属块与第二层金属层上的虚拟金属块之间的寄生电容的有效面积，从而减少寄生电容。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求书指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求书来限制。

Claims (15)

  1. 一种半导体结构，其中，包括：多层金属层和衬底，所述多层金属层包括第一层金属层，第二层金属层以及第三层金属层；
    所述金属层上设有多个虚拟金属块和至少一个信号线；
    所述金属层上的虚拟金属块在垂直于所述衬底的方向上相互错开；
    目标信号线在所述衬底上的投影到第二虚拟金属块在所述衬底上的投影之间的第二距离，大于所述目标信号线在所述衬底上的投影到第一虚拟金属块在所述衬底上的投影之间的第一距离；所述目标信号线位于所述第一层金属层；
    所述目标信号线在所述衬底上的投影到第三虚拟金属块在所述衬底上的投影之间的第三距离大于所述第一距离；
    所述第一虚拟金属块是所述第一层金属层中距离所述目标信号线最近的虚拟金属块，所述第二虚拟金属块是所述第二层金属层中距离所述目标信号线最近的虚拟金属块，所述第三虚拟金属块是所述第三层金属层中距离所述目标信号线最近的虚拟金属块。
  2. 根据权利要求1所述的半导体结构，其中，所述多层金属层上的虚拟金属块在所述衬底的投影不重叠。
  3. 根据权利要求2所述的半导体结构，其中，每层金属层上的虚拟金属块呈阵列分布。
  4. 根据权利要求3所述的半导体结构，其中，所述第一层金属层上的所述虚拟金属块在所述衬底上的投影矩阵和其他金属层上的所述虚拟金属块在所述衬底上的投影矩阵相互交叉布置；
    所述其他金属层是所述第一层金属层以外的金属层。
  5. 根据权利要求4所述的半导体结构，其中，所述第一层金属层上的所述虚拟金属块的投影之间有一个所述第三层金属层上的所述虚拟金属块的投影。
  6. 根据权利要求5所述的半导体结构，其中，所述第一层金属层上的两个相邻的虚拟金属块是位于同一行的相邻虚拟金属块。
  7. 根据权利要求6所述的半导体结构，其中，所述第一层金属层上的两个相邻的虚拟金属块的投影和所述第三层金属层上的虚拟金属块的 投影相互接触。
  8. 根据权利要求4所述的半导体结构，其中，所述第三层金属层上的两个相邻的虚拟金属块的投影之间有一个所述第二层金属层上的虚拟金属块的投影。
  9. 根据权利要求8所述的半导体结构，其中，所述第三层金属层上的两个相邻的虚拟金属块是位于同一列的相邻虚拟金属块。
  10. 根据权利要求9所述的半导体结构，其中，所述第三层金属层上的两个相邻的虚拟金属块的投影和所述第二层金属层上的虚拟金属块的投影相互接触。
  11. 根据权利要求10所述的半导体结构，其中，所述第三距离和所述第二距离相等。
  12. 根据权利要求1至11中任意一项所述的半导体结构，其中，所述第二层金属层高于所述第一层金属层，且所述第三层金属层高于所述第二层金属层。
  13. 根据权利要求1至11中任意一项所述的半导体结构，其中，所述目标信号线是根据所述至少一个信号线的布局，从所述至少一个信号线中选择的。
  14. 根据权利要求1至11中任意一项所述的半导体结构，其中，所述虚拟金属块在所述衬底的投影呈四边形。
  15. 根据权利要求1至11中任意一项所述的半导体结构，其中，所述信号线用于传输时钟信号。
PCT/CN2021/120350 2021-05-19 2021-09-24 半导体结构 Ceased WO2022242000A1 (zh)

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CN1378266A (zh) * 2001-04-04 2002-11-06 华邦电子股份有限公司 产生金属层虚拟图案的方法
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