WO2022241960A1 - 接触电阻的测试方法及设备 - Google Patents

接触电阻的测试方法及设备 Download PDF

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Publication number
WO2022241960A1
WO2022241960A1 PCT/CN2021/113062 CN2021113062W WO2022241960A1 WO 2022241960 A1 WO2022241960 A1 WO 2022241960A1 CN 2021113062 W CN2021113062 W CN 2021113062W WO 2022241960 A1 WO2022241960 A1 WO 2022241960A1
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Prior art keywords
contact resistance
resistance
mos transistor
resistance value
temperature
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PCT/CN2021/113062
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English (en)
French (fr)
Inventor
林仕杰
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长鑫存储技术有限公司
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Priority to US17/491,950 priority Critical patent/US11703531B2/en
Publication of WO2022241960A1 publication Critical patent/WO2022241960A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices

Definitions

  • the embodiments of the present application relate to the technical field of semiconductors, and in particular to a method and equipment for testing contact resistance.
  • MOSFET Metal-Oxide Semiconductor Field Effect Transistor
  • MOS transistors In the process of measuring MOS transistors and extracting device models, it is usually necessary to test the electrical characteristics of MOS transistors, such as Idsat, Vtlin, Vtsat, Idlin, etc.
  • the contact resistance of MOS transistors In the DRAM manufacturing process, due to the coexistence of memory cells and MOS transistors in peripheral circuits, the contact resistance of MOS transistors is high, resulting in large parasitic resistances, which cannot be removed during measurement, resulting in limited test accuracy. Accurate electrical parameters and device models cannot be extracted.
  • the resistance value of the contact resistance will be affected by various factors, for example, the resistance value of the contact resistance will change with the change of the ambient temperature. Therefore, how to accurately measure the resistance value of the contact resistance to improve the test accuracy of the MOS transistor needs to be solved urgently.
  • Embodiments of the present application provide a contact resistance testing method and equipment, which can accurately measure the resistance value of the contact resistance, thereby improving the testing accuracy of MOS transistors.
  • the present application provides a contact resistance testing method for testing the contact resistance of a MOS transistor, the MOS transistor works in a linear region, and the method includes:
  • the first resistance value is the relationship between the resistance value of the channel resistance of the MOS transistor and the contact The sum of the resistance values of the resistors;
  • the resistance value of the contact resistance of the MOS transistor at each sampling temperature determine the calibration coefficient of the contact resistance at the current ambient temperature
  • the resistance value of the contact resistance at the current ambient temperature is determined according to the calibration coefficient, the resistance value per unit area of the contact resistance, and the area of the contact resistance.
  • the present application provides a contact resistance testing device for testing the contact resistance of a MOS transistor, the MOS transistor works in a linear region, and the device includes:
  • the first processing module is used to determine the functional relationship between the first resistance value of the MOS transistor at each sampling temperature and the channel width of the MOS transistor, and the first resistance value is the channel width of the MOS transistor.
  • the second processing module is configured to determine the resistance value of the contact resistance of the MOS transistor at each sampling temperature according to the functional relationship
  • the first calculation module is used to determine the calibration coefficient of the contact resistance at the current ambient temperature according to the resistance value of the contact resistance of the MOS transistor at each sampling temperature;
  • the second calculation module is configured to determine the resistance value of the contact resistance at the current ambient temperature according to the calibration coefficient, the resistance value per unit area of the contact resistance, and the area of the contact resistance.
  • the present application provides an electronic device, including: at least one processor and a memory;
  • the memory stores computer-executable instructions
  • the at least one processor executes the computer-executed instructions stored in the memory, so that the at least one processor executes the contact resistance testing method provided in the first aspect.
  • the present application provides a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the processor executes the computer-executable instructions, the contact resistance as provided in the first aspect is realized. testing method.
  • the present application provides a computer program product, including a computer program.
  • the computer program is executed by a processor, the method for testing contact resistance as provided in the first aspect is implemented.
  • the contact resistance testing method and equipment when testing the contact resistance of the MOS transistor operating in the linear region, determine the first resistance value of the MOS transistor at each sampling temperature and the channel width of the MOS transistor To determine the resistance value of the contact resistance of the MOS transistor at each sampling temperature; according to the resistance value of the contact resistance of the MOS transistor at each sampling temperature, determine the calibration coefficient of the contact resistance at the current ambient temperature , and then according to the calibration coefficient of the contact resistance at the current ambient temperature, the measurement results of the contact resistance are corrected to obtain the accurate resistance value of the contact resistance at the current ambient temperature, which can effectively eliminate the ambient temperature and parasitic effects on the measurement results of the contact resistance The resulting influence improves the measurement accuracy of the MOS transistor.
  • FIG. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an equivalent resistance of a MOS transistor in an embodiment of the present application
  • FIG. 3 is a schematic diagram of the curve between the gate voltage of the MOS transistor and the resistance value of the channel resistance in the embodiment of the present application;
  • FIG. 4 is a schematic flow chart of a method for testing contact resistance provided in the embodiments of the present application.
  • FIG. 5 is a schematic diagram of a function curve corresponding to the first resistance value of the MOS transistor at each sampling temperature and the channel width of the MOS transistor in the Cartesian coordinate system in the embodiment of the present application;
  • FIG. 6 is a schematic diagram of the function curve corresponding to the resistance value of the contact resistance of the MOS transistor at each sampling temperature and each sampling temperature in the Cartesian coordinate system in the embodiment of the present application;
  • FIG. 7 is a schematic diagram of program modules of a device for testing contact resistance provided in an embodiment of the present application.
  • Fig. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application.
  • the above-mentioned semiconductor device is formed based on a MOS transistor, specifically including:
  • P-type substrate 100 P-substrate, Psub for short
  • deep N well structure 200 deep n-well, DNW for short
  • P well structure 300 PWell for short
  • shallow trench isolation structure 400 shallow trench isolation, STI for short
  • the N+ implantation region 501 and the N+ implantation region 502 the polysilicon structure 600 (poly), the first contact resistor 701 and the second contact resistor 702 .
  • the N+ implantation region 501 and the N+ implantation region 502 are trapped inside the P well structure 300, the first contact resistance 701 is located above the N+ implantation region 501, and forms an ohmic contact with the N+ implantation region 501; the second contact resistance 702 is located in the N+ implantation region region 502 and forms an ohmic contact with the N+ implant region 502 .
  • the N+ implantation region 501 constitutes the source of the MOS transistor
  • the N+ implantation region 502 constitutes the drain of the MOS transistor
  • the polysilicon structure 600 constitutes the gate of the MOS transistor.
  • the electrical parameters of the MOS transistor can be extracted and modeled based on the BSIM4 test model.
  • the BSIM4 test model is a software simulation system based on physics, with the characteristics of accuracy, upgradeability, robustness, and language, which is used for test circuit simulation and CMOS technology development. It can provide standard circuit DC analysis, instantaneous analysis, exchange analysis and other data.
  • the resistance value of the contact resistance is crucial to the electrical characteristics of the MOS transistor, so It is also necessary to add the resistance value of the contact resistance of the MOS transistor to the parameter model. In the actual test process, the resistance value of the contact resistance will be affected by various factors, for example, the resistance value of the contact resistance will change with the change of the ambient temperature.
  • the embodiment of the present application provides a method for testing and extracting the contact resistance.
  • the contact resistance of the MOS transistor is determined at each sampling temperature.
  • determine the calibration coefficient of the contact resistance at the current ambient temperature and then correct the measurement results of the contact resistance according to the calibration coefficient of the contact resistance at the current ambient temperature, and obtain the accurate resistance of the contact resistance at the current ambient temperature. Value, so that the influence of ambient temperature and parasitic effects on the measurement results of the contact resistance can be effectively eliminated, and the measurement accuracy of the MOS transistor can be improved.
  • Specific embodiments can refer to the description in the following embodiments.
  • a MOS transistor generally has three working regions, which are a fully conducting region, a cutoff region and a linear region. Wherein, when the MOS transistor works in the linear region, the MOS transistor can be equivalent to a resistor, and its total resistance is the sum of the channel resistance and the contact resistance of the MOS transistor.
  • FIG. 2 is a schematic diagram of an equivalent resistance of a MOS transistor in the embodiment of the present application.
  • d represents a drain
  • s represents a source
  • g represents a gate.
  • the MOS transistor includes two contact resistors licon, one of which is connected to the source s of the MOS transistor, and the other contact resistor licon is connected to the drain d.
  • the total resistance Rtotal of the MOS transistor is the sum of the resistance Rch of the channel resistance and the resistance Rlicon of the two contact resistances licon.
  • the resistance value Rch of the channel resistance can be determined in the following way:
  • ⁇ eff represents the effective mobility
  • C ox represents the effective oxide capacitance
  • W represents the channel width
  • L represents the channel length
  • Vg represents the gate voltage
  • Von represents the threshold voltage
  • m represents the body effect coefficient
  • Vds represents the drain The voltage between d and source s.
  • FIG. 3 is a schematic diagram of the curve between the gate voltage of the MOS transistor and the resistance value of the channel resistance in the embodiment of the present application.
  • the MOS transistors always work in the linear region and the gate voltage is greater than a certain threshold, which will not be repeated in the following embodiments.
  • FIG. 4 is a schematic flowchart of a contact resistance testing method provided in the embodiment of the present application, which can be used to test the contact resistance of a MOS transistor operating in the linear region.
  • the method includes:
  • S401 Determine a functional relationship between a first resistance value of a MOS transistor at each sampling temperature and a channel width of the MOS transistor.
  • the above-mentioned first resistance value is the sum of the resistance value of the channel resistance and the resistance value of the contact resistance of the MOS transistor, that is, Rtotal.
  • multiple MOS transistor test units with different channel widths (device width) can be preset, and multiple different sampling temperatures can be set. Then at each sampling temperature, measure the first resistance value Rtotal of each MOS transistor test unit with different channel widths, and determine the first resistance value Rtotal and MOS of the MOS transistor at each sampling temperature according to the measurement results.
  • x1 represents the resistance coefficient of the channel resistance, which can be determined by the channel widths of the MOS transistor test units with different channel widths and the first resistance value Rtotal1 at the above-mentioned sampling temperature t1 .
  • the resistance value of the contact resistance of the MOS transistor at each sampling temperature can be obtained.
  • the resistance value of the contact resistance has a linear relationship with its ambient temperature
  • the above calibration coefficient can be used to characterize the relationship between the resistance change of the contact resistance and its ambient temperature. For example, it can be used to indicate the relative change of the resistance value when the ambient temperature of the above-mentioned contact resistance changes by 1 degree Celsius.
  • the above-mentioned resistance value per unit area of the contact resistance can be understood as the resistance value generated by the contact resistance in each unit area.
  • the measurement result of the contact resistance is corrected, which can effectively eliminate the influence of the ambient temperature and parasitic effects on the measurement result of the contact resistance, and improve the MOS Transistor measurement accuracy.
  • the first resistance value of the MOS transistor at each sampling temperature can be determined by measuring the first resistance value of the MOS transistor at each sampling temperature when the MOS transistor adopts different channel widths.
  • the functional relationship between the first resistance value at temperature and the channel width of the MOS transistor, and then according to the functional relationship, determine that the first resistance value of the MOS transistor at each sampling temperature is at a preset right angle to the channel width of the MOS transistor The corresponding function curve in the coordinate system.
  • FIG. 5 is a functional curve corresponding to the first resistance value of the MOS transistor at each sampling temperature and the channel width of the MOS transistor in the Cartesian coordinate system in the embodiment of the present application. schematic diagram.
  • L1, L2, L3, and L4 are the first resistance value Rtotal of the MOS transistor at four different sampling temperatures t1, t2, t3, and t4, respectively, corresponding to the channel width W of the MOS transistor in the Cartesian coordinate system function curve.
  • the intercepts of the above-mentioned function curves L1, L2, L3, and L4 in the vertical axis of the rectangular coordinate system can be determined as the resistance values of the contact resistance of the MOS transistor at each sampling temperature t1, t2, t3, and t4. That is, according to the above functional relationship, the value of 2Rlicon at each sampling temperature t1, t2, t3, t4 can be determined.
  • x is a fixed value, which can be determined by the slopes of the function curves L1, L2, L3, and L4 at each sampling temperature.
  • the resistance of the contact resistance is determined based on each sampling temperature and the resistance value of the contact resistance of the MOS transistor at each sampling temperature. Resistance temperature parameter between values and temperature.
  • each sampling temperature and the resistance value of the contact resistance of the MOS transistor at each sampling temperature are respectively input into the above-mentioned one-dimensional n-degree function, and several points can be obtained in the Cartesian coordinate system. Combined, the optimal value of the above-mentioned resistance temperature parameter tc can be obtained.
  • FIG. 6 is a schematic diagram of the function curve corresponding to the resistance value of the contact resistance of the MOS transistor at each sampling temperature and each sampling temperature in the Cartesian coordinate system in the embodiment of the present application.
  • the least squares method can be used to perform curve fitting on the above-mentioned unary n-degree function, or matlab software can be used to perform curve fitting on the above-mentioned one-variable n-degree function.
  • the embodiment of the present application does not limit the specific curve fitting method .
  • the calibration coefficient of the contact resistance at the current environment temperature can be calculated according to the preset standard temperature, the current environment temperature and the above resistance temperature parameter.
  • the calibration coefficient Rt of the contact resistance at the current ambient temperature can be obtained in the following way:
  • Te represents the current ambient temperature
  • some conventional temperature measurement methods may be used in this application to detect the ambient temperature of the current test environment.
  • Tn represents the above-mentioned standard temperature, which is set to standardize the measurement conditions to allow comparisons between different groups of data.
  • the standard temperature can be selected from an internationally recognized temperature referenced by many measurement models. Numerical values, such as the melting temperature of ice, that is, the freezing point of water: 0°C (273.15K).
  • Tc represents the above-mentioned resistance temperature parameter.
  • the calibration coefficient, the resistance value per unit area of the contact resistance at the standard temperature, and the area of the first contact resistance can be determined, Calculate the resistance value of the contact resistance at the current ambient temperature.
  • the resistance value Rdc of the first contact resistance at the current ambient temperature is calculated in the following manner:
  • the resistance value Rsc of the second contact resistance at the current ambient temperature is calculated by the following method:
  • Rc represents the resistance value per unit area of the contact resistance at the above-mentioned standard temperature
  • Rt represents the above-mentioned calibration coefficient
  • S1 represents the area of the first contact resistance
  • S2 represents the area of the second contact resistance.
  • the measurement result of the contact resistance is corrected according to the calibration coefficient of the contact resistance at the current ambient temperature. Obtaining the accurate resistance value of the contact resistance at the current ambient temperature can effectively eliminate the influence of the ambient temperature and parasitic effects on the measurement result of the contact resistance, and improve the measurement accuracy of the MOS transistor.
  • FIG. 7 is a schematic diagram of a program module of a contact resistance testing device provided in the embodiment of the present application, which is used to test the contact resistance of a MOS transistor, and the MOS transistor works online.
  • the test device for the above-mentioned contact resistance includes:
  • the first processing module 701 is configured to determine the functional relationship between the first resistance value of the MOS transistor at each sampling temperature and the channel width of the MOS transistor, where the first resistance value is the resistance value of the channel resistance of the MOS transistor The sum of resistance and contact resistance.
  • the second processing module 702 is configured to determine the resistance value of the contact resistance of the MOS transistor at each sampling temperature according to the above functional relationship.
  • the first calculation module 703 is configured to determine the calibration coefficient of the contact resistance at the current ambient temperature according to the resistance value of the contact resistance of the MOS transistor at each sampling temperature.
  • the second calculation module 704 is configured to determine the resistance value of the contact resistance at the current ambient temperature according to the calibration coefficient, the resistance value per unit area of the contact resistance, and the area of the contact resistance.
  • the contact resistance testing device when testing the contact resistance of the MOS transistor operating in the linear region, determines the difference between the first resistance value of the MOS transistor at each sampling temperature and the channel width of the MOS transistor. To determine the resistance value of the contact resistance of the MOS transistor at each sampling temperature; according to the resistance value of the contact resistance of the MOS transistor at each sampling temperature, determine the calibration coefficient of the contact resistance at the current ambient temperature, and then According to the calibration coefficient of the contact resistance at the current ambient temperature, the measurement results of the contact resistance are corrected to obtain the accurate resistance value of the contact resistance at the current ambient temperature, which can effectively eliminate the influence of the ambient temperature and parasitic effects on the measurement results of the contact resistance , to improve the measurement accuracy of the MOS transistor.
  • the first processing module 701 is used to:
  • the second processing module 702 is used to:
  • the first resistance value of the MOS transistor at each sampling temperature and the corresponding function curve of the channel width of the MOS transistor in a preset Cartesian coordinate system determines the resistance value of the contact resistance of the MOS transistor at each sampling temperature; wherein, the contact resistance of the MOS transistor and the channel used by the MOS transistor Lane width is not relevant.
  • the first calculating module 703 is used for:
  • the first calculating module 703 is used for:
  • the calibration coefficient Rt of the contact resistance at the current ambient temperature is obtained by the following method:
  • Te represents the current ambient temperature
  • Tn represents the standard temperature
  • Tc represents the resistance temperature parameter
  • the contact resistance includes a first contact resistance and a second contact resistance, the first contact resistance is connected to the drain of the MOS transistor, and the second contact resistance is connected to the source of the MOS transistor.
  • the second calculation module 704 is used for:
  • the resistance value per unit area of the contact resistance at standard temperature, and the area of the first contact resistance determine the first target resistance value of the first contact resistance at the current ambient temperature
  • the resistance value per unit area at temperature and the area of the second contact resistance determine the second target resistance value of the second contact resistance at the current ambient temperature
  • the second calculating module 704 is used for:
  • the first target resistance value Rdc is determined in the following manner:
  • the second target resistance value Rsc is determined in the following manner:
  • Rc represents the resistance value per unit area of the contact resistance at standard temperature
  • Rt represents the calibration coefficient
  • S 1 represents the area of the first contact resistance
  • S 2 represents the area of the second contact resistance.
  • each functional module in the above-mentioned contact resistance testing device correspond to each step in the contact resistance testing method described in the above-mentioned embodiment, therefore, in the above-mentioned contact resistance testing device
  • each step in the method for testing contact resistance described in the above-mentioned embodiments which will not be repeated here.
  • the embodiments of the present application also provide an electronic device, the electronic device includes at least one processor and a memory; wherein, the memory stores computer-executed instructions; the at least one processor executes memory-stored The computer executes the instruction to realize each step in the method for testing the contact resistance as described in the above-mentioned embodiment, and this embodiment will not repeat them here.
  • the embodiments of the present application also provide a computer-readable storage medium, the computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions, In order to realize each step in the method for testing the contact resistance as described in the above-mentioned embodiments.
  • the embodiments of the present application also provide a computer program product, the computer program product includes a computer program, when the computer program processor is executed by the processor, it can implement the above implementation Each step in the test method of contact resistance described in the example.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the modules is only a logical function division. In actual implementation, there may be other division methods, for example, multiple modules can be combined or integrated. to another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or modules may be in electrical, mechanical or other forms.
  • modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional module in each embodiment of the present application may be integrated into one processing unit, each module may exist separately physically, or two or more modules may be integrated into one unit.
  • the units formed by the above modules can be implemented in the form of hardware, or in the form of hardware plus software functional units.
  • the above-mentioned integrated modules implemented in the form of software function modules can be stored in a computer-readable storage medium.
  • the above-mentioned software functional modules are stored in a storage medium, and include several instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) or a processor (English: processor) to execute the functions described in various embodiments of the present application. part of the method.
  • processor can be a central processing unit (English: Central Processing Unit, referred to as: CPU), and can also be other general-purpose processors, digital signal processors (English: Digital Signal Processor, referred to as: DSP), application-specific integrated circuits (English: Application Specific Integrated Circuit, referred to as: ASIC), etc.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The steps of the method disclosed in conjunction with the application can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
  • the storage may include a high-speed RAM memory, and may also include a non-volatile storage NVM, such as at least one disk storage, and may also be a U disk, a mobile hard disk, a read-only memory, a magnetic disk, or an optical disk.
  • NVM non-volatile storage
  • the bus can be an Industry Standard Architecture (Industry Standard Architecture, ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus, etc.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into address bus, data bus, control bus and so on.
  • the buses in the drawings of the present application are not limited to only one bus or one type of bus.
  • the above-mentioned storage medium can be realized by any type of volatile or non-volatile storage device or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable In addition to programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read-only memory
  • EPROM programmable read-only memory
  • ROM read-only memory
  • magnetic memory magnetic memory
  • flash memory magnetic disk or optical disk.
  • a storage media may be any available media that can be accessed by a general purpose or special purpose computer.
  • An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
  • the storage medium may also be a component of the processor.
  • the processor and the storage medium may be located in Application Specific Integrated Circuits (ASIC for short).
  • ASIC Application Specific Integrated Circuits
  • the processor and the storage medium can also exist in the electronic device or the main control device as discrete components.
  • the aforementioned program can be stored in a computer-readable storage medium.
  • the program executes the steps including the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

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Abstract

一种接触电阻的测试方法及设备，在测试工作在线性区的MOS晶体管的接触电阻时，通过确定MOS晶体管在各个采样温度下的总阻值与MOS晶体管的沟道宽度之间的函数关系，来确定出MOS晶体管的接触电阻在各个采样温度下的阻值；根据MOS晶体管的接触电阻在各个采样温度下的阻值，确定出接触电阻在当前环境温度下的校准系数，进而根据接触电阻在当前环境温度下的校准系数，对接触电阻的测量结果进行校正，得到接触电阻在当前环境温度下的准确阻值。

Description

接触电阻的测试方法及设备
本申请要求于2021年05月20日提交中国专利局、申请号为202110551274.X、申请名称为“接触电阻的测试方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种接触电阻的测试方法及设备。
背景技术
金属-氧化物半导体场效应晶体管(Metal-Oxide Semiconductor Field Effect Transistor,简称MOSFET)又称MOS晶体管，是半导体器件制造过程中最基本的元器件，已经广泛应用于各种集成电路中。
在MOS晶体管量测及提取器件模型过程中，通常需要对MOS晶体管的电学特性进行测试，比如Idsat、Vtlin、Vtsat、Idlin等。在DRAM制备过程中，由于存储单元和外围电路中的MOS晶体管并存，使得MOS晶体管的接触电阻阻值较高，造成较大的寄生电阻，且在量测中无法去除，导致测试精度受限，无法提取出准确的电学参数和器件模型。
在实际测试接触电阻的过程中，接触电阻的阻值会受到多种因素的影响，例如，接触电阻的阻值会随着环境温度的变化而变化。因此，如何准确测量接触电阻的阻值以提升MOS晶体管的测试精确度，目前亟需解决。
发明内容
本申请实施例提供一种接触电阻的测试方法及设备，可以准确测量接触电阻的阻值，从而提升MOS晶体管的测试精确度。
第一方面，本申请提供一种接触电阻的测试方法，用于测试MOS晶体管的接触电阻，该MOS晶体管工作在线性区，所述方法包括：
确定所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度之间的函数关系，所述第一阻值为所述MOS晶体管的沟道电阻的阻值与接触电阻的阻值之和；
根据所述函数关系，确定所述MOS晶体管的接触电阻在所述各个采 样温度下的阻值；
根据所述MOS晶体管的接触电阻在所述各个采样温度下的阻值，确定所述接触电阻在当前环境温度下的校准系数；
根据所述校准系数、所述接触电阻的单位面积电阻值、所述接触电阻的面积，确定所述接触电阻在当前环境温度下的阻值。
第二方面，本申请提供一种接触电阻的测试装置，用于测试MOS晶体管的接触电阻，该MOS晶体管工作在线性区，所述装置包括：
第一处理模块，用于确定所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度之间的函数关系，所述第一阻值为所述MOS晶体管的沟道电阻的阻值与接触电阻的阻值之和；
第二处理模块，用于根据所述函数关系，确定所述MOS晶体管的接触电阻在所述各个采样温度下的阻值；
第一计算模块，用于根据所述MOS晶体管的接触电阻在所述各个采样温度下的阻值，确定所述接触电阻在当前环境温度下的校准系数；
第二计算模块，用于根据所述校准系数、所述接触电阻的单位面积电阻值、所述接触电阻的面积，确定所述接触电阻在当前环境温度下的阻值。
第三方面，本申请提供一种电子设备，包括：至少一个处理器和存储器；
所述存储器存储计算机执行指令；
所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如第一方面提供的接触电阻的测试方法。
第四方面，本申请提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，实现如第一方面提供的接触电阻的测试方法。
第五方面，本申请提供一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时，实现如第一方面提供的接触电阻的测试方法。
本申请实施例所提供的接触电阻的测试方法及设备，在测试工作于线性区的MOS晶体管的接触电阻时，通过确定MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度之间的函数关系，来确定出MOS晶体管的接触电阻在各个采样温度下的阻值；根据MOS晶体管的接触电 阻在各个采样温度下的阻值，确定出接触电阻在当前环境温度下的校准系数，进而根据接触电阻在当前环境温度下的校准系数，对接触电阻的测量结果进行校正，得到接触电阻在当前环境温度下的准确阻值，可以有效消除环境温度以及寄生效应对接触电阻的测量结果产生的影响，提升MOS晶体管的测量精确度。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对本申请实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。
图1为本申请实施例中提供的一种半导体器件的结构示意图；
图2为本申请实施例中MOS晶体管的等效电阻示意图；
图3为本申请实施例中MOS晶体管的栅极电压与沟道电阻的阻值之间的曲线示意图；
图4为本申请实施例中提供的一种接触电阻的测试方法的流程示意图；
图5为本申请实施例中MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度在直角坐标系中对应的函数曲线示意图；
图6为本申请实施例中MOS晶体管的接触电阻在各个采样温度下的阻值与各个采样温度在直角坐标系中对应的函数曲线示意图；
图7为本申请实施例中提供的一种接触电阻的测试装置的程序模块示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
MOS晶体管作为半导体器件制造过程中最基本的元器件，已经广泛应用于各种集成电路中。参见图1，图1为本申请实施例中提供的一种半导 体器件的结构示意图，在图1中，上述半导体器件基于MOS晶体管构成，具体包括：
P型衬底100(P-substrate，简称Psub)、深N阱结构200(deep n-well，简称DNW)、P阱结构300(简称PWell)、浅槽隔离结构400(shallow trench isolation，简称STI)、N+注入区501与N+注入区502、多晶硅结构600(poly)、第一接触电阻701以及第二接触电阻702。
其中，N+注入区501与N+注入区502陷入P阱结构300的内部，第一接触电阻701位于N+注入区501的上方，并与N+注入区501形成欧姆接触；第二接触电阻702位于N+注入区502的上方，并与N+注入区502形成欧姆接触。
其中，N+注入区501构成MOS晶体管的源极，N+注入区502构成MOS晶体管的漏极，多晶硅结构600构成MOS晶体管的栅极。
在一些实施例中，在对MOS晶体管进行测试时，可以基于BSIM4测试模型对MOS晶体管的电学参数进行提取、建模。其中，BSIM4测试模型是一种用于测试电路仿真和CMOS技术发展的一种基于物理的、具有精确性、可升级性、健壮性、语言性等特点的软件模拟系统，能提供标准电路的直流分析，瞬时分析，交流分析等数据。
在一些实施例中，在基于上述BSIM4测试模型对MOS晶体管进行参数提取时，由于量测时无法去除接触电阻的影响，接触电阻的阻值大小对MOS晶体管的电学特性而言至关重要，因此需要在参数模型中也添加MOS晶体管的接触电阻的阻值。而在实际测试过程中，接触电阻的阻值会受到多种因素的影响，例如，接触电阻的阻值会随着环境温度的变化而变化。
为了更加准确的测量和提取接触电阻的阻值，本申请实施例提供了一种接触电阻的测试及提取方法，在MOS晶体管工作于线性区时，确定出MOS晶体管的接触电阻在各个采样温度下的阻值；同时确定接触电阻在当前环境温度下的校准系数，进而根据接触电阻在当前环境温度下的校准系数，对接触电阻的测量结果进行校正，得到接触电阻在当前环境温度下的准确阻值，从而可以有效消除环境温度以及寄生效应对接触电阻的测量结果产生的影响，提升MOS晶体管的测量精确度。具体实施方式可以参加以下实施例中的描述。
可以理解的是，MOS晶体管通常具有三个工作区，分别为完全导通区、截止区以及线性区。其中，当MOS晶体管工作在线性区时，MOS晶体管可以等效为一个电阻，其总阻值为MOS晶体管的沟道电阻的阻值与接触电阻的阻值之和。
为了更好的理解本申请实施例，参照图2，图2为本申请实施例中MOS晶体管的等效电阻示意图。
在图2中，d表示漏极，s表示源极，g表示栅极。MOS晶体管包括两个接触电阻licon，其中一个接触电阻licon与MOS晶体管的源极s连接，另一个接触电阻licon与漏极d连接。
当MOS晶体管工作在线性区时，MOS晶体管的总阻值Rtotal为沟道电阻的阻值Rch与两个接触电阻licon的阻值Rlicon之和。
即：
Rtotal＝Rch+2Rlicon
基于MOS晶体管的特性，沟道电阻的阻值Rch可以通过以下方式确定：
Figure PCTCN2021113062-appb-000001
其中，μ eff表示有效迁移率，C ox表示有效氧化物电容，W表示沟道宽度，L表示沟道长度，Vg表示栅极电压，Von表示阈值电压，m表示体效应系数，Vds表示漏极d与源极s之间的电压。
参照图3，图3为本申请实施例中MOS晶体管的栅极电压与沟道电阻的阻值之间的曲线示意图。
从图3中可知，在MOS晶体管工作在线性区的情况下，当栅极电压Vg大于一定的阈值(如Vt)时，MOS晶体管的沟道电阻的阻值(图3中所示Rds)会趋于一固定值，即此时
Figure PCTCN2021113062-appb-000002
的值为固定值，沟道电阻的阻值Rch与沟道宽度W成反比例关系。
需要说明的是，本申请实施例中所提供的接触电阻的测试方法，MOS晶体管始终工作在线性区、且栅极电压大于一定阈值，以下实施例中不再 赘述。
参照图4，图4为本申请实施例中提供的一种接触电阻的测试方法的流程示意图，可以用于测试工作在线性区的MOS晶体管的接触电阻，在本申请一种可行的实施方式中，该方法包括：
S401、确定MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度之间的函数关系。
其中，上述第一阻值为MOS晶体管的沟道电阻的阻值与接触电阻的阻值之和，即Rtotal。
本实施例中，可以预先设置多种具有不同沟道宽度(device width)的MOS晶体管测试单元(testkey)，以及设置多个不同的采样温度。然后在每个采样温度下，分别测量各个具有不同沟道宽度的MOS晶体管测试单元的第一阻值Rtotal，并根据测量结果，确定出MOS晶体管在各个采样温度下的第一阻值Rtotal与MOS晶体管的沟道宽度W之间的函数关系。
S402、根据上述函数关系，确定MOS晶体管的接触电阻在各个采样温度下的阻值。
在本申请实施例中，假设在某个采样温度t1下，MOS晶体管的第一阻值Rtotal 1与MOS晶体管的沟道宽度W之间的函数关系为：
Figure PCTCN2021113062-appb-000003
其中，x1表示沟道电阻的阻值系数，可以由各个具有不同沟道宽度的MOS晶体管测试单元的沟道宽度与在上述采样温度t1下的第一阻值Rtotal 1确定。
由于Rtotal＝Rch+2Rlicon，且MOS晶体管的接触电阻的阻值与沟道宽度不相关，因此根据上述函数关系即可确定出MOS晶体管的各个接触电阻licon在上述采样温度t1下的阻值为
Figure PCTCN2021113062-appb-000004
同理，采样相同的计算方式，即可得到MOS晶体管的接触电阻在各个采样温度下的阻值。
S403、根据MOS晶体管的接触电阻在各个采样温度下的阻值，确定接触电阻在当前环境温度下的校准系数。
在半导体结构中，接触电阻的阻值在与它所在的环境温度具有线性关系，上述校准系数可以用来表征接触电阻的阻值变化量和它所在的环境温度之间的关系。例如，可以用于表示当上述接触电阻所在的环境温度改变1摄氏度时，其电阻值的相对变化量。
S404、根据上述校准系数、接触电阻的单位面积电阻值、接触电阻的面积，确定接触电阻在当前环境温度下的阻值。
可以理解的是，在温度一定的情况下，常规材料的电阻值R与材料的长度L成正比，与材料的面积S成反比，通常表示为：R＝ρL/S，其中，ρ表示材料的电阻率。
在一些实施例中，上述接触电阻的单位面积电阻值可以理解为是接触电阻在每个单位面积内所产生的电阻值。
可以理解的是，本申请实施例中根据接触电阻在当前环境温度下的校准系数，对接触电阻的测量结果进行校正，可以有效消除环境温度以及寄生效应对接触电阻的测量结果的影响，提升MOS晶体管的测量精确度。
基于上述实施例中所描述的内容，在一种可行的实施方式中，可以先通过分别测量MOS晶体管采用不同沟道宽度时，在各个采样温度下的第一阻值，确定MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度之间的函数关系，然后根据该函数关系，确定MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度在预设直角坐标系中对应的函数曲线。
为了更好地理解本申请实施例，参照图5，图5为本申请实施例中MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度在直角坐标系中对应的函数曲线示意图。
在图5中，L1、L2、L3、L4分别为MOS晶体管在4个不同采样温度t1、t2、t3、t4下的第一阻值Rtotal与MOS晶体管的沟道宽度W在直角坐标系中对应的函数曲线。
由于MOS晶体管的第一阻值Rtotal与MOS晶体管的沟道宽度W之间的函数关系为：
Figure PCTCN2021113062-appb-000005
因此，可以将上述函数曲线L1、L2、L3、L4在直角坐标系纵轴中的 截距，确定为MOS晶体管的接触电阻在各个采样温度t1、t2、t3、t4下的阻值。即根据上述函数关系，即可确定出在各个采样温度t1、t2、t3、t4下2Rlicon的值。其中，x为固定值，可以由各个采样温度下的函数曲线L1、L2、L3、L4的斜率确定。
在一种可行的实施方式中，在确定MOS晶体管的接触电阻在各个采样温度下的阻值之后，基于各个采样温度以及MOS晶体管的接触电阻在各个采样温度下的阻值,确定接触电阻的阻值与温度之间的电阻温度参数。
示例性的，假设tc表示上述电阻温度参数，tx表示采样温度，则接触电阻的电阻值R与tc、tx的关系可以通过一个一元n次函数来表示。例如：
R＝tc*tx+C，C为预设系数；
在一种可行的实施方式中，将各个采样温度以及MOS晶体管的接触电阻在各个采样温度下的阻值分别输入上述一元n次函数，即可在直角坐标系中获得若干个点，通过曲线拟合，即可得到上述电阻温度参数tc的最佳取值。
为了更好地理解本申请实施例，参照图6，图6为本申请实施例中MOS晶体管的接触电阻在各个采样温度下的阻值与各个采样温度在直角坐标系中对应的函数曲线示意图。
可选的，可以采用最小二乘法对上述一元n次函数进行曲线拟合，也可以采用matlab软件对上述一元n次函数进行曲线拟合，本申请实施例对具体的曲线拟合方式不做限定。
在一种可行的实施方式中，在确定上述电阻温度参数之后，即可根据预设的标准温度、当前环境温度以及上述电阻温度参数，计算出接触电阻在当前环境温度下的校准系数。
可选的，可以通过以下方式得到接触电阻在当前环境温度下的校准系数Rt：
Rt＝1+(Te-Tn)*Tc
其中，Te表示当前环境温度，本申请中可以采用一些常规的测温方式，来检测当前测试环境的环境温度。
Tn表示上述标准温度，该标准温度是为了使测量条件标准化而设定的， 以允许在不同组数据之间进行比较，可选的，该标准温度可以选用一个被许多测量模型所引用的国际公认数值，例如冰的熔化温度，即水的凝点：0℃(273.15K)。
Tc表示上述电阻温度参数。
在一种可行的实施方式中，在确定出接触电阻在当前环境温度下的校准系数之后，即可根据该校准系数、接触电阻在标准温度下的单位面积电阻值、第一接触电阻的面积，计算出接触电阻在当前环境温度下的阻值。
示例性的，通过以下方式计算第一接触电阻在当前环境温度下的阻值Rdc：
Rdc＝Rc*Rt*1/S 1
通过以下方式计算第二接触电阻在当前环境温度下的阻值Rsc：
Rsc＝Rc*Rt*1/S 2
其中，Rc表示接触电阻在上述标准温度下的单位面积电阻值，Rt表示上述校准系数，S 1表示第一接触电阻的面积，S 2表示第二接触电阻的面积。
可以理解的是，在一些实施方式中，MOS晶体管的接触结构可能会连接多条金属导线，因此，当MOS晶体管的接触结构连接多条金属导线时，S 1＝N 1*S 1’，S 2＝N 2*S 2’。其中，N 1、N 2分别表示第一接触电阻与第二接触电阻所采用金属导线的根数，S 1’、S 2’分别表示第一接触电阻与第二接触电阻所采用金属导线的的面积。
本申请实施例所提供的接触电阻的测试方法，在测试工作在线性区的MOS晶体管的接触电阻时，根据接触电阻在当前环境温度下的校准系数，对接触电阻的测量结果进行校正，即可得到接触电阻在当前环境温度下的准确阻值，可以有效消除环境温度以及寄生效应对接触电阻的测量结果的影响，提升MOS晶体管的测量精确度。
基于上述实施例中所描述的内容，参照图7，图7为本申请实施例中提供的一种接触电阻的测试装置的程序模块示意图，用于测试MOS晶体管的接触电阻，该MOS晶体管工作在线性区，在本申请实施例中，上述接触电阻的测试装置包括：
第一处理模块701，用于确定MOS晶体管在各个采样温度下的第一阻 值与MOS晶体管的沟道宽度之间的函数关系，所述第一阻值为MOS晶体管的沟道电阻的阻值与接触电阻的阻值之和。
第二处理模块702，用于根据上述函数关系，确定MOS晶体管的接触电阻在各个采样温度下的阻值。
第一计算模块703，用于根据MOS晶体管的接触电阻在各个采样温度下的阻值，确定接触电阻在当前环境温度下的校准系数。
第二计算模块704，用于根据上述校准系数、接触电阻的单位面积电阻值、接触电阻的面积，确定接触电阻在当前环境温度下的阻值。
本申请实施例所提供的接触电阻的测试装置，在测试工作在线性区的MOS晶体管的接触电阻时，通过确定MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度之间的函数关系，来确定出MOS晶体管的接触电阻在各个采样温度下的阻值；根据MOS晶体管的接触电阻在各个采样温度下的阻值，确定出接触电阻在当前环境温度下的校准系数，进而根据接触电阻在当前环境温度下的校准系数，对接触电阻的测量结果进行校正，得到接触电阻在当前环境温度下的准确阻值，可以有效消除环境温度以及寄生效应对接触电阻的测量结果的影响，提升MOS晶体管的测量精确度。
在一种可行的实施方式中，第一处理模块701用于：
分别测量所述MOS晶体管采用不同沟道宽度时，在各个采样温度下的第一阻值；根据MOS晶体管采用不同沟道宽度时，在各个采样温度下的第一阻值，确定MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度之间的函数关系。
在一种可行的实施方式中，第二处理模块702用于：
根据上述函数关系，确定MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度在预设直角坐标系中对应的函数曲线；根据MOS晶体管在各个采样温度下的第一阻值与MOS晶体管的沟道宽度在预设直角坐标系中对应的函数曲线的截距，确定MOS晶体管的接触电阻在各个采样温度下的阻值；其中，MOS晶体管的接触电阻与MOS晶体管采用的沟道宽度不相关。
在一种可行的实施方式中，第一计算模块703用于：
基于各个采样温度以及MOS晶体管的接触电阻在各个采样温度下的阻值,确定接触电阻的阻值与温度之间的电阻温度参数；根据预设的标准温度、当前环境温度以及电阻温度参数，得到接触电阻在当前环境温度下的校准系数。
在一种可行的实施方式中，第一计算模块703用于：
通过以下方式得到接触电阻在当前环境温度下的校准系数Rt：
Rt＝1+(Te-Tn)*Tc
其中，Te表示当前环境温度，Tn表示标准温度，Tc表示电阻温度参数。
在一种可行的实施方式中，接触电阻包括第一接触电阻与第二接触电阻，第一接触电阻与MOS晶体管的漏极连接，第二接触电阻与MOS晶体管的源极连接。
第二计算模块704用于：
根据上述校准系数、接触电阻在标准温度下的单位面积电阻值、第一接触电阻的面积，确定第一接触电阻在当前环境温度下的第一目标阻值；根据上述校准系数、接触电阻在标准温度下的单位面积电阻值、第二接触电阻的面积，确定第二接触电阻在当前环境温度下的第二目标阻值。
在一种可行的实施方式中，第二计算模块704用于：
通过以下方式确定第一目标阻值Rdc：
Rdc＝Rc*Rt*1/S 1
通过以下方式确定第二目标阻值Rsc：
Rsc＝Rc*Rt*1/S 2
其中，Rc表示接触电阻在标准温度下的单位面积电阻值，Rt表示校准系数，S 1表示第一接触电阻的面积，S 2表示第二接触电阻的面积。
可以理解的是，上述接触电阻的测试装置中的各个功能模块所实现的功能，与上述实施例中所描述的接触电阻的测试方法中的各个步骤相对应，因此，上述接触电阻的测试装置中的各个功能模块详细的实现过程，可以参照上述实施例中所描述的接触电阻的测试方法中的各个步骤，在此不再赘述。
基于上述实施例中所描述的内容，本申请实施例中还提供了一种电子 设备，该电子设备包括至少一个处理器和存储器；其中，存储器存储计算机执行指令；上述至少一个处理器执行存储器存储的计算机执行指令，以实现如上述实施例中描述的接触电阻的测试方法中的各个步骤，本实施例此处不再赘述。
基于上述实施例中所描述的内容，本申请实施例中还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，以实现如上述实施例中描述的接触电阻的测试方法中的各个步骤。
基于上述实施例中所描述的内容，本申请实施例中还提供了一种计算机程序产品，该计算机程序产品中包括计算机程序，当该计算机程序处理器被处理器执行时，可以实现如上述实施例中描述的接触电阻的测试方法中的各个步骤。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理单元中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个单元中。上述模块成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述以软件功能模块的形式实现的集成的模块，可以存储在一个计算机可读取存储介质中。上述软件功能模块存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络 设备等)或处理器(英文：processor)执行本申请各个实施例所述方法的部分步骤。
应理解，上述处理器可以是中央处理单元(英文：Central Processing Unit，简称：CPU)，还可以是其他通用处理器、数字信号处理器(英文：Digital Signal Processor，简称：DSP)、专用集成电路(英文：Application Specific Integrated Circuit，简称：ASIC)等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合申请所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
存储器可能包含高速RAM存储器，也可能还包括非易失性存储NVM，例如至少一个磁盘存储器，还可以为U盘、移动硬盘、只读存储器、磁盘或光盘等。
总线可以是工业标准体系结构(Industry Standard Architecture，ISA)总线、外部设备互连(Peripheral Component，PCI)总线或扩展工业标准体系结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，本申请附图中的总线并不限定仅有一根总线或一种类型的总线。
上述存储介质可以是由任何类型的易失性或非易失性存储设备或者它们的组合实现，如静态随机存取存储器(SRAM)，电可擦除可编程只读存储器(EEPROM)，可擦除可编程只读存储器(EPROM)，可编程只读存储器(PROM)，只读存储器(ROM)，磁存储器，快闪存储器，磁盘或光盘。存储介质可以是通用或专用计算机能够存取的任何可用介质。
一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于专用集成电路(Application Specific Integrated Circuits，简称：ASIC)中。当然，处理器和存储介质也可以作为分立组件存在于电子设备或主控设备中。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步 骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (17)

  1. 一种接触电阻的测试方法，用于测试MOS晶体管的接触电阻，所述MOS晶体管工作在线性区，所述方法包括：
    确定所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度之间的函数关系，所述第一阻值为所述MOS晶体管的沟道电阻的阻值与接触电阻的阻值之和；
    根据所述函数关系，确定所述MOS晶体管的接触电阻在所述各个采样温度下的阻值；
    根据所述MOS晶体管的接触电阻在所述各个采样温度下的阻值，确定所述接触电阻在当前环境温度下的校准系数；
    根据所述校准系数、所述接触电阻的单位面积电阻值、所述接触电阻的面积，确定所述接触电阻在当前环境温度下的阻值。
  2. 根据权利要求1所述的方法，其中，所述确定所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度之间的函数关系，包括：
    分别测量所述MOS晶体管采用不同沟道宽度时，在所述各个采样温度下的第一阻值；
    根据所述MOS晶体管采用不同沟道宽度时，在所述各个采样温度下的第一阻值，确定所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度之间的函数关系。
  3. 根据权利要求1所述的方法，其中，所述根据所述函数关系，确定所述MOS晶体管的接触电阻在所述各个采样温度下的阻值，包括：
    根据所述函数关系，确定所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度在预设直角坐标系中对应的函数曲线；
    根据所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度在预设直角坐标系中对应的函数曲线的截距，确定所述MOS晶体管的接触电阻在所述各个采样温度下的阻值；其中，所述MOS晶体管的接触电阻与所述MOS晶体管采用的沟道宽度不相关。
  4. 根据权利要求1所述的方法，其中，所述根据所述MOS晶体管的接触电阻在所述各个采样温度下的阻值，确定所述接触电阻在当前环境温 度下的校准系数，包括：
    基于所述各个采样温度以及所述MOS晶体管的接触电阻在所述各个采样温度下的阻值,确定所述接触电阻的阻值与温度之间的电阻温度参数；
    根据预设的标准温度、所述当前环境温度以及所述电阻温度参数，得到所述接触电阻在所述当前环境温度下的校准系数。
  5. 根据权利要求4所述的方法，其中，所述根据预设的标准温度、所述当前环境温度以及所述电阻温度参数，得到所述接触电阻在所述当前环境温度下的校准系数，包括：
    通过以下方式得到所述接触电阻在所述当前环境温度下的校准系数Rt：
    Rt＝1+(Te-Tn)*Tc
    其中，Te表示所述当前环境温度，Tn表示所述标准温度，Tc表示所述电阻温度参数。
  6. 根据权利要求5所述的方法，其中，所述接触电阻包括第一接触电阻与第二接触电阻，所述第一接触电阻与所述MOS晶体管的漏极连接，所述第二接触电阻与所述MOS晶体管的源极连接；
    所述根据所述校准系数、所述接触电阻的单位面积电阻值、所述接触电阻的面积，确定所述接触电阻在当前环境温度下的阻值，包括：
    根据所述校准系数、所述接触电阻在所述标准温度下的单位面积电阻值、所述第一接触电阻的面积，确定所述第一接触电阻在当前环境温度下的第一目标阻值；
    根据所述校准系数、所述接触电阻在所述标准温度下的单位面积电阻值、所述第二接触电阻的面积，确定所述第二接触电阻在当前环境温度下的第二目标阻值。
  7. 根据权利要求6所述的方法，其中，所述根据所述校准系数、所述接触电阻在所述标准温度下的单位面积电阻值、所述第一接触电阻的面积，确定所述第一接触电阻在当前环境温度下的第一目标阻值，包括：
    通过以下方式确定所述第一目标阻值Rdc：
    Rdc＝Rc*Rt*1/S 1
    所述根据所述校准系数、所述接触电阻在所述标准温度下的单位面积 电阻值、所述第二接触电阻的面积，确定所述第二接触电阻在当前环境温度下的第二目标阻值，包括：
    通过以下方式确定所述第二目标阻值Rsc：
    Rsc＝Rc*Rt*1/S 2
    其中，Rc表示所述接触电阻在所述标准温度下的单位面积电阻值，Rt表示所述校准系数，S 1表示所述第一接触电阻的面积，S 2表示所述第二接触电阻的面积。
  8. 一种接触电阻的测试装置，用于测试MOS晶体管的接触电阻，所述MOS晶体管工作在线性区，所述装置包括：
    第一处理模块，用于确定所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度之间的函数关系，所述第一阻值为所述MOS晶体管的沟道电阻的阻值与接触电阻的阻值之和；
    第二处理模块，用于根据所述函数关系，确定所述MOS晶体管的接触电阻在所述各个采样温度下的阻值；
    第一计算模块，用于根据所述MOS晶体管的接触电阻在所述各个采样温度下的阻值，确定所述接触电阻在当前环境温度下的校准系数；
    第二计算模块，用于根据所述校准系数、所述接触电阻的单位面积电阻值、所述接触电阻的面积，确定所述接触电阻在当前环境温度下的阻值。
  9. 根据权利要求8所述的装置，其中，所述第一处理模块用于：
    分别测量所述MOS晶体管采用不同沟道宽度时，在所述各个采样温度下的第一阻值；
    根据所述MOS晶体管采用不同沟道宽度时，在所述各个采样温度下的第一阻值，确定所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度之间的函数关系。
  10. 根据权利要求8所述的装置，其中，第二处理模块用于：
    根据所述函数关系，确定所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度在预设直角坐标系中对应的函数曲线；
    根据所述MOS晶体管在各个采样温度下的第一阻值与所述MOS晶体管的沟道宽度在预设直角坐标系中对应的函数曲线的截距，确定所述MOS晶体管的接触电阻在所述各个采样温度下的阻值；其中，所述MOS晶体 管的接触电阻与所述MOS晶体管采用的沟道宽度不相关。
  11. 根据权利要求8所述的装置，其中，所述第一计算模块用于：
    基于所述各个采样温度以及所述MOS晶体管的接触电阻在所述各个采样温度下的阻值,确定所述接触电阻的阻值与温度之间的电阻温度参数；
    根据预设的标准温度、所述当前环境温度以及所述电阻温度参数，得到所述接触电阻在所述当前环境温度下的校准系数。
  12. 根据权利要求11所述的装置，其中，所述第一计算模块用于：
    通过以下方式得到所述接触电阻在所述当前环境温度下的校准系数Rt：
    Rt＝1+(Te-Tn)*Tc
    其中，Te表示所述当前环境温度，Tn表示所述标准温度，Tc表示所述电阻温度参数。
  13. 根据权利要求10所述的装置，其中，所述接触电阻包括第一接触电阻与第二接触电阻，所述第一接触电阻与所述MOS晶体管的漏极连接，所述第二接触电阻与所述MOS晶体管的源极连接；
    所述第二计算模块用于：
    根据所述校准系数、所述接触电阻在所述标准温度下的单位面积电阻值、所述第一接触电阻的面积，确定所述第一接触电阻在当前环境温度下的第一目标阻值；
    根据所述校准系数、所述接触电阻在所述标准温度下的单位面积电阻值、所述第二接触电阻的面积，确定所述第二接触电阻在当前环境温度下的第二目标阻值。
  14. 根据权利要求13所述的装置，其中，所述第二计算模块用于：
    通过以下方式确定所述第一目标阻值Rdc：
    Rdc＝Rc*Rt*1/S 1
    通过以下方式确定所述第二目标阻值Rsc：
    Rsc＝Rc*Rt*1/S 2
    其中，Rc表示所述接触电阻在所述标准温度下的单位面积电阻值，Rt表示所述校准系数，S 1表示所述第一接触电阻的面积，S 2表示所述第二接触电阻的面积。
  15. 一种电子设备，包括：至少一个处理器和存储器；
    所述存储器存储计算机执行指令；
    所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如权利要求1所述的接触电阻的测试方法。
  16. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，实现权利要求1所述的接触电阻的测试方法。
  17. 一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时，实现权利要求1所述的接触电阻的测试方法。
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