WO2022227337A1 - 栅极结构及其制造方法 - Google Patents

栅极结构及其制造方法 Download PDF

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WO2022227337A1
WO2022227337A1 PCT/CN2021/111883 CN2021111883W WO2022227337A1 WO 2022227337 A1 WO2022227337 A1 WO 2022227337A1 CN 2021111883 W CN2021111883 W CN 2021111883W WO 2022227337 A1 WO2022227337 A1 WO 2022227337A1
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gate
gate structure
layer
material layer
thickness
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French (fr)
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张书浩
李宁
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials

Definitions

  • the present application relates to the field of electronic technology, and in particular, to a gate structure and a manufacturing method thereof.
  • MOS tube Metal-oxide semiconductor field effect transistor
  • MOS tube is a transistor widely used in analog circuits and digital circuits. It uses doped semiconductor materials as semiconductor substrates, and ion doping is performed on the semiconductor substrates. Two inversion diffusion layers are formed, which are respectively connected to the source and drain electrodes, and the charge channel formed between the source and drain regions is controlled by an applied voltage on the gate structure.
  • the gate structure of a MOS transistor includes: an oxide layer, a polysilicon material (Poly) layer, an adhesive layer and a metal layer, wherein the metal layer is used to draw out the gate electrode, and the adhesive layer is used to connect the Poly layer and the metal layer.
  • the Ploy layer adjusts the work function of the gate structure by injecting N-type or P-type ions, which is consistent with the conductivity type of the MOS tube to reduce the metal-semiconductor barrier and form an ohmic contact.
  • the oxide layer acts as a dielectric layer to prevent gate charge. Diffusion into the channel region, forming gate leakage.
  • the metal gate of the NMOS or PMOS transistor needs to change its work function by adjusting the ion implantation type of the Poly layer in the gate structure, reduce the potential barrier between the metal gate and the semiconductor channel, and form an ohmic contact, As a result, the gate structure of the MOS transistor is complicated, and the production process of the manufacturing process is complicated.
  • the present application provides a gate structure and a manufacturing method thereof, so as to overcome the technical problems in the prior art that the gate structure of the transistor is relatively complex and the manufacturing process is relatively cumbersome.
  • the application provides a gate structure, comprising: a gate dielectric layer formed by bonding with a semiconductor substrate; a gate material layer formed by bonding with the gate dielectric layer; the material of the gate material layer It is atomic crystal WSe2 or MoSe2; the gate metal layer is formed by bonding with the gate material layer, and the gate metal layer leads out the gate electrode.
  • the present application provides a method for manufacturing a gate structure for manufacturing the gate structure provided in the first aspect of the present application, including: obtaining a semiconductor substrate; forming a gate dielectric layer on the surface of the substrate; A gate material layer is deposited on the surface of the dielectric layer; the material of the gate material layer is atomic crystal WSe2 or MoSe2; the gate material layer and the gate dielectric layer are coated and developed to obtain a preset position A gate dielectric layer and a gate material layer; deposit a gate metal layer on the surface of the gate material layer.
  • the gate structure and the manufacturing method thereof provided by the present application realize the gate material layer in the gate structure through the atomic crystal whose work function thickness depends, so that the gate structure in the MOS transistor can be formed by forming atomic crystal layers of different thicknesses.
  • the adjustment of the work function can be realized, thereby reducing the complexity of the gate structure of the MOS transistor and simplifying the production process in the manufacturing process.
  • the layers of atomic crystals are directly bonded by van der Waals forces instead of chemical bonds, the surface of atomic crystals is cleaner, and since the gate structure using atomic crystals does not adjust the work function by implanting ions, it will not be due to The implanted ions affect the reliability of the MOS tube device.
  • the gate material layer does not need to be additionally provided with an adhesive layer such as TiN in the gate structure. It can be directly connected with the gate metal layer, which further reduces the complexity and manufacturing cost of the gate structure of the MOS transistor.
  • FIG. 1 is a schematic structural diagram of a MOS tube
  • FIG. 2 is a schematic diagram of a gate structure
  • FIG. 3 is a schematic structural diagram of an embodiment of a gate structure provided by the present application.
  • Fig. 4 is the schematic diagram of the photoluminescence spectrum of atomic crystal WSe 2 ;
  • Fig. 5 is the energy band diagram of atomic crystal WSe 2 ;
  • FIG. 6 is a schematic diagram of a metal gate structure corresponding to a P-type work function provided by the present application.
  • FIG. 7 is a schematic diagram of a metal gate structure corresponding to an N-type work function provided by the present application.
  • FIG. 8 is a schematic diagram of the conduction characteristics of the MOS transistor using the gate structure of the atomic crystal provided by the application;
  • FIG. 9 is a schematic flowchart of an embodiment of a method for manufacturing a gate structure provided by the present application.
  • FIG. 10 is a schematic structural diagram of each process according to an embodiment of a method for fabricating a gate structure provided by the present application.
  • FIG. 11 is a schematic structural diagram of each process according to another embodiment of the method for fabricating a gate structure provided by the present application.
  • FIG. 1 is a schematic structural diagram of a MOS transistor.
  • the MOS transistor shown in FIG. 1 is provided on a semiconductor substrate 10 , and a first diffusion region 101 and a second diffusion region are provided on the semiconductor substrate 10 .
  • the first diffusion region 101 can lead out the electrode S as the source level (Source) of the MOS transistor
  • the second diffusion region 102 can lead out the electrode D as the drain level (Drain) of the MOS transistor.
  • a gate structure 20 is also provided on the substrate 10 of the MOS tube, and the gate structure 20 can be used to lead the electrode G as the gate of the MOS tube, so that the voltage on the electrode G can be controlled by the dielectric layer.
  • the on or off state of the channel formed between the diffusion region 101, the second diffusion region 102 and the substrate are provided on the semiconductor substrate 10 .
  • the MOS transistor when the MOS transistor is an N-type conductive transistor, the first diffusion region 101 and the second diffusion region 102 are N-type diffusion regions, and the substrate 10 constitutes a P-type active region, under the control of the gate G , the first diffusion region 101 and the second diffusion region 102 are turned on and off through the N-type channel, so that the current between the electrode S and the electrode D is turned on and off.
  • the MOS transistor when the MOS transistor is a P-type conductive crystal, the first diffusion region 101 and the second diffusion region 102 are P-type diffusion regions, and the substrate 10 constitutes an N-type active region. Then, the first diffusion region 101 and the second diffusion region 102 are turned on and off through the P-type channel, so that the current between the electrode S and the electrode D is turned on and off.
  • FIG. 2 is a schematic diagram of a gate structure, and FIG. 2 shows the gate structure part of the MOS transistor shown in FIG. 1 , which is formed on the substrate 10 .
  • This part of the gate structure includes, from bottom to top, an oxide layer 201, a polysilicon material (Poly) layer 204, an adhesive layer 203 and a metal layer 202, wherein the oxide layer 201 can be composed of materials such as silicon oxide, and serves as a dielectric layer , which can be used to prevent the gate charge from diffusing into the channel region in the substrate 10 to form gate leakage; the metal layer 202 can be a conductive metal material for drawing out the gate electrode G; For connecting the Poly layer 204 and the metal layer 202; the Ploy layer 204 can be formed by using a vapor deposition method (Chemical Vapor Deposition, referred to as: CVD) to grow amorphous silicon and then anneal and crystallize, and adjust the function of the poly layer by ion implantation.
  • CVD Chemical
  • the function further adjusts the work function type of the metal gate to be P-type or N-type, so that the metal gate 20 can form a good ohmic contact with the N-type or P-type conductive channel formed in the substrate 10, which is easy to conduct the channel. and deadline.
  • the metal gate of the MOS transistor needs to be changed by adjusting the ion implantation type of the Poly layer 204 in the gate structure, its functional function can be changed, so as to reduce the difference between the metal gate and the semiconductor channel. Therefore, the gate structure of the MOS tube is complicated, the production process of the manufacturing process is complicated, and the ions implanted during the ion implantation process will affect the reliability of the MOS tube device.
  • the poly layer 204 of the MOS transistor needs to be additionally provided with an adhesive layer 203 to be connected to the metal layer 202, which further increases the complexity and cost of the gate structure of the MOS transistor.
  • the present application provides a gate structure and a manufacturing method thereof.
  • Atomic crystals depending on the thickness of the work function are used as gate materials in the gate structure, so that the gate structure can realize the work function by forming atomic crystal layers of different thicknesses. Therefore, the complexity of the gate structure of the MOS tube is reduced, the production process in the manufacturing process is simplified, and since the work function is not adjusted by implanting ions, the reliability of the MOS tube device will not be affected by the implanted ions. sex.
  • the atomic crystal is an atomic material such as tungsten compound, it has good natural adhesion to the gate metal layer using materials such as metal W, and the gate material does not need to be provided with an additional adhesive layer in the gate structure.
  • FIG. 3 is a schematic structural diagram of an embodiment of the gate structure provided by the application.
  • the gate structure shown in FIG. 3 can be applied to the MOS transistor shown in FIG. 1 , and the structures other than the gate structure shown in FIG. 3 Not limited.
  • the gate structure of the embodiment shown in FIG. 3 is provided on the surface of the semiconductor substrate 10.
  • the semiconductor substrate 10 is set below as an example, the gate structure sequentially includes: A polar dielectric layer 201 , a gate material layer 205 and a gate metal layer 202 .
  • the semiconductor substrate 10 can be a Si substrate, a Ge substrate, a SiGe substrate, SOI or GOI, etc.; or, can also be a substrate including other semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc.; or, can also It is a stacked structure, such as Si/SiGe, etc., or can also be other epitaxial structures, such as SGOI and the like.
  • the gate dielectric layer 201 is formed by adhering to the semiconductor substrate 10, and can be one of SiOx , AlOx , AlOx , SiC, HfOx, TiOx , h-BN and SiNx , or a mixture of them Any one of the above, or it can also be a mixture of the above; or it can also be other forms of oxides, mixtures, and the like.
  • the lower part of the gate material layer 205 is formed by bonding with the gate material layer 201, and the upper part is bonded with the gate metal layer 202.
  • the material of the gate material layer 205 is atomic crystal WSe 2 or atomic crystal MoSe 2 .
  • the gate metal layer 202 is formed by bonding with the gate material layer 205, which can be one of W, Mo, Al, Au, Cu, Ni, Ti, Cr, Ag, Pt and Pd, or a mixture of multiple metals such as Conductor implementation.
  • the gate material layer 205 can be one of W, Mo, Al, Au, Cu, Ni, Ti, Cr, Ag, Pt and Pd, or a mixture of multiple metals such as Conductor implementation.
  • the characteristics of the atomic crystal in the gate material layer 205 provided by the present application will be described by taking the atomic crystal WSe 2 as an example.
  • Figure 4 is a schematic diagram of the photoluminescence spectrum (Photoluminescence Spectroscopy, PL spectrum for short) of the atomic crystal WSe 2 , wherein photoluminescence refers to the transition of electrons in the atomic crystal from the valence band to the lead when the atomic crystal is excited by light. band and leave holes in the valence band, the electrons and holes in the respective conduction and valence bands reach their respective unoccupied lowest excited states to become quasi-equilibrium states, while the electrons and empty states in the quasi-equilibrium state The hole then emits light through recombination to form a spectral map of the intensity or energy distribution of light of different wavelengths. As shown in Fig.
  • Fig. 5 is the energy band diagram of atomic crystal WSe 2. It can be seen from Fig. 5 that by adjusting the thickness (number of layers, L) of atomic crystal WSe 2 in the abscissa, the energy difference (energy difference) of the work function of atomic crystal WSe 2 can be realized. difference, in eV), which proves that the atomic crystal WSe2 is the material on which the work function thickness depends.
  • the work function of the gate structure provided in the embodiment shown in FIG. 3 of the present application is also related to the thickness of using these atomic crystals as the gate material layer , so that the gate structure is divided into a P-type work function metal gate and an N-type work function metal gate by forming different thicknesses of the gate material layer.
  • FIG. 6 is a schematic diagram corresponding to a P-type work function metal gate structure provided by the application
  • FIG. 7 is a schematic diagram corresponding to an N-type work function metal gate structure provided by the application, wherein, as shown in FIG. 6
  • the thickness h1 of the P-type work function metal gate material layer 205 is smaller than the thickness h3 of the N-type work function metal gate material layer 205 as shown in FIG. 7 .
  • the gate material layer with a thickness smaller than the preset thickness can realize the P-type work function
  • the gate material layer with a thickness larger than the preset thickness can realize the P-type work function.
  • N-type work function For example, FIG.
  • FIG. 8 is a schematic diagram of the conduction characteristics of a MOS transistor using an atomic crystal gate structure provided by the present application, wherein, if the preset thickness is 6.5 nm, it can be seen that when the thickness of the gate material layer 205 is 2.5 nm When a voltage less than 0V is applied to the gate G of the MOS transistor, as the absolute value of the voltage increases, the current Ids in the direction of the electrode D-electrode S of the MOS transistor will increase, and at the same time, a voltage greater than 0V is applied to the gate G When the voltage is 20 nm, the voltage change has little effect on the current Ids, so that the MOS transistor exhibits a P-type conductivity type as a whole; when the thickness of the gate material layer 205 is 20 nm, when a voltage greater than 0V is applied to the gate of the MOS transistor, with the When the voltage increases, the current Ids in the direction of the MOS tube electrode D-electrode S will increase.
  • the thickness of the gate material layer corresponds to the conductivity type of the gate structure, so that when the conductivity type of the gate structure is different, the thickness of the gate material layer also varies. Therefore, in the gate structure provided by the embodiments of the present application, the thickness of the gate metal layer can be set correspondingly, so that the MOS transistor is located at the gate When the conductive types of the structures are inconsistent, the overall height of the gate structure remains the same.
  • the thickness of the gate metal layer 202 is h2 .
  • the overall height of the part on 10 is H; when the thickness of the N-type work function metal gate material layer 205 is h3 as shown in FIG. 7, the thickness of the gate metal layer 202 is h4, and the gate structure is on the substrate 10.
  • the overall height of the part is also H.
  • the gate structure provided by the embodiments of the present application realizes the gate material layer in the gate structure through atomic crystal WSe 2 or atomic crystal MoSe 2 whose work function thickness depends. Therefore, the gate structure in the MOS transistor is made to pass through
  • the adjustment of the work function can be realized by forming atomic crystal layers of different thicknesses, thereby reducing the complexity of the gate structure of the MOS transistor and simplifying the production process in the manufacturing process.
  • the gate structure using atomic crystals since the layers of atomic crystals are directly bonded by van der Waals force instead of chemical bonds, the surface of atomic crystals is cleaner, and since the gate structure using atomic crystals does not adjust the work function by implanting ions as shown in Figure 2 , the reliability of the MOS tube device will not be affected by the implanted ions.
  • the gate material layer can be directly connected to the gate metal layer, which further reduces the complexity and manufacturing cost of the gate structure of the MOS transistor.
  • the atomic crystal WSe 2 in the gate structure in the embodiment of the present application can be directly grown on the surface of the gate dielectric layer such as silicon oxide or sapphire by the CVD method, and the gate structure shown in FIG. 2 is grown on the Ploy layer. Compared with annealing and crystal formation after the CVD method, the process flow of the gate structure is also reduced.
  • the manufacturing method of the gate structure provided by the embodiments of the present application will be described below with reference to the accompanying drawings.
  • FIG. 9 is a schematic flowchart of an embodiment of a method for manufacturing a gate structure provided by the present application. The method shown in FIG. 9 includes:
  • FIG. 10 is a schematic structural diagram of each process according to an embodiment of the gate structure fabrication method provided by the present application, wherein S1 corresponds to the semiconductor substrate 10 obtained in the process T11 of FIG. 10 .
  • S3 depositing a gate material layer on the surface of the gate dielectric layer.
  • the entire area covers the gate material layer 205 , and the thickness of the grown gate material layer is related to the work function type of the gate structure.
  • the thickness of the deposited gate material layer may be 2.5 nm, and when the gate structure is an N-type work function, the thickness of the deposited gate material layer may be is 20nm.
  • the gate material layer 205 is atomic crystal WSe 2
  • WSe 2 may be grown on the gate dielectric layer 201 by CVD, ALD and other methods in S3 .
  • the gate dielectric layer 201 and the gate material layer 205 are obtained at preset positions on the substrate 10 , and the gate dielectric layer 201 is grown on the substrate 10 beyond the preset position grown by T12 .
  • the electrical and gate material layers will be etched.
  • the preset position can be the gate position of the MOS tube, which is marked by a mask window, etc., so that in the process of coating and developing, the preset position can be blocked by the mask window, and exposed parts except the preset position.
  • the gate dielectric layer and the gate material layer outside the preset position are etched, and the preset area is protected from being etched by a mask window.
  • FIG. 11 is a schematic structural diagram of each process according to another embodiment of the gate structure fabrication method provided by the present application, and two gate structures G1 and G2 are simultaneously provided on one substrate 10 as an example, and the gate The structure G1 corresponds to a P-type work function, and the gate structure G2 corresponds to an N-type work function. Then, the states T21-T22 shown in FIG. 11 are the same as T11-T12, and details are not repeated here. Subsequently, in the state T23, the gate material layer 205 and the gate dielectric layer 201 at the preset positions where the two gate structures G1 and G2 are located may be retained through the coating and developing process.
  • the gate material layer of the gate structure G1 is etched, so that the gate The gate material layer thickness of structure G1 corresponds to the P-type work function.
  • the thickness of the gate material layer generated in T22 can correspond to the N-type work function, so G2 does not need to be etched in T24, so as to reduce the etching area and improve the manufacturing efficiency.

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Abstract

本申请提供一种栅极结构及其制造方法，通过功函数厚度依靠的原子晶体实现栅极结构中的栅极材料层，使得MOS管中的栅极结构通过形成不同厚度的原子晶体层即可实现功函数的调节，从而降低了MOS管的栅极结构的复杂度，简化制造过程中的生产工艺。

Description

栅极结构及其制造方法
本申请要求于2021年04月30日提交中国专利局、申请号为202110483826.8、申请名称为“栅极结构及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，尤其涉及一种栅极结构及其制造方法。
背景技术
金属-氧化物半导体场效应管(简称：MOS管)，是一种广泛应用在模拟电路与数字电路中的晶体管，使用掺杂半导体材料作为半导体衬底，并在半导体衬底上进行离子掺杂形成两个反型扩散层，分别连接源、漏两个电极，由栅极结构上外加电压对源漏区之间形成的电荷沟道进行控制。
现有技术中，MOS管的栅极结构包括：氧化物层、多晶硅材料(Poly)层、粘贴层和金属层，其中，金属层用于引出栅极电极，粘贴层用于连接Poly层与金属层，Ploy层通过注入N型或者P型离子调节栅极结构功函数，和MOS管的导电类型保持一致，以降低金属半导体势垒，形成欧姆接触，氧化物层作为介质层，防止栅极电荷扩散到沟道区域，形成栅极漏电。
采用现有技术，NMOS或者PMOS管的金属栅极需要通过调节栅极结构中Poly层的离子注入类型来改变其功函数，降低金属栅极和半导体沟道之间的势垒，形成欧姆接触，导致了MOS管的栅极结构较为复杂、制造过程的生产工艺较为繁琐。
发明内容
本申请提供一种栅极结构及其制造方法，以克服现有技术中晶体管的 栅极结构较为复杂，制造过程的工艺较为繁琐的技术问题。
本申请提供一种栅极结构，包括：栅极介电层，与半导体衬底贴合形成；栅极材料层，与所述栅极介电层贴合形成；所述栅极材料层的材料为原子晶体WSe2或者MoSe2；栅极金属层，与所述栅极材料层贴合形成，所述栅极金属层引出栅极电极。
本申请提供一种栅极结构的制造方法，用于制作如本申请第一方面提供的栅极结构，包括：获取半导体衬底；在所述衬底表面形成栅极介电层；在栅极介电层表面沉积栅极材料层；所述栅极材料层的材料为原子晶体WSe2或者MoSe2；对所述栅极材料层和所述栅极介电层进行涂布显影处理，得到预设位置的栅极介电层和栅极材料层；在所述栅极材料层表面沉积栅极金属层。
综上，本申请提供的栅极结构及其制作方法，通过功函数厚度依靠的原子晶体实现栅极结构中的栅极材料层，使得MOS管中的栅极结构通过形成不同厚度的原子晶体层即可实现功函数的调节，从而降低了MOS管的栅极结构的复杂度，简化制造过程中的生产工艺。同时，由于原子晶体的层与层之间直接通过范德华力结合，而非化学键，使得原子晶体表面更加整洁，并且由于使用原子晶体的栅极结构不通过注入离子的方式调节功函数，不会由于所注入的离子而影响MOS管器件的可靠性。此外，由于原子晶体WSe2等钨的化合物与使用金属钨W等材料的栅极金属层天然的粘黏性良好，在栅极结构中无需额外设置TiN等粘贴层的情况下，栅极材料层就能够直接与栅极金属层连接，进一步减少了MOS管的栅极结构的复杂度和制造成本。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为一种MOS管的结构示意图；
图2为一种栅极结构的示意图；
图3为本申请提供的栅极结构一实施例的结构示意图；
图4为原子晶体WSe 2的光致发光光谱的示意图；
图5为原子晶体WSe 2的能带图；
图6为本申请提供的对应于P型功函数金属栅极结构的示意图；
图7为本申请提供的对应于N型功函数金属栅极结构的示意图；
图8为本申请提供的应用原子晶体的栅极结构的MOS管的导电特性示意图；
图9为本申请提供的栅极结构的制造方法一实施例的流程示意图；
图10为本申请提供的栅极结构制作方法一实施例在各个流程的结构示意图；
图11为本申请提供的栅极结构制作方法另一实施例在各个流程的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
在正式介绍本申请实施例之前，先结合附图，对本申请所应用的场景以及现有技术中所存在的问题进行介绍。其中，本申请应用在金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，简称：MOSFET、MOS管等)，可以在电压的控制下实现截止或导通两种状态，因此作为开关元件被广泛使用在模拟电路及数字电路中。
在一些实施例中，图1为一种MOS管的结构示意图，如图1所示的MOS管设置在半导体衬底10上，半导体衬底10上设置有第一扩散区101和第二扩散区102，第一扩散区101可以引出电极S作为MOS管的源级(Source)，第二扩散区102可以引出电极D作为MOS管的漏级(Drain)。同时，MOS管的衬底10上还设置有栅极结构20，栅极结构20可用于引出电极G作为MOS管的栅极(Gate)，使得电极G上的电压能够通过介电层控制第一扩散区101、第二扩散区102与衬底之间形成的沟道的导通或截止状态。
在一些实施例中，当MOS管为N型导电晶体管时，第一扩散区101和第二扩散区102为N型扩散区，衬底10构成P型有源区，在栅极G的控制下，第一扩散区101和第二扩散区102之间通过N型沟道导通与截止，实现电极S和电极D之间电流的导通与截止。在另一些实施例中，当MOS管为P型导电晶体时，第一扩散区101和第二扩散区102为P型扩散区，衬底10构成N型有源区，在栅极G的控制下，第一扩散区101和第二扩散区102之间通过P型沟道导通与截止，实现电极S和电极D之间电流的导通与截止。
更为具体地，在一些实施例中，图2为一种栅极结构的示意图，如图2示出了如图1所示的MOS管中的栅极结构部分，在衬底10上形成的该部分栅极结构由下至上依次包括：氧化物层201、多晶硅材料(Poly)层204、粘贴层203和金属层202，其中，氧化物层201可以是氧化硅等材料构成，充当介电层，可用于防止栅极电荷扩散到衬底10内的沟道区域形成栅极漏电；金属层202可以是导电金属材料，用于引出栅极电极G；粘贴层203可以使用TiN等材料实现，用于连接Poly层204与金属层202；Ploy层204可以是使用气相沉积法(Chemical Vapor Deposition，简称：CVD)方法生长无定形硅后再进行退火结晶形成，并通过离子注入类型调节poly层的功函数进而调节金属栅极的功函数类型为P型或N型，使得金属栅极 20能够和衬底10内形成的N型或者P型导电沟道形成良好的欧姆接触，易于沟道的导通和截止。
然而，在上述图2所示的实施例中，由于MOS管的金属栅极需要通过调节栅极结构中Poly层204的离子注入类型来改变其功能函数，以降低金属栅极和半导体沟道之间的势垒，形成欧姆接触，因此导致了MOS管的栅极结构较为复杂、制造过程的生产工艺较为繁琐，并且在离子注入过程中所注入的离子会影响MOS管器件的可靠性。同时，MOS管的Poly层204还需要额外设置粘贴层203才能与金属层202连接，进一步提高了MOS管的栅极结构的复杂度和成本。
因此，本申请提供一种栅极结构及其制造方法，通过功函数厚度依靠的原子晶体充当栅极结构中的栅极材料，使得栅极结构通过形成不同厚度的原子晶体层即可实现功函数的调节，从而降低了MOS管的栅极结构的复杂度，简化制造过程中的生产工艺，并且由于不通过注入离子的方式调节功函数，不会由于所注入的离子而影响MOS管器件的可靠性。此外，当原子晶体为钨化物等原子材料时，其与采用金属W等材料的栅极金属层天然的粘黏性良好，在栅极结构中无需额外设置粘贴层的情况下，栅极材料就能够直接与栅极金属连接，进一步减少了MOS管的栅极结构的复杂度。同时，由于原子晶体的层与层之间直接通过范德华力结合，而非化学键，使得原子晶体表面更加整洁，减少界面电荷以及陷阱的产生。
下面以具体地实施例对本申请的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
图3为本申请提供的栅极结构一实施例的结构示意图，如图3所示的栅极结构可应用于如图1所示的MOS管中，图3中对栅极结构之外的结构不作限定。具体地，如图3所示实施例的栅极结构设置在半导体衬底10表面，在图3中以下方设置半导体衬底10为例，则栅极结构从图中下方到上方依次包括：栅极介电层201、栅极材料层205和栅极金属层202。
半导体衬底10可以是Si衬底、Ge衬底、SiGe衬底、SOI或者GOI等；或者，还可以为包括其他半导体或者化合物半导体的衬底，例如GaAs、InP或者SiC等；或者，还可以为叠层结构，例如Si/SiGe等，或者还可以 为其他外延结构，例如SGOI等。
栅极介电层201与半导体衬底10贴合形成，可以是SiO x、AlO x、AlO x、SiC、HfO x、TiO x、h-BN和SiNx中的一种，或多种的混合物中的任一种，或者还可以是上述多种的混合物；又或者还可以是其他形式的氧化物、混合物等。
栅极材料层205下方与栅极材料层201贴合形成，上方与栅极金属层202贴合，在本申请实施例中，栅极材料层205的材料为原子晶体WSe 2或者原子晶体MoSe 2。
栅极金属层202与栅极材料层205贴合形成，可以是W、Mo、Al、Au、Cu、Ni、Ti、Cr、Ag、Pt和Pd中的一种，或多种的混合物等金属导体实现。
下面结合附图，以原子晶体WSe 2作为示例，对本申请提供的栅极材料层205中，原子晶体的特性进行说明。
图4为原子晶体WSe 2的光致发光光谱(Photoluminescence Spectroscopy，简称：PL光谱)的示意图，其中，光致发光是指原子晶体在光线的激励下，原子晶体内的电子从价带跃迁至导带并在价带留下空穴，电子和空穴在各自的导带和价带中通过弛豫达到各自未被占据的最低激发态成为准平衡态，而在准平衡态下的电子和空穴再通过复合发光，形成不同波长光的强度或能量分布的光谱图。如图4示出了，通过层数堆叠(Layer)方式实现的不同层厚度的原子晶体WSe 2，在受到不同光子能量(Photon energy，单位eV)的激励下，所表现出的PL光谱(Normalized PL)，可以看出，当原子晶体的厚度不同时，PL光谱的带隙不同，且PL光谱的强度与层数强相关。
图5为原子晶体WSe 2的能带图，从图5中看出，可以通过调节横坐标中原子晶体WSe 2的厚度(层数，L)，实现对原子晶体WSe 2功函数能量差(energy difference，单位eV)的调节，证明了原子晶体WSe2是功函数厚度依靠的材料。
在一些实施例中，基于原子晶体的功函数与其厚度相关的特性，本申请如图3所示实施例中提供的栅极结构的功函数也与使用这些原子晶体作为栅极材料层的厚度相关，从而通过形成栅极材料层的不同厚度，将栅极结构区分为P型功函数金属栅极和N型功函数金属栅极。
例如，图6为本申请提供的对应于P型功函数金属栅极结构的示意图，图7为本申请提供的对应于N型功函数金属栅极结构的示意图，其中，如图6所示的P型功函数金属栅极材料层205的厚度h1，小于如图7所示的N型功函数金属栅极材料层205的厚度h3。
在一些实施例中，可以通过设置栅极材料层205的预设厚度，将小于该预设厚度的栅极材料层可以实现P型功函数、将大于该预设厚度的栅极材料层可以实现N型功函数。例如，图8为本申请提供的应用原子晶体的栅极结构的MOS管的导电特性示意图，其中，记预设厚度为6.5nm，则可以看出，当栅极材料层205的厚度为2.5nm时，在MOS管的栅极G施加小于0V的电压时，随着电压的绝对值增大，MOS管的电极D-电极S方向的电流Ids将增大，同时，在栅极G施加大于0V的电压时，电压变化对电流Ids影响较小，使得MOS管整体呈现P型导电类型；当栅极材料层205的厚度为20nm时，在MOS管的栅极施加大于0V的电压时，随着电压增大，MOS管电极D-电极S方向的电流Ids将增大，同时，在栅极G施加小于0V的电压时，电压变化对电流Ids影响较小，使得MOS管整体呈现N型导电类型。
在一些实施例中，由于本申请实施例提供的栅极结构中，栅极材料层的厚度根据栅极结构的导电类型对应，使得栅极结构在导电类型不同时，栅极材料层的厚度也不同，从而会导致使用这种栅极结构的MOS管的高度不同，因此，本申请实施例提供的栅极结构中，可以将栅极金属层的厚度进行相应的设置，使得MOS管在栅极结构的导电类型不一致的情况下，栅极结构整体的高度仍然保持一致。
例如，结合图6和图7所示，在如图6所示的P型功函数金属栅极材料层205的厚度h1时，栅极金属层202的厚度为h2，栅极结构中在衬底10上的部分整体高度为H；在如图7所示的N型功函数金属栅极材料层205的厚度h3时，栅极金属层202的厚度为h4，栅极结构中在衬底10上的部分整体高度同样为H。
综上，本申请实施例提供的栅极结构，通过功函数厚度依靠的原子晶体WSe 2或者原子晶体MoSe 2实现栅极结构中的栅极材料层，因此，使得MOS管中的栅极结构通过形成不同厚度的原子晶体层即可实现功函数的调节，从而降低了MOS管的栅极结构的复杂度，简化制造过程中的生产 工艺。同时，由于原子晶体的层与层之间直接通过范德华力结合，而非化学键，使得原子晶体表面更加整洁，并且由于使用原子晶体的栅极结构不通过如图2中注入离子的方式调节功函数，不会由于所注入的离子而影响MOS管器件的可靠性。此外，由于原子晶体WSe 2等钨的化合物与使用金属钨W等材料的栅极金属层天然的粘黏性良好，在栅极结构中无需额外如图2中设置TiN等粘贴层的情况下，使得栅极材料层就能够直接与栅极金属层连接，进一步减少了MOS管的栅极结构的复杂度和制造成本。
此外，本申请实施例中栅极结构中的原子晶体WSe 2可以直接通过CVD方法生长在氧化硅或者蓝宝石等栅极介电层的表面，与图2中所示的栅极结构在生长Ploy层时在CVD方法后还要再进行退火结晶形成相比，还减少了栅极结构在制作时的工艺流程。下面结合附图，对本申请实施例提供的栅极结构的制造方法进行说明。
图9为本申请提供的栅极结构的制造方法一实施例的流程示意图，如图9所示的方法包括：
S1：获取半导体衬底。参照图10，图10为本申请提供的栅极结构制作方法一实施例在各个流程的结构示意图，其中S1对应于图10的流程T11中，获取的半导体衬底10。
S2：在所述衬底表面形成栅极介电层。对应于图10的流程T12中，在半导体衬底10表面上，整个区域所覆盖形成的栅极介电层201。
S3：在栅极介电层表面沉积栅极材料层。对应于图10的流程T12中，在栅极介电层201的表面上，整个区域所覆盖形成的栅极材料层205，并且所生长的栅极材料层的厚度与栅极结构的功函数类型相关，例如，当栅极结构是P型功函数时，所沉积的栅极材料层的厚度可以是2.5nm，当栅极结构是N型功函数时，所沉积的栅极材料层的厚度可以是20nm。在一些实施例中，当栅极材料层205为原子晶体WSe 2时，S3中可以具体是利用CVD，ALD等方法在栅极介电层201上生长WSe 2。
S4：对栅极材料层201和栅极介电层205进行涂布显影处理。对应于图10的流程T13中，得到衬底10上预设位置的栅极介电层201和栅极材料层205，而在衬底10上T12所生长的预设位置之外的栅极介电层和栅极材料层将被蚀刻。其中，预设位置处可以是MOS管的栅极位置，由掩模窗口等方式 进行标记，使得在涂布显影的过程中，可以通过掩模窗口对预设位置进行遮挡，并暴露出除了预设位置之外的区域，将预设位置之外的栅极介电层和栅极材料层被蚀刻、而通过掩模窗口保护预设区域内不被蚀刻。
S6：在所述栅极材料层205表面沉积栅极金属层202。对应于图10的流程T14中，在栅极材料层205表面上，整个区域所覆盖形成的栅极金属层202。
结合上述图9所示的S1-S4和S6，以及图10所示的流程示意，可应用于在衬底10上单独生成一个栅极结构时，所对应的栅极结构的制造方法。而当需要在衬底10上形成多个栅极结构、且多个栅极结构对应于不同的导电类型时，在S4之后、S6之前，还需要通过S5，根据不同栅极结构的导电类型，对已经生长的栅极材料层进行蚀刻，以调整不同栅极材料层的厚度。
参照图11，图11为本申请提供的栅极结构制作方法另一实施例在各个流程的结构示意图，以在一个衬底10上同时设置两个栅极结构G1和G2作为示例，且栅极结构G1对应于P型功函数、栅极结构G2对应于N型功函数。则如图11所示的状态T21-T22与T11-T12相同，不再赘述。随后，在状态T23中，通过涂布显影处理可以保留两个栅极结构G1和G2所在的预设位置处的栅极材料层205和栅极介电层201。由于P型功函数对应的栅极材料层的厚度小于N型功函数对应的栅极材料层的厚度，因此在状态T24中，对栅极结构G1的栅极材料层进行蚀刻处理，使得栅极结构G1的栅极材料层厚度对应于P型功函数。此时，T22中生成的栅极材料层的厚度可以对应于N型功函数，则在T24中就不需要对G2进行蚀刻，以减少蚀刻的面积，提高制造效率。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或 者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种栅极结构，包括：
    栅极介电层，与半导体衬底贴合形成；
    栅极材料层，与所述栅极介电层贴合形成；所述栅极材料层的材料为原子晶体WSe 2或者MoSe 2；
    栅极金属层，与所述栅极材料层贴合形成，所述栅极金属层引出栅极电极。
  2. 根据权利要求1所述的栅极结构，其中，
    所述栅极结构的功函数与所述栅极材料层的厚度相关。
  3. 根据权利要求2所述的栅极结构，其中，
    当所述栅极结构为P型导电类型，所述栅极材料层的厚度小于预设厚度值；
    当所述栅极结构为N型导电类型，所述栅极材料层的厚度大于所述预设厚度值。
  4. 根据权利要求3所述的栅极结构，其中，
    所述预设厚度值为6.5nm。
  5. 根据权利要求1-4任一项所述的栅极结构，其中，
    所述栅极金属层材料包括：W、Mo、Al、Au、Cu、Ni、Ti、Cr、Ag、Pt和Pd中的一种，或多种的混合物。
  6. 根据权利要求5所述的栅极结构，其中，
    当所述栅极结构为P型导电类型时所述栅极金属层与所述栅极材料层的厚度之和，与当所述栅极结构为N型导电类型时所述栅极金属层与所述栅极材料层的厚度之和相同。
  7. 根据权利要求1-6任一项所述的栅极结构，其中，
    所述栅极介电层的材料为：SiO x、AlO x、AlO x、SiC、HfO x、TiO x、h-BN和SiNx中的一种，或多种的混合物。
  8. 一种栅极结构的制造方法，包括：
    获取半导体衬底；
    在所述衬底表面形成栅极介电层；
    在栅极介电层表面沉积栅极材料层；所述栅极材料层的材料为原子晶体 WSe 2或者MoSe 2；
    对所述栅极材料层和所述栅极介电层进行涂布显影处理，得到预设位置的栅极介电层和栅极材料层；
    在所述栅极材料层表面沉积栅极金属层。
  9. 根据权利要求8所述的方法，其中，所述在所述栅极材料层表面沉积栅极金属层之前，还包括：
    根据所述栅极结构的导电类型，对所述栅极材料层进行蚀刻，以调整不同栅极材料层的厚度。
  10. 根据权利要求9所述的方法，其中，
    所述栅极结构的功函数与所述栅极材料层的厚度相关。
  11. 根据权利要求10所述的方法，其中，
    当所述栅极结构为P型导电类型，所述栅极材料层的厚度小于预设厚度值；
    当所述栅极结构为N型导电类型，所述栅极材料层的厚度大于所述预设厚度值。
  12. 根据权利要求11所述的方法，其中，
    所述预设厚度值为6.5nm。
  13. 根据权利要求8-12任一项所述的方法，其中，
    所述栅极金属层材料包括：W、Mo、Al、Au、Cu、Ni、Ti、Cr、Ag、Pt和Pd中的一种，或多种的混合物。
  14. 根据权利要求13所述的方法，其中，
    当所述栅极结构为P型导电类型时所述栅极金属层与所述栅极材料层的厚度之和，与当所述栅极结构为N型导电类型时所述栅极金属层与所述栅极材料层的厚度之和相同。
  15. 根据权利要求8-14任一项所述的方法，其中，
    所述栅极介电层的材料为：SiO x、AlO x、AlO x、SiC、HfO x、TiO x、h-BN和SiNx中的一种，或多种的混合物。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009282A (zh) * 2005-12-09 2007-08-01 株式会社东芝 半导体装置及其制造方法
US20170179263A1 (en) * 2015-12-22 2017-06-22 Imec Vzw Two-dimensional material semiconductor device
CN108258035A (zh) * 2018-01-15 2018-07-06 中国科学院微电子研究所 一种GaN基增强型场效应器件及其制作方法
CN109326652A (zh) * 2018-09-27 2019-02-12 上海电力学院 一种激光局部加热制备p型二维材料mosfet的方法
CN110828564A (zh) * 2018-08-13 2020-02-21 香港科技大学 具有半导体性栅极的场效应晶体管
CN111490045A (zh) * 2020-04-27 2020-08-04 复旦大学 一种基于二维材料的半浮栅存储器及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373984A (ja) * 2001-06-14 2002-12-26 Nec Corp 半導体装置及び製造方法
KR102356682B1 (ko) * 2015-05-11 2022-01-27 삼성전자주식회사 2ｄ 물질을 이용한 비휘발성 메모리 소자 및 그 제조방법
CN112018039B (zh) * 2019-05-29 2024-12-06 长鑫存储技术有限公司 半导体结构及其制作方法
US11121214B2 (en) * 2019-08-22 2021-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain contact with 2-D material

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009282A (zh) * 2005-12-09 2007-08-01 株式会社东芝 半导体装置及其制造方法
US20170179263A1 (en) * 2015-12-22 2017-06-22 Imec Vzw Two-dimensional material semiconductor device
CN108258035A (zh) * 2018-01-15 2018-07-06 中国科学院微电子研究所 一种GaN基增强型场效应器件及其制作方法
CN110828564A (zh) * 2018-08-13 2020-02-21 香港科技大学 具有半导体性栅极的场效应晶体管
CN109326652A (zh) * 2018-09-27 2019-02-12 上海电力学院 一种激光局部加热制备p型二维材料mosfet的方法
CN111490045A (zh) * 2020-04-27 2020-08-04 复旦大学 一种基于二维材料的半浮栅存储器及其制备方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KIM HAN-GYU, CHOI HYOUNG JOON: "Thickness dependence of work function, ionization energy, and electron affinity of Mo and W dichalcogenides from DFT and GW calculations", PHYSICAL REVIEW B, vol. 103, no. 8, 1 February 2021 (2021-02-01), XP055982065, ISSN: 2469-9950, DOI: 10.1103/PhysRevB.103.085404 *
PUDASAINI, PUSHPA RAJ ET AL.: "High-performance multilayer WSe2 field-effect transistors with carrier type control", NANO RESEARCH, vol. 11, no. 2, 28 February 2018 (2018-02-28), XP036412986, ISSN: 1998-0124, DOI: 10.1007/s12274-017-1681-5 *

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