WO2022226911A1 - 压电mems硅谐振器及其形成方法、电子设备 - Google Patents

压电mems硅谐振器及其形成方法、电子设备 Download PDF

Info

Publication number
WO2022226911A1
WO2022226911A1 PCT/CN2021/091096 CN2021091096W WO2022226911A1 WO 2022226911 A1 WO2022226911 A1 WO 2022226911A1 CN 2021091096 W CN2021091096 W CN 2021091096W WO 2022226911 A1 WO2022226911 A1 WO 2022226911A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
silicon layer
layer
sacrificial
doping concentration
Prior art date
Application number
PCT/CN2021/091096
Other languages
English (en)
French (fr)
Inventor
张孟伦
杨清瑞
宫少波
Original Assignee
天津大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 天津大学 filed Critical 天津大学
Priority to PCT/CN2021/091096 priority Critical patent/WO2022226911A1/zh
Publication of WO2022226911A1 publication Critical patent/WO2022226911A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/05—Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/50—Piezoelectric or electrostrictive devices having a stacked or multilayer structure

Definitions

  • the invention relates to the technical field of resonators, in particular to a piezoelectric MEMS silicon resonator and a method for forming the same, and an electronic device.
  • Piezoelectric MEMS silicon resonator is a kind of MEMS resonator that uses silicon as the resonant body to use the piezoelectric effect of piezoelectric film for mechanical driving and electrical signal detection. This kind of device usually needs to suspend the device part during the processing process. Most of the resonators are fabricated by the following two methods.
  • 1001 is the bottom silicon layer of the SOI silicon wafer
  • 1002 is the buried oxide layer of the SOI silicon wafer
  • 1003 is the top silicon layer of the SOI silicon wafer
  • 1004 is the lower electrode
  • 1005 is the piezoelectric layer
  • 1006 is the upper electrode.
  • the bottom silicon is removed by etching from the back side, and finally the buried oxide layer is washed with HF to release the cantilever beam, and the structure shown in Figure 2 is obtained. This process is usually called back engraving process.
  • the device made by the back-etching process needs to be packaged on both the top and bottom sides, which increases the processing cost and the final thickness of the device.
  • the back-etching process will increase the strength of the substrate. It is not conducive to the high-density arrangement of devices, resulting in a reduction in the number of devices on the entire wafer and an increase in the cost of a single device.
  • the fabrication process is generally as follows: deposit and pattern the lower electrode, piezoelectric layer and upper electrode in turn on SOI with cavity, and then connect the free end and both sides of the beam The top silicon and buried oxide layers are etched away to release the beam, and finally encapsulated by bonding silicon caps.
  • the devices made by the above two processes also have common shortcomings. Although the cantilever beam is released, its fixed end is fixed on the bottom silicon by the original silicon-silicon oxide interface of SOI. This fixation is a rigid connection, so parasitic in SOI Stress, packaging stress, environmental thermal stress, etc. will seriously affect the performance of the device, resulting in resonant frequency drift and low stability. At the same time, devices such as resonators are easily affected by external shock, vibration, thermal noise, etc., and devices fabricated by these two processes cannot effectively shield these noises. Therefore, it is difficult to further improve the quality factor and stability of devices fabricated by traditional processes, which has become a key obstacle to commercialization of products.
  • the present invention provides a piezoelectric MEMS silicon resonator with less resonance frequency drift and high stability, a manufacturing method thereof, and an electronic device including the piezoelectric MEMS silicon resonator.
  • a first aspect of the present invention provides a piezoelectric MEMS silicon resonator, comprising: a silicon substrate; a lower cavity located on the silicon substrate, the top plane of the lower cavity being higher or lower than the top of the substrate a plane; a reserved silicon layer on the lower cavity; a piezoelectric layer and an upper electrode stacked in sequence on the reserved silicon layer.
  • the reserved silicon layer is single crystal silicon.
  • one of the silicon substrate and the reserved silicon layer is a common N-type doping, and the other of the two is a P-type doping with a first doping concentration; or, the silicon substrate and the remaining silicon layer are doped.
  • One of the two reserved silicon layers is of ordinary P-type doping, and the other of the two is of N-type doping of the first doping concentration.
  • the first doping concentration is 10 19 to 9 ⁇ 10 20 cm ⁇ 3 .
  • it further includes: a lower electrode located between the reserved silicon layer and the piezoelectric layer.
  • the piezoelectric MEMS silicon resonator is one of the following: a cantilever beam type, an extensional vibration mode, a thickness longitudinal vibration mode, a Lamb wave vibration mode, an in-plane bending vibration mode, and a surface acoustic wave vibration mode.
  • a second aspect of the present invention provides a method for forming a piezoelectric MEMS silicon resonator, comprising: providing a silicon substrate; forming a sacrificial silicon layer on the silicon substrate; forming a reserved silicon layer on the sacrificial silicon layer; A piezoelectric layer and an upper electrode are sequentially formed on the reserved silicon layer; an etching window is opened, and then the sacrificial silicon layer is selectively removed to form a lower cavity, wherein the sacrificial silicon layer has a second doping concentration
  • P-type doping one of the silicon substrate and the reserved silicon layer is ordinary N-type doping, and the other of the two is P-type doping with a first doping concentration, or the In the case where the sacrificial silicon layer is N-type doped with the second doping concentration, one of the silicon substrate and the reserved silicon layer is ordinary P-type doping, and the other of the two is the first doping concentration N-type doping.
  • the first doping concentration is greater than the second doping concentration.
  • the first doping concentration is 10 19 to 9 ⁇ 10 20 cm ⁇ 3
  • the second doping concentration is 10 13 to 9 ⁇ 10 18 cm ⁇ 3 .
  • the step of forming a sacrificial silicon layer on the silicon substrate includes: forming the sacrificial silicon layer on the silicon substrate by epitaxy.
  • the step of forming a reserved silicon layer on the sacrificial silicon layer includes: using an epitaxial method to form the reserved silicon layer on the sacrificial silicon layer.
  • the method further includes: forming a lower electrode between the reserved silicon layer and the piezoelectric layer.
  • the bottom plane of the sacrificial silicon layer is lower than the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is higher than the top plane of the silicon substrate; or, the bottom plane of the sacrificial silicon layer The plane is lower than the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is equal to the top plane of the silicon substrate; alternatively, the bottom plane of the sacrificial silicon layer is equal to the top plane of the silicon substrate, and the the top plane of the sacrificial silicon layer is higher than the top plane of the silicon substrate; or, the bottom plane of the sacrificial silicon layer is lower than the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is lower than the top plane of the sacrificial silicon layer The top plane of the silicon substrate.
  • the piezoelectric MEMS silicon resonator is a cantilever beam type, an extensional vibration mode, a thickness longitudinal vibration mode, a Lamb wave vibration mode, an in-plane bending vibration mode or a surface acoustic wave vibration mode.
  • a third aspect of the present invention provides a piezoelectric MEMS silicon resonator, which is manufactured by the forming method disclosed in the present invention.
  • a fourth aspect of the present invention provides an electronic device, which is characterized by comprising the piezoelectric MEMS silicon resonator disclosed in the present invention.
  • the use of cavity SOI and ordinary SOI is avoided, thus reducing the cost, and at the same time avoiding the bending phenomenon existing in the production process of using SOI with cavity, thus avoiding the problem caused by the release of cavity SOI. stress problem.
  • SOI is not used, but gold-gold bonding is used. Since gold is a soft material, the stress problem caused by the hard bonding of silicon oxide and silicon is eliminated.
  • a three-dimensional structure (such as a longitudinally raised or lowered beam structure) can be fabricated on the fixed end of the beam, which can greatly eliminate the interference of external stress, vibration and thermal noise, so the device has high stability and signal-to-noise ratio.
  • the three-dimensional structure can also prevent the energy of beam vibration from dissipating outward, which helps to improve the quality factor.
  • the silicon epitaxy process has a controllable thickness and a large range (eg, more than 20 microns), so it has certain advantages in the fabrication of devices with large amplitudes (eg, cantilever beam resonators).
  • the process of the present invention all adopts the plane process, and has better compatibility with the micro-mechanical process compared with the cavity SOI produced by the bulk process. The quality factor of the device is significantly improved due to the substantial reduction of stress and reduction of mechanical losses.
  • Fig. 1 is the device cross-sectional schematic diagram of making cantilever arm on SOI of the prior art before back-etching operation;
  • FIG. 2 is a schematic cross-sectional view of a device after a back-etching operation of a cantilever arm made on the SOI of the prior art
  • FIG. 3 is a schematic cross-sectional view of a piezoelectric MEMS silicon resonator according to an embodiment of the present invention
  • 4a to 4i are schematic diagrams of the fabrication process of the piezoelectric MEMS silicon resonator according to the first embodiment of the present invention
  • 5a to 5c are respectively a schematic cross-sectional view of a piezoelectric MEMS silicon resonator according to a second embodiment of the present invention, a schematic view of a step of forming a heavily doped sacrificial layer, and a schematic view of the step of surface grinding;
  • 6a and 6b are respectively a schematic cross-sectional view of a piezoelectric MEMS silicon resonator according to a third embodiment of the present invention and a schematic view of a step of forming a heavily doped sacrificial layer;
  • FIG. 7a and 7b are respectively a schematic cross-sectional view of a piezoelectric MEMS silicon resonator according to a fourth embodiment of the present invention and a schematic view of a step of forming a heavily doped sacrificial layer;
  • FIG. 8 is a schematic cross-sectional view of a piezoelectric MEMS silicon resonator according to a fifth embodiment of the present invention.
  • the core is to use the single crystal silicon epitaxy and selective etching method to manufacture the cantilever beam of the resonator, and the single crystal silicon A piezoelectric film is deposited thereon to form a resonator.
  • the method of the embodiment of the present invention is simple and easy to implement, and the fabricated device has the advantages of low cost, high quality factor, and high stability.
  • the piezoelectric MEMS silicon resonator mainly includes: a silicon substrate 100 ; a lower cavity 210 located on the silicon substrate 100 , and the lower cavity 210 is obtained by sacrificing the sacrificial silicon layer 200 ; The remaining silicon layer 300 on the lower cavity 210 ; the lower electrode 400 , the piezoelectric layer 500 and the upper electrode 600 are sequentially stacked on the remaining silicon layer 300 .
  • the reserved silicon layer 300 may be single crystal silicon.
  • One of the silicon substrate 100 and the reserved silicon layer 300 is a common N-type doping, and the other of the two is a P-type doping with a first doping concentration; or, one of the silicon substrate 100 and the reserved silicon layer 300 is doped.
  • One is ordinary P-type doping, and the other of the two is N-type doping with a first doping concentration.
  • the doping concentration of ordinary N-type doping and ordinary P-type doping is lower than 10 19 cm -3 .
  • the first doping concentration may be 10 19 to 9 ⁇ 10 20 cm ⁇ 3 .
  • the lower electrode 400 is an optional structure. When the material of the remaining silicon layer 300 is degenerate silicon, it has good conductivity and can directly serve as an electrode, so that the lower electrode 400 can be omitted.
  • the upper electrode 600, the piezoelectric layer 500, the lower electrode 400 and the reserved silicon layer 300 together form a cantilever beam.
  • the piezoelectric MEMS silicon resonator of other embodiments of the present invention may also be an extensional vibration mode, a thickness longitudinal vibration mode, a Lamb wave vibration mode, an in-plane bending vibration mode or a surface acoustic wave vibration mode, etc. .
  • the bottom plane of the lower cavity 210 is lower than the top plane of the silicon substrate 100 , and the top plane of the lower cavity 210 is higher than the top plane of the silicon substrate 100 .
  • the bottom plane of the lower cavity may be lower than the top plane of the silicon substrate, and the top plane of the lower cavity is equal to the top plane of the silicon substrate; or, the lower cavity The bottom plane is equal to the top plane of the silicon substrate, and the top plane of the lower cavity is higher than the top plane of the silicon substrate; or, the bottom plane of the lower cavity is lower than the top plane of the silicon substrate, and the top plane of the lower cavity is lower than The top plane of the silicon substrate.
  • the formation methods of piezoelectric MEMS silicon resonators with lower cavities in different ways will be mentioned in detail later. It should be noted that the SOI wafer processing-based resonator mentioned in the background art cannot satisfy the feature of "the top plane of the lower cavity and the top plane of the silicon substrate are not coplanar". Therefore, compared with the prior art, the piezoelectric MEMS silicon resonator of the embodiment of the present invention has the advantages of flexible design and can meet certain special application requirements and the like.
  • the piezoelectric MEMS silicon resonator may further include a silicon cap 900 , and the silicon cap 900 includes an insulating layer 930 , an upper substrate 920 and a metal connection region 910 .
  • the insulating layer 930 is optional, and the metal connection region 910 may be composed of one layer of metal material or multiple layers of metal material.
  • the silicon cap 900 is bonded to the remaining silicon layer 300 through the bonding layer 800, and an upper cavity 700 is constructed.
  • the material selection for each part is as follows:
  • the substrate 100 is described by taking N-type single crystal silicon as an example in Embodiments 1 to 4 of the present invention, and can also be made of other materials, such as aluminum nitride, gallium arsenide, sapphire, and the like.
  • the remaining silicon layer 300 which matches the substrate 100 in this example, can use P-type single crystal silicon with a first doping concentration.
  • the specific material can be selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a combination of the above metals or their alloys, or a non-metallic conductive material, such as doped silicon Wait.
  • the lower electrode 400 is an optional structure.
  • the remaining silicon layer 300 can directly function as the lower electrode.
  • the fabrication of the lower electrode is omitted, which is simple and easy to implement; on the other hand, the frequency temperature drift coefficient of the lower electrode is usually large. , the temperature stability of the resonator will be improved by omitting the lower electrode.
  • the piezoelectric layer 500 can be selected from materials such as aluminum nitride, zinc oxide, and PZT, and includes a rare earth element doped material with a certain atomic ratio of the above materials.
  • the specific material can be selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a combination of the above metals or their alloys, or a non-metallic conductive material, such as doped silicon Wait.
  • the bonding layer 800 is generally a combination of gold-gold, and can also be a combination of other metals (eg, aluminum-germanium, copper-copper, copper-gold-copper, gold-tin, gold-tin-copper, etc.) or silicon dioxide , polymers and other commonly used bonding materials.
  • other metals eg, aluminum-germanium, copper-copper, copper-gold-copper, gold-tin, gold-tin-copper, etc.
  • silicon dioxide silicon dioxide
  • Silicon cap 900 including:
  • the metal connection area 910, the specific material can be selected from gold, copper, aluminum or a composite of the above metals or their alloys;
  • the upper substrate 920 the material can be selected from single crystal silicon, polycrystalline silicon, aluminum nitride, gallium arsenide, sapphire, metal, etc.;
  • the specific material of the insulating layer 930 can be selected from silicon oxide, aluminum nitride, aluminum oxide, silicon nitride, and the like.
  • FIGS. 4 a to 4 i The method for forming the piezoelectric MEMS silicon resonator according to the first embodiment of the present invention is shown in FIGS. 4 a to 4 i . It mainly includes the following steps:
  • Step 1 Open the window.
  • a layer of silicon dioxide 110 is first deposited on the single crystal silicon substrate 100, and the silicon dioxide 110 is patterned by using a photoresist as a mask to expose the area where the cavity under the resonator is to be formed.
  • Step 2 Etch the grooves.
  • the silicon dioxide 110 patterned in the previous step is used as a mask, and the silicon is etched by dry etching or wet etching.
  • the depth of the etched grooves here is controllable, and thus the height of the resulting lower cavity is controllable.
  • Step 3 Epitaxial sacrificial layer.
  • the second doping concentration P-type single crystal silicon is epitaxial (for example, boron doping is used, and the doping concentration is 10 18 cm -3 ), and hydrogen chloride gas is added during the epitaxy. And controlling its flow rate can realize selective epitaxy only on single crystal silicon without growing epitaxial silicon layer on the surface of silicon dioxide mask.
  • the epitaxial second doping concentration P-type silicon is used as the sacrificial layer, its thickness can be controlled by the epitaxial time, and a larger cavity can be formed, and the thickness is in the range of 1-50um.
  • Step 4 Epitaxially retaining the silicon layer 300 and depositing the lower electrode 400 .
  • the oxide layer of the structure obtained in step 3 is first removed with HF, and then the surface is epitaxially doped with P-type silicon with a first doping concentration (for example, boron doping is used, and the doping concentration is 10 20 cm -3 ) to obtain The silicon layer 300 is retained, and then a layer of molybdenum is deposited as the lower electrode 400 .
  • a first doping concentration for example, boron doping is used, and the doping concentration is 10 20 cm -3
  • Step 5 Deposition of piezoelectric layer 500 and patterning. As shown in Figure 4e, a piezoelectric layer of aluminum nitride is first deposited, and the aluminum nitride is patterned by dry method, and then the lower electrode is etched by dry method or wet method to make it patterned.
  • Step 6 Depositing the upper electrode 600 .
  • a layer of molybdenum is deposited first, and then the molybdenum electrode is etched by using the patterned photoresist as a mask to make it patterned to obtain the upper electrode 600 .
  • the processing sequence of the lower electrode 400, the piezoelectric layer 500, and the upper electrode 600 may not be limited to the above scheme.
  • the lower electrode 400 can also be patterned first, and then the piezoelectric layer can be deposited. 500 and the upper electrode 600, and then the upper electrode 600 and the piezoelectric layer 500 are patterned in sequence.
  • Step 7 Open the etching window.
  • a layer of silicon oxide is first deposited, and then the silicon oxide is wet-etched using the photoresist as a mask, and then the P-type silicon layer with the first doping concentration is dry-etched using the silicon oxide as a hard mask. Etch until the right end and both sides of the beam are etched to reveal the second doping concentration P-type silicon layer, and HF is used as an etchant to remove the silicon oxide on the surface.
  • Step 8 Beam Release. As shown in Figure 4h, the structure obtained in step 7 is placed in an etching solution, and a pulse signal is applied as described above to selectively etch away the heavily doped sacrificial layer 200 with the second doping concentration P-type.
  • Step 9 Bond Package.
  • the pre-fabricated silicon cap 900 is placed on the structure obtained in step 8 for bonding and packaging. It can be Au-Au bonding, Al-Ge bonding, Cu-Au-Cu bonding or other metal or polymer bonding.
  • the piezoelectric MEMS silicon resonator of the second embodiment of the present invention is shown in FIG. 5a.
  • the difference between Embodiment 2 and Embodiment 1 is that the main body of the resonator is straight.
  • the difference from Embodiment 1 is that, as shown in Figure 5b, the sacrificial layer is epitaxially extended to a level slightly higher than the interface between silicon and silicon oxide, and then the silicon oxide is washed away with HF, and the The surface of Guiping was polished by mechanical polishing technology, as shown in Figure 5c. Since a flat surface is obtained here, a flat resonator body is obtained in subsequent operations.
  • the piezoelectric MEMS silicon resonator of the third embodiment of the present invention is shown in FIG. 6a.
  • the lower cavity is completely formed by the lifting of the epitaxial beam, and there is no groove on the silicon substrate 100 .
  • the difference in the process steps is that after opening the window in step 1, step 2 of etching the groove is skipped, and the deposition of the sacrificial layer is directly performed, as shown in FIG. 6b.
  • the piezoelectric MEMS silicon resonator of the fourth embodiment of the present invention is shown in FIG. 7a.
  • the beam is recessed downward.
  • the difference in the manufacturing process is: when depositing the sacrificial layer, the surface of the sacrificial layer is lower than the interface between silicon and silicon oxide, as shown in Figure 7b, the remaining steps and examples 1 is the same.
  • the piezoelectric MEMS silicon resonator according to the fourth embodiment of the present invention is shown in FIG. 8 .
  • the remaining silicon layer 300' is N-type single crystal silicon
  • the silicon substrate 100' is P-type single crystal silicon with a first doping concentration.
  • the process difference from Embodiment 1 is that the operation is performed with the first doping concentration P-type silicon as the raw material, the sacrificial layer is still the second doping concentration P-type silicon, and the N-type single crystal silicon is epitaxially formed on the sacrificial layer.
  • the N-type silicon is still connected to a positive voltage during selective etching.
  • the doping concentration of the silicon layer of the first doping concentration can be adjusted as required, thereby changing its temperature coefficient of frequency TCF. Since the frequency temperature coefficient of the beam is related to the frequency temperature coefficient of each layer material and the thickness structure, the doping concentration of the silicon layer with the first doping concentration can be adjusted to make the TCF to be an appropriate value, and the TCF of other parts of the resonator can be adjusted. Therefore, the total equivalent TCF of the resonator beam is made zero, so as to achieve the purpose of temperature compensation and avoid temperature drift.
  • the formation process of the piezoelectric MEMS silicon resonator according to the embodiment of the present invention may be as follows: sequentially epitaxially growing P-type silicon with a second doping concentration and P-type silicon with a first doping concentration on an N-type silicon substrate, wherein the second doping concentration is P-type silicon.
  • P-type silicon with doping concentration is a sacrificial layer; it is also possible to sequentially epitaxially epitaxy P-type silicon and N-type silicon with a second doping concentration on a P-type silicon substrate with a first doping concentration, wherein the P-type silicon with the second doping concentration is a sacrificial layer Floor.
  • N-type silicon with a second doping concentration and N-type silicon with a first doping concentration on P-type silicon
  • sequentially epitaxially grow N-type silicon with a second doping concentration and N-type silicon with a second doping concentration on the N-type silicon with a first doping concentration P-type silicon, wherein the second doping concentration N-type silicon is a sacrificial layer.
  • the first doping concentration is greater than the second doping concentration.
  • the second doping concentration is 10 13 to 9 ⁇ 10 18 cm -3
  • the first doping concentration is 10 19 to 9 ⁇ 10 20 cm -3 .
  • the dopant for P-type doping is generally boron element, and may also be group III elements such as aluminum, gallium, and indium; the dopant for N-type doping is generally group five elements such as phosphorus element or arsenic.
  • a passivation film is formed on the surface of the substrate and the surface of the P-type silicon with the first doping concentration; when the voltage is zero, the etching solution is etched in the same direction, and the passivation film on the surface of the N-type silicon substrate and the surface of the P-type silicon with the first doping concentration and the second doping concentration P-type silicon is etched.
  • the pulse signal is used to control this process to repeat, so as to realize the selective etching of the P-type silicon with the second doping concentration.
  • a cavity is formed under the P-type silicon with the first doping concentration, and a cantilever beam is formed based on the P-type silicon with the first doping concentration.
  • the electronic device includes any piezoelectric MEMS silicon resonator disclosed in the present invention.
  • the silicon resonator is fabricated by silicon epitaxial growth and selective etching of silicon with different doping concentrations, avoiding the use of cavity SOI and common SOI and thus reducing the cost. At the same time, the bending phenomenon existing in the manufacturing process of the SOI with the cavity is avoided, so the stress problem caused by the release of the SOI with the cavity is avoided.
  • SOI is not used, but gold-gold bonding is used. Since gold is a soft material, the stress problem caused by the hard bonding of silicon oxide and silicon is eliminated.
  • a three-dimensional structure (such as a longitudinally raised or lowered beam structure) can be fabricated on the fixed end of the epitaxial beam, which can greatly eliminate the interference of external stress, vibration and thermal noise, so the device has high stability and signal-to-noise.
  • the three-dimensional structure can also prevent the energy of beam vibration from dissipating outward, helping to improve the quality factor.
  • the silicon epitaxy process has a controllable thickness and a large range (eg, more than 20 microns), so it has certain advantages in the fabrication of devices with large amplitudes (eg, cantilever beam resonators).
  • the process of the present invention all adopts the plane process, and has better compatibility with the micro-mechanical process compared with the cavity SOI produced by the bulk process. The quality factor of the device is significantly improved due to the substantial reduction of stress and reduction of mechanical losses.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

本发明公开了一种压电MEMS硅谐振器及其形成方法，以及电子设备。该压电MEMS硅谐振器包括：硅基底；下空腔，下空腔的顶平面高于或者低于基底的顶平面；位于下空腔之上的保留硅层；位于保留硅层之上的压电层和上电极。形成方法包括：提供硅基底；在硅基底之上依次形成牺牲硅层、保留硅层、压电层和上电极；开刻蚀窗，去除牺牲硅层以形成下空腔，其中，牺牲硅层为第二掺杂浓度P型掺杂的情况下，硅基底与保留硅层二者中之一为普通N型掺杂，二者中另一为第一掺杂浓度P型掺杂，或者，牺牲硅层为第二掺杂浓度N型掺杂的情况下，硅基底与保留硅层二者中之一为普通P型掺杂，二者中另一为第一掺杂浓度N型掺杂，所述第一掺杂浓度大于所述第二掺杂浓度。

Description

压电MEMS硅谐振器及其形成方法、电子设备 技术领域
本发明涉及谐振器技术领域，具体涉及一种压电MEMS硅谐振器及其形成方法，以及一种电子设备。
背景技术
压电MEMS硅谐振器是一类以硅为谐振主体利用压电薄膜的压电效应进行机械驱动及电信号检测的MEMS谐振器，这类器件在加工过程通常需要将器件部分悬空，当前这类谐振器大多采用以下两种方法制作。
(1)参考图1和图2，1001为SOI硅片的底硅层，1002为SOI硅片的埋氧层，1003为SOI硅片的顶硅层，1004为下电极，1005为压电层，1006为上电极。如图1在SOI硅片的顶硅层中制作好悬臂梁后，从背面刻蚀将底硅除去，最后用HF洗掉埋氧层使悬臂梁得到释放，得到图2所示结构。这种工艺通常叫做背刻工艺。由于谐振器在使用时通常需要密封封装，因此背刻工艺制作的器件需要在顶底两面均进行封装，从而使器件加工成本以及最终厚度增加，另一方面，采用背刻工艺会使衬底强度降低，不利于器件高密度排列，从而导致整片晶圆上器件数量减少，单个器件成本增加。
(2)通过带空腔的SOI硅片制作，其制作流程一般为：在带空腔的SOI上依次沉积并图形化下电极、压电层、上电极，随后将梁的自由端及两侧的顶硅和埋氧层刻蚀掉使梁释放，最后用键合硅帽的方式进行封装。在这个工艺过程中存在很多缺点，首先，由于空腔SOI的空腔内气压较低，通常在大气压力下空腔上的顶硅层会发生凹陷，在空腔上制作的器件也会相应的弯曲；当梁被释放后空腔与大气连通，顶硅和埋氧层趋向于恢复平直状态而电极层和压电层的初始状态是弯曲状态，因此在这个过程中顶硅 和压电层之间产生较大应力。该应力将导致器件品质因数Q降低。其次，带空腔的SOI需要根据不同谐振器定制，因此，制作周期较长，且非常昂贵，因此采用空腔SOI制造的器件成本也随之升高。
采用以上两种工艺制作的器件还有共同的缺点，虽然悬臂梁被释放但其固定端由SOI原有的硅-氧化硅界面固定在底硅上，这一固定属于刚性连接，因而SOI中寄生应力、封装应力、环境热应力等都将严重影响器件的性能，导致谐振频率漂移，稳定性不高。同时，谐振器等器件很容易受到外界冲击、振动、热噪音等影响，通过这两种工艺制作的器件不能有效地屏蔽这些噪音。因此，采用传统工艺制作的器件很难进一步提高品质因数及稳定性，成为实现产品商业化的关键障碍。
发明内容
有鉴于此，本发明提出一种谐振频率漂移较少，稳定性较高的压电MEMS硅谐振器及其制造方法，以及包括该压电MEMS硅谐振器的电子设备。
本发明第一方面提出一种压电MEMS硅谐振器，包括：硅基底；位于所述硅基底之上的下空腔，所述下空腔的顶平面高于或者低于所述基底的顶平面；位于所述下空腔之上的保留硅层；位于所述保留硅层之上的依次堆叠的压电层和上电极。
可选地，所述保留硅层为单晶硅。
可选地，所述硅基底与所述保留硅层二者中之一为普通N型掺杂，二者中另一为第一掺杂浓度P型掺杂；或者，所述硅基底与所述保留硅层二者中之一为普通P型掺杂，二者中另一为第一掺杂浓度N型掺杂。
可选地，所述第一掺杂浓度为10 19至9×10 20cm -3。
可选地，还包括：位于所述保留硅层与所述压电层之间的下电极。
可选地，所述压电MEMS硅谐振器为如下之一种：悬臂梁式、延伸振动模式、厚度纵向振动模式、兰姆波振动模式、面内弯曲振动模式、声表面波振动模式。
本发明第二方面提出一种压电MEMS硅谐振器的形成方法，包括：提供硅基底；在所述硅基底之上形成牺牲硅层；在所述牺牲硅层之上形成保留硅层；在所述保留硅层之上依次形成压电层和上电极；开刻蚀窗，然后选择性地去除所述牺牲硅层以形成下空腔，其中，所述牺牲硅层为第二掺杂浓度P型掺杂的情况下，所述硅基底与所述保留硅层二者中之一为普通N型掺杂，二者中另一为第一掺杂浓度P型掺杂，或者，所述牺牲硅层为第二掺杂浓度N型掺杂的情况下，所述硅基底与所述保留硅层二者中之一为普通P型掺杂，二者中另一为第一掺杂浓度N型掺杂。
可选地，所述第一掺杂浓度大于所述第二掺杂浓度。
可选地，所述第一掺杂浓度为10 19至9×10 20cm -3，所述第二掺杂浓度为10 13至9×10 18cm -3。
可选地，所述在所述硅基底之上形成牺牲硅层的步骤包括：在所述硅基底之上使用外延方式形成所述牺牲硅层。
可选地，所述在所述牺牲硅层之上形成保留硅层的步骤包括：在所述牺牲硅层之上使用外延方式形成所述保留硅层。
可选地，还包括：在所述保留硅层与所述压电层之间形成下电极。
可选地，所述牺牲硅层的底平面低于所述硅基底的顶平面，并且所述牺牲硅层的顶平面高于所述硅基底的顶平面；或者，所述牺牲硅层的底平 面低于所述硅基底的顶平面，并且所述牺牲硅层的顶平面等于所述硅基底的顶平面；或者，所述牺牲硅层的底平面等于所述硅基底的顶平面，并且所述牺牲硅层的顶平面高于所述硅基底的顶平面；或者，所述牺牲硅层的底平面低于所述硅基底的顶平面，并且所述牺牲硅层的顶平面低于所述硅基底的顶平面。
可选地，所述压电MEMS硅谐振器为悬臂梁式、延伸振动模式、厚度纵向振动模式、兰姆波振动模式、面内弯曲振动模式或者声表面波振动模式。
本发明第三方面提出一种压电MEMS硅谐振器，其通过本发明公开的形成方法制得。
本发明第四方面提出一种电子设备，其特征在于，包括本发明公开的压电MEMS硅谐振器。
根据本发明的技术方案，避免了空腔SOI及普通SOI的使用，因此降低了成本，同时避免了采用带空腔SOI制作过程中存在的弯曲现象，因此避免了由于空腔SOI释放后带来的应力问题。其次，在本发明实例中不使用SOI，采用金-金键合，由于金为软质材料，因此消除了由于氧化硅-硅硬质结合带来的应力问题。另外，可在梁的固定端制作三维结构(如纵向上抬起或降低的梁结构)，可以大幅度消除外界应力、振动和热噪音的干扰，因而器件具有较高的稳定性和信噪比，三维结构还可以防止梁振动的能量向外耗散，有助于提高品质因数。再次，硅外延工艺的生长硅薄膜厚度可控且范围大(如20微米以上)，因而在振幅较大的器件(如悬臂梁式谐振器)制作中具有一定优势。最后，本发明工艺全部采用平面工艺，和采用体工艺制作的空腔SOI相比，具有更好的微机械工艺兼容性。由于应力的大幅度减少及机械损耗减少使得器件的品质因数明显提高。
附图说明
为了说明而非限制的目的，现在将根据本发明的优选实施例、特别是参考附图来描述本发明，其中：
图1为现有技术的SOI上制作悬梁臂在背刻操作前的器件剖面示意图；
图2为现有技术的SOI上制作悬梁臂在背刻操作后的器件剖面示意图；
图3为本发明实施方式的压电MEMS硅谐振器的剖面示意图；
图4a至图4i为本发明第一实施例的压电MEMS硅谐振器的制作过程示意图；
图5a至图5c分别为本发明第二实施例的压电MEMS硅谐振器的剖面示意图、形成重掺牺牲层步骤示意图和表面磨平步骤示意图；
图6a和图6b分别为本发明第三实施例的压电MEMS硅谐振器的剖面示意图和形成重掺牺牲层步骤示意图；
图7a和图7b分别为本发明第四实施例的压电MEMS硅谐振器的剖面示意图和形成重掺牺牲层步骤示意图；
图8为本发明第五实施例的压电MEMS硅谐振器的剖面示意图。
具体实施方式
鉴于现有技术存在的问题，本发明实施方式的压电MEMS硅谐振器及其制造方法，核心为采用单晶硅外延并选择性刻蚀的方法制作谐振器的悬臂梁，并在单晶硅之上沉积压电薄膜形成谐振器。本发明实施方式的方法简便易行，制作的器件具有低成本、高品质因数、稳定性高等优势。
如图3所示，本发明实施方式的压电MEMS硅谐振器主要包括：硅基底100；位于硅基底100之上的下空腔210，该下空腔210通过牺牲硅层200牺牲得到；位于下空腔210之上的保留硅层300；位于保留硅层300之上的依次堆叠的下电极400、压电层500和上电极600。其中，保留硅层300可以为单晶硅。硅基底100与保留硅层300二者中之一为普通N型掺杂，二者中另一为第一掺杂浓度P型掺杂；或者，硅基底100与保留硅层300二者中之一为普通P型掺杂，二者中另一为第一掺杂浓度N型掺杂。其中，普通N型掺杂和普通P型掺杂的掺杂浓度低于10 19cm -3。第一掺杂浓度可以为10 19至9×10 20cm -3。需要说明的是，下电极400是可选结构。 当保留硅层300材料为简并硅时具有良好导电性，可以直接充当电极，从而可以省略下电极400。
该实施例中，上电极600、压电层500、下电极400以及保留硅层300共同组成悬臂梁。但是除了悬臂梁式，本发明其他实施方式的压电MEMS硅谐振器中还可以为延伸振动模式、厚度纵向振动模式、兰姆波振动模式、面内弯曲振动模式或者声表面波振动模式等等。
该实施例中，下空腔210的底平面低于硅基底100的顶平面，并且下空腔210的顶平面高于硅基底100的顶平面。在其他实施方式的压电MEMS硅谐振器中，还可以为：下空腔的底平面低于硅基底的顶平面，并且下空腔的顶平面等于硅基底的顶平面；或者，下空腔的底平面等于硅基底的顶平面，并且下空腔的顶平面高于硅基底的顶平面；或者，下空腔的底平面低于硅基底的顶平面，并且下空腔的顶平面低于硅基底的顶平面。具有不同方式的下空腔的压电MEMS硅谐振器的形成方法将在后文中详细提及。需要说明的是，背景技术中提到的基于SOI晶圆加工的谐振器是无法满足“下空腔顶平面与硅基底顶平面二者不共面”特征的。因此，本发明实施方式的压电MEMS硅谐振器与现有技术对比，具有设计灵活、可以满足某些特殊应用需求等优点。
该实施例中，压电MEMS硅谐振器还可以包括硅帽900，该硅帽900包括绝缘层930、上基底920和金属连接区910。其中，绝缘层930为可选项，金属连接区910可以是一层金属材料也可以是多层金属材料构成。硅帽900通过键合层800与保留硅层300键合，并且构造出上空腔700。
各个部分的材料选择情况如下：
基底100，本发明实施例1至实施例4中以N型单晶硅为例说明，也可以是其他材料，如氮化铝、砷化镓、蓝宝石等。
下空腔210。
保留硅层300，本实例中与基底100相匹配，可以使用第一掺杂浓度 P型单晶硅。
下电极400，具体材料可选钼、钌、金、铝、镁、钨、铜、钛、铱、锇、铬或以上金属的复合或其合金，也可以采用非金属导电材料，如掺杂硅等。下电极400为可选结构，例如保留硅层300可直接起到下电极作用，这样一方面省去了下电极的制作，简便易行；另一方面由于下电极的频率温漂系数通常较大，省去下电极后谐振器的温度稳定性将得到改善。
压电层500，可选氮化铝、氧化锌、PZT等材料并包含上述材料的一定原子比的稀土元素掺杂材料。
上电极600，具体材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金，也可以采用非金属导电材料，如掺杂硅等。
上空腔700。
键合层800，一般为金-金组合，也可以是其他金属组合(如：铝-锗、铜-铜、铜-金-铜、金-锡、金-锡-铜等)或二氧化硅、高聚物等常用的键合材料等。
硅帽900，包括：
金属连接区910，具体材料可选金、铜、铝或以上金属的复合或其合金；
上基底920，材料可选单晶硅、多晶硅、氮化铝、砷化镓、蓝宝石、金属等；
绝缘层930，具体材料可选氧化硅、氮化铝、氧化铝、氮化硅等。
下面介绍五个实施例的压电MEMS硅谐振器的制造过程。
实施例1
本发明第一实施例的压电MEMS硅谐振器的形成方法如图4a至图4i所示。主要包括如下步骤：
步骤1：开窗。如图4a，先在单晶硅基底100上沉积一层二氧化硅110，以光刻胶为掩膜图形化二氧化硅110，将要制作谐振器下空腔的区域露出。
步骤2：刻蚀凹槽。如图4b，以上步图形化的二氧化硅110为掩膜， 刻蚀硅，可以采用干法刻蚀，也可以采用湿法刻蚀。这里刻蚀凹槽的深度可控，因而得到的下空腔高度可控。
步骤3：外延牺牲层。如图4c，在步骤2得到的凹槽上外延第二掺杂浓度P型单晶硅(如：采用硼掺杂，掺杂浓度为10 18cm -3)，在外延时通过增加氯化氢气体，并控制其流量，可实现只在单晶硅上选择性外延，而在二氧化硅掩膜表面不生长外延硅层。外延第二掺杂浓度P型硅作为牺牲层时其厚度可通过外延时间进行控制，可形成较大空腔，厚度范围在1～50um。
步骤4：外延保留硅层300及沉积下电极400。如图4d，首先将步骤3得到的结构用HF除去氧化层，之后再在表面外延第一掺杂浓度P型硅(如：采用硼掺杂，掺杂浓度为10 20cm -3)即得到保留硅层300，然后再沉积一层钼作为下电极400。
步骤5：沉积压电层500并图形化。如图4e，先沉积一层氮化铝压电层，采用干法图形化氮化铝，随后用干法或湿法刻蚀下电极，使其图形化。
步骤6：沉积上电极600。如图4f，先沉积一层钼，随后以图形化的光刻胶作为掩膜刻蚀钼电极，使其图形化，得到上电极600。
注意在上述步骤4到6中，下电极400、压电层500、上电极600三层的加工顺序可以不限于上述方案，例如：也可以先对下电极400进行图形化，再沉积压电层500和上电极600，随后再依次对上电极600和压电层500进行图形化。
步骤7：开刻蚀窗。如图4g，首先沉积一层氧化硅，随后以光刻胶为掩膜对氧化硅进行湿法刻蚀，然后以氧化硅作为硬掩模对第一掺杂浓度P型硅层进行干法刻蚀直至右端及梁的两侧刻透露出第二掺杂浓度P型硅层，以HF为刻蚀剂去除表面的氧化硅。
步骤8：梁释放。如图4h，将步骤7得到的结构置于刻蚀液中，并按上述说明施加脉冲信号，选择性地刻蚀掉第二掺杂浓度P型的重掺牺牲层200。
步骤9：键合封装。如图4i，将事先制作好的硅帽900置于步骤8得到的结构上方进行键合封装。可以是Au-Au键合、也可以是Al-Ge键合、Cu-Au-Cu键合或其他金属或聚合物键合等方式。
实施例2
本发明第二实施例的压电MEMS硅谐振器如图5a所示。实施例2与实施例1的区别在于其谐振器主体为平直。在本实施例的制造过程中，与实施例1的区别在于，如图5b，外延牺牲层时外延至牺牲层略高于硅与氧化硅的界面，之后用HF洗去氧化硅，在用化学机械抛光技术将桂平表面抛光，如图5c。由于此处得到平整的表面，因而在后续操作中得到平直的谐振器主体。
实施例3
本发明第三实施例的压电MEMS硅谐振器如图6a所示。实施例3中下空腔完全由外延梁的翘起形成，而在硅基底100上没有凹槽。与实施例1相比，其工艺步骤的不同之处在于：经过步骤1开窗后，跳过刻蚀凹槽的步骤2，直接进行牺牲层的沉积，如图6b。
实施例4
本发明第四实施例的压电MEMS硅谐振器如图7a所示。实施例4中梁为向下凹陷，与实施例1相比，其在制作工艺上的差异在于：沉积牺牲层时使牺牲层表面低于硅和氧化硅界面如图7b，其余步骤和实施例1相同。
实施例5
本发明第四实施例的压电MEMS硅谐振器如图8所示。与实施例1的结构相比，本实施例中保留硅层300’为N型单晶硅，而硅基底100’为第一掺杂浓度P型单晶硅。与实施例1的工艺区别在于：以第一掺杂浓度P型硅为原材料进行作业，牺牲层仍为第二掺杂浓度P型硅，在牺牲层上外延N型单晶硅。选择性刻蚀时仍为N型硅接正电压。
根据本发明实施方式的压电MEMS硅谐振器，第一掺杂浓度的硅层可根据需要调节掺杂浓度，从而改变其频率温度系数TCF。由于梁的频率温度系数与各层材料的频率温度系数以及厚度结构均有关系，因此可调节第一掺杂浓度的硅层的掺杂浓度使TCF为适当的值，和谐振器其他部分的 TCF相抵消，进而使谐振器梁的总等效TCF为零，达到温度补偿的目的，避免温漂。
根据本发明实施方式的压电MEMS硅谐振器的形成过程，可以为：在N型硅衬底上依次外延生长第二掺杂浓度P型硅和第一掺杂浓度P型硅，其中第二掺杂浓度P型硅为牺牲层；也可以在第一掺杂浓度P型硅衬底上依次外延第二掺杂浓度P型硅和N型硅，其中第二掺杂浓度P型硅为牺牲层。还可以在P型硅上依次外延生长第二掺杂浓度N型硅和第一掺杂浓度N型硅，或在第一掺杂浓度N型硅上依次外延第二掺杂浓度N型硅和P型硅，其中第二掺杂浓度N型硅为牺牲层。其中第一掺杂浓度大于第二掺杂浓度。可选的，第二掺杂浓度为10 13到9×10 18cm -3，第一掺杂浓度为10 19到9×10 20cm -3。其中，P型掺杂的掺杂剂一般为硼元素，也可以是铝、镓、铟等三族元素；N型掺杂的掺杂剂一般为磷元素或砷等五族元素。
以“在N型硅衬底上依次外延生长第二掺杂浓度P型硅和第一掺杂浓度P型硅，其中第二掺杂浓度P型硅为牺牲层”为例，说明在进行牺牲层释放时采用的工艺流程如下：在N型硅衬底上加正脉冲电信号，负极接第一掺杂浓度P型硅。当N型硅衬底上加正电压时，电流通过刻蚀液由N型硅衬底流向第二掺杂浓度P型硅，第二掺杂浓度P型硅被刻蚀，而在N型硅衬底和第一掺杂浓度P型硅表面形成钝化薄膜；当电压为零时，刻蚀液同向刻蚀，N型硅衬底和第一掺杂浓度P型硅表面的钝化膜及第二掺杂浓度P型硅被刻蚀。通过脉冲信号控制此过程反复进行，实现对第二掺杂浓度P型硅的选择性刻蚀。结果，第一掺杂浓度P型硅的下方形成空腔，及形成以第一掺杂浓度P型硅为基底的悬臂梁。
本发明实施方式的电子设备，包括本发明公开的任一种压电MEMS硅谐振器。
根据本发明实施方式的技术方案，采用硅外延生长和对不同掺杂浓度硅进行选择性刻蚀的方法制作硅谐振器，避免了空腔SOI及普通SOI的使 用因此降低了成本。同时，避免了采用带空腔SOI制作过程中存在的弯曲现象，因此避免了由于空腔SOI释放后带来的应力问题。其次，在本发明实例中不使用SOI，采用金-金键合，由于金为软质材料，因此消除了由于氧化硅-硅硬质结合带来的应力问题。另外，可在外延梁的固定端制作三维结构(如纵向上抬起或降低的梁结构)，可以大幅度消除外界应力、振动和热噪音的干扰，因而器件具有较高的稳定性和信噪比，三维结构还可以防止梁振动的能量向外耗散，有助于提高品质因数。再次，硅外延工艺的生长硅薄膜厚度可控且范围大(如20微米以上)，因而在振幅较大的器件(如悬臂梁式谐振器)制作中具有一定优势。最后，本发明工艺全部采用平面工艺，和采用体工艺制作的空腔SOI相比，具有更好的微机械工艺兼容性。由于应力的大幅度减少及机械损耗减少使得器件的品质因数明显提高。
上述具体实施方式，并不构成对本发明保护范围的限制。本领域技术人员应该明白的是，取决于设计要求和其他因素，可以发生各种各样的修改、组合、子组合和替代。任何在本发明的精神和原则之内所作的修改、等同替换和改进等，均应包含在本发明保护范围之内。

Claims (16)

  1. 一种压电MEMS硅谐振器，其特征在于，包括：
    硅基底；
    位于所述硅基底之上的下空腔，所述下空腔的顶平面高于或者低于所述基底的顶平面；
    位于所述下空腔之上的保留硅层；
    位于所述保留硅层之上的依次堆叠的压电层和上电极。
  2. 根据权利要求1所述的压电MEMS硅谐振器，其特征在于，所述保留硅层为单晶硅。
  3. 根据权利要求2所述的压电MEMS硅谐振器，其特征在于，所述硅基底与所述保留硅层二者中之一为普通N型掺杂，二者中另一为第一掺杂浓度P型掺杂；或者，所述硅基底与所述保留硅层二者中之一为普通P型掺杂，二者中另一为第一掺杂浓度N型掺杂。
  4. 根据权利要求3所述的压电MEMS硅谐振器，其特征在于，所述第一掺杂浓度为10 19至9×10 20cm -3。
  5. 根据权利要求1所述的压电MEMS硅谐振器，其特征在于，还包括：位于所述保留硅层与所述压电层之间的下电极。
  6. 根据权利要求1至5中任一项所述的压电MEMS硅谐振器，其特征在于，所述压电MEMS硅谐振器为如下之一种：悬臂梁式、延伸振动模式、厚度纵向振动模式、兰姆波振动模式、面内弯曲振动模式、声表面波振动模式。
  7. 一种压电MEMS硅谐振器的形成方法，其特征在于，包括：
    提供硅基底；
    在所述硅基底之上形成牺牲硅层；
    在所述牺牲硅层之上形成保留硅层；
    在所述保留硅层之上依次形成压电层和上电极；
    开刻蚀窗，然后选择性地去除所述牺牲硅层以形成下空腔，其中，
    所述牺牲硅层为第二掺杂浓度P型掺杂的情况下，所述硅基底与所述保留硅层二者中之一为普通N型掺杂，二者中另一为第一掺杂浓度P型掺杂，或者，
    所述牺牲硅层为第二掺杂浓度N型掺杂的情况下，所述硅基底与所述保留硅层二者中之一为普通P型掺杂，二者中另一为第一掺杂浓度N型掺杂。
  8. 根据权利要求7所述的形成方法，其特征在于，所述第一掺杂浓度大于所述第二掺杂浓度。
  9. 根据权利要求8所述的形成方法，其特征在于，所述第一掺杂浓度为10 19至9×10 20cm -3，所述第二掺杂浓度为10 13至9×10 18cm -3。
  10. 根据权利要求7所述的形成方法，其特征在于，所述在所述硅基底之上形成牺牲硅层的步骤包括：在所述硅基底之上使用外延方式形成所述牺牲硅层。
  11. 根据权利要求7所述的形成方法，其特征在于，所述在所述牺牲硅层之上形成保留硅层的步骤包括：在所述牺牲硅层之上使用外延方式形成所述保留硅层。
  12. 根据权利要求7所述的形成方法，其特征在于，还包括：在所述保留硅层与所述压电层之间形成下电极。
  13. 根据权利要求7所述的形成方法，其特征在于，
    所述牺牲硅层的底平面低于所述硅基底的顶平面，并且所述牺牲硅层 的顶平面高于所述硅基底的顶平面；或者，
    所述牺牲硅层的底平面低于所述硅基底的顶平面，并且所述牺牲硅层的顶平面等于所述硅基底的顶平面；或者，
    所述牺牲硅层的底平面等于所述硅基底的顶平面，并且所述牺牲硅层的顶平面高于所述硅基底的顶平面；或者，
    所述牺牲硅层的底平面低于所述硅基底的顶平面，并且所述牺牲硅层的顶平面低于所述硅基底的顶平面。
  14. 根据权利要求7至13中任一项所述的形成方法，其特征在于，所述压电MEMS硅谐振器为悬臂梁式、延伸振动模式、厚度纵向振动模式、兰姆波振动模式、面内弯曲振动模式或者声表面波振动模式。
  15. 一种压电MEMS硅谐振器，其特征在于，通过权利要求7至14中任一项所述的形成方法制得。
  16. 一种电子设备，其特征在于，包括权利要求1至6以及权利要求15中任一项所述的压电MEMS硅谐振器。
PCT/CN2021/091096 2021-04-29 2021-04-29 压电mems硅谐振器及其形成方法、电子设备 WO2022226911A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/091096 WO2022226911A1 (zh) 2021-04-29 2021-04-29 压电mems硅谐振器及其形成方法、电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/091096 WO2022226911A1 (zh) 2021-04-29 2021-04-29 压电mems硅谐振器及其形成方法、电子设备

Publications (1)

Publication Number Publication Date
WO2022226911A1 true WO2022226911A1 (zh) 2022-11-03

Family

ID=83846575

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/091096 WO2022226911A1 (zh) 2021-04-29 2021-04-29 压电mems硅谐振器及其形成方法、电子设备

Country Status (1)

Country Link
WO (1) WO2022226911A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040253760A1 (en) * 2003-06-13 2004-12-16 Agency For Science, Technology And Research Method to fabricate a highly perforated silicon diaphragm with controlable thickness and low stress
CN103618044A (zh) * 2013-11-29 2014-03-05 上海集成电路研发中心有限公司 压电悬臂梁传感器结构制造方法
CN108183163A (zh) * 2018-01-08 2018-06-19 杭州士兰微电子股份有限公司 一种超声波传感器的制造方法
CN108736856A (zh) * 2017-04-19 2018-11-02 三星电机株式会社 体声波谐振器及制造体声波谐振器的方法
CN110350885A (zh) * 2019-08-06 2019-10-18 杭州左蓝微电子技术有限公司 一种滤波器及其制备方法
CN111786644A (zh) * 2019-04-04 2020-10-16 中芯集成电路（宁波）有限公司上海分公司 体声波谐振器及其制造方法和滤波器、射频通信系统
CN111902915A (zh) * 2018-03-23 2020-11-06 法语天主教鲁汶大学 对衬底进行电化学处理的方法和集成电路装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040253760A1 (en) * 2003-06-13 2004-12-16 Agency For Science, Technology And Research Method to fabricate a highly perforated silicon diaphragm with controlable thickness and low stress
CN103618044A (zh) * 2013-11-29 2014-03-05 上海集成电路研发中心有限公司 压电悬臂梁传感器结构制造方法
CN108736856A (zh) * 2017-04-19 2018-11-02 三星电机株式会社 体声波谐振器及制造体声波谐振器的方法
CN108183163A (zh) * 2018-01-08 2018-06-19 杭州士兰微电子股份有限公司 一种超声波传感器的制造方法
CN111902915A (zh) * 2018-03-23 2020-11-06 法语天主教鲁汶大学 对衬底进行电化学处理的方法和集成电路装置
CN111786644A (zh) * 2019-04-04 2020-10-16 中芯集成电路（宁波）有限公司上海分公司 体声波谐振器及其制造方法和滤波器、射频通信系统
CN110350885A (zh) * 2019-08-06 2019-10-18 杭州左蓝微电子技术有限公司 一种滤波器及其制备方法

Similar Documents

Publication Publication Date Title
WO2021109426A1 (zh) 体声波谐振器及制造方法、体声波谐振器单元、滤波器及电子设备
WO2021109444A1 (zh) 体声波谐振器及其制造方法、滤波器及电子设备
JP3965026B2 (ja) 基板実装型バルク波音響共鳴器の空洞全体にまたがる下部電極
CN108923766A (zh) 具有改进的腔体的单晶压电射频谐振器和滤波器
CN111262543A (zh) 一种钪掺杂氮化铝兰姆波谐振器与制备方法
CN110401428A (zh) 薄膜体声波谐振器及其制造方法
WO2021114556A1 (zh) 电极具有空隙层的体声波谐振器及制造方法、滤波器及电子设备
WO2020125308A1 (zh) 一种体声波谐振器及其制备方法
WO2021135022A1 (zh) 带电学隔离层的体声波谐振器及其制造方法、滤波器及电子设备
CN112134540B (zh) 一种复合电极的体声波谐振器及其制备方法
CN111697937A (zh) 一种薄膜体声波谐振器及其制备方法
CN113746446A (zh) 具有稳定频率功能的体声波谐振器
CN112511129A (zh) 一种薄膜体声波谐振器的气密封装结构及其制备方法
CN113708740A (zh) 压电薄膜体声波谐振器及其制备方法
WO2022228385A1 (zh) 具有加厚电极的体声波谐振器、滤波器及电子设备
CN113472307B (zh) 压电mems硅谐振器及其形成方法、电子设备
CN212163290U (zh) 一种钪掺杂氮化铝兰姆波谐振器
CN114337585A (zh) 一种单晶薄膜体声波谐振器及其制备方法、滤波器
WO2022226911A1 (zh) 压电mems硅谐振器及其形成方法、电子设备
CN113472308B (zh) 谐振器及其形成方法、电子设备
CN113364423B (zh) 压电mems谐振器及其形成方法、电子设备
CN114268290A (zh) 一种高q值单晶薄膜体声波谐振器的制备方法
KR100609508B1 (ko) 에어갭 타입 에프비에이알장치 및 그 제조방법
CN113824420A (zh) 具有双环形结构电极的单晶薄膜体声波谐振器制备方法
WO2022226912A1 (zh) 谐振器及其形成方法、电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21938390

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21938390

Country of ref document: EP

Kind code of ref document: A1