WO2022224811A1 - 半導体装置、および半導体装置の製造方法 - Google Patents

半導体装置、および半導体装置の製造方法 Download PDF

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Publication number
WO2022224811A1
WO2022224811A1 PCT/JP2022/017044 JP2022017044W WO2022224811A1 WO 2022224811 A1 WO2022224811 A1 WO 2022224811A1 JP 2022017044 W JP2022017044 W JP 2022017044W WO 2022224811 A1 WO2022224811 A1 WO 2022224811A1
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WO
WIPO (PCT)
Prior art keywords
lead
semiconductor device
sealing resin
exposed
thickness direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/017044
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English (en)
French (fr)
Japanese (ja)
Inventor
光俊 齊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
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Rohm Co Ltd
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Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to DE112022001601.9T priority Critical patent/DE112022001601T5/de
Priority to JP2023516422A priority patent/JPWO2022224811A1/ja
Priority to CN202280028084.2A priority patent/CN117121191A/zh
Publication of WO2022224811A1 publication Critical patent/WO2022224811A1/ja
Priority to US18/452,875 priority patent/US20230395451A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H10W70/457—Materials of metallic layers on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/464—Additional interconnections in combination with leadframes
    • H10W70/466—Tape carriers or flat leads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/868—Die-attach connectors and strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/886—Die-attach connectors and strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/766—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to a semiconductor device and its manufacturing method.
  • Patent Document 1 discloses an example of a semiconductor device.
  • the semiconductor device includes a columnar conductor that conducts to a semiconductor element.
  • the columnar conductor has a rear surface side exposed surface and a side surface side exposed surface exposed from the sealing resin.
  • the semiconductor device includes an external electrode covering the exposed back surface and the exposed side surface. Since the semiconductor device has this structure, when the semiconductor device is mounted on the wiring board, solder creeps up to the external electrode portion covering the side exposed surface. Therefore, the bonding state of the semiconductor device to the wiring board can be easily confirmed visually.
  • the present disclosure aims to provide a semiconductor device and a method of manufacturing the same in which a coating layer covering the back surface and side surfaces of the leads exposed from the sealing resin can be formed more efficiently. Let it be the first issue.
  • a semiconductor device provided by a first aspect of the present disclosure includes a first lead, a second lead positioned next to the first lead in a direction orthogonal to a thickness direction of the first lead, a third lead positioned next to the second lead in a direction orthogonal to the thickness direction; a first semiconductor element mounted on the first lead and conducting to the second lead; A sealing resin covering the lead, a part of each of the second lead and the third lead, and the first semiconductor element, and a coating layer containing a metal element.
  • the sealing resin has a bottom surface facing the thickness direction, and an outer side surface connected to the bottom surface and facing outward of the sealing resin in a direction orthogonal to the thickness direction.
  • a recess recessed from the bottom surface is formed in the sealing resin, and the recess has an inner surface connected to the bottom surface and facing inward of the sealing resin in a direction orthogonal to the thickness direction.
  • the second lead has a back surface exposed from the bottom surface and a side surface connected to the back surface and exposed from the outer surface.
  • the covering layer covers the back surface and the side surfaces.
  • the recess is between the first lead and the second lead.
  • the second lead and at least one of the first lead and the third lead have inner end surfaces exposed from the inner surface.
  • a method for manufacturing a semiconductor device provided by a second aspect of the present disclosure includes steps of mounting a semiconductor element on any one of a plurality of leads each having a back surface and a side surface connected to the back surface; and forming a sealing resin covering a portion of each of the leads and the semiconductor element.
  • the sealing resin the back surface and the side surface of at least one of the plurality of leads are exposed from the sealing resin. At least any two leads among the plurality of leads are connected to each other by a connecting band including the same composition as the plurality of leads.
  • the manufacturing method includes, after the step of forming the sealing resin, the step of forming, by electrolytic plating, a coating layer that covers the back surface and the side surface exposed from the sealing resin and contains a metal element; After the step of forming the coating layer, the step of cutting the connecting band by removing part of the sealing resin from the side where the back surface is exposed.
  • FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure
  • FIG. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1, seen through the sealing resin.
  • 3 is a bottom view of the semiconductor device shown in FIG. 1.
  • FIG. 4 is a right side view of the semiconductor device shown in FIG. 1.
  • FIG. 5 is a left side view of the semiconductor device shown in FIG. 1.
  • FIG. 6 is a rear view of the semiconductor device shown in FIG. 1.
  • FIG. FIG. 7 is a cross-sectional view along line VII-VII of FIG.
  • FIG. 10 is a partially enlarged view of FIG. 7.
  • FIG. 11 is a partially enlarged view of FIG. 9.
  • FIG. 12A and 12B are plan views for explaining the manufacturing process of the semiconductor device shown in FIG. 13A and 13B are plan views for explaining the manufacturing process of the semiconductor device shown in FIG. 14A and 14B are cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG. 15A and 15B are plan views for explaining the manufacturing process of the semiconductor device shown in FIG. 16A and 16B are cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG. 17A and 17B are bottom views for explaining the manufacturing process of the semiconductor device shown in FIG. 18A and 18B are partially enlarged cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 19A and 19B are partially enlarged cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG. 20A and 20B are plan views for explaining the manufacturing process of the semiconductor device shown in FIG. 21 is a partially enlarged cross-sectional view of a first modification of the semiconductor device shown in FIG. 1.
  • FIG. 22 is a partially enlarged cross-sectional view of a second modification of the semiconductor device shown in FIG. 1.
  • FIG. 23 is a partially enlarged cross-sectional view of a third modification of the semiconductor device shown in FIG. 1.
  • FIG. 24A and 24B are partially enlarged cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 25 is a plan view of the semiconductor device according to the second embodiment of the present disclosure, which is transparent through the sealing resin.
  • FIG. 26 is a bottom view of the semiconductor device shown in FIG. 25.
  • FIG. 27 is a right side view of the semiconductor device shown in FIG. 25.
  • FIG. 28 is a rear view of the semiconductor device shown in FIG. 25.
  • FIG. 29 is a cross-sectional view along line XXIX-XXIX in FIG. 25.
  • FIG. 30 is a partially enlarged view of FIG. 29.
  • FIG. 31 is a plan view for explaining the manufacturing process of the semiconductor device shown in FIG. 25.
  • FIG. 32 is a plan view for explaining the manufacturing process of the semiconductor device shown in FIG. 25.
  • FIG. 33A to 33C are cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG. 34 is a bottom view for explaining the manufacturing process of the semiconductor device shown in FIG. 25.
  • FIG. 35A to 35C are cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG. 36 is a bottom view for explaining the manufacturing process of the semiconductor device shown in FIG. 25.
  • FIG. 37A to 37C are cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 38 is a plan view of the semiconductor device according to the third embodiment of the present disclosure, which is transparent through the sealing resin. 39 is a bottom view of the semiconductor device shown in FIG. 38.
  • FIG. 40 is a cross-sectional view along line XL-XL in FIG. 38.
  • FIG. 41 is a cross-sectional view along line XLI-XLI in FIG. 38.
  • FIG. 42 is a cross-sectional view along line XLII-XLII in FIG. 38.
  • FIG. 43 is a partially enlarged view of FIG. 40.
  • FIG. FIG. 44 is a plan view of the semiconductor device according to the fourth embodiment of the present disclosure, which is transparent through the sealing resin.
  • 45 is a bottom view of the semiconductor device shown in FIG. 44.
  • FIG. FIG. 46 is a bottom view of the semiconductor device according to the fifth embodiment of the present disclosure; 47 is a cross-sectional view of the semiconductor device shown in FIG. 46.
  • FIG. 48 is a cross-sectional view of the semiconductor device shown in FIG. 46.
  • FIG. 49 is a partially enlarged view of FIG. 48.
  • FIG. 1 A semiconductor device A10 according to the first embodiment of the present disclosure will be described based on FIGS. 1 to 11.
  • FIG. The semiconductor device A10 is surface-mounted on a wiring board.
  • a semiconductor device A10 includes a plurality of leads 10, a plurality of semiconductor elements 20, a plurality of conductive members 30, a sealing resin 40 and a coating layer 50.
  • FIG. 2 is transparent through the sealing resin 40 and is indicated by an imaginary line (chain double-dashed line).
  • the thickness direction of the plurality of leads 10 (furthermore, any one lead 10) will be referred to as "thickness direction z".
  • One direction perpendicular to the thickness direction z is called a “first direction x”.
  • a direction orthogonal to the thickness direction z and the first direction x is called a “second direction y”.
  • the semiconductor device A10 has a rectangular shape when viewed in the thickness direction z.
  • the plurality of leads 10 mounts the plurality of semiconductor elements 20 and forms a part of the conductive path between the wiring board on which the semiconductor device A10 is mounted and the plurality of semiconductor elements 20.
  • a plurality of leads 10 all consist of a common lead frame. Therefore, all the leads 10 have the same composition.
  • the composition of the plurality of leads 10 includes copper (Cu) (ie, each lead 10 contains copper).
  • the multiple leads 10 include a first lead 101 , a second lead 102 , a third lead 103 and a fourth lead 104 .
  • the second lead 102 is positioned next to the first lead 101 in the first direction x.
  • the third lead 103 is positioned next to the second lead 102 in the second direction y.
  • the fourth lead 104 is positioned next to the third lead 103 in the first direction x and next to the first lead 101 in the second direction y.
  • the second lead 102 and the third lead 103 have a major surface 112, two back surfaces 122, two side surfaces 13, a first outer end surface 141, an inner It has an end surface 15 , an inner peripheral surface 16 , a canopy portion 17 , an outer convex portion 18 and an inner convex portion 19 .
  • the main surface 112 faces the thickness direction z.
  • Main surface 112 is covered with sealing resin 40 .
  • the two back surfaces 122 face the side opposite to the main surface 112 in the thickness direction z.
  • the two main surfaces 112 are positioned apart from each other in the second direction y.
  • Two back surfaces 122 are exposed from the sealing resin 40 .
  • the two side surfaces 13 are individually connected to the two back surfaces 122 and face the first direction x. Two side surfaces 13 are exposed from the sealing resin 40 .
  • the first outer end surface 141 faces outward from the sealing resin 40 in the second direction y.
  • the first outer end face 141 is exposed from the sealing resin 40 .
  • the area of the first outer end surface 141 is smaller than the area of each of the two side surfaces 13 .
  • a first outer end surface 141 is connected to the main surface 112 and is located away from the two back surfaces 122 .
  • the inner end face 15 faces inward of the sealing resin 40 in the second direction y.
  • the inner end surface 15 is exposed from the sealing resin 40 .
  • the area of the inner end surface 15 is smaller than the area of each of the two side surfaces 13 .
  • the inner end surface 15 joins the main surface 112 and is located away from the two back surfaces 122 and the two side surfaces 13 .
  • the inner peripheral surface 16 is connected to two back surfaces 122 and faces a direction perpendicular to the thickness direction z.
  • the inner peripheral surface 16 is covered with a sealing resin 40 .
  • the eaves portion 17 protrudes from the inner peripheral surface 16 in a direction perpendicular to the thickness direction z.
  • the canopy portion 17 includes a principal surface 112 .
  • the eaves portion 17 has an overhanging surface 171 facing away from the main surface 112 in the thickness direction z.
  • the projecting surface 171 is connected to the inner peripheral surface 16 and positioned between the main surface 112 and the two back surfaces 122 in the thickness direction z.
  • the eaves portion 17 is covered with a sealing resin 40 .
  • the outward convex portion 18 protrudes outward from the sealing resin 40 from the eaves portion 17 in the second direction y.
  • the outward protrusion 18 includes a main surface 112 and a first outer end surface 141 .
  • the lower surface of the outward protrusion 18 facing the same side as the two back surfaces 122 in the thickness direction z is flush with the projecting surface 171 of the eaves portion 17 .
  • the inward convex portion 19 protrudes inward from the sealing resin 40 from the eaves portion 17 in the second direction y.
  • Inner protrusion 19 includes major surface 112 and inner end surface 15 .
  • the lower surface of the inward convex portion 19 facing the same side as the two back surfaces 122 in the thickness direction z is flush with the projecting surface 171 of the eaves portion 17 .
  • the first lead 101 and the fourth lead 104 have a mounting surface 111, a mounting surface 121, a first outer end surface 141 and two second outer end surfaces 142. , an inner end surface 15 , an inner peripheral surface 16 , an eaves portion 17 , an outer convex portion 18 and an inner convex portion 19 .
  • the inner end surface 15, the inner peripheral surface 16, the eaves portion 17, the outer convex portion 18 and the inner convex portion 19 are configured as follows. 16, the eaves portion 17, the outward convex portion 18, and the inward convex portion 19, the description thereof is omitted here.
  • the mounting surface 111 faces the same side as the main surface 112 of the second lead 102 and the third lead 103 in the thickness direction z.
  • the mounting surface 111 is covered with the sealing resin 40 . Any one of the plurality of semiconductor elements 20 is mounted on the mounting surface 111 .
  • the mounting surface 121 faces the side opposite to the mounting surface 111 in the thickness direction z.
  • the mounting surface 121 is exposed from the sealing resin 40 .
  • the area of mounting surface 121 is smaller than the area of each of the two back surfaces 122 of second lead 102 and third lead 103 .
  • the first outer end surfaces 141 of the first lead 101 and the fourth lead 104 face outward from the sealing resin 40 in the second direction y. Therefore, the direction in which the first outer end surface 141 faces is different from the direction in which the two side surfaces 13 of the second lead 102 and the third lead 103 face.
  • the first outer end face 141 is exposed from the sealing resin 40 .
  • the area of the first outer end surface 141 is smaller than the area of each of the two side surfaces 13 .
  • the first outer end surface 141 is connected to the mounting surface 111 and is located away from the mounting surface 121 .
  • the two second outer end faces 142 are connected to the mounting surface 121 and face the first direction x.
  • the two second outer end faces 142 face in the same direction as the two side faces 13 of the second lead 102 and the third lead 103 and face opposite to the two side faces 13 .
  • the two second outer end faces 142 are positioned apart from each other in the second direction y.
  • the two second outer end faces 142 are exposed from the sealing resin 40 .
  • the area of each of the two second outer end faces 142 is larger than the area of the first outer end faces 141 of the first lead 101 and the fourth lead 104 .
  • the plurality of semiconductor elements 20 are individually mounted on the mounting surface 111 of the first lead 101 and the mounting surface 111 of the fourth lead 104, as shown in FIGS.
  • the plurality of semiconductor elements 20 are diodes.
  • the plurality of semiconductor elements 20 have first electrodes 21 and second electrodes 22 .
  • the first electrode 21 is provided on the side facing the mounting surface 111 of the first lead 101 .
  • the first electrode 21 corresponds to an anode electrode.
  • the second electrode 22 is provided on the side opposite to the first electrode 21 in the thickness direction z.
  • the second electrode 22 faces either the mounting surface 111 of the first lead 101 or the mounting surface 111 of the fourth lead 104 .
  • the second electrode 22 corresponds to a cathode electrode.
  • the plurality of semiconductor elements 20 includes first semiconductor elements 201 and second semiconductor elements 202.
  • the first semiconductor element 201 is mounted on the mounting surface 111 of the first lead 101 .
  • the second electrode 22 of the first semiconductor element 201 is bonded to the mounting surface 111 of the first lead 101 via the bonding layer 29 .
  • the bonding layer 29 has conductivity. Bonding layer 29 is, for example, solder. Alternatively, the bonding layer 29 may be a sintered metal containing silver (Ag) or the like.
  • the second electrode 22 of the first semiconductor element 201 is electrically connected to the first lead 101 .
  • the second electrode 22 of the second semiconductor element 202 is bonded to the mounting surface 111 of the fourth lead 104 through the bonding layer 29 .
  • the second electrode 22 of the second semiconductor element 202 is electrically connected to the fourth lead 104 .
  • the plurality of conducting members 30 includes two first members 31, as shown in FIG.
  • One first member 31 of the two first members 31 is bonded to the first electrode 21 of the first semiconductor element 201 and the main surface 112 of the second lead 102 via the bonding layer 29 .
  • the first electrode 21 of the first semiconductor element 201 is electrically connected to the second lead 102 .
  • the other first member 31 of the two first members 31 is bonded to the first electrode 21 of the second semiconductor element 202 and the main surface 112 of the third lead 103 via the bonding layer 29 .
  • the first electrode 21 of the second semiconductor element 202 is electrically connected to the third lead 103 .
  • the two first members 31 are metal clips.
  • the composition of the two first members 31 contains copper. Alternatively, the two first members 31 may be wires.
  • the sealing resin 40 covers a part of each of the plurality of leads 10, the plurality of semiconductor elements 20, and the plurality of conduction members 30, as shown in FIGS.
  • the sealing resin 40 has electrical insulation.
  • Sealing resin 40 is made of a material containing, for example, black epoxy resin. As shown in FIGS. 4 and 5 , the sealing resin 40 has a top surface 41 , a bottom surface 42 , an outer surface 43 and a recess 44 .
  • the top surface 41 and the bottom surface 42 face opposite sides in the thickness direction z.
  • the bottom surface 42 faces the same side as the two back surfaces 122 of the second lead 102 and the third lead 103 in the thickness direction z.
  • Two rear surfaces 122 and mounting surfaces 121 for the first lead 101 and the fourth lead 104 are exposed from the bottom surface 42 .
  • the outer side surface 43 is connected to the top surface 41 and the bottom surface 42 and faces outward from the sealing resin 40 in a direction orthogonal to the thickness direction z.
  • the outer surface 43 includes a pair of first surfaces 431 and a pair of second surfaces 432 .
  • the pair of first surfaces 431 face opposite sides in the first direction x.
  • two side surfaces 13 of the second lead 102 and the third lead 103 are exposed from one first surface 431 of the pair of first surfaces 431 .
  • the two second outer end faces 142 of the first lead 101 and the fourth lead 104 are exposed from the other first face 431 of the pair of first faces 431 .
  • the pair of second surfaces 432 face opposite sides in the second direction y.
  • the first outer end surface 141 of the first lead 101 and the first outer end surface 141 of the second lead 102 are mounted.
  • a side face 141 is exposed.
  • the first outer end surface 141 of the fourth lead 104 and the first outer end surface 141 of the third lead 103 are mounted.
  • a side face 141 is exposed.
  • the recess 44 is recessed from the bottom surface 42 in the thickness direction z.
  • the recess 44 is a groove extending in a direction perpendicular to the thickness direction z.
  • the recess 44 extends in the first direction x. Both sides of the recess 44 in the first direction x are connected to the pair of first surfaces 431 of the outer side surfaces 43 . Thereby, the bottom surface 42 is divided into two regions by the recess 44 .
  • the fourth lead 104 is positioned next to the first lead 101 with the recess 44 interposed therebetween.
  • the third lead 103 is positioned next to the second lead 102 with the recess 44 interposed therebetween.
  • recess 44 has an inner surface 441 .
  • the inner side surface 441 is connected to the bottom surface 42 and faces the inside of the sealing resin 40 in a direction orthogonal to the thickness direction z. Further, the inner side surface 441 includes a pair of regions separated from each other in a direction perpendicular to the thickness direction z and the direction in which the recess 44 extends (the second direction y in the semiconductor device A10).
  • the inner end faces 15 of the first lead 101 and the fourth lead 104 and the inner end faces 15 of the second lead 102 and the third lead 103 are exposed from the pair of regions.
  • the recess 44 has an intermediate surface 442.
  • the intermediate surface 442 faces the same side as the bottom surface 42 in the thickness direction z and is connected to the inner surface 441 .
  • the intermediate surface 442 is located farther from the bottom surface 42 than the main surface 112 of the second lead 102 and the third lead 103 in the thickness direction z.
  • the covering layer 50 covers the two rear surfaces 122 and the two side surfaces 13 of the second lead 102 and the third lead 103, as shown in FIGS. Furthermore, the covering layer 50 covers the mounting surface 121 of the first lead 101 and the fourth lead 104 and the two second outer end surfaces 142 . The first outer end faces 141 and the inner end faces 15 of the leads 10 are not covered with the covering layer 50 .
  • the composition of the coating layer 50 contains a metal element.
  • the metal element is tin (Sn), for example.
  • the metal element may include at least one of nickel (Ni), palladium (Pd) and gold (Au).
  • the metal element contained in the coating layer 50 is desirably an element having a property of improving the wettability of the solder used when mounting the semiconductor device A10 on the wiring board.
  • FIG. 14 and 16 are the same as the cross-sectional positions of FIG.
  • the cross-sectional positions of FIGS. 18 and 19 are the same as the cross-sectional positions of FIG.
  • a plurality of semiconductor elements 20 are individually mounted on the mounting surface 111 of the first lead 101 and the fourth lead 104 of the plurality of leads 10 .
  • the mounting surface 111 is located on the side opposite to the back surfaces 122 of the second leads 102 and the third leads 103 among the plurality of leads 10 in the thickness direction z.
  • a plurality of conducting members 30 are individually joined to the first electrodes 21 of the plurality of semiconductor elements 20 and the main surfaces 112 of the second leads 102 and the third leads 103 .
  • the leads 10 are connected to the frame 80 via tie bars 81. As shown in FIG. Furthermore, at least two leads 10 among the plurality of leads 10 are connected to each other by a connecting band 82 . In the semiconductor device A10, the first lead 101 and the fourth lead 104, and the second lead 102 and the third lead 103 are connected to each other by the connecting bands 82, respectively.
  • the frame 80 , tie bars 81 and connecting bands 82 are made of the same composition as the plurality of leads 10 . Therefore, the frame 80, the tie bars 81 and the connecting bands 82 are all conductive.
  • a sealing resin 40 is formed to cover a portion of each of the plurality of leads 10, the plurality of semiconductor elements 20, and the plurality of conduction members 30.
  • the sealing resin 40 is formed by transfer molding. In this step, the rear surface 122 and the side surface 13 of at least one of the plurality of leads 10 (the second leads 102 and the third leads 103) are exposed from the sealing resin 40.
  • the mounting surface 121 of each of the first lead 101 and the fourth lead 104 and the two second outer end surfaces 142 are also exposed from the sealing resin 40 .
  • a coating layer 50 that covers the back surface 122 and side surfaces 13 exposed from the sealing resin 40 and contains a metal element is formed by electrolytic plating.
  • Coating layer 50 is, for example, a tin-plated layer.
  • the mounting surface 121 of each of the first lead 101 and the fourth lead 104 and the two second outer end surfaces 142 are also covered with the coating layer 50 .
  • the connecting band 82 is cut by removing part of the sealing resin 40 from the side where the back surface 122 is exposed in the thickness direction z.
  • a cutting device such as a dicing blade or a laser is used to cut the connecting band 82 .
  • FIG. 18 shows the state of the two leads 10 before the connecting band 82 is cut.
  • FIG. 19 shows the state of the two leads 10 after the connecting band 82 has been cut. As shown in FIG. 19 , this step forms the recess 44 in the sealing resin 40 and exposes the inner end surface 15 from the two leads 10 connected by the connecting band 82 .
  • the plurality of leads 10 are separated from the frame 80 by cutting the tie bars 81 .
  • the first outer end face 141 emerges from the plurality of leads 10 connected by the tie bar 81 .
  • the semiconductor device A10 is obtained.
  • FIG. 21 a semiconductor device A11, which is a first modification of the semiconductor device A10, will be described.
  • the cross-sectional position of FIG. 21 is the same as the cross-sectional position of FIG.
  • the semiconductor device A11 differs from the semiconductor device A10 in the configurations of the inner end surfaces 15 and the inner projections 19 of the second leads 102 and the third leads 103 .
  • the lower surface of the inward convex portion 19 facing the same side as the back surface 122 in the thickness direction z is separated from the overhanging surface 171 of the eaves portion 17 to the side where the main surface 112 is located in the thickness direction z.
  • the upper surface of the inward protrusion 19 facing the same side as the main surface 112 in the thickness direction z corresponds to the main surface 112 .
  • the inner end surface 15 is connected to the major surface 112 .
  • the area of inner end face 15 is smaller than the area of each inner end face 15 of second lead 102 and third lead 103 in semiconductor device A10.
  • the configurations of the inner end surfaces 15 and the inner protrusions 19 of the first lead 101 and the fourth lead 104 are also the same as the present configuration.
  • FIG. 22 the cross-sectional position of FIG. 22 is the same as the cross-sectional position of FIG.
  • the configuration of the inner end surfaces 15 and the inner protrusions 19 of the second lead 102 and the third lead 103 and the configuration of the recess 44 of the sealing resin 40 are the same as those of the semiconductor device A12. Differs from device A10.
  • the upper surface of the inner end surface 15 facing the same side as the main surface 112 in the thickness direction z is separated from the main surface 112 to the side where the back surface 122 is located in the thickness direction z.
  • a lower surface of the inward protrusion 19 facing the same side as the back surface 122 in the thickness direction z corresponds to the projecting surface 171 of the eaves portion 17 .
  • the inner end surface 15 is connected to the projecting surface 171 .
  • the area of inner end face 15 is smaller than the area of each inner end face 15 of second lead 102 and third lead 103 in semiconductor device A10.
  • the configurations of the inner end surfaces 15 and the inner protrusions 19 of the first lead 101 and the fourth lead 104 are also the same as the present configuration.
  • the intermediate surface 442 of the recess 44 is located between the main surface 112 and the back surface 122 in the thickness direction z. Therefore, the depth of the recess 44 is smaller than the depth of the recess 44 of the semiconductor device A10.
  • FIG. 23 the cross-sectional positions of FIGS. 23 and 24 are the same as the cross-sectional positions of FIG.
  • the semiconductor device A13 differs from the semiconductor device A10 in the configurations of the inner end faces 15 and the inner projections 19 of the second lead 102 and the third lead 103 .
  • the lower surface of the inward protrusion 19 facing the same side as the back surface 122 in the thickness direction z is flush with the back surface 122 .
  • a lower surface of the inward protrusion 19 is covered with a coating layer 50 .
  • the upper surface of the inward protrusion 19 facing the same side as the main surface 112 in the thickness direction z corresponds to the main surface 112 .
  • the inner end surface 15 is connected to the major surface 112 .
  • FIG. 24 shows the state before cutting the connecting band 82 in the step of cutting the connecting band 82 shown in FIG. 17 in the manufacturing process of the semiconductor device A13.
  • the connecting band 82 connects the eaves portion 17 of the second lead 102 and the eaves portion 17 of the third lead 103 .
  • a semiconductor device A13 is obtained by leaving both ends of the connecting band 82 connected to the eaves portion 17 when the connecting band 82 is cut. Therefore, the dimension of the long side of the inner end face 15 (dimension in the thickness direction z) is the dimension of the long sides of the two side surfaces 13 of the second lead 102 and the two side surfaces 13 of the third lead 103.
  • the area of inner end face 15 is larger than the area of inner end face 15 of each of second lead 102 and third lead 103 in semiconductor device A10.
  • the dimension of the short side of the inner end surface 15 is smaller than the dimension of the short side of each of the two side surfaces 13 . Therefore, in the semiconductor device A13, the area of the inner end surface 15 is smaller than the area of each of the two side surfaces 13.
  • the configurations of the inner end surfaces 15 and the inner protrusions 19 of the first lead 101 and the fourth lead 104 are also the same as the present configuration.
  • the semiconductor device A10 includes a second lead 102 having a back surface 122 and side surfaces 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and side surfaces 13.
  • a concave portion 44 having an inner side surface 441 and recessed from the bottom surface 42 is formed in the sealing resin 40 .
  • the second lead 102 and at least one of the first lead 101 and the third lead 103 positioned with the recess 44 interposed therebetween have an inner end surface 15 exposed from the inner surface 441. .
  • a stopper resin 40 is formed.
  • coating layer 50 shown in FIGS. 15 and 16 coating layer 50 can be formed by electroplating.
  • at this stage of the process at least two leads 10 including the second lead 102 are connected by a connecting band 82 that includes the same composition as the plurality of leads 10, that is, has conductivity.
  • the leads 10 that are not connected to the frame 80 can be electrically connected to the frame 80 by the tie bars 81 .
  • the two leads 10 connected by the connecting band 82 are electrically insulated.
  • the inner end surface 15 and the recess 44 of the semiconductor device A10 are traces obtained by this process.
  • all of the plurality of leads 10 are electrically insulated from each other.
  • the covering layer 50 covering the rear surface 122 and the side surface 13 of the second lead 102 can be easily formed by electroplating. Therefore, in the semiconductor device A10, the step of exposing the side surface 13 from the sealing resin 40 after forming the sealing resin 40 is unnecessary. Furthermore, the formation efficiency of the coating layer 50 can be improved as compared with the case of forming the coating layer 50 by electroless plating. As described above, according to the semiconductor device A10 and its manufacturing method, the coating layer 50 covering the back surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 is formed more efficiently. It becomes possible to
  • the recess 44 of the sealing resin 40 is a groove extending in a direction perpendicular to the thickness direction z.
  • An inner side surface 441 of the recess 44 includes a pair of regions spaced apart from each other in a direction orthogonal to the thickness direction z and the direction in which the recess 44 extends.
  • the concave portion 44 of this configuration is obtained by using a cutting device such as a dicing blade in the step of cutting the connecting band 82 shown in FIG. 17 in the manufacturing process of the semiconductor device A10. By using such a cutting device, the connecting band 82 can be cut efficiently. Further, when the bottom surface 42 of the sealing resin 40 is divided into a plurality of regions by the recesses 44, the connecting band 82 can be smoothly cut without lowering the cutting speed, thereby suppressing a decrease in manufacturing efficiency of the semiconductor device A10.
  • the inner end surface 15 of the second lead 102 is located away from the side surface 13 .
  • the area of the inner end surface 15 of the second lead 102 is smaller than the area of the side surface 13 . As a result, it is possible to suppress the occurrence of metal burrs on the edge of the inner end face 15 in the step of cutting the connecting band 82 shown in FIG. 17 in the manufacturing process of the semiconductor device A10. Further, the inner end surface 15 is located away from the back surface 122 . As a result, when the semiconductor device A10 is mounted on the wiring board, it is possible to prevent the bonding strength of the semiconductor device A10 with respect to the wiring board from decreasing due to the metal burr.
  • the inner end surface 15 of the second lead 102 is connected to the principal surface 112 .
  • the first lead 101 has a first outer end face 141 exposed from the outer side surface 43 of the sealing resin 40 , which is different from the direction in which the side surface 13 of the second lead 102 faces.
  • the outer surface 43 is a trace obtained by cutting the tie bar 81 shown in FIG. 20 in the manufacturing process of the semiconductor device A10. As a result, it is possible to prevent the portion of the coating layer 50 covering the side surface 13 from being damaged due to the cutting of the tie bar 81 in this step.
  • a first outer end surface 141 of the first lead 101 is positioned away from the mounting surface 121 .
  • the step of cutting tie bars 81 shown in FIG. Therefore, by adopting this configuration, when the semiconductor device A10 is mounted on the wiring board, it is possible to prevent the reduction in bonding strength of the semiconductor device A10 to the wiring board due to the metal burr.
  • the first lead 101 has a second outer end surface 142 connected to the mounting surface 121 and exposed from the outer surface 43 of the sealing resin 40 . If the first lead 101 has at least the first outer end surface 141, the mounting surface 121 and the second outer end surface 121 and the second outer end surface 121 and the second outer end surface 121 are removed in the step of forming the covering layer 50 shown in FIGS.
  • the coating layer 50 covering the lateral end face 142 can be easily formed by electroplating. As a result, when the semiconductor device A10 is mounted on the wiring board, not only the second lead 102 but also the first lead 101 can be visually confirmed to be easily connected to the wiring board.
  • the area of the mounting surface 121 of the first lead 101 is larger than the area of the back surface 122 of the second lead 102 .
  • a first semiconductor element 201 is mounted on the first lead 101 . As a result, the heat generated from the first semiconductor element 201 can be released to the outside more efficiently.
  • the semiconductor device A10 further includes a fourth lead 104 on which the second semiconductor element 202 is mounted.
  • the recess 44 of the sealing resin 40 is also located between the first lead 101 and the fourth lead 104 .
  • First lead 101 and fourth lead 104 have inner end surfaces 15 exposed from inner side surface 441 of recess 44 . 15 and 16 in the manufacturing process of the semiconductor device A10, the mounting surface 121 and the second outer end surface 142 of the fourth lead 104 as well as the first lead 101 are
  • the covering layer 50 can be easily formed by electroplating.
  • the inner end face 15 of the second lead 102 is smaller in area than the inner end face 15 of the second lead 102 in the semiconductor device A10.
  • the depth of the recess 44 of the sealing resin 40 is smaller than the depth of the recess 44 of the semiconductor device A10.
  • the volume of the sealing resin 40 to be removed can be reduced in the step of cutting the connecting band 82 shown in FIG. 17 in the manufacturing process of the semiconductor device A10. This contributes to suppression of strength reduction of the sealing resin 40 .
  • FIG. 25 is transparent through the sealing resin 40 and is indicated by imaginary lines.
  • the configurations of the plurality of leads 10 and the sealing resin 40 are different from those of the semiconductor device A10 described above.
  • the pair of first surfaces 431 of the outer side surface 43 of the sealing resin 40 has a first area 431A, a second area 431B and a third area 431C.
  • the first region 431A is connected to the top surface 41 of the sealing resin 40.
  • the second region 431B connects to the bottom surface 42 of the sealing resin 40 and is located inside the sealing resin 40 relative to the first region 431A.
  • Two side surfaces 13 of the second lead 102 and the third lead 103 are exposed from one of the second regions 431B of the pair of first surfaces 431, the second region 431B.
  • the third region 431C is located between the top surface 41 and the bottom surface 42 in the thickness direction z, and is connected to the first region 431A and the second region 431B.
  • the third region 431C faces the same side as the bottom surface 42 in the thickness direction z.
  • the coating layer 50 is located inside the sealing resin 40 relative to the first regions 431A of the pair of first surfaces 431 of the outer side surface 43. As shown in FIGS. As shown in FIG. 26, the third regions 431C of the pair of first surfaces 431 overlap the coating layer 50 when viewed in the thickness direction z. The third region 431C is positioned closer to the top surface 41 than the main surface 112 of the second lead 102 and the third lead 103 in the thickness direction z.
  • FIGS. 33, 35 and 37 are the same as the cross-sectional position of FIG.
  • a plurality of semiconductor elements 20 are individually mounted on the mounting surfaces 111 of the first leads 101 and the fourth leads 104 of the plurality of leads 10 .
  • a plurality of conducting members 30 are individually bonded to the first electrodes 21 of the plurality of semiconductor elements 20 and the major surfaces 112 of the second leads 102 and the third leads 103 of the plurality of leads 10 .
  • the frame 80 has multiple first frame portions 801 and multiple second frame portions 802 .
  • the plurality of first frame portions 801 extend along the first direction x and are positioned apart from each other in the second direction y.
  • the plurality of second frame portions 802 extend along the second direction y and are positioned apart from each other in the first direction x. Both ends of each of the plurality of second frame portions 802 are connected to two first frame portions 801 adjacent to each other in the second direction y.
  • the tie bars 81 are connected to the plurality of first frame portions 801 .
  • each of the plurality of leads 10 is connected to one of two second frame portions 802 adjacent to each other in the first direction x.
  • a sealing resin 40 is formed to cover a portion of each of the plurality of leads 10, the plurality of semiconductor elements 20, and the plurality of conduction members 30.
  • the sealing resin 40 is formed over the entire frame 80 by compression molding. In this step, the rear surface 122 of at least one of the plurality of leads 10 (the second leads 102 and the third leads 103) is exposed from the sealing resin 40. As shown in FIG. Furthermore, in this step, the mounting surfaces 121 of the first lead 101 and the fourth lead 104 are also exposed from the sealing resin 40 .
  • the plurality of second frame portions 802 are removed from the side where the back surface 122 is exposed in the thickness direction z.
  • the removal of the plurality of second frame portions 802 is performed by half-cut dicing.
  • a portion of each of the plurality of leads 10 positioned at the boundary with the plurality of second frame portions 802 and a portion of the sealing resin 40 positioned at the boundary with the plurality of second frame portions 802 are aligned. removed.
  • the sealing resin 40 is formed with a plurality of grooves 83 recessed in the thickness direction z and extending along the second direction y.
  • a coating layer 50 is formed by electroplating to cover the back surface 122 and the side surfaces 13 exposed from the sealing resin 40.
  • the mounting surface 121 of each of the first lead 101 and the fourth lead 104 and the two second outer end surfaces 142 are also covered with the coating layer 50 .
  • the connecting band 82 is cut by removing part of the sealing resin 40 from the side where the back surface 122 is exposed in the thickness direction z. The method of cutting the connecting band 82 is the same as the cutting method in the manufacturing process of the semiconductor device A10 shown in FIGS.
  • the plurality of leads 10 are separated from the frame 80 by cutting the sealing resin 40 and the tie bars 81 in a grid shape along the first direction x and the second direction y.
  • the semiconductor device A20 is obtained.
  • the semiconductor device A20 includes a second lead 102 having a back surface 122 and side surfaces 13 exposed from the sealing resin 40, and a covering layer 50 covering the back surface 122 and side surfaces 13.
  • a concave portion 44 having an inner side surface 441 and recessed from the bottom surface 42 is formed in the sealing resin 40 .
  • the second lead 102 and at least one of the first lead 101 and the third lead 103 positioned with the recess 44 interposed therebetween have an inner end surface 15 exposed from the inner surface 441. . Therefore, in the semiconductor device A20 as well, the covering layer 50 covering the rear surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 can be formed more efficiently. . Furthermore, since the semiconductor device A20 has the same configuration as the semiconductor device A10, the semiconductor device A20 also exhibits the effects of the configuration.
  • the pair of first surfaces 431 of the outer side surface 43 of the sealing resin 40 has a first area 431A, a second area 431B and a third area 431C.
  • This configuration is obtained by removing the plurality of second frame portions 802 after forming the sealing resin 40 in manufacturing the semiconductor device A20.
  • Each of the plurality of leads 10 is connected to one of the plurality of second frame portions 802 until the plurality of second frame portions 802 is removed.
  • the sealing resin 40 can be formed over the entire frame body 80 by compression molding. Therefore, formation of the sealing resin 40 becomes easier than in the case of the semiconductor device A10.
  • FIG. 38 is transparent through the sealing resin 40 for convenience of understanding.
  • the permeated sealing resin 40 is indicated by imaginary lines.
  • the configurations of the plurality of leads 10, the plurality of semiconductor elements 20, the plurality of conduction members 30, and the sealing resin 40 are different from those of the semiconductor device A10 described above.
  • the plurality of leads 10 includes first lead 101, second lead 102, third lead 103 and fourth lead 104, as well as fifth lead 105 and sixth lead 106.
  • the fifth lead 105 is positioned next to the second lead 102 in the second direction y and on the opposite side of the second lead 102 to the third lead 103 in the second direction y.
  • the sixth lead 106 is positioned next to the third lead 103 in the second direction y and on the opposite side of the third lead 103 to the second lead 102 in the second direction y.
  • the fifth lead 105 and the sixth lead 106 have a main surface 112, a back surface 122, a side surface 13, a first outer end surface 141, an inner peripheral surface 16, an eaves portion 17 and a It has an outward protrusion 18 .
  • the second lead 102 and the third lead 103 have a main surface 112, a back surface 122, a side surface 13, an inner end surface 15, an inner peripheral surface 16, an eaves portion 17 and an inward convex portion 19.
  • the inner end surface 15 of the second lead 102 includes a region facing inward of the sealing resin 40 in the first direction x and a region facing inward of the sealing resin 40 in the second direction y.
  • the inward protrusion 19 of the second lead 102 has a region protruding inward from the sealing resin 40 from the eaves portion 17 in the first direction x and a region protruding inward from the sealing resin 40 from the eaves portion 17 in the second direction y. 40 inwardly projecting regions.
  • the first lead 101 includes a mounting surface 111, a mounting surface 121, a first outer end surface 141, two second outer end surfaces 142, an inner end surface 15, an inner peripheral surface 16, It has a canopy portion 17 , an outer convex portion 18 and an inner convex portion 19 .
  • the inner end surface 15 of the first lead 101 includes a region facing inward of the sealing resin 40 in the first direction x and a region facing inward of the sealing resin 40 in the second direction y.
  • the inward protrusion 19 of the first lead 101 protrudes inward from the sealing resin 40 in the first direction x from the eaves portion 17 and protrudes inward from the sealing resin 40 in the second direction y from the eaves portion 17 .
  • the plurality of semiconductor elements 20 are n-channel type vertical MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).
  • a plurality of semiconductor devices 20 includes a compound semiconductor substrate.
  • the main material of the compound semiconductor substrate is silicon carbide (SiC).
  • silicon (Si) may be used as the main material of the compound semiconductor substrate.
  • the plurality of semiconductor elements 20 may be other switching elements such as IGBTs (Insulated Gate Bipolar Transistors).
  • the multiple semiconductor elements 20 include a first semiconductor element 201 and a second semiconductor element 202 .
  • a plurality of semiconductor elements 20 have first electrodes 21, second electrodes 22 and gate electrodes 23.
  • the first electrode 21 is provided on the side facing the mounting surface 111 of the first lead 101 .
  • a current corresponding to the power converted by the semiconductor element 20 flows through the first electrode 21 . That is, the first electrode 21 corresponds to the source electrode.
  • the second electrode 22 is provided on the side opposite to the first electrode 21 in the thickness direction z.
  • the second electrode 22 faces either the mounting surface 111 of the first lead 101 or the mounting surface 111 of the fourth lead 104 .
  • a current corresponding to the power before being converted by the semiconductor element 20 flows through the second electrode 22 . That is, the second electrode 22 corresponds to a drain electrode.
  • the gate electrode 23 is provided on the same side as the first electrode 21 in the thickness direction z and is located away from the first electrode 21 .
  • a gate voltage for driving the semiconductor element 20 is applied to the gate electrode 23 .
  • the area of the gate electrode 23 is smaller than the area of the first electrode 21 when viewed in the thickness direction z.
  • the plurality of conducting members 30 includes two first members 31 and two second members 32, as shown in FIG.
  • One of the two first members 31 is bonded to the first electrode 21 of the first semiconductor element 201 and the main surface 112 of the fifth lead 105 via the bonding layer 29 .
  • the first electrode 21 of the first semiconductor element 201 is electrically connected to the fifth lead 105 .
  • the other first member 31 of the two first members 31 is bonded to the first electrode 21 of the second semiconductor element 202 and the main surface 112 of the sixth lead 106 via the bonding layer 29 .
  • the first electrode 21 of the second semiconductor element 202 is electrically connected to the sixth lead 106 .
  • one of the two second members 32 is joined to the gate electrode 23 of the first semiconductor element 201 and the main surface 112 of the second lead 102 .
  • the gate electrode 23 of the first semiconductor element 201 is electrically connected to the second lead 102 .
  • the other second member 32 of the two second members 32 is joined to the gate electrode 23 of the second semiconductor element 202 and the main surface 112 of the third lead 103 .
  • the gate electrode 23 of the second semiconductor element 202 is electrically connected to the third lead 103 .
  • the two second members 32 are wires.
  • the composition of the two second members 32 includes gold.
  • the composition of the two second members 32 may contain aluminum (Al) or copper.
  • the plurality of conductive members 30 are separated from the inner end surfaces 15 of the plurality of leads 10 (first lead 101, second lead 102 and third lead 103). To position.
  • the recess 44 of the sealing resin 40 includes a first groove 44A and a second groove 44B, as shown in FIGS. 39-41.
  • the first groove 44A extends in the first direction x. Both sides of the first groove 44A in the first direction x are connected to the pair of first surfaces 431 of the outer side surface 43 .
  • the second groove 44B extends in the second direction y. Both sides of the second groove 44B in the second direction y are connected to the pair of second surfaces 432 of the outer side surface 43 .
  • the second groove 44B crosses the first groove 44A.
  • a bottom surface 42 of the sealing resin 40 is divided into four regions by recesses 44 .
  • the fourth lead 104 is positioned next to the first lead 101 across the first groove 44A.
  • the third lead 103 is positioned next to the second lead 102 with the first groove 44A interposed therebetween. From the inner side surface 441 of the first groove 44A, the region of the inner end surface 15 of the first lead 101 facing the second direction y, the inner end surface 15 of the fourth lead 104, and the inner end surface 15 of the second lead 102 A region facing the second direction y and the inner end face 15 of the third lead 103 are exposed.
  • the first lead 101 is positioned next to the second lead 102 with the second groove 44B interposed therebetween. A region of the inner end surface 15 of the first lead 101 facing the first direction x and a region of the second lead 102 facing the first direction x are exposed from the inner side surface 441 of the second groove 44B.
  • the semiconductor device A30 includes a second lead 102 having a back surface 122 and side surfaces 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and side surfaces 13.
  • a concave portion 44 having an inner side surface 441 and recessed from the bottom surface 42 is formed in the sealing resin 40 .
  • the second lead 102 and at least one of the first lead 101 and the third lead 103 positioned with the recess 44 interposed therebetween have an inner end surface 15 exposed from the inner surface 441. . Therefore, in the semiconductor device A30 as well, the covering layer 50 covering the rear surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 can be formed more efficiently. . Further, since the semiconductor device A30 has the same configuration as the semiconductor device A10, the semiconductor device A30 also exhibits the effects of the configuration.
  • the recess 44 of the sealing resin 40 includes a first groove 44A extending in the first direction x and a second groove 44B extending in the second direction y.
  • the inner end face 15 of the second lead 102 includes a region facing the first direction x and a region facing the second direction y.
  • the plurality of conducting members 30 When viewed in the thickness direction z, the plurality of conducting members 30 are positioned apart from the inner end surfaces 15 of the plurality of leads 10 . As a result, the risk of cutting the plurality of conductive members 30 together with the connecting band 82 in the step of cutting the connecting band 82 (see FIG. 17) in the manufacturing process of the semiconductor device A30 can be reduced.
  • FIG. 44 is transparent through the sealing resin 40 for convenience of understanding.
  • the permeated sealing resin 40 is indicated by imaginary lines.
  • the configurations of the plurality of leads 10, the plurality of conductive members 30, and the sealing resin 40 are different from the above-described configuration of the semiconductor device A10.
  • the semiconductor element 20 is composed of one first semiconductor element 201. As shown in FIG.
  • the multiple leads 10 include a first lead 101, a second lead 102, a third lead 103 and a fifth lead 105.
  • FIG. The semiconductor device A40 does not include the fourth lead 104 .
  • the first lead 101 includes a mounting surface 111, a mounting surface 121, two first outer end surfaces 141, four second outer end surfaces 142, an inner end surface 15, an inner peripheral surface 16, an overhang portion 17, two outer It has a convex portion 18 and an inner convex portion 19 .
  • the inner end surface 15 of the first lead 101 faces the inside of the sealing resin 40 in the first direction x.
  • the inward convex portion 19 of the first lead 101 protrudes inward from the sealing resin 40 from the eaves portion 17 in the first direction x.
  • the structure of the first lead 101 is obtained by integrating the first lead 101 and the fourth lead 104 of the semiconductor device A10.
  • the second lead 102 has a main surface 112, a back surface 122, a side surface 13, an inner end surface 15, an inner peripheral surface 16, an eaves portion 17 and an inward convex portion 19.
  • the inner end surface 15 of the second lead 102 faces the first direction x. Accordingly, the inward convex portion 19 of the second lead 102 protrudes from the eaves portion 17 in the first direction x.
  • the configuration of the third lead 103 is the same as the configuration of the third lead 103 of the semiconductor device A10, description thereof will be omitted here.
  • the configuration of the fifth lead 105 is the same as the configuration of the fifth lead 105 of the semiconductor device A30, so the description is omitted here.
  • the first semiconductor element 201 is an n-channel MOSFET with a vertical structure, like the semiconductor device A30.
  • the plurality of conducting members 30 includes a first member 31, a second member 32 and a third member 33, as shown in FIG.
  • the first member 31 is bonded to the first electrode 21 of the first semiconductor element 201 and the main surface 112 of the third lead 103 via the bonding layer 29 .
  • the first electrode 21 of the first semiconductor element 201 is electrically connected to the third lead 103 .
  • the second member 32 is joined to the gate electrode 23 of the first semiconductor element 201 and the main surface 112 of the fifth lead 105 .
  • the gate electrode 23 of the first semiconductor element 201 is electrically connected to the fifth lead 105 .
  • the third member 33 is joined to the first electrode 21 of the first semiconductor element 201 and the main surface 112 of the second lead 102 .
  • the first electrode 21 of the first semiconductor element 201 is electrically connected to the second lead 102 .
  • the third member 33 is a wire.
  • the composition of the third member 33 contains gold.
  • the composition of the third member 33 may contain aluminum or copper.
  • the recess 44 of the sealing resin 40 is a groove extending in the second direction y, as shown in FIG. Both sides of the recess 44 in the second direction y are connected to the pair of second surfaces 432 of the outer side surface 43 .
  • the first lead 101 is positioned next to the second lead 102 with the recess 44 interposed therebetween.
  • the inner end surface 15 of the first lead 101 and the inner end surface 15 of the second lead 102 are exposed from the inner surface 441 of the recess 44 .
  • the semiconductor device A40 includes a second lead 102 having a back surface 122 and side surfaces 13 exposed from the sealing resin 40, and a covering layer 50 covering the back surface 122 and side surfaces 13.
  • a concave portion 44 having an inner side surface 441 and recessed from the bottom surface 42 is formed in the sealing resin 40 .
  • the second lead 102 and at least one of the first lead 101 and the third lead 103 positioned with the recess 44 interposed therebetween have an inner end surface 15 exposed from the inner surface 441. . Therefore, even in the semiconductor device A40, the covering layer 50 that covers the rear surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 can be formed more efficiently. . Further, since the semiconductor device A40 has the same configuration as the semiconductor device A10, the semiconductor device A40 also exhibits the effects of the configuration.
  • the semiconductor element 20 is composed of one first semiconductor element 201. Therefore, the present disclosure can be applied regardless of the number of semiconductor devices 20. FIG.
  • FIG. 46 shows the sealing resin 40 through for convenience of understanding.
  • the permeated sealing resin 40 is indicated by imaginary lines.
  • the cross-sectional position of FIG. 47 is the same as the cross-sectional position of FIG. 8 showing the semiconductor device A10.
  • the cross-sectional position of FIG. 48 is the same as the cross-sectional position of FIG. 9 showing the semiconductor device A10.
  • the semiconductor device A50 differs from the semiconductor device A10 described above in that an insulator 60 is further provided.
  • the insulator 60 is filled in the concave portion 44 of the sealing resin 40, as shown in FIGS.
  • Insulator 60 is, for example, a resin used for underfill.
  • An inner end surface 15 of each lead 10 is covered with an insulator 60 .
  • Insulator 60 abuts intermediate surface 442 of recess 44 .
  • the insulator 60 may be separated from the intermediate surface 442 as long as the insulator 60 covers the two inner end surfaces 15 facing each other with the recess 44 interposed therebetween.
  • the semiconductor device A50 includes a second lead 102 having a back surface 122 and side surfaces 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and side surfaces 13.
  • a concave portion 44 having an inner side surface 441 and recessed from the bottom surface 42 is formed in the sealing resin 40 .
  • the second lead 102 and at least one of the first lead 101 and the third lead 103 positioned with the recess 44 interposed therebetween have an inner end surface 15 exposed from the inner surface 441. . Therefore, even in the semiconductor device A50, the covering layer 50 covering the rear surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 can be formed more efficiently. . Furthermore, since the semiconductor device A50 has the same configuration as the semiconductor device A10, the semiconductor device A50 also exhibits the effects of the configuration.
  • the semiconductor device A50 further includes an insulator 60 filled in the concave portion 44 of the sealing resin 40 .
  • Appendix 1 a first lead; a second lead positioned next to the first lead in a direction perpendicular to the thickness direction of the first lead; a third lead positioned next to the second lead in a direction orthogonal to the thickness direction; a first semiconductor element mounted on the first lead and conducting to the second lead; a sealing resin covering a portion of each of the first lead, the second lead, and the third lead, and the first semiconductor element; a coating layer containing a metal element; with The sealing resin has a bottom surface facing the thickness direction and an outer side surface connected to the bottom surface and facing outward of the sealing resin in a direction perpendicular to the thickness direction, A recess recessed from the bottom surface is formed in the sealing resin, the recess has an inner side surface that is connected to the bottom surface and faces inward of the sealing resin in a direction orthogonal to the thickness direction; the second lead has a back surface exposed from the bottom surface and a side surface connected to the back surface and exposed from the outer surface; The coating layer covers the back surface and the
  • the recess is a groove extending in a direction orthogonal to the thickness direction,
  • the inner surface includes a pair of regions separated from each other in a direction orthogonal to the thickness direction and the direction in which the recess extends,
  • the semiconductor device according to appendix 1 wherein the inner end surface is exposed from the pair of regions.
  • Appendix 3. The semiconductor device according to appendix 2, wherein the bottom surface is divided into a plurality of regions by the recess.
  • the recess includes a first groove and a second groove, The semiconductor device according to appendix 3, wherein the second groove intersects the first groove. Appendix 5. 5.
  • the recess has an intermediate surface facing the same side as the bottom surface in the thickness direction and connected to the inner surface,
  • the semiconductor device according to appendix 8 wherein the intermediate surface is located further from the bottom surface than the main surface in the thickness direction.
  • Appendix 10. the first lead has a first outer end surface exposed from the outer surface, 10.
  • Appendix 11. the first lead has a mounting surface exposed from the bottom surface, 11.
  • Appendix 12. 12 The semiconductor device according to appendix 11, wherein the area of the mounting surface is larger than the area of the back surface.
  • Appendix 13 the first lead has a second outer end surface connected to the mounting surface and exposed from the outer surface; 13.
  • Appendix 14 The direction in which the second outer end face faces is the same as the direction in which the side face faces, 14.
  • Appendix 15. 15.
  • the sealing resin In the step of forming the sealing resin, the back surface and the side surface of at least one of the plurality of leads are exposed from the sealing resin; at least any two of the plurality of leads are connected to each other by a connecting band having the same composition as the plurality of leads; forming, after the step of forming the sealing resin, a coating layer that covers the back surface and the side surface exposed from the sealing resin and contains a metal element by electrolytic plating;
  • a method of manufacturing a semiconductor device further comprising, after the step of forming the coating layer, cutting the connecting band by removing part of the sealing resin from the side where the back surface is exposed.

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