WO2022222151A1 - 一种显示基板、显示面板及显示设备 - Google Patents

一种显示基板、显示面板及显示设备 Download PDF

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Publication number
WO2022222151A1
WO2022222151A1 PCT/CN2021/089426 CN2021089426W WO2022222151A1 WO 2022222151 A1 WO2022222151 A1 WO 2022222151A1 CN 2021089426 W CN2021089426 W CN 2021089426W WO 2022222151 A1 WO2022222151 A1 WO 2022222151A1
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Prior art keywords
sub
area
display
pixel circuits
electrically connected
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PCT/CN2021/089426
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English (en)
French (fr)
Inventor
邱远游
王彬艳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/089426 priority Critical patent/WO2022222151A1/zh
Priority to CN202180000877.9A priority patent/CN115516545A/zh
Publication of WO2022222151A1 publication Critical patent/WO2022222151A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • a display substrate provided by an embodiment of the present disclosure includes a display area and a frame area, and the display area includes: a first display area and a second display area located at least on one side of the first display area;
  • the display substrate includes a plurality of first pixel circuits located in the frame area, the frame area includes a first sub-area and a second sub-area, and the plurality of first pixel circuits includes a first sub-pixel circuit and a second sub-area a sub-pixel circuit, the first sub-pixel circuit is located in the first sub-region, and the second sub-pixel circuit is located in the second sub-region;
  • the display substrate further includes a plurality of first light-emitting devices located in the first display area, the plurality of first light-emitting devices include first sub-light-emitting devices and second sub-light-emitting devices, the first sub-light-emitting devices and the first sub-pixel circuit is electrically connected, and the second sub-light-emitting device is electrically connected to the second sub-pixel circuit;
  • the display substrate includes a plurality of first control lines, the first control lines are used to provide control signals for the plurality of first pixel circuits, and the first sub-pixel circuits and the first control lines pass through a first a connecting line is coupled, and the second sub-pixel circuit is coupled with the first control line through a second connecting line.
  • the frame area includes at least one group of the first sub-area and the second sub-area, and the first sub-area and the second sub-area of the same group
  • the second sub-regions are arranged in the row direction, and the first sub-regions and the second sub-regions in different groups are arranged in sequence in the column direction; the first sub-pixel circuits and all the first sub-regions in the same group of the first sub-regions the second sub-pixel circuits of the second sub-region are located in the same row;
  • the first sub-region and the second sub-region of the same group are coupled to the same first control line, and the first sub-region and the second sub-region of different groups are connected to the different first sub-regions.
  • a control line is coupled.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a first driving circuit located in the frame area, and the first driving circuit includes a plurality of first shift register units arranged in cascade, so The first control line is electrically connected to the signal output end of the first shift register unit.
  • the second display area further includes a plurality of second pixel circuits and a plurality of second control lines, and each row of the second pixel circuits is connected to the same the second control lines are electrically connected, and the second pixel circuits in different rows are electrically connected with the different second control lines;
  • the second control line is electrically connected to the first driving circuit.
  • the first pixel circuit corresponding to the first display area and the second pixel circuit corresponding to the second display area both use bilateral driving, and each of the The first control line is electrically connected to the two first shift register units, and each of the second control lines is electrically connected to the two first shift register units.
  • the second display area further includes a plurality of second pixel circuits and a plurality of second control lines, and each row of the second pixel circuits is connected to the same the second control lines are electrically connected, and the second pixel circuits in different rows are electrically connected with the different second control lines;
  • the display substrate further includes: a second drive circuit located in the frame area, the second drive circuit including a plurality of second shift register units arranged in cascade;
  • the second shift register unit is electrically connected to one row of the second pixel circuits through the second control line.
  • the trigger signals of the first shift register unit of the first stage and the trigger signal of the second shift register unit of the first stage are the same.
  • the first pixel circuit corresponding to the first display area and the second pixel circuit corresponding to the second display area both use bilateral driving, and each of the The first control line is electrically connected to two of the first shift register units, and each of the second control lines is electrically connected to two of the second shift register units.
  • the display substrate further includes a plurality of data lines for providing data signals for the plurality of first pixel circuits
  • the display substrate further includes a plurality of data lines a third control line, the data line is electrically connected to the third control line, and the different data lines are electrically connected to the different third control lines
  • the first sub-pixel circuit is connected through a third connection line is coupled to the corresponding third control line
  • the second sub-pixel circuit is coupled to the corresponding third control line through a fourth connection line
  • the first sub-pixel circuit and the second sub-pixel circuit are The pixel circuits are coupled to different of the third control lines.
  • the remaining regions are provided with corresponding compensation capacitors;
  • the capacitor is used to compensate the load of the first control line electrically connected to the corresponding area;
  • the compensation capacitance corresponding to each of the areas decreases sequentially.
  • one end of the compensation capacitor is electrically connected to the first control line, and the other end of the compensation capacitor is electrically connected to a regulated power supply end;
  • the compensation capacitor is configured to compensate the load of the first control line electrically connected to the corresponding area according to the voltage stabilization signal provided by the voltage stabilization power supply terminal.
  • the frame area includes: a target row with the largest number of the first pixel circuits in the row direction, and the number of the first pixel circuits in the row direction is smaller than all the first pixel circuits in the row direction.
  • the other rows of the target row further include dummy first pixel circuits, and the sum of the numbers of the first pixel circuits of the other rows and the dummy first pixel circuits is equal to the number of the first pixel circuits of the target row.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes a plurality of second light-emitting devices located in the second display area, each of the plurality of second light-emitting devices is respectively connected with the plurality of second light-emitting devices.
  • Each of the second pixel circuits is electrically connected; wherein, the resolution of the first display area is the same as the resolution of the second display area.
  • the plurality of first pixel circuits are located in the frame area adjacent to the plurality of first light emitting devices.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure, it further includes a plurality of transparent conductive layers that are stacked between the first pixel circuit and the first light-emitting device and are insulated from each other, each of the transparent conductive layers.
  • the transparent conductive layer includes a plurality of transparent wires, and each of the transparent wires is connected between the first pixel circuit and the first light-emitting device in a one-to-one correspondence.
  • the plurality of transparent wires included in each of the transparent conductive layers do not overlap with each other, and the plurality of transparent wires included in the different transparent conductive layers
  • the orthographic projections on the base substrate of the display substrate do not overlap or partially overlap each other.
  • the shape of the first display area is a circle, an ellipse, a square or a polygon.
  • the first display area is configured to install a light extraction module.
  • an embodiment of the present disclosure further provides a display panel, including the above-mentioned display substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a display device, comprising: a light-taking module, and the above-mentioned display panel provided by the embodiment of the present disclosure; wherein, the light-taking module is arranged on a first display of the display panel. Area.
  • FIG. 1 is a schematic top-view structure diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a partial enlarged structural schematic diagram corresponding to the display substrate shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram corresponding to the pixel circuit in the display substrate shown in FIG. 2;
  • FIG. 4 is a schematic layout diagram corresponding to the pixel circuit shown in FIG. 3;
  • FIG. 5 is a schematic diagram corresponding to the working timing of the pixel circuit shown in FIG. 3;
  • FIG. 6 is a schematic top-view structure diagram of still another display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a partially enlarged structure corresponding to the display substrate shown in FIG. 6;
  • FIG. 8 is another partially enlarged structural schematic diagram corresponding to the display substrate shown in FIG. 6;
  • FIG. 9 is a schematic diagram of a first shift register unit corresponding to the display substrate shown in FIG. 6;
  • FIG. 10 is a schematic top-view structure diagram of still another display substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a first shift register unit corresponding to the display substrate shown in FIG. 10;
  • FIG. 12 is another partially enlarged structural schematic diagram corresponding to the display substrate shown in FIG. 6;
  • FIG. 13 is another partially enlarged structural schematic diagram corresponding to the display substrate shown in FIG. 6;
  • FIG. 14 is a schematic structural diagram of a compensation capacitor in the first sub-region
  • FIG. 15 is another partially enlarged structural schematic diagram corresponding to the display substrate shown in FIG. 6 .
  • the under-screen camera technology generally sets a first display area AA1 and a second display area AA2 in the display area AA, wherein the second display area AA2 occupies most of the display screen, and the first display area AA1 occupies the remaining part, and the first display area AA1 is where the camera under the screen is placed.
  • FIG. 2 is only a part of the area in schematic diagram 1.
  • One of the design schemes of the first display area AA1 corresponding to the under-screen camera is to set the pixel circuit of the first display area AA1 in the border area above the first display area AA1.
  • the pixel circuit is connected to the light emitting device EL in the first display area AA1 through ITO wiring.
  • the same column of light-emitting devices in the first display area AA1 is controlled by the pixel circuit in the same row (for example, the light-emitting device EL1 is controlled by the pixel circuit A2, and the light-emitting device EL2 is controlled by the pixel circuit A1.
  • control and the pixel circuits in the same row are usually controlled by the same control line 20 (eg, gate line).
  • the pixel circuits described in the embodiments of the present disclosure may have a 7T1C structure, that is, include 7 transistors and 1 capacitor.
  • FIG. 3 shows a schematic structural diagram of a 7T1C pixel circuit
  • FIG. 4 shows a structural layout of the 7T1C pixel circuit.
  • the 7T1C pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, and a third light-emitting control transistor T5.
  • the pixel circuit can be connected to the gate signal terminal Gate, the data signal terminal Data, the reset signal terminals Reset1 and Reset2, the light emission control signal terminal EM, the power supply terminal VDD, the initial power supply terminals Vinit1 and Vinit2, and the light emitting device EL.
  • the light emitting device EL is connected to It can also be connected to the power supply terminal VSS.
  • the pixel circuit can be used to drive the connected light-emitting device EL to emit light in response to signals provided by the connected signal terminals.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the embodiments of the present disclosure are described by taking the transistors all adopting P-type transistors as an example. Based on the description and teachings of the present disclosure, those of ordinary skill in the art can easily imagine that at least some of the transistors in the pixel circuit structure of the embodiments of the present disclosure use N-type transistors, that is, use N-type transistors. Therefore, these implementations are also within the protection scope of the embodiments of the present disclosure.
  • FIG. 5 which is a schematic diagram of the working sequence of the pixel circuit shown in FIG. 3
  • the first reset transistor T6 is turned on, and the first node N1 is reset
  • the second reset transistor T7 is turned on , reset the light-emitting device EL, the threshold compensation transistor T3, the driving transistor T1, and the data writing transistor T2 are turned on, and the data signal terminal Data is charged to the first node N1.
  • the charging time is determined by the control line 20 (such as the gate line Gate). ) The time when the signal is turned on is determined.
  • the load on the gate line Gate will affect the rise time (rise time) and the falling edge (fall time) of the gate line Gate signal. , which affects the turn-on time of the Gate signal, and the first node N also has a difference; in the stage t3, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on, and the light-emitting device EL continues to emit light.
  • the rise time and the falling edge of the control line 20 corresponding to the pixel circuits at different positions in the same row of pixel circuits correspond to the rise time and the falling edge. (fall time) is different, resulting in different charging times of pixel circuits (such as A1, A2) in different positions in the same row of pixel circuits (such as A1...A2), resulting in the corresponding electrically connected light-emitting devices (such as EL1, The brightness of EL2) varies greatly, resulting in uneven display.
  • an embodiment of the present disclosure provides a display substrate, as shown in FIGS. 6-8 , including: a display area AA and a frame area BB, and FIG. 7 shows the area a in FIG. 6 , etc. 8 is an enlarged schematic diagram of the details of the area a in FIG.
  • the display area AA includes: a first display area AA1 and a second display area AA2 located at least on one side of the first display area AA1; wherein, the first display area AA1
  • the transmittance of the area AA1 is greater than that of the second display area AA2; wherein, the area of the second display area AA2 can be much larger than the area of the first display area AA1, so the resolution of the second display area AA2 can be greater than Resolution of the first display area AA1. Since the resolution of the second display area AA2 is higher than that of the first display area AA1, a larger part of a display picture can be displayed in the second display area AA2, so the second display area AA2 can also Called the main display area.
  • the first display area AA1 may be a transparent display area capable of transmitting light, that is, the area where the first display area AA1 is located can transmit light. In this way, some light-taking modules (eg, cameras, fingerprint identification devices, etc.) required for the display device can be arranged in the first display area AA1 to lay a foundation for the narrow frame design of the display panel.
  • the second display area AA2 may be an opaque display area.
  • the first display area AA1 may be a transparent display area
  • the second display area AA2 may be a non-transparent display area.
  • the display substrate includes a plurality of first pixel circuits located in the frame area BB, the frame area BB includes a first sub-area BB1 and a second sub-area BB2, and the plurality of first pixel circuits includes a first sub-area BB2.
  • Pixel circuits (A11, A12...A1n) and second sub-pixel circuits (A21, A22...A2n) the first sub-pixel circuits (A11, A12...A1n) are located in the first sub-area BB1, and the second sub-pixel circuits (A21, A22...A2n) are located in the second sub-region BB2;
  • the display substrate further includes a plurality of first light emitting devices located in the first display area AA1, and the plurality of first light emitting devices include first sub-light emitting devices (EL11, EL12...EL1n...) and a first light emitting device
  • first sub-light emitting devices EL11, EL12...EL1n
  • Two sub-light-emitting devices EL21, EL22...EL2n
  • the first sub-light-emitting device (EL11, EL12...EL1n) is electrically connected to the first sub-pixel circuit (A11, A12...A1n)
  • the second sub-light-emitting device ( EL21, EL22...EL2n) and the second sub-pixel circuits (A21, A22...A2n) are electrically connected correspondingly;
  • the first sub-light-emitting device EL11 is electrically connected to the first sub-pixel circuit A1n
  • the first sub-light-emitting device EL12 is electrically connected to the first sub-pixel circuit A11...
  • the second The sub-light-emitting device EL21 is electrically connected to the second sub-pixel circuit A2n
  • the second sub-light-emitting device EL22 is electrically connected to the second sub-pixel circuit A21 .
  • the orthographic projection of the plurality of first pixel circuits on the base substrate 2 of the display substrate is different from the plurality of first pixel circuits.
  • the orthographic projections of the light-emitting devices on the base substrate 2 do not overlap, that is, the plurality of first pixel circuits and the plurality of first light-emitting devices do not have any overlapping areas in the direction perpendicular to the display substrate. In this way, the aperture ratio of the first display area AA1 can be ensured, so that the light transmission effect of the first display area AA1 is better.
  • the display area AA of the display substrate includes a first control line 1, the first control line 1 is used to provide control signals for a plurality of first pixel circuits, the first sub-pixel circuits (A11, A12... A1n) is coupled with the first control line 1 through the first connection line 11 , and the second sub-pixel circuits (A21 , A22 . . . A2n ) are coupled with the first control line 1 through the second connection line 12 .
  • the first control line may also be divided into a frame area or a display area.
  • the present disclosure uses different connecting lines to couple the first pixel circuits controlled by the same first control line to the same first control line, which can reduce the number of first sub-regions.
  • the RC loading (load) of the first control line corresponding to the second sub-region, so the RC loading (load) difference experienced by the signals of the first control line in different regions is reduced by half, so the first
  • the difference in charging time between the sub-pixel circuit and the second sub-pixel circuit in the second sub-area is reduced, so that the brightness of the first sub-light-emitting device electrically connected to the first sub-pixel circuit in the first sub-area is the same as that of the second sub-area.
  • the brightness difference of the second sub-light-emitting device electrically connected to the second sub-pixel circuit is also reduced, thereby improving the uniformity of the display image.
  • the shape of the first display area AA1 may be a square as shown in FIG. 6 , or may be other shapes such as a circle, an ellipse, or a polygon, which can be specifically designed according to actual needs, and is not described here. Do limit.
  • the second display area AA2 may surround the periphery of the first display area AA1 as shown in FIG. 6; it may also surround part of the first display area AA1, for example, surrounding the left side, the lower side and the right side of the first display area AA1, while the first display area AA1 may be surrounded by the first display area AA1.
  • the upper boundary of the display area AA1 coincides with the upper boundary of the second display area AA2.
  • the first light-emitting device eg, EL1, EL2, (7) refers to a pixel actually used for displaying light emission
  • the first pixel circuit eg, A1, A2, ...) is a circuit for connecting the first light-emitting device.
  • a plurality of first pixel circuits are located in the frame area BB adjacent to the plurality of first light-emitting devices. It is shown that a plurality of first pixel circuits are located in the upper border area.
  • the length of the transparent wiring between the first pixel circuit and the first light-emitting device can be effectively reduced, thereby reducing the transparent wiring resistance to improve the long-range uniformity of the drive signal.
  • the frame area BB includes at least one set of the first sub-area BB1 and the second sub-area BB2 (in FIG. group as an example), the first sub-region BB1 and the second sub-region BB2 in the same group are arranged in the row direction, the first sub-region BB1 and the second sub-region BB2 in different groups are arranged in sequence in the column direction;
  • the first sub-pixel circuit of the area BB1 and the second sub-pixel circuit of the second sub-area BB2 are located in the same row;
  • the first sub-region BB1 and the second sub-region BB2 of the same group are coupled to the same first control line 1
  • the first sub-region BB1 and the second sub-region BB2 of different groups are coupled to different first control lines 1 .
  • the RC loading of the first control lines corresponding to all the first pixel circuits in the frame area BB can be reduced, so that the brightness of the first sub-light-emitting devices electrically connected to the first sub-pixel circuits of all the first sub-areas BB1 is the same as
  • the luminance differences of the second sub-light-emitting devices electrically connected to the second sub-pixel circuits of the second sub-region BB2 are all reduced, thereby further improving the uniformity of the display image.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes a first drive circuit 100 located in the frame area BB, and the first drive circuit 100 includes a plurality of cascaded In the first shift register unit (GOA1, GOA2, GOA3...), the first control line 1 is electrically connected to the signal output end of the first shift register unit.
  • Each of the plurality of first shift register units (GOA1, GOA2, GOA3...) is respectively electrically connected to each of the plurality of first control lines 1.
  • the first pixel circuit in one row is electrically connected to the first shift register unit GOA1 of the first level
  • the first pixel circuit of the second row is electrically connected to the first shift register unit GOA2 of the second level
  • the first pixel circuit of the third row is electrically connected to the first shift register unit GOA2 of the third row.
  • the third stage first shift register unit GOA3 is connected, and so on.
  • the second display area AA2 further includes a plurality of second pixel circuits 3 and a plurality of second control lines 4 , each row The second pixel circuits 3 are electrically connected to the same second control line 4, and the second pixel circuits 3 of different rows are electrically connected to different second control lines 4;
  • the second control line 4 is electrically connected to the first driving circuit 100 , that is, the first display area AA1 and the second display area AA2 may share the first driving circuit 100 .
  • the first pixel circuits (eg, A1, A2 . . . ) corresponding to the first display area AA1 and the second display area AA2
  • the corresponding second pixel circuits 3 are all driven by bilateral driving.
  • the first control line 1 corresponding to the first pixel circuit in the first row is electrically connected to two first shift register units GOA1, such as the corresponding second pixel circuit in the first row.
  • the second control line 4 is correspondingly electrically connected to the two first shift register units GOAn.
  • FIG. 9 is a schematic diagram showing that the first display area AA1 and the second display area AA2 in FIGS. 6-8 can share the first driving circuit 100 (including cascaded GOA1, GOA2, GOA3...),
  • the output end of each stage of the first shift register unit (GOA1, GOA2, GOA3...) is used to connect to the control line electrically connected to the pixel circuit of the corresponding row, and at least one stage of the first shift register unit (such as the first stage GOA1 ) of the output end is divided into two channels, one is electrically connected to the first connecting line 11 corresponding to the first sub-region, and the other is electrically connected to the second connecting line 12 corresponding to the second sub-region;
  • the output signal of the register unit (eg GOA1) is used as the input signal of the first shift register unit (eg GOA2) of the next stage.
  • a first pixel circuit that is electrically connected to the first light-emitting device included in a row corresponds to the working timing of the first shift register unit, and a second pixel circuit that is electrically connected to the second light-emitting device included in the row.
  • the working timings of the corresponding second shift register units are the same, so that the first light-emitting device and the second light-emitting device in the same row emit light synchronously.
  • the second display area AA2 further includes a plurality of second pixel circuits 3 and a plurality of second control lines 4 , each row The second pixel circuits 3 are electrically connected to the same second control line 4, and the second pixel circuits 3 of different rows are electrically connected to different second control lines 4;
  • the display substrate further includes: a second drive circuit 200 located in the frame area BB, and the second drive circuit includes a plurality of second shift register units (GOA1', GOA2', GOA3'...) arranged in cascade;
  • a second drive circuit 200 located in the frame area BB, and the second drive circuit includes a plurality of second shift register units (GOA1', GOA2', GOA3'...) arranged in cascade;
  • the second shift register unit is electrically connected to a row of the second pixel circuits 3 through the second control line 4, so that the first display area AA1 and the second display area AA2 can be independently driven by independent driving circuits.
  • FIG. 11 shows the independent first drive circuits (GOA1, GOA2%) and second drive circuits (GOA1', GOA2'%) corresponding to the first display area AA1 and the second display area AA2.
  • the signal output by the output terminal Gout()' corresponds to the signal on the second control line 4 of the second display area AA2
  • Gout1() corresponds to the signal on the first control line 1 of the first display area AA1, so that Signals Gout1( ) and Gout( )' on the control lines of the pixel circuits of the first display area AA1 and the second display area AA2 can be simultaneously charged.
  • the trigger signals of the first-stage first shift register unit GOA1 and the first-stage second shift register unit GOA1 ′ may be the same, That is, the 0th stage shift register unit GOA0 can be used to input the trigger signal to the first stage first shift register unit GOA1 and the first stage second shift register unit GOA1 ′.
  • the trigger signals of the first-stage first shift register unit GOA1 and the first-stage second shift register unit GOA1' may also use different GOA inputs.
  • the first pixel circuit corresponding to the first display area AA1 and the second pixel circuit corresponding to the second display area AA2 both use Bilateral driving, for example, the first control line 1 corresponding to the first pixel circuit in the first row is electrically connected to two first shift register units GOA1, and the second control line 4 corresponding to the second pixel circuit in the first row is electrically connected to the two A second shift register unit GOA1'.
  • This can prevent the problem of insufficient charging of the pixel circuits farther away from the GOA when the large-size display adopts unilateral driving.
  • Using bilateral driving to simultaneously charge a row of pixel circuits from both ends of the control line can improve the charging efficiency.
  • control lines in the present disclosure may be gate lines (Gate), reset signal lines (Reset) and light emission control signal lines (EM). These control lines provide corresponding signals through corresponding shift register units.
  • the gate lines, reset signal lines, and light emission control signal lines may be formed of molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum, nickel, alloys thereof, and combinations thereof.
  • the first driving circuit 100 and the second driving circuit 200 in the embodiment of the present disclosure may be gate driving circuits for providing, for example, a line-by-line shift to the display area of the display substrate.
  • the gate scanning signal of the bit cell; the first driving circuit 100 and the second driving circuit 200 may also be light-emitting control driving circuits, which are used to provide the light-emitting control signal, eg, shifted line by line, to the second display area of the display substrate.
  • the light-emitting device refers to the overlapping portion of the anode, the light-emitting (EL) functional layer, and the cathode.
  • the display substrate provided in the embodiment of the present disclosure, as shown in FIG. 6 and FIG. 8 , it further includes a plurality of second light emitting devices 5 located in the second display area AA2 , among the plurality of second light emitting devices 5
  • Each of the plurality of second pixel circuits 3 is respectively electrically connected with each other; wherein, the resolution of the first display area AA1 is the same as the resolution of the second display area AA2.
  • the number of light-emitting devices included in each inch in the first display area AA1 and the second display area AA2 is the same, that is, there are no two partitions with different resolutions in the display area, thereby avoiding the resolution of the first display area AA1 and the first display area AA1.
  • the dividing line between light and dark caused by the different resolutions of the two display areas AA2 improves the overall display effect.
  • FIG. 12 is another equivalent enlarged schematic diagram of the area a in FIG. 6, the display substrate includes a plurality of first pixel circuits located in the frame area BB, and the frame area BB includes a plurality of areas (shown in FIG. 12 ) Take five regions as an example, namely D1, D2, D3, D4 and D5), each region may include multiple rows of first pixel circuits, and each region may correspond to the first pixel circuit in the cascade setting in FIG. 9 or FIG. 11 respectively.
  • Shift register unit (GOA1, GOA2, GOA3...), that is, one area corresponds to a set of cascaded GOAs, for example, the D1 area corresponds to a set of cascaded GOA1-GOAn, the output of GOA1 and the first of the D1 area Row pixel circuit, the output terminal of GOA2 and the second row pixel circuit in the D1 area, the output terminal of GOA3 and the third row pixel circuit in the D1 area, and so on.
  • the D2 area corresponds to a set of cascaded GOA1-GOAn, the output terminal of GOA1 and the first row of pixel circuits in the D2 area, the output terminal of GOA2 and the second row of pixel circuits in the D2 area, and the output terminal of GOA3 and the D2 area.
  • the D3 area corresponds to a set of cascaded GOA1-GOAn, the output terminal of GOA1 and the first row of pixel circuits in the D3 area, the output terminal of GOA2 and the second row of pixel circuits in the D3 area, and the output terminal of GOA3 and the D3 area.
  • FIG. 13 is a partial enlarged schematic view of the display substrate shown in FIG. 6, illustrating the first light-emitting device (eg EL1n) located in the first display area AA1 and the second light-emitting device located in the second display area AA2 Device 5, in conjunction with FIG. 11, it can be seen that the size of the first light-emitting device (EL1n, EL2n) can be smaller than the size of the second light-emitting device 5, that is, the anode of the light-emitting device in the first display area AA1 is compared to the second display area AA2 The anode of the inner light emitting device is smaller. In this way, it can be ensured that the light transmittance of the first display area AA1 is larger than that of the second display area AA2.
  • the first light-emitting device eg EL1n
  • the above-mentioned display substrate provided in the embodiment of the present disclosure may further include a plurality of transparent conductive layers that are stacked and insulated from each other between the first pixel circuit and the first light-emitting device, and each transparent conductive layer includes a plurality of transparent conductive layers.
  • There are a plurality of transparent wirings (FIG. 8 specifically shows a plurality of transparent wirings L1 and L2 on the same layer), and each transparent wiring is connected between the first pixel circuit and the first light emitting device in a one-to-one correspondence.
  • each first pixel circuit (such as A11) can be connected to a first light-emitting device (such as EL1n) through a transparent wire L1, and each first pixel circuit (such as A1n) can be connected to a first light emitting device through a transparent wire L2.
  • a light-emitting device eg, EL11
  • EL11 is connected, and so on; and the first light-emitting devices connected to each first pixel circuit are different.
  • each transparent trace extending in the row direction has a certain width in the column direction
  • each transparent trace extending in the column direction also has a certain width in the row direction
  • the pixels in the column direction have a certain width.
  • the dimensions in the direction and the row direction are also fixed, so the number of pixels in each row or column in the first display area AA1 is limited.
  • multiple transparent conductive layers that are stacked and insulated from each other are used, so that more transparent traces can be provided within a certain size range in the column direction or row direction, so as to drive more first light-emitting devices, thereby satisfying the requirements with the first light-emitting device.
  • the plurality of transparent wires included in each transparent conductive layer do not overlap with each other, and the plurality of transparent wires included in different transparent conductive layers are on the base substrate.
  • the orthographic projections on do not overlap each other.
  • the orthographic projections of the multiple transparent traces contained in the different transparent conductive layers on the substrate may also partially overlap or completely overlap. , which is not limited here.
  • the same column of light-emitting devices may be controlled by the first pixel circuit in the same row in the first display area. Therefore, in the above-mentioned display substrate provided by the embodiment of the present disclosure, as shown in FIG. 8 , at least A column of first light-emitting devices (eg, EL11 . . . EL1n ) is electrically connected to the first pixel circuits (eg, A11 . . . A1n ) in the same row.
  • first light-emitting devices eg, EL11 . . . EL1n
  • the display substrate further includes a plurality of pieces of data for providing data signals for a plurality of first pixel circuits (eg, A11 . . . A2n ).
  • the display area AA also includes a plurality of third control lines 6, the data lines are electrically connected to the third control lines 6, and different data lines are electrically connected to different third control lines 6, for example
  • the data line S1 is electrically connected to the third control line 6
  • the data line S2 is electrically connected to another third control line 6 ;
  • the first sub-pixel circuit eg A12
  • the second sub-pixel circuit such as A23
  • the first control line 1 , the second control line 4 , and the third control line 6 are arranged in the same layer, and the first connection line 11 , the second connection line 12 , the third connection line 13 and the The fourth connection lines 14 are arranged in the same layer, and the above-mentioned control lines and the above-mentioned connection lines may be arranged in the same layer or in different layers.
  • the first control line 1 and the third control line 6 may be divided into the display area AA, and may also be divided into the frame area BB.
  • the third control lines 6 may be arranged alternately with the first control lines 1 , and of course, all the third control lines 6 may be located above or below all the first control lines 1 . .
  • the data lines (S1, S2%) can be located in the first display area AA1 or in the second display area AA2, which are designed according to the actual situation of the product.
  • the first pixel circuit is generally electrically connected to the first light-emitting device through a transparent wire, and the first pixel circuit located in the same row is not necessarily electrically connected to the first light-emitting device in the same column. Divided into several small areas, the placement of the first pixel circuit is related to the transparent wiring, and the specific connection relationship between the first pixel circuit and the first light-emitting device is set according to the actual situation.
  • the signals output by the same output terminal of the first driving circuit 100 are output to the first connecting line 11 and the first connecting line 11 through the first control line 1 .
  • Each area (such as the first sub-area BB1) is provided with a corresponding compensation capacitor C'; the compensation capacitor C' is used to compensate the load on the first control line 1 electrically connected to the corresponding area (such as the first sub-area BB1);
  • the compensation capacitance corresponding to each area decreases sequentially. Only divided into two areas, the first pixel circuit of the first sub-area BB1 is provided with a corresponding compensation capacitor C', and the second sub-area BB2 is not provided.
  • the compensation capacitor C' is set in the first sub-area BB1 shown in FIG. 8 as an example, as shown in FIG. A control line 1 is electrically connected, and the other end of the compensation capacitor C' is electrically connected to the regulated power supply terminal VGL;
  • the compensation capacitor C' is configured to compensate the load on the first control line 1 electrically connected to the corresponding area (the first sub-area BB1 ) according to the voltage-stabilized signal provided by the voltage-stabilized power supply terminal VGL, so that the first sub-area BB1 is electrically connected to the load on the first control line 1 .
  • the difference between the load on the first control line 1 and the load on the first control line 1 electrically connected to the second sub-region BB2 is reduced, so that the brightness of each first light-emitting device electrically connected to the first control line 1 corresponding to different regions can be reduced
  • the difference is further reduced, thereby further improving the uniformity of the displayed images in the first display area AA1.
  • the compensation capacitor C' may be set by connecting the gate line Gate to the gate line.
  • the area of the connected gate increases, and the enlarged part can be used as one end of the compensation capacitor C'.
  • the regulated power supply terminal may also be a power supply signal terminal such as VGH, VDD, and VSS.
  • FIG. 8 takes an example where the first pixel circuit of a row is divided into two areas.
  • the first pixel circuit of a row is divided into three or more areas, except for the areas farthest away from the first driving circuit 100
  • the corresponding compensation capacitor C' is set in the remaining areas.
  • the first pixel circuit in a row is set according to the size of the border area BB and actual needs.
  • the display substrate there may be a target row (eg The fourth row and the fifth row), and other rows (such as the first row, the second row and the third row) in which the number of the first pixel circuits along the row direction is smaller than the target row, in order to ensure the consistency of the pixel circuits to ensure the uniformity of the display screen
  • the other rows eg, the first row, the second row, and the third row
  • also include dummy first pixel circuits 300 shown by the dotted box
  • the first row eg, the first row, the second row, and the third row
  • the sum of the numbers of the pixel circuits and the dummy first pixel circuits 300 is equal to the number of the first pixel circuits of the target row (eg, the fourth row and the fifth row).
  • the first display area AA1 is configured to install a light extraction module, such as a camera module.
  • a light extraction module such as a camera module.
  • the first light emitting device exists in the first display area AA1, so it can provide a light transmission area with a larger area, which is helpful for adapting to a camera module of a larger size.
  • an embodiment of the present disclosure further provides a display panel including the above-mentioned display substrate provided by an embodiment of the present disclosure.
  • the display panel may be an organic electroluminescent display panel (OLED), a quantum dot light emitting display panel (QLED), or a micro light emitting diode display panel (Micro LED). Since the principle of solving the problem of the display panel is similar to the principle of solving the problem of the above-mentioned display substrate, the implementation of the display panel provided by the embodiment of the present invention may refer to the implementation of the above-mentioned display substrate provided by the embodiment of the present invention, and the repetition will not be repeated. Repeat.
  • an embodiment of the present disclosure also provides a display device, including: a light-taking module (eg, a camera module), and the above-mentioned display panel; wherein, the light-taking module is disposed in the first display area AA1 of the display panel.
  • the light taking module can be a camera module.
  • the display device can be: a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component that has a display function.
  • the first pixel circuits controlled by the same first control line are coupled to the same first control line using different connecting lines, which can reduce the number of first pixel circuits controlled by the same first control line.
  • the RC loading (load) of the first control line corresponding to the sub-region and the second sub-region, so the RC loading (load) difference experienced by the signals of the first control line in different regions is reduced by half, so the first sub-region’s RC loading (load) difference
  • the difference in charging time between the first sub-pixel circuit and the second sub-pixel circuit in the second sub-area is reduced, so that the brightness of the first sub-light-emitting device electrically connected to the first sub-pixel circuit in the first sub-area is the same as that of the second sub-pixel circuit.
  • the brightness difference of the second sub-light-emitting devices electrically connected to the second sub-pixel circuits in the region is also reduced, thereby improving the uniformity of the display image.

Abstract

本公开实施例公开了一种显示基板、显示面板及显示设备，显示基板包括位于边框区的多个第一像素电路，边框区包括第一子区和第二子区，多个第一像素电路包括第一子像素电路和第二子像素电路，第一子像素电路位于第一子区，第二子像素电路位于第二子区；显示基板还包括位于第一显示区的多个第一发光器件，多个第一发光器件包括第一子发光器件和第二子发光器件，第一子发光器件与第一子像素电路电连接，第二子发光器件与第二子像素电路电连接，显示基板的第二显示区包括多条第一控制线，第一控制线用于为多个第一像素电路提供控制信号，第一子像素电路与第一控制线通过第一连接线耦接，第二子像素电路与第一控制线通过第二连接线耦接。

Description

一种显示基板、显示面板及显示设备 技术领域
本公开涉及显示技术领域，特别涉及一种显示基板、显示面板及显示设备。
背景技术
随着智能手机的高速发展，不仅要求手机的外形美观，还需兼顾给手机使用者带来更出色的视觉体验。各大厂商开始在智能手机上提高屏占比，使得全面屏成为智能手机的一个新竞争点。随着全面屏的发展，在性能和功能上的提升需求也与日俱增，屏下摄像头在不影响高屏占比的前提下，在一定程度上可以带来视觉和使用体验上的冲击感。
发明内容
本公开实施例提供的一种显示基板，包括显示区和边框区，所述显示区包括：第一显示区和至少位于所述第一显示区一侧的第二显示区；
所述显示基板包括位于所述边框区的多个第一像素电路，所述边框区包括第一子区和第二子区，所述多个第一像素电路包括第一子像素电路和第二子像素电路，所述第一子像素电路位于所述第一子区，所述第二子像素电路位于所述第二子区；
所述显示基板还包括位于所述第一显示区的多个第一发光器件，所述多个第一发光器件包括第一子发光器件和第二子发光器件，所述第一子发光器件与所述第一子像素电路电连接，所述第二子发光器件与所述第二子像素电路电连接；
所述显示基板包括多条第一控制线，所述第一控制线用于为所述多个第一像素电路提供控制信号，所述第一子像素电路与所述第一控制线通过第一连接线耦接，所述第二子像素电路与所述第一控制线通过第二连接线耦接。
可选地，在本公开实施例提供的上述显示基板中，所述边框区包括至少一组所述第一子区和所述第二子区，同一组的所述第一子区和所述第二子区沿行方向排列，不同组的所述第一子区和所述第二子区沿列方向依次排列；同一组的所述第一子区的所述第一子像素电路和所述第二子区的所述第二子像素电路位于同一行；
同一组的所述第一子区和所述第二子区与相同的所述第一控制线耦接，不同组的所述第一子区和所述第二子区与不同的所述第一控制线耦接。
可选地，在本公开实施例提供的上述显示基板中，还包括位于所述边框区的第一驱动电路，所述第一驱动电路包括级联设置的多个第一移位寄存单元，所述第一控制线与所述第一移位寄存单元的信号输出端电连接。
可选地，在本公开实施例提供的上述显示基板中，所述第二显示区还包括多个第二像素电路和多条第二控制线，每一行所述第二像素电路与同一条所述第二控制线电连接，不同行所述第二像素电路与不同的所述第二控制线电连接；
所述第二控制线与所述第一驱动电路电连接。
可选地，在本公开实施例提供的上述显示基板中，所述第一显示区对应的第一像素电路和所述第二显示区对应的第二像素电路均采用双边驱动，每一条所述第一控制线对应电连接两个所述第一移位寄存单元，每一条所述第二控制线对应电连接两个所述第一移位寄存单元。
可选地，在本公开实施例提供的上述显示基板中，所述第二显示区还包括多个第二像素电路和多条第二控制线，每一行所述第二像素电路与同一条所述第二控制线电连接，不同行所述第二像素电路与不同的所述第二控制线电连接；
所述显示基板还包括：位于所述边框区的第二驱动电路，所述第二驱动电路包括级联设置的多个第二移位寄存单元；
所述第二移位寄存单元通过所述第二控制线与一行所述第二像素电路电连接。
可选地，在本公开实施例提供的上述显示基板中，第一级所述第一移位寄存单元和第一级所述第二移位寄存单元的触发信号相同。
可选地，在本公开实施例提供的上述显示基板中，所述第一显示区对应的第一像素电路和所述第二显示区对应的第二像素电路均采用双边驱动，每一条所述第一控制线对应电连接两个所述第一移位寄存单元，每一条所述第二控制线对应电连接两个所述第二移位寄存单元。
可选地，在本公开实施例提供的上述显示基板中，所述显示基板还包括用于为所述多个第一像素电路提供数据信号的多条数据线，所述显示基板还包括多条第三控制线，所述数据线与所述第三控制线电连接，且不同的所述数据线与不同的所述第三控制线电连接；所述第一子像素电路通过第三连接线与对应的所述第三控制线耦接，所述第二子像素电路通过第四连接线与对应的所述第三控制线耦接，且所述第一子像素电路和所述第二子像素电路与不同的所述第三控制线耦接。
可选地，在本公开实施例提供的上述显示基板中，一行所述第一像素电路中，除最远离所述第一驱动电路的区域，其余区域均设置有对应的补偿电容；所述补偿电容用于补偿对应区域电连接的第一控制线的负载；
从所述最靠近所述第一驱动电路的区域指向最远离所述第一驱动电路的区域，各所述区域对应的补偿电容依次减小。
可选地，在本公开实施例提供的上述显示基板中，所述补偿电容的一端与所述第一控制线电连接，所述补偿电容的另一端与稳压电源端电连接；
所述补偿电容被配置为根据所述稳压电源端提供的稳压信号，补偿所述对应区域电连接的第一控制线的负载。
可选地，在本公开实施例提供的上述显示基板中，所述边框区包括：沿行方向所述第一像素电路数量最多的目标行，以及沿行方向所述第一像素电路数量小于所述目标行的其它行，所述其它行还包括虚设第一像素电路，所述其它行的第一像素电路和虚设第一像素电路的数量总和等于所述目标行的第一像素电路数量。
可选地，在本公开实施例提供的上述显示基板中，还包括位于所述第二显示区的多个第二发光器件，所述多个第二发光器件中的每个分别与所述多个第二像素电路中的每个对应电连接；其中，所述第一显示区的分辨率与所述第二显示区的分辨率相同。
可选地，在本公开实施例提供的上述显示基板中，所述多个第一像素电路位于所述多个第一发光器件邻近的所述边框区。
可选地，在本公开实施例提供的上述显示基板中，还包括位于所述第一像素电路与所述第一发光器件之间层叠设置且相互绝缘的多个透明导电层，每一所述透明导电层包括多条透明走线，每一条所述透明走线一一对应连接于所述第一像素电路与所述第一发光器件之间。
可选地，在本公开实施例提供的上述显示基板中，每一所述透明导电层所含的多条透明走线互不交叠，不同所述透明导电层所含的多条透明走线在所述显示基板的衬底基板上的正投影互不交叠或部分交叠。
可选地，在本公开实施例提供的上述显示基板中，所述第一显示区的形状为圆形、椭圆形、方形或多边形。
可选地，在本公开实施例提供的上述显示基板中，所述第一显示区被配置为安装取光模块。
相应地，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述显示基板。
相应地，本公开实施例还提供了一种显示设备，包括：取光模块，以及本公开实施例提供的上述显示面板；其中，所述取光模块被设置在所述显示面板的第一显示区。
附图说明
图1为本公开实施例提供的一种显示基板的俯视结构示意图；
图2为对应图1所示的显示基板的局部放大结构示意图；
图3为对应图2所示的显示基板中像素电路的结构示意图；
图4为对应图3所示的像素电路的版图示意图；
图5为对应图3所示的像素电路的工作时序示意图；
图6为本公开实施例提供的又一种显示基板的俯视结构示意图；
图7为对应图6所示的显示基板的一种局部放大结构示意图；
图8为对应图6所示的显示基板的又一种局部放大结构示意图；
图9为对应图6所示的显示基板的第一移位寄存单元的示意图；
图10为本公开实施例提供的又一种显示基板的俯视结构示意图；
图11为对应图10所示的显示基板的第一移位寄存单元的示意图；
图12为对应图6所示的显示基板的又一种局部放大结构示意图；
图13为对应图6所示的显示基板的又一种局部放大结构示意图；
图14为第一子区域补偿电容的结构示意图；
图15为对应图6所示的显示基板的又一种局部放大结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的组件或者对象涵盖出现在该词后面列举的组件或者对象及其等同，而不排除其他组件或者对象。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地 改变。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的组件或具有相同或类似功能的组件。
相关技术中，如图1所示，屏下摄像头技术一般在显示区域AA内设置第一显示区AA1和第二显示区AA2，其中第二显示区AA2占显示屏幕绝大部分，第一显示区AA1占据剩余部分，第一显示区AA1是屏下摄像头放置的位置。如图2所示，图2仅示意图1中部分区域，屏下摄像头对应的第一显示区AA1设计方案之一是将第一显示区AA1的像素电路设置在第一显示区AA1上方的边框区BB，像素电路与第一显示区AA1内的发光器件EL通过ITO走线连接。由于第一显示区AA1与边框区BB的空间有限，第一显示区AA1内会出现同一列发光器件由同行的像素电路控制(例如发光器件EL1由像素电路A2控制，发光器件EL2由像素电路A1控制)，而同一行的像素电路通常使用同一条控制线20(如栅线Gate)控制。
可选的，结合图3和图4所示的像素电路，本公开实施例记载的像素电路可以为7T1C结构，即包括7个晶体管和1个电容器。图3示出了7T1C像素电路的结构示意图，图4示出了7T1C像素电路的结构版图。其中，结合图3和图4所示像素电路可知，该7T1C像素电路10包括驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7以及存储电容C1。该像素电路可以与栅极信号端Gate，数据信号端Data，复位信号端Reset1和Reset2，发光控制信号端EM，电源端VDD，初始电源端Vinit1和Vinit2，以及发光器件EL连接，该发光器件EL还可以与电源端VSS连接。该像素电路可以用于响应于所连接的各信号端提供的信号，驱动所连接的发光器件EL发光。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本公开实施例以晶体管均采用P型晶体管为例进行说明。基于本公开对该实现 方式的描述和教导，本领域普通技术人员在无需做出创造性劳动前提下，能够容易想到将本公开实施例的像素电路结构中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开实施例的保护范围内的。
如图5所示，图5为图3所示的像素电路的工作时序示意图，在t1阶段，第一复位晶体管T6管打开，第一节点N1点重置；t2阶段，第二复位晶体管T7打开，对发光器件EL进行重置，阈值补偿晶体管T3、驱动晶体管T1、数据写入晶体管T2打开，数据信号端Data向第一节点N1点充电，此时充电时间由控制线20(如栅线Gate)信号打开的时间决定，在设置的栅线Gate上信号开启时间的基础上，栅线Gate上的负载会影响栅线Gate信号的上升沿时间(rise time)和下降沿(fall time)的大小，从而影响了Gate信号的打开时间，第一节点N也会出现差异；t3阶段，第一发光控制晶体管T4、第二发光控制晶体管T5打开，发光器件EL持续发光。因此在t2阶段，由于控制线20(如栅线Gate)上的信号受RC delay的影响，同一行像素电路中不同位置的像素电路对应的控制线20的上升沿时间(rise time)和下降沿(fall time)不同，导致同一行像素电路(例如A1……A2)中不同位置的像素电路(如A1、A2)的充电时长不同，导致该行像素电路对应电连接的发光器件(如EL1、EL2)的亮度出现较大差异，从而显示画面不均匀。
针对相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图6-图8所示，包括：显示区AA和边框区BB，图7为图6中区域a的等效放大示意图，图8为图6中区域a的细节放大示意图；该显示区AA包括：第一显示区AA1和至少位于第一显示区AA1一侧的第二显示区AA2；其中，第一显示区AA1的透光率大于第二显示区AA2的透光率；其中，第二显示区AA2的面积可以远大于第一显示区AA1的面积，如此，第二显示区AA2的分辨率即可以大于第一显示区AA1的分辨率。由于第二显示区AA2的分辨率较第一显示区AA1的分辨率更高，因此一副显示画面的较大部分可以显示于该第二显示区AA2内，故该第二显示区AA2也可以称为主显示区。 并且，该第一显示区AA1可以为能够透光的可透光显示区，即该第一显示区AA1所在区域能够透光。如此，即可以将显示设备所需配置的一些取光模块(例如，摄像头，指纹识别器件等)设置在该第一显示区AA1内，以为显示面板的窄边框设计奠定基础。该第二显示区AA2可以为不可透光显示区。例如，该第一显示区AA1可以为透明显示区，该第二显示区AA2可以为非透明显示区。
继续参考图7和图8，该显示基板包括位于边框区BB的多个第一像素电路，边框区BB包括第一子区BB1和第二子区BB2，多个第一像素电路包括第一子像素电路(A11、A12……A1n)和第二子像素电路(A21、A22……A2n)，第一子像素电路(A11、A12……A1n)位于第一子区BB1，第二子像素电路(A21、A22……A2n)位于第二子区BB2；
继续参考图7和图8，显示基板还包括位于第一显示区AA1的多个第一发光器件，多个第一发光器件包括第一子发光器件(EL11、EL12……EL1n……)和第二子发光器件(EL21、EL22……EL2n)，第一子发光器件(EL11、EL12……EL1n)与第一子像素电路(A11、A12……A1n)对应电连接，第二子发光器件(EL21、EL22……EL2n)与第二子像素电路(A21、A22……A2n)对应电连接；图7仅示意出一行第一子发光器件(EL11、EL12……EL1n……)和一行第二子发光器件(EL21、EL22……EL2n)；例如，第一子发光器件EL11与第一子像素电路A1n电连接，第一子发光器件EL12与第一子像素电路A11电连接……；第二子发光器件EL21与第二子像素电路A2n电连接，第二子发光器件EL22与第二子像素电路A21电连接……。在一些实施例中，由于多个第一像素电路和多个第一发光器件位于不同区域，因此该多个第一像素电路在显示基板的衬底基板2上的正投影，与多个第一发光器件在衬底基板2上的正投影不重叠，即该多个第一像素电路与多个第一发光器件在垂直于显示基板方向上没有任何重叠面积。如此，可以确保第一显示区AA1的开口率，使得第一显示区AA1的透光效果较好。
继续参考图7和图8，显示基板的显示区AA包括第一控制线1，第一控 制线1用于为多个第一像素电路提供控制信号，第一子像素电路(A11、A12……A1n)与第一控制线1通过第一连接线11耦接，第二子像素电路(A21、A22……A2n)与第一控制线1通过第二连接线12耦接。
需要说明书的是，所述第一控制线也可以划分到边框区，也可以划分到显示区。
在本公开实施例提供的上述显示基板中，本公开将同一条第一控制线控制的第一像素电路采用不同的连接线耦接至该同一条第一控制线，这样可以降低第一子区和第二子区对应的第一控制线的RC loading(负载)，因此不同区域的第一控制线的信号所经历的RC loading(负载)差异减小了一半，因此第一子区的第一子像素电路和第二子区的第二子像素电路的充电时长差异有所减小，从而第一子区的第一子像素电路电连接的第一子发光器件的亮度与第二子区的第二子像素电路电连接的第二子发光器件的亮度差异也减小，从而提高显示画面的均匀性。
需要说明的是，在本公开中第一显示区AA1的形状可以为图6所示的正方形，也可以为圆形、椭圆形或多边形等其他形状，具体可根据实际需要进行设计，在此不做限定。第二显示区AA2可以如图6所示环绕第一显示区AA1的周边；也可以包围部分第一显示区AA1，例如包围第一显示区AA1的左侧、下侧和右侧，而第一显示区AA1的上侧边界与第二显示区AA2的上侧边界重合。另外，在本公开中第一发光器件(如EL1、EL2……)是指实际用于显示发光的像素，第一像素电路(如A1、A2……)是用于连接第一发光器件的电路。
可选地，在本公开实施例提供的上述显示基板中，如图6-图8所示，多个第一像素电路位于多个第一发光器件邻近的边框区BB，图6-图8具体示出了多个第一像素电路位于上边框区域。
通过将多个第一像素电路设置在多个第一发光器件邻近的边框区BB，可以有效减小第一像素电路与第一发光器件之间透明走线的长度，进而减小该透明走线电阻，提高驱动信号的长程均一性。
可选地，在本公开实施例提供的上述显示基板中，如图6和图8所示，边框区BB包括至少一组第一子区BB1和所述第二子区BB2(图8以6组为例)，同一组的第一子区BB1和第二子区BB2沿行方向排列，不同组的第一子区BB1和第二子区BB2沿列方向依次排列；同一组的第一子区BB1的第一子像素电路和第二子区BB2的第二子像素电路位于同一行；
同一组的第一子区BB1和第二子区BB2与相同的第一控制线1耦接，不同组的第一子区BB1和第二子区BB2与不同的第一控制线1耦接。这样边框区BB的所有第一像素电路对应的第一控制线的RC loading(负载)均可以降低，因此所有第一子区BB1的第一子像素电路电连接的第一子发光器件的亮度与第二子区BB2的第二子像素电路电连接的第二子发光器件的亮度差异均减小，从而进一步提高显示画面的均匀性。
可选地，在本公开实施例提供的上述显示基板中，如图6和图8所示，还包括位于边框区BB的第一驱动电路100，第一驱动电路100包括级联设置的多个第一移位寄存单元(GOA1、GOA2、GOA3……)，第一控制线1与第一移位寄存单元的信号输出端电连接。多个第一移位寄存单元(GOA1、GOA2、GOA3……)的每个分别与多条第一控制线1中的每个对应电连接，图8仅示意出5行第一像素电路，第一行第一像素电路对应电连接第一级第一移位寄存单元GOA1，第二行第一像素电路对应电连接第二级第一移位寄存单元GOA2，第三行第一像素电路对应电连接第三级第一移位寄存单元GOA3，依次类推。
可选地，在本公开实施例提供的上述显示基板中，如图6和图8所示，第二显示区AA2还包括多个第二像素电路3和多条第二控制线4，每一行第二像素电路3与同一条第二控制线4电连接，不同行第二像素电路3与不同的第二控制线4电连接；
第二控制线4与第一驱动电路100电连接，即第一显示区AA1和第二显示区AA2可以共享第一驱动电路100。
可选地，在本公开实施例提供的上述显示基板中，如图6和图8所示， 第一显示区AA1对应的第一像素电路(如A1、A2……)和第二显示区AA2对应的第二像素电路3均采用双边驱动，如第一行第一像素电路对应的第一控制线1对应电连接两个第一移位寄存单元GOA1，如第一行第二像素电路对应的第二控制线4对应电连接两个第一移位寄存单元GOAn。
如图9所示，图9为图6-图8中第一显示区AA1和第二显示区AA2可以共享第一驱动电路100(包括级联设置的GOA1、GOA2、GOA3……)的示意图，每一级第一移位寄存单元(GOA1、GOA2、GOA3……)的输出端用于与对应行像素电路电连接的控制线相连，至少一级第一移位寄存单元(如第一级GOA1)的输出端一分两路，一路与第一子区对应的第一连接线11电连接，另一路与第二子区对应的第二连接线12电连接；且上一级第一移位寄存单元(如GOA1)的输出信号作为下一级第一移位寄存单元(如GOA2)的输入信号。
可选地，在显示区中，一行所含第一发光器件电连接的第一像素电路对应第一移位寄存单元的工作时序，与该行所含第二发光器件电连接的第二像素电路对应第二移位寄存单元的工作时序相同，以使得同行的第一发光器件和第二发光器件同步发光。
可选地，在本公开实施例提供的上述显示基板中，如图10和图11所示，第二显示区AA2还包括多个第二像素电路3和多条第二控制线4，每一行第二像素电路3与同一条第二控制线4电连接，不同行第二像素电路3与不同的第二控制线4电连接；
显示基板还包括：位于边框区BB的第二驱动电路200，第二驱动电路包括级联设置的多个第二移位寄存单元(GOA1’、GOA2’、GOA3’……)；
第二移位寄存单元通过第二控制线4与一行第二像素电路3电连接，这样第一显示区AA1和第二显示区AA2可以采用各自独立的驱动电路单独驱动。
具体地，如图11所示，图11为第一显示区AA1和第二显示区AA2对应的独立的第一驱动电路(GOA1、GOA2……)和第二驱动电路(GOA1’、GOA2’……)的示意图，输出端Gout()’输出的信号对应第二显示区AA2 的第二控制线4上的信号，Gout1()对应第一显示区AA1的第一控制线1上的信号，这样第一显示区AA1和第二显示区AA2的像素电路的控制在线的信号Gout1()和Gout()’可以同时充电。
可选地，在本公开实施例提供的上述显示基板中，如图11所示，第一级第一移位寄存单元GOA1和第一级第二移位寄存单元GOA1’的触发信号可以相同，即可以采用第0级移位寄存单元GOA0向第一级第一移位寄存单元GOA1和第一级第二移位寄存单元GOA1’输入触发信号。当然，第一级第一移位寄存单元GOA1和第一级第二移位寄存单元GOA1’的触发信号也可以采用不同的GOA输入。
可选地，在本公开实施例提供的上述显示基板中，如图10和图11所示，第一显示区AA1对应的第一像素电路和第二显示区AA2对应的第二像素电路均采用双边驱动，如第一行第一像素电路对应的第一控制线1对应电连接两个第一移位寄存单元GOA1，如第一行第二像素电路对应的第二控制线4对应电连接两个第二移位寄存单元GOA1’。这样可以防止大尺寸显示屏采用单边驱动时出现距离GOA较远处的像素电路充电不足的问题，采用双边驱动从控制线的两端同时给一行像素电路充电，可以提高充电效率。
可选地，本公开中控制线可以为栅线(Gate)、复位信号线(Reset)和发光控制信号线(EM)。这些控制线通过相应地移位寄存单元来提供相应的信号。具体地，可由钼、铝、银、铜、钛、铂、钨、钽、镍、其合金及其组合形成栅线、复位信号线和发光控制信号线。
可选地，如图6和图10所示，本公开实施例中的第一驱动电路100和第二驱动电路200可以是栅极驱动电路，用于向显示基板的显示区提供例如逐行移位元的栅极扫描信号；第一驱动电路100和第二驱动电路200也可以是发光控制驱动电路，用于向显示基板的第二显示区提供例如逐行移位的发光控制信号。
可选地，在本公开实施例提供的上述显示基板中，发光器件指阳极、发光(EL)功能层与阴极三者重叠的部分。
可选地，在本公开实施例提供的上述显示基板中，如图6和图8所示，还包括位于第二显示区AA2的多个第二发光器件5，多个第二发光器件5中的每个分别与多个第二像素电路3中的每个对应电连接；其中，第一显示区AA1的分辨率与第二显示区AA2的分辨率相同。即，第一显示区AA1和第二显示区AA2内每英寸所包括的发光器件数量相同，即显示区不存在分辨率不同的两个分区，进而避免了第一显示区AA1的分辨率与第二显示区AA2的分辨率不同造成的明暗分界线，提高了整体显示效果。
如图12所示，图12为图6中区域a的又一种等效放大示意图，该显示基板包括位于边框区BB的多个第一像素电路，边框区BB包括多个区域(图12示意出5个区域为例，分别为D1、D2、D3、D4和D5)，每个区域可以包括多行第一像素电路，每个区域可以分别对应图9或图11中级联设置的第一移位寄存单元(GOA1、GOA2、GOA3……)，即一个区域对应一组级联设置的GOA，例如D1区域对应一组级联设置的GOA1-GOAn，GOA1的输出端与D1区域的第一行像素电路，GOA2的输出端与D1区域的第二行像素电路，GOA3的输出端与D1区域的第三行像素电路，依次类推。例如D2区域对应一组级联设置的GOA1-GOAn，GOA1的输出端与D2区域的第一行像素电路，GOA2的输出端与D2区域的第二行像素电路，GOA3的输出端与D2区域的第三行像素电路，依次类推。例如D3区域对应一组级联设置的GOA1-GOAn，GOA1的输出端与D3区域的第一行像素电路，GOA2的输出端与D3区域的第二行像素电路，GOA3的输出端与D3区域的第三行像素电路，依次类推。
如图13所示，图13为图6所示的显示基板的局部放大示意图，示意出了位于第一显示区AA1的第一发光器件(如EL1n)和位于第二显示区AA2的第二发光器件5，结合图11可以看出，第一发光器件(EL1n、EL2n)的尺寸可以小于第二发光器件5的尺寸，即第一显示区AA1内发光器件的阳极相比于第二显示区AA2内发光器件的阳极较小。如此，可以确保第一显示区AA1的透光率较第二显示区AA2的透光率更大。
可选地，在本公开实施例提供的上述显示基板中，还可以包括位于第一 像素电路与第一发光器件之间层叠设置且相互绝缘的多个透明导电层，每一透明导电层包括多条透明走线(图8具体示出了多条同层的透明走线L1和L2)，每一条透明走线一一对应连接于第一像素电路与第一发光器件之间。即每个第一像素电路(如A11)可以通过一条透明走线L1与一个第一发光器件(如EL1n)连接，每个第一像素电路(如A1n)可以通过一条透明走线L2与一个第一发光器件(如EL11)连接，依次类推；且各个第一像素电路所连接的第一发光器件不同。本申请实施例对连接关系不做限定。
如图8所示，由于沿行方向延伸的每一透明走线在列方向上具有一定的宽度，沿列方向延伸的每一透明走线在行方向也上具有一定的宽度，而像素在列方向和行方向上的尺寸也是一定的，因此第一显示区AA1内每行或每列像素的数量受到了限制。本公开中采用层叠置且互相绝缘的多个透明导电层，使得可以在列方向或行方向上一定尺寸范围内提供更多的透明走线，以驱动更多的第一发光器件，进而满足与第二显示区AA2的相同分辨率。
可选地，在本公开实施例提供的上述显示基板中，每一透明导电层所含的多条透明走线互不交叠，不同透明导电层所含的多条透明走线在衬底基板上的正投影互不交叠。当然，由于不同透明导电层之间是相互绝缘的，因此在具体实施时，不同透明导电层所含的多条透明走线在衬底基板上的正投影也可以部分交叠，也可以完全重合，在此不做限定。
由于显示区与边框区的空间有限，第一显示区内可能出现同一列发光器件由同行的第一像素电路控制，因此在本公开实施例提供的上述显示基板中，如图8所示，至少一列第一发光器件(如EL11……EL1n)与同一行第一像素电路(如A11……A1n)对应电连接。
可选地，在本公开实施例提供的上述显示基板中，如图8所示，该显示基板还包括用于为多个第一像素电路(如A11……A2n)提供数据信号的多条数据线(S1、S2……)，显示区AA还包括多条第三控制线6，数据线与第三控制线6电连接，且不同的数据线与不同的第三控制线6电连接，例如数据线S1与第三控制线6电连接，数据线S2与另一条第三控制线6电连接；第 一子像素电路(如A12)通过第三连接线13与对应的第三控制线6耦接，第二子像素电路(如A23)通过第四连接线14与对应的第三控制线6耦接，且第一子像素电路(如A12)和第二子像素电路(如A23)与不同的第三控制线6耦接。
在具体实施时，如图8所示，第一控制线1、第二控制线4、第三控制线6同层设置，第一连接线11、第二连接线12、第三连接线13和第四连接线14同层设置，上述控制线和上述连接线可以同层设置，也可以不同层设置。第一控制线1、第三控制线6可以划分到显示区AA，也可以划分到边框区BB。
在具体实施时，如图8所示，第三控制线6可以与第一控制线1交替间隔排布，当然也可以所有的第三控制线6均位于所有第一控制线1的上方或下方。
在具体实施时，如图8所示，数据线(S1、S2……)可以位于第一显示区AA1，也可以位于第二显示区AA2，根据产品的实际情况进行设计。
需要说明的是，第一像素电路一般通过透明走线和第一发光器件电连，位于同一行的第一像素电路也不一定电连接同一列的第一发光器件，具体的，边框区域可以被分成若干个小区域，第一像素电路的放置和透明走线有关，第一像素电路和第一发光器件的具体连接关系根据实际情况设置。
如图8所示，以第一行第一像素电路(A11……A1n)为例，第一驱动电路100的同一输出端输出的信号经过第一控制线1输出至第一连接线11和第二连接线，由于第二连接线12接收到的信号经过的第一控制线1的长度大于第一连接线11接收到的信号的第一控制线11的长度，由于显示基板包括多层金属膜层，设置有多类信号走线，因此第一控制线1和第一子区BB1之间会形成耦合电容，导致第二子区BB2的负载比第一子区BB1的负载大，为了进一步减小第一子区BB1和第二子区BB2的负载差异，可选地，在本公开实施例提供的上述显示基板中，如图14所示，图14是本公开实施例提供的第一子区BB1对应的补偿电容的结构示意图，至少一行第一像素电路(以第一行A11……A1n为例)中，除最远离第一驱动电路100的区域(如第子二区 BB2)，其余区域(如第一子区BB1)均设置有对应的补偿电容C’；补偿电容C’用于补偿对应区域(如第一子区BB1)电连接的第一控制线1上的负载；
从最靠近第一驱动电路100的区域(如第一子区BB1)指向最远离第一驱动电路100的区域(如第二子区BB2)，各区域对应的补偿电容依次减小，若一行像素仅分为两个区域，则第一子区BB1的第一像素电路设置有对应的补偿电容C’，第二子区BB2不设置。
可选地，在本公开实施例提供的上述显示基板中，以图8所示的第一子区BB1设置该补偿电容C’为例，如图14所示，补偿电容C’的一端与第一控制线1电连接，补偿电容C’的另一端与稳压电源端VGL电连接；
补偿电容C’被配置为根据稳压电源端VGL提供的稳压信号，补偿对应区域(第一子区BB1)电连接的第一控制线1上的负载，使得第一子区BB1电连接的第一控制线1上的负载和第二子区BB2电连接的第一控制线1上的负载差异降低，从而可以使不同区域对应的第一控制线1电连接的各第一发光器件的亮度差异进一步减小，从而进一步提高第一显示区AA1显示画面的均匀性。
可选地，在本公开实施例提供的上述显示基板中，由于第一控制线为栅线Gate，栅线Gate与栅极电连接，设置补偿电容C’的方式可以是将与栅线Gate电连接的栅极面积增大，增大的部分即可作为补偿电容C’的一端。
可选地，在本公开实施例提供的上述显示基板中，稳压电源端也可以为VGH、VDD、VSS等电源信号端。
需要说明的，图8是以一行第一像素电路分为两个区域为例进行说明的，当然，若一行第一像素电路分为三个或更多个区域，除了最远离第一驱动电路100的区域外，其余区域均设置对应的补偿电容C’。当然，一行第一像素电路根据边框区BB的尺寸以及实际需要进行设置。
可选地，在本公开实施例提供的上述显示基板中，如图15所示，边框区BB可能存在包括：沿行方向第一像素电路(实线框所示)数量最多的目标行(如第四行和第五行)，以及沿行方向第一像素电路数量小于目标行的其它行 (如第一行、第二行和第三行)，为了保证像素电路一致以保证显示画面均一性，其它行(如第一行、第二行和第三行)还包括虚设第一像素电路300(虚线框所示)，其它行(如第一行、第二行和第三行)的第一像素电路和虚设第一像素电路300的数量总和等于目标行(如第四行和第五行)的第一像素电路数量。
可选地，在本公开实施例提供的上述显示基板中，如图6和图10所示，第一显示区AA1被配置为安装取光模块，例如摄像头模块。本公开中第一显示区AA1内仅存在第一发光器件，因此能够提供更大面积的透光区域，有助于适配更大尺寸的摄像头模块。
另一方面，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述显示基板。可选地，该显示面板可以为有机电致发光显示面板(OLED)、量子点发光显示面板(QLED)、或微发光二极管显示面板(Micro LED)。由于该显示面板解决问题的原理与上述显示基板解决问题的原理相似，因此，本发明实施例提供的该显示面板的实施可以参见本发明实施例提供的上述显示基板的实施，重复之处不再赘述。
另一方面，本公开实施例还提供了一种显示设备，包括：取光模块(例如摄像头模块)，以及上述显示面板；其中，取光模块被设置在显示面板的第一显示区AA1。可选地，取光模块可以为摄像头模块。该显示设备可以为：手机、平板计算机、电视机、显示器、笔记本电脑、数码相框、导航仪、智慧手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。对于显示设备的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。另外，由于该显示设备解决问题的原理与上述显示面板解决问题的原理相似，因此，该显示设备的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本公开实施例提供的上述显示基板、显示面板及显示设备，将同一条第一控制线控制的第一像素电路采用不同的连接线耦接至该同一条第一控制线，这样可以降低第一子区和第二子区对应的第一控制线的RC loading(负载)， 因此不同区域的第一控制线的信号所经历的RC loading(负载)差异减小了一半，因此第一子区的第一子像素电路和第二子区的第二子像素电路的充电时长差异有所减小，从而第一子区的第一子像素电路电连接的第一子发光器件的亮度与第二子区的第二子像素电路电连接的第二子发光器件的亮度差异也减小，从而提高显示画面的均匀性。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种显示基板，其中，包括显示区和边框区，所述显示区包括：第一显示区和至少位于所述第一显示区一侧的第二显示区；
    所述显示基板包括位于所述边框区的多个第一像素电路，所述边框区包括第一子区和第二子区，所述多个第一像素电路包括第一子像素电路和第二子像素电路，所述第一子像素电路位于所述第一子区，所述第二子像素电路位于所述第二子区；
    所述显示基板还包括位于所述第一显示区的多个第一发光器件，所述多个第一发光器件包括第一子发光器件和第二子发光器件，所述第一子发光器件与所述第一子像素电路电连接，所述第二子发光器件与所述第二子像素电路电连接；
    所述显示基板包括多条第一控制线，所述第一控制线用于为所述多个第一像素电路提供控制信号，所述第一子像素电路与所述第一控制线通过第一连接线耦接，所述第二子像素电路与所述第一控制线通过第二连接线耦接。
  2. 如权利要求1所述的显示基板，其中，所述边框区包括至少一组所述第一子区和所述第二子区，同一组的所述第一子区和所述第二子区沿行方向排列，不同组的所述第一子区和所述第二子区沿列方向依次排列；同一组的所述第一子区的所述第一子像素电路和所述第二子区的所述第二子像素电路位于同一行；
    同一组的所述第一子区和所述第二子区与相同的所述第一控制线耦接，不同组的所述第一子区和所述第二子区与不同的所述第一控制线耦接。
  3. 如权利要求1或2所述的显示基板，其中，还包括位于所述边框区的第一驱动电路，所述第一驱动电路包括级联设置的多个第一移位寄存单元，所述第一控制线与所述第一移位寄存单元的信号输出端电连接。
  4. 如权利要求3所述的显示基板，其中，所述第二显示区还包括多个第二像素电路和多条第二控制线，每一行所述第二像素电路与同一条所述第二 控制线电连接，不同行所述第二像素电路与不同的所述第二控制线电连接；
    所述第二控制线与所述第一驱动电路电连接。
  5. 如权利要求4所述的显示基板，其中，所述第一显示区对应的第一像素电路和所述第二显示区对应的第二像素电路均采用双边驱动，每一条所述第一控制线对应电连接两个所述第一移位寄存单元，每一条所述第二控制线对应电连接两个所述第一移位寄存单元。
  6. 如权利要求3所述的显示基板，其中，所述第二显示区还包括多个第二像素电路和多条第二控制线，每一行所述第二像素电路与同一条所述第二控制线电连接，不同行所述第二像素电路与不同的所述第二控制线电连接；
    所述显示基板还包括：位于所述边框区的第二驱动电路，所述第二驱动电路包括级联设置的多个第二移位寄存单元；
    所述第二移位寄存单元通过所述第二控制线与一行所述第二像素电路电连接。
  7. 如权利要求6所述的显示基板，其中，第一级所述第一移位寄存单元和第一级所述第二移位寄存单元的触发信号相同。
  8. 如权利要求6所述的显示基板，其中，所述第一显示区对应的第一像素电路和所述第二显示区对应的第二像素电路均采用双边驱动，每一条所述第一控制线对应电连接两个所述第一移位寄存单元，每一条所述第二控制线对应电连接两个所述第二移位寄存单元。
  9. 如权利要求1所述的显示基板，其中，所述显示基板还包括用于为所述多个第一像素电路提供数据信号的多条数据线，所述显示基板还包括多条第三控制线，所述数据线与所述第三控制线电连接，且不同的所述数据线与不同的所述第三控制线电连接；所述第一子像素电路通过第三连接线与对应的所述第三控制线耦接，所述第二子像素电路通过第四连接线与对应的所述第三控制线耦接，且所述第一子像素电路和所述第二子像素电路与不同的所述第三控制线耦接。
  10. 如权利要求3所述的显示基板，其中，一行所述第一像素电路中， 除最远离所述第一驱动电路的区域，其余区域均设置有对应的补偿电容；所述补偿电容用于补偿对应区域电连接的第一控制线的负载；
    从所述最靠近所述第一驱动电路的区域指向最远离所述第一驱动电路的区域，各所述区域对应的补偿电容依次减小。
  11. 如权利要求10所述的显示基板，其中，所述补偿电容的一端与所述第一控制线电连接，所述补偿电容的另一端与稳压电源端电连接；
    所述补偿电容被配置为根据所述稳压电源端提供的稳压信号，补偿所述对应区域电连接的第一控制线的负载。
  12. 如权利要求1所述的显示基板，其中，所述边框区包括：沿行方向所述第一像素电路数量最多的目标行，以及沿行方向所述第一像素电路数量小于所述目标行的其它行，所述其它行还包括虚设第一像素电路，所述其它行的第一像素电路和虚设第一像素电路的数量总和等于所述目标行的第一像素电路数量。
  13. 如权利要求4或6所述的显示基板，其中，还包括位于所述第二显示区的多个第二发光器件，所述多个第二发光器件中的每个分别与所述多个第二像素电路中的每个对应电连接；其中，所述第一显示区的分辨率与所述第二显示区的分辨率相同。
  14. 如权利要求1所述的显示基板，其中，所述多个第一像素电路位于所述多个第一发光器件邻近的所述边框区。
  15. 如权利要求1所述的显示基板，其中，还包括位于所述第一像素电路与所述第一发光器件之间层叠设置且相互绝缘的多个透明导电层，每一所述透明导电层包括多条透明走线，每一条所述透明走线一一对应连接于所述第一像素电路与所述第一发光器件之间。
  16. 如权利要求15所述的显示基板，其中，每一所述透明导电层所含的多条透明走线互不交叠，不同所述透明导电层所含的多条透明走线在所述显示基板的衬底基板上的正投影互不交叠或部分交叠。
  17. 如权利要求1所述的显示基板，其中，所述第一显示区的形状为圆 形、椭圆形、方形或多边形。
  18. 如权利要求1所述的显示基板，其中，所述第一显示区被配置为安装取光模块。
  19. 一种显示面板，其中，包括如权利要求1-18任一项所述的显示基板。
  20. 一种显示设备，其中，包括：取光模组，以及如权利要求19所述的显示面板；其中，所述取光模块被设置在所述显示面板的第一显示区。
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