WO2022213323A1 - 钳位模组、钳位方法、开关单元和电子设备 - Google Patents

钳位模组、钳位方法、开关单元和电子设备 Download PDF

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Publication number
WO2022213323A1
WO2022213323A1 PCT/CN2021/085950 CN2021085950W WO2022213323A1 WO 2022213323 A1 WO2022213323 A1 WO 2022213323A1 CN 2021085950 W CN2021085950 W CN 2021085950W WO 2022213323 A1 WO2022213323 A1 WO 2022213323A1
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WIPO (PCT)
Prior art keywords
clamping
circuit
terminal
voltage
control
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PCT/CN2021/085950
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English (en)
French (fr)
Inventor
王天宇
Original Assignee
罗姆股份有限公司
王天宇
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Application filed by 罗姆股份有限公司, 王天宇 filed Critical 罗姆股份有限公司
Priority to PCT/CN2021/085950 priority Critical patent/WO2022213323A1/zh
Publication of WO2022213323A1 publication Critical patent/WO2022213323A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels

Definitions

  • the present disclosure relates to the technical field of voltage clamping, and in particular, to a clamping module, a clamping method, a switch unit and an electronic device.
  • Wide-bandgap semiconductor transistors are high-speed switching devices and are generally widely used in bridge circuits.
  • the main purpose of the present disclosure is to provide a clamping module, a clamping method, a switch unit and an electronic device.
  • an embodiment of the present disclosure provides a clamping module, which is electrically connected to a clamping terminal, the clamping terminal is electrically connected to a driving voltage terminal, and the driving voltage terminal is used to provide a driving voltage signal;
  • the clamping module includes a clamping circuit and a control circuit;
  • the control terminal of the clamping circuit is electrically connected to the control circuit, the first terminal of the clamping circuit is electrically connected to the clamping terminal, and the second terminal of the clamping circuit is electrically connected to the clamping voltage terminal;
  • the control circuit is used for controlling the potential of the control terminal of the clamping circuit after the potential of the driving voltage signal drops from the first voltage to the second voltage and the potential of the clamping terminal drops to the second voltage , so that the clamping circuit controls the connection between the clamping terminal and the clamping voltage terminal.
  • an embodiment of the present disclosure provides a clamping method, which is applied to the above-mentioned clamping method, and the clamping method includes:
  • the control circuit controls the potential of the control terminal of the clamping circuit to make the clamping circuit The connection between the clamping terminal and the clamping voltage terminal is controlled.
  • an embodiment of the present disclosure further provides a switch unit, including a wide band gap semiconductor transistor and the above clamping module;
  • the control electrode of the wide band gap semiconductor transistor is electrically connected to the clamping terminal.
  • an embodiment of the present disclosure further provides an electronic device, including the above switch unit.
  • FIG. 1 is a structural diagram of a clamping module according to at least one embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a clamping module according to at least one embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a clamping module according to at least one embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a clamping module according to at least one embodiment of the present disclosure.
  • FIG. 5 is a first working timing diagram of at least one embodiment of the clamping module shown in FIG. 4 of the present disclosure
  • FIG. 6 is a second operation timing diagram of at least one embodiment of the clamping module shown in FIG. 4 of the present disclosure
  • FIG. 7 is a circuit diagram of a clamping module according to at least one embodiment of the present disclosure.
  • FIG. 8 is a first operation timing diagram of at least one embodiment of the clamping module shown in FIG. 7 of the present disclosure
  • FIG. 9 is a second operation timing diagram of at least one embodiment of the clamping module shown in FIG. 7 of the present disclosure.
  • FIG. 10 is a circuit diagram of a bridge circuit to which the clamping module according to at least one embodiment of the present disclosure is applied;
  • FIG. 11 is a structural diagram of a clamping module according to at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • control electrode when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode electrode, the first electrode can be an emitter electrode, and the second electrode can be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode;
  • the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the clamping module is electrically connected to the clamping terminal K, the clamping terminal K is electrically connected to the driving voltage terminal P0 through the first resistor R1 , and the driving voltage terminal P0 is electrically connected to the driving voltage terminal P0.
  • the voltage terminal P0 is used to provide a driving voltage signal;
  • the clamping module includes a clamping circuit 11 and a control circuit 12 ; the control terminal of the clamping circuit 11 is electrically connected to the control circuit 12 , The first end of the clamp circuit 11 is electrically connected to the clamp end K, and the second end of the clamp circuit 11 is electrically connected to the clamp voltage end P1;
  • the control circuit 12 is used for controlling the clamping circuit 11 after the potential of the driving voltage signal drops from the first voltage to the second voltage and the potential of the clamping terminal K drops to the second voltage.
  • the potential of the control terminal of so that the clamping circuit 11 controls the connection between the clamping terminal K and the clamping voltage terminal P1; the clamping voltage terminal P1 is used to provide a clamping voltage;
  • the clamping terminal K is electrically connected to the first control terminal S1, the first control terminal S1 is electrically connected to the gate of the wide bandgap semiconductor transistor M1, and the source of the M1 can be connected to the high-end of the bridge circuit.
  • the high-side switching transistor (not shown in FIG. 1 ) included in the (High Side) sub-circuit is electrically connected, the drain of M1 is electrically connected to the ground terminal GND, and M1 may be the low-side (Low Side) sub-circuit in the bridge circuit
  • the circuit includes low-side switching transistors.
  • the driving voltage terminal P0 may be electrically connected to the driving integrated circuit 10 , and the driving voltage signal is provided by the driving integrated circuit 10 to the driving voltage terminal P0 , the driving voltage signal may be a pulse signal.
  • the clamping terminal K may be a node electrically connected to the gate of the wide band gap semiconductor transistor.
  • the first voltage may be a positive voltage, for example, the first voltage may be 18V or 16V, but not limited thereto;
  • the second voltage may be a ground voltage or a negative voltage, but not limited thereto.
  • the wide band gap semiconductor transistor M1 may be a SiC (silicon carbide) field effect transistor or a GaN (gallium nitride) field effect transistor, but not limited thereto.
  • the clamping module when the potential of the driving voltage signal drops from the first voltage to the second voltage, the potential of the clamping terminal K drops to the second voltage
  • the control circuit 12 controls the potential of the control terminal of the clamping circuit 11, so that the clamping circuit 11 controls the connection between the clamping terminal K and the clamping voltage terminal P1;
  • the clamping module according to at least one embodiment is disclosed, which can realize that when the potential of the driving voltage signal drops from the first voltage to the second voltage, the action response speed of the wide-bandgap semiconductor transistor M1 is faster than that of the clamping circuit.
  • the action of 11 has a fast response speed, so the voltage of the clamping terminal K is discharged to the driving voltage terminal P0 through the first resistor R1, not through the clamping circuit 11, so as to improve the discharge speed, and can be adjusted by adjusting
  • the parameter of R1 (for example, a resistance value, etc.) is used to control the discharge speed of the clamp terminal K, and the like.
  • the clamping circuit may include a Si (silicon) device, and the action response speed of the Si device is relatively slow.
  • the clamp circuit 11 is used to control the clamp
  • the bit terminal K is connected with the clamping voltage terminal P1, so that the potential of the gate of the wide band gap semiconductor transistor M1 is the clamping voltage, which can ensure that the wide band gap semiconductor transistor M1 is turned off and avoid the wide band gap semiconductor transistor M1. The case where the transistor M1 is turned on by mistake occurs, reducing the circuit loss.
  • the clamping voltage terminal may be a ground terminal or a negative voltage terminal, but is not limited thereto;
  • the clamping voltage terminal may be a positive voltage terminal, but is not limited thereto.
  • control circuit 12 is further configured to control the clamping circuit after the potential of the driving voltage signal drops from the first voltage and before the potential of the clamping terminal K drops to the second voltage The potential of the control terminal of 11, so that the clamping circuit 11 controls the connection between the clamping terminal K and the clamping voltage terminal P1 to be disconnected.
  • the control The circuit 12 controls the potential of the control terminal of the clamping circuit 11 so that the clamping circuit 11 controls the connection between the clamping terminal K and the clamping voltage terminal P1 to be disconnected, so as to ensure the clamping terminal K There is no discharge through the clamp circuit 11 .
  • control circuit 12 is further configured to control the potential of the control terminal of the clamping circuit 11 when the potential of the driving voltage signal is the first voltage, so that the clamping circuit 11 controls the clamping circuit 11
  • the bit terminal K is disconnected from the clamping voltage terminal P1.
  • the control circuit 12 controls the potential of the control terminal of the clamping circuit 11 to make The clamping circuit 11 controls the disconnection between the clamping terminal K and the clamping voltage terminal P1 to ensure that the wide band gap semiconductor transistor can be turned on.
  • the clamping terminal K may be directly electrically connected to the driving voltage terminal P0, or the clamping terminal K may be connected to the driving voltage terminal P0.
  • the driving voltage terminals P0 may be electrically connected through capacitors.
  • the first resistor R1 may also be disposed between the clamping terminal K and the first control terminal S1 .
  • the clamping circuit may include a clamping transistor
  • the control electrode of the clamp transistor is electrically connected to the control circuit, the first electrode of the clamp transistor is electrically connected to the clamp terminal, and the second electrode of the clamp transistor is electrically connected to the clamp voltage terminal ;
  • the control circuit is used to control the voltage of the control electrode of the clamping transistor after the potential of the driving voltage signal drops from the first voltage to the second voltage and the potential of the clamping terminal drops to the second voltage. potential to turn on the clamp transistor.
  • control circuit may include an on-off sub-circuit, a discharge resistor and a voltage supply sub-circuit;
  • the voltage providing sub-circuit is used for providing a control voltage signal to the control terminal of the clamping circuit
  • the control terminal of the on-off sub-circuit is electrically connected to the driving voltage terminal through the discharge resistor, the first terminal of the on-off sub-circuit is electrically connected to the control terminal of the clamp circuit, and the on-off sub-circuit is electrically connected to the control terminal of the clamping circuit.
  • the second end of the circuit is electrically connected to the third voltage end, and the on-off sub-circuit is used to control the connection between the control end of the clamping circuit and the third voltage end under the control of the potential of the control end thereof, or disconnect.
  • the on-off sub-circuit may include a Si (silicon) device, and the action response speed of the Si device is relatively slow.
  • the control circuit may include an on-off sub-circuit 21 , a discharge resistor R0 and a voltage supply sub-circuit 22 ;
  • the voltage providing sub-circuit 22 is electrically connected to the control terminal of the clamping circuit 11 for providing a control voltage signal to the control terminal of the clamping circuit 11;
  • the control terminal of the on-off sub-circuit 21 is electrically connected to the driving voltage terminal P0 through the discharge resistor R0, the first terminal of the on-off sub-circuit 21 is electrically connected to the control terminal of the clamp circuit 11, The second terminal of the on-off sub-circuit 21 is electrically connected to the third voltage terminal P3, and the on-off sub-circuit 21 is used to control the control terminal of the clamping circuit 11 to be connected to the control terminal under the control of the potential of the control terminal.
  • the third voltage terminal V3 is connected or disconnected.
  • the voltage providing sub-circuit 22 provides a control voltage signal to the control terminal of the clamping circuit 11 ; when the potential of the driving voltage signal is determined by After the first voltage drops to the second voltage, the control terminal of the on-off sub-circuit 21 discharges to the driving voltage terminal P0 through the discharge resistor R0, and after the potential of the clamping terminal K drops to the second voltage , the on-off sub-circuit 21 controls the control terminal of the clamp circuit 11 to be disconnected from the third voltage terminal V3 under the control of the potential of the control terminal, and the clamp circuit 11 is connected to the control terminal of the clamp circuit 11. Under the control of the control voltage signal, the connection between the clamping terminal K and the clamping voltage terminal P1 is controlled.
  • control terminal of the on-off sub-circuit 21 can be directly electrically connected to the driving voltage terminal P0, or the control terminal of the on-off sub-circuit 21 can pass through other elements such as a discharge capacitor.
  • the device is electrically connected to the driving voltage terminal P0.
  • the resistance value of the discharge resistor may be 100 ohms to 1000 ohms. In the embodiment shown in FIG. 2 , the resistance value of the discharge resistor may be 200 ohms, but not limited.
  • the resistance value of the first resistor may be 1 ohm to 10 ohms. In the embodiment shown in FIG. 2 , the resistance value of the first resistor may be 2 ohms, but not limited.
  • the resistance value of the discharge resistor is greater than that of the first resistor, and more preferably, the resistance value of the discharge resistor may be 20-500 times that of the first resistor.
  • the third voltage terminal V3 may be a ground terminal or a negative voltage terminal, but not limited thereto;
  • the third voltage terminal V3 may be a positive voltage terminal, but not limited thereto.
  • the control circuit when the control circuit includes the on-off sub-circuit 21, the discharge resistor R0 and the voltage supply sub-circuit 22, after the potential of the driving voltage signal drops from the first voltage to the second voltage, the on-off sub-circuit
  • the control terminal of the circuit 21 discharges to the driving voltage terminal P0 through the discharge resistor R0, so that the drop speed of the voltage of the control terminal of the on-off sub-circuit 21 is reduced, so that the potential at the clamping terminal K drops as After the second voltage, the potential of the control terminal of the on-off sub-circuit 22 drops to a predetermined potential, so that the on-off sub-circuit 22 can control the control terminal of the clamping circuit 11 and the third voltage terminal V3
  • the clamping circuit 11 controls the connection between the clamping terminal K and the clamping voltage terminal P1 under the control of the control voltage signal provided by the voltage supply sub-circuit 22 to ensure that all The wide band gap semiconductor transistor M1 is turned off.
  • control circuit may include an on-off sub-circuit, a voltage divider sub-circuit and a voltage supply sub-circuit;
  • the voltage providing sub-circuit is used for providing a control voltage signal to the control terminal of the clamping circuit
  • the voltage dividing sub-circuit is used for dividing the voltage of the clamping terminal to obtain the divided voltage, and providing the divided voltage to the control terminal of the on-off sub-circuit;
  • the first end of the on-off sub-circuit is electrically connected to the control end of the clamping circuit
  • the second end of the on-off sub-circuit is electrically connected to the third voltage terminal
  • the on-off sub-circuit is used for Under the control of the potential of the control terminal, the control terminal of the clamping circuit is controlled to be connected or disconnected from the third voltage terminal.
  • the control circuit may include an on-off sub-circuit 21 , a voltage divider sub-circuit 20 and a voltage supply sub-circuit 22 ;
  • the voltage providing sub-circuit 22 is electrically connected to the control terminal of the clamping circuit 11 for providing a control voltage signal to the control terminal of the clamping circuit 11;
  • the voltage divider circuit 20 is electrically connected to the clamp terminal K and the control terminal of the on-off sub-circuit 21 respectively, and is used to divide the voltage of the clamp terminal K to obtain a divided voltage, and providing the divided voltage to the control terminal of the on-off sub-circuit 21;
  • the first end of the on-off sub-circuit 21 is electrically connected to the control end of the clamping circuit 11
  • the second end of the on-off sub-circuit 21 is electrically connected to the third voltage terminal V3
  • the on-off sub-circuit 21 is electrically connected to the third voltage terminal V3. 21 is used to control the connection or disconnection between the control terminal of the clamping circuit 11 and the third voltage terminal V3 under the control of the potential of the control terminal.
  • the voltage supply sub-circuit 22 provides a control voltage signal to the control terminal of the clamp circuit 11 ;
  • the voltage divider sub-circuit 20 It is used to divide the voltage of the clamping terminal K to obtain the divided voltage, and provide the divided voltage to the control terminal of the on-off sub-circuit 21;
  • the on-off sub-circuit 21 controls the control terminal of the clamping circuit 11 under the control of the divided voltage connected to its control terminal. It is disconnected from the third voltage terminal V3, and the clamping circuit 11, under the control of the control voltage signal connected to its control terminal, controls the connection between the clamping terminal K and the clamping voltage terminal P1 to ensure the The wide band gap semiconductor transistor M1 is turned off.
  • the third voltage terminal V3 may be a ground terminal or a negative voltage terminal, but not limited thereto;
  • the third voltage terminal V3 may be a positive voltage terminal, but not limited thereto.
  • the voltage dividing sub-circuit includes a first voltage dividing resistor and a second voltage dividing resistor;
  • the first end of the first voltage dividing resistor is electrically connected to the clamping end, and the second end of the first voltage dividing resistor is electrically connected to the control end of the on-off sub-circuit;
  • the first end of the second voltage dividing resistor is electrically connected to the second end of the first voltage dividing resistor, and the second end of the second voltage dividing resistor is electrically connected to the third voltage end.
  • control circuit may further include a control diode, the anode of the control diode is electrically connected to the driving voltage terminal, and the cathode of the control diode is electrically connected to the control terminal of the on-off sub-circuit.
  • control circuit may further include a control diode, and after the potential of the driving voltage signal provided by the driving voltage terminal rises from the second voltage to the first voltage, the driving voltage signal can pass through the
  • the control diode rapidly raises the potential of the control terminal of the on-off sub-circuit, so that the on-off sub-circuit can control the connection between the control terminal of the clamping circuit and the third voltage terminal, so as to control the connection between the control terminal of the clamping circuit and the third voltage terminal.
  • the clamping circuit disconnects the clamping terminal from the clamping voltage terminal, so that the wide band gap semiconductor transistor can be quickly turned on.
  • the on-off sub-circuit includes on-off control transistors
  • the control electrode of the on-off control transistor is electrically connected to the control terminal of the on-off sub-circuit, the first electrode of the on-off control transistor is electrically connected to the control terminal of the clamp circuit, and the on-off control transistor is electrically connected to the control terminal of the clamp circuit.
  • the second pole of the is electrically connected to the third voltage terminal.
  • the voltage providing sub-circuit may include a second resistor and a voltage source
  • the voltage source is electrically connected to the control terminal of the clamping circuit through the second resistor, and the voltage source is used for providing a fourth voltage signal.
  • the fourth voltage signal may be a positive voltage signal, for example, the fourth voltage signal may be a 18V voltage signal, but not limited to this;
  • the fourth voltage signal may be a negative voltage signal, but is not limited thereto.
  • the clamping module is electrically connected to the clamping terminal K, the clamping terminal K is electrically connected to the driving voltage terminal P0 through the first resistor R1 , and the driving voltage The terminal P0 is used to provide a driving voltage signal;
  • the clamping module includes a clamping circuit and a control circuit;
  • the control circuit includes an on-off sub-circuit, a discharge resistor R0, a voltage supply sub-circuit and a control diode D1;
  • the clamping terminal K is electrically connected to the first control terminal S1, the first control terminal S1 is electrically connected to the gate of the wide bandgap semiconductor transistor M1, and the source of M1 is connected to the high terminal in the bridge circuit.
  • the high-side switching transistor (not shown in FIG. 4 ) included in the circuit is electrically connected, and the drain of M1 is electrically connected to the ground terminal GND;
  • the clamping circuit includes a clamping transistor M2;
  • the on-off sub-circuit includes an on-off control transistor M3;
  • the voltage providing sub-circuit includes a second resistor R2 and a voltage source S0;
  • the gate of the clamping transistor M2 is electrically connected to the control circuit, the source of the clamping transistor M2 is electrically connected to the clamping terminal K, and the drain of the clamping transistor M2 is electrically connected to the ground terminal GND. connect;
  • the anode of the control diode D1 is electrically connected to the driving voltage terminal P0, and the cathode of the control diode D1 is electrically connected to the gate of the on-off control transistor M3;
  • the gate of M3 is electrically connected to the driving voltage terminal P0 through the discharge resistor R0;
  • the source of the on-off control transistor M3 is electrically connected to the gate of the clamping transistor M2, and the drain of the on-off control transistor M3 is electrically connected to the ground terminal GND;
  • the voltage source S0 is electrically connected to the gate of the clamping transistor M2 through the second resistor R2, and the voltage source S0 is used to provide a voltage signal of 18V, but is not limited to this voltage.
  • the driving voltage terminal P0 may be electrically connected to the driving integrated circuit 10 , and the driving voltage signal is provided by the driving integrated circuit 10 to the driving voltage terminal P0 , the driving voltage signal may be a pulse signal.
  • the clamping voltage terminal is a ground terminal
  • the third voltage terminal is a ground terminal
  • the fourth voltage signal is a 18V voltage signal, but is not limited to this voltage.
  • M1 can be an N-type Sic MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide-semiconductor field effect transistor), and M2 and M3 can both be made of Si material.
  • N-type MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide-semiconductor field effect transistor
  • M1 can also be an N-type GaN MOSFET.
  • the switching speed of M1 is faster than the switching speed of M2, and the switching speed of M1 is faster than that of M3, so that the voltage of the clamping terminal K passes through the first resistor R1 to the direction of The driving voltage terminal P0 is discharged instead of the clamping circuit 11, so that the discharge speed of the clamping terminal K can be controlled by adjusting the parameter of R1 (the parameter may be, for example, a resistance value, etc.).
  • the resistance value of R1 may be 2 ohms
  • the resistance value of R0 may be 200 ohms
  • the resistance value of R2 may be 800 ohms, but not limited thereto.
  • the resistance value of the discharge resistor R0 may be 100 ohms to 1000 ohms, and the resistance value of the first resistor R1 may be 1 ohm to 10 ohms, but not limited thereto.
  • the resistance value of the discharge resistor R0 is greater than the resistance value of the first resistor R1, and more preferably, the resistance value of the discharge resistor R0 may be the resistance value of the first resistor R1 20-500 times.
  • At least one embodiment of the clamp module shown in FIG. 4 of the present disclosure controls the closing action of the entire circuit by the closing speed of M1 itself, that is, the clamp module shown in FIG.
  • the high-speed response speed of M1 can be maintained to close the circuit.
  • the driving voltage The signal can quickly raise the potential of the gate of M3 through R1 and R0, so that M3 is turned on, the gate of M2 is connected to the ground terminal GND, M2 is turned off, and the potential of the gate of M1 rises to a high voltage.
  • the switching speed of the transistor M3 is controlled by on-off to turn on the transistor M3, so as to clamp the switch of the transistor M2. speed, the clamping transistor M2 is turned off, and then the wide band gap semiconductor transistor M1 is turned on at the switching speed of the wide band gap semiconductor transistor M1, so that the entire circuit is turned on.
  • the wide-bandgap semiconductor transistor M1 is a silicon carbide transistor or a gallium nitride transistor
  • at least one of the on-off control transistor M2 and the clamping transistor M3 is a silicon transistor
  • the switching speed of the silicon carbide transistor and the switching speed of the gallium nitride transistor are far from each other. Faster than the switching speed of silicon transistors, so that the operation speed of the entire circuit is roughly equivalent to the switching speed of silicon transistors.
  • the gate of M1 is grounded through M2, so it can resist external noise.
  • the closing action of the overall circuit is faster than the opening action.
  • the reference number S2 is the potential of the gate of M2.
  • the horizontal axis of each waveform graph is time t, and the unit is microseconds.
  • the clamping module is electrically connected to the clamping terminal K, the clamping terminal K is electrically connected to the driving voltage terminal P0 through the first resistor R1 , and the driving voltage The terminal P0 is used to provide a driving voltage signal;
  • the clamping module includes a clamping circuit and a control circuit;
  • the control circuit includes an on-off sub-circuit, a voltage divider circuit, a voltage supply sub-circuit and a control diode D1;
  • the clamping terminal K is electrically connected to the first control terminal S1, the first control terminal S1 is electrically connected to the gate of the wide band gap semiconductor transistor M1, and the source of the M1 is connected to the high terminal included in the high terminal circuit in the bridge circuit.
  • the switching transistor (not shown in FIG. 7 ) is electrically connected, and the drain of M1 is electrically connected to the ground terminal GND;
  • the clamping circuit includes a clamping transistor M2;
  • the on-off sub-circuit includes an on-off control transistor M3;
  • the The voltage supply sub-circuit includes a second resistor R2 and a voltage source S0;
  • the voltage dividing circuit includes a first voltage dividing resistor R3 and a second voltage dividing resistor R4;
  • the gate of the clamping transistor M2 is electrically connected to the control circuit, the source of the clamping transistor M2 is electrically connected to the clamping terminal K, and the drain of the clamping transistor M2 is electrically connected to the ground terminal GND. connect;
  • the anode of the control diode D1 is electrically connected to the driving voltage terminal P0, and the cathode of the control diode D1 is electrically connected to the gate of the on-off control transistor M3;
  • the first end of the first voltage dividing resistor R3 is electrically connected to the clamping terminal K, and the second end of the first voltage dividing resistor R3 is electrically connected to the gate of the on-off control transistor M3;
  • the first end of the second voltage dividing resistor R4 is electrically connected to the second end of the first voltage dividing resistor R1, and the second end of the second voltage dividing resistor R2 is electrically connected to the ground terminal GND;
  • the source of the on-off control transistor M3 is electrically connected to the gate of the clamping transistor M2, and the drain of the on-off control transistor M3 is electrically connected to the ground terminal GND;
  • the voltage source S0 is electrically connected to the gate of the clamping transistor M2 through the second resistor R2, and the voltage source S0 is used to provide a 18V voltage signal.
  • the driving voltage terminal P0 may be electrically connected to the driving integrated circuit 10 , and the driving voltage signal is provided by the driving integrated circuit 10 to the driving voltage terminal P0 , the driving voltage signal may be a pulse signal.
  • the clamping voltage terminal is a ground terminal
  • the third voltage terminal is a ground terminal
  • the fourth voltage signal is a 18V voltage signal.
  • M1 may be an N-type Sic MOSFET or an N-type GaN MOSFET, and both M2 and M3 are N-type Si MOSFETs, but not limited thereto.
  • the resistance value of R1 may be 2 ohms
  • the resistance value of R2 may be 800 ohms
  • the resistance value of R3 may be 800 ohms
  • the resistance value of R4 may be 300 ohms, but not This is the limit.
  • R3 and R4 divide the voltage of S1 to obtain the divided voltage.
  • M3 is turned on, the gate of M2 is grounded, and M2 is turned off.
  • R3 and R4 divide the voltage of S1 to obtain the divided voltage , the divided voltage can still control M3 to turn on, the gate of M2 is grounded, M2 is turned off, and the gate of M1 discharges to the driving voltage terminal P0 through R1;
  • R3 and R4 divide the voltage of S1 to obtain the divided voltage voltage
  • the divided voltage controls M3 to turn off and M2 to turn on, so that the gate of M1 is grounded to ensure that M1 is turned off; and because R3 and R4 are divided, and M3 is turned off under the control of the divided voltage, it takes a certain time , so when M2 is turned on, the voltage of S1 has dropped to 0V; in this way, the gate of M1 can be discharged to the driving voltage terminal P0 through R1 instead of through M2, so the resistance value of R1 can be adjusted to Adjust the discharge speed.
  • the driving voltage The signal can quickly raise the potential of the gate of M3 through R1, R3 and R4, so that M3 is turned on, the gate of M2 is connected to the ground terminal GND, M2 is turned off, and the potential of the gate of M1 rises to a high voltage.
  • the reference number S2 is the potential of the gate of M2.
  • the horizontal axis of each waveform graph is time t, and the unit is microseconds.
  • At least one embodiment of the present disclosure adds a voltage divider circuit composed of R3 and R4, so that the circuit can operate more stably and the overall circuit The action time becomes more controllable.
  • the initial action is turned on by the voltage divider of R1, R3, and R4 to turn on M3, so , the turn-on speed of M3 is determined by the turn-on speed of M3 itself, R4, and the parasitic capacitance of M3.
  • clamping method described in at least one embodiment of the present disclosure is applied to the above-mentioned clamping method, and the clamping method includes:
  • the control circuit controls the potential of the control terminal of the clamping circuit to make the clamping circuit The connection between the clamping terminal and the clamping voltage terminal is controlled.
  • the clamping circuit is used to control the clamping terminal and the clamping terminal to be connected to the second voltage.
  • the clamping voltage terminals are connected, so that the potential of the gate of the wide-bandgap semiconductor transistor is the clamping voltage, which can ensure that the wide-bandgap semiconductor transistor is turned off, and avoid the occurrence of wrong turn-on of the wide-bandgap semiconductor transistor, Reduce circuit losses.
  • the clamping method described in at least one embodiment of the present disclosure may further include:
  • the control circuit controls the potential of the control terminal of the clamping circuit to make the The clamping circuit controls the disconnection between the clamping terminal and the clamping voltage terminal.
  • the control circuit controls the The potential of the control terminal of the clamping circuit is controlled, so that the clamping circuit controls the connection between the clamping terminal and the clamping voltage terminal to be disconnected, so as to ensure that the clamping terminal is not discharged through the clamping circuit.
  • the clamping method may further include: when the potential of the driving voltage signal is the first voltage, the control circuit controls the potential of the control terminal of the clamping circuit to The clamping circuit controls the disconnection between the clamping terminal and the clamping voltage terminal.
  • the control circuit controls the potential of the control terminal of the clamping circuit, so that the clamping circuit controls The clamping terminal is disconnected from the clamping voltage terminal to ensure that the wide band gap semiconductor transistor can be turned on
  • control circuit includes an on-off sub-circuit and a voltage supply sub-circuit;
  • clamping method includes:
  • the voltage providing sub-circuit provides a control voltage signal to the control terminal of the clamping circuit
  • the control terminal of the on-off sub-circuit discharges to the driving voltage terminal, and after the potential of the clamping terminal drops to the second voltage, the Under the control of the potential of its control terminal, the on-off sub-circuit controls the disconnection between the control terminal of the clamping circuit and the third voltage terminal, and the clamping circuit is controlled by the control voltage signal connected to the control terminal of the clamping circuit. The connection between the clamping terminal and the clamping voltage terminal is controlled.
  • control circuit includes an on-off sub-circuit, a voltage divider sub-circuit and a voltage supply sub-circuit;
  • clamping method includes:
  • the voltage providing sub-circuit provides a control voltage signal to the control terminal of the clamping circuit; the voltage dividing sub-circuit divides the voltage of the clamping terminal to obtain the divided voltage, and provides the divided voltage to the the control terminal of the on-off sub-circuit;
  • the on-off sub-circuit is controlled by the divided voltage connected to the control terminal.
  • the control terminal of the clamping circuit is disconnected from the third voltage terminal, and the clamping circuit controls the connection between the clamping terminal and the clamping voltage terminal under the control of the control voltage signal connected to the control terminal of the clamping circuit. .
  • the switch unit described in at least one embodiment of the present disclosure includes a wide-bandgap semiconductor transistor and the above-mentioned clamping module;
  • the control electrode of the wide band gap semiconductor transistor is electrically connected to the clamping terminal.
  • the switch unit described in at least one embodiment of the present disclosure can be applied to a bridge circuit.
  • the bridge circuit may include a high terminal circuit and a low terminal circuit
  • the high-terminal circuit includes a high-side switching transistor M0, a power supply E, a high-side driving voltage source S11, an inductance L, a control resistor R01 and a first control diode D01;
  • the low-terminal circuit includes a first resistor R1, a low-side driving voltage source S12 , the second control diode D02, the wide band gap semiconductor transistor M1 and the clamping module described in the embodiment of the present disclosure;
  • the low-end driving voltage signal provided by the low-end driving voltage source 120 is the driving voltage signal provided by the voltage signal terminal P0;
  • the clamping module includes a clamping transistor M2 and the control circuit 12, and the control circuit 12 is used to control the potential of the gate of M2.
  • the gate-source parasitic capacitance of M0 is labeled C11
  • the gate-drain parasitic capacitance of M0 is labeled C12
  • the gate-source parasitic capacitance of M1 is labeled C21
  • the gate-drain capacitance of M0 is labeled C22.
  • the wide-bandgap semiconductor transistor M1 is a low-side switching transistor included in the low-terminal circuit.
  • the reference numeral GND is the ground terminal.
  • M1 may be a SiC MOSFET or a GaN MOSFET.
  • the low-voltage driving voltage signal provided by the low-side driving voltage source S12 can be provided by a driver IC, and the high-side driving voltage signal provided by the high-side driving voltage source S11 is also Can be provided by the driver IC.
  • the electronic device includes the above-mentioned switch unit.
  • an embodiment of the present disclosure provides a clamping module, which is electrically connected to a clamping terminal K, the clamping terminal K is electrically connected to a driving voltage terminal P0, and the driving voltage terminal P0 is used to provide driving voltage signal;
  • the clamping module includes a clamping circuit 11 and a control circuit 12;
  • the control terminal of the clamping circuit 11 is electrically connected to the control circuit 12 , the first terminal of the clamping circuit 11 is electrically connected to the clamping terminal K, and the second terminal of the clamping circuit 11 is electrically connected to the clamping voltage Terminal P1 is electrically connected;
  • the control circuit 12 is used for controlling the clamping circuit 11 after the potential of the driving voltage signal drops from the first voltage to the second voltage and the potential of the clamping terminal K drops to the second voltage.
  • the potential of the control terminal of so that the clamping circuit 11 controls the connection between the clamping terminal and the clamping voltage terminal P1.
  • the clamping module when the potential of the driving voltage signal drops from the first voltage to the second voltage, and after the potential of the clamping terminal K drops to the second voltage,
  • the connection between the clamping terminal K and the clamping voltage terminal P1 is controlled by the clamping circuit 11, so that the potential of the gate of the wide-bandgap semiconductor transistor M1 is the clamping voltage, which can ensure the wide-bandgap semiconductor
  • the transistor M1 is turned off to avoid the accidental turn-on of the wide-bandgap semiconductor transistor M1, thereby reducing circuit loss.
  • the clamping terminal is directly electrically connected to the driving voltage terminal; alternatively, the clamping terminal is electrically connected to the driving voltage terminal through a resistor or a capacitor; or, the driving voltage provided by the driving voltage terminal
  • the signal is a high-frequency pulse signal, and the clamping terminal is electrically connected to the driving voltage terminal through a capacitor.
  • control circuit is further configured to control the potential of the control terminal of the clamping circuit after the potential of the driving voltage signal drops from the first voltage and before the potential of the clamping terminal drops to the second voltage. , so that the clamping circuit controls the disconnection between the clamping terminal and the clamping voltage terminal.
  • control circuit is further configured to control the potential of the control terminal of the clamping circuit when the potential of the driving voltage signal is the first voltage, so that the clamping circuit controls the clamping terminal disconnected from the clamp voltage terminal.
  • control circuit includes an on-off sub-circuit and a voltage supply sub-circuit
  • the voltage providing sub-circuit is used for providing a control voltage signal to the control terminal of the clamping circuit
  • the control terminal of the on-off sub-circuit is electrically connected to the driving voltage terminal
  • the first terminal of the on-off sub-circuit is electrically connected to the control terminal of the clamp circuit
  • the second terminal of the on-off sub-circuit is electrically connected It is electrically connected to the third voltage terminal
  • the on-off sub-circuit is used to control the connection or disconnection between the control terminal of the clamping circuit and the third voltage terminal under the control of the potential of the control terminal.
  • control terminal of the on-off sub-circuit is directly electrically connected to the driving voltage terminal; or, the control terminal of the on-off sub-circuit is electrically connected to the driving voltage terminal through a discharge resistor; or, the The control terminal of the on-off sub-circuit is electrically connected to the driving voltage terminal through a discharge capacitor.
  • control circuit includes an on-off sub-circuit, a voltage divider sub-circuit and a voltage supply sub-circuit;
  • the voltage providing sub-circuit is used for providing a control voltage signal to the control terminal of the clamping circuit
  • the voltage dividing sub-circuit is used for dividing the voltage of the clamping terminal to obtain the divided voltage, and providing the divided voltage to the control terminal of the on-off sub-circuit;
  • the first end of the on-off sub-circuit is electrically connected to the control end of the clamping circuit
  • the second end of the on-off sub-circuit is electrically connected to the third voltage terminal
  • the on-off sub-circuit is used for Under the control of the potential of the control terminal, the control terminal of the clamping circuit is controlled to be connected or disconnected from the third voltage terminal.
  • the voltage dividing sub-circuit includes a first voltage dividing resistor and a second voltage dividing resistor;
  • the first end of the first voltage dividing resistor is electrically connected to the clamping end, and the second end of the first voltage dividing resistor is electrically connected to the control end of the on-off sub-circuit;
  • the first end of the second voltage dividing resistor is electrically connected to the second end of the first voltage dividing resistor, and the second end of the second voltage dividing resistor is electrically connected to the third voltage end.
  • control circuit further includes a control diode, the anode of the control diode is electrically connected to the driving voltage terminal, and the cathode of the control diode is electrically connected to the control terminal of the on-off sub-circuit.
  • the on-off sub-circuit includes on-off control transistors
  • the control electrode of the on-off control transistor is electrically connected to the control terminal of the on-off sub-circuit, the first electrode of the on-off control transistor is electrically connected to the control terminal of the clamp circuit, and the on-off control transistor is electrically connected to the control terminal of the clamp circuit.
  • the second pole of the is electrically connected to the third voltage terminal.
  • the voltage providing sub-circuit includes a second resistor and a voltage source
  • the voltage source is electrically connected to the control terminal of the clamping circuit through the second resistor, and the voltage source is used for providing a fourth voltage signal.
  • the clamping circuit includes a clamping transistor
  • the control electrode of the clamp transistor is electrically connected to the control circuit, the first electrode of the clamp transistor is electrically connected to the clamp terminal, and the second electrode of the clamp transistor is electrically connected to the clamp voltage terminal ;
  • the control circuit is used to control the voltage of the control electrode of the clamping transistor after the potential of the driving voltage signal drops from the first voltage to the second voltage and the potential of the clamping terminal drops to the second voltage. potential to turn on the clamp transistor.
  • An embodiment of the present disclosure also provides a clamping method, which is applied to the above-mentioned clamping method, and the clamping method includes:
  • the control circuit controls the potential of the control terminal of the clamping circuit to make the clamping circuit The connection between the clamping terminal and the clamping voltage terminal is controlled.
  • the clamping method described in at least one embodiment of the present disclosure further includes:
  • the control circuit controls the potential of the control terminal of the clamping circuit to make the The clamping circuit controls the disconnection between the clamping terminal and the clamping voltage terminal.
  • At least one embodiment of the present disclosure further includes: when the potential of the driving voltage signal is the first voltage, the control circuit controls the potential of the control terminal of the clamping circuit to make the clamping circuit The clamping terminal and the clamping voltage terminal are controlled to be disconnected.
  • control circuit includes an on-off sub-circuit and a voltage supply sub-circuit;
  • clamping method includes:
  • the voltage providing sub-circuit provides a control voltage signal to the control terminal of the clamping circuit
  • the control terminal of the on-off sub-circuit discharges to the driving voltage terminal, and after the potential of the clamping terminal drops to the second voltage, the Under the control of the potential of its control terminal, the on-off sub-circuit controls the disconnection between the control terminal of the clamping circuit and the third voltage terminal, and the clamping circuit is controlled by the control voltage signal connected to the control terminal of the clamping circuit. The connection between the clamping terminal and the clamping voltage terminal is controlled.
  • control circuit includes an on-off sub-circuit, a voltage divider sub-circuit and a voltage supply sub-circuit;
  • clamping method includes:
  • the voltage providing sub-circuit provides a control voltage signal to the control terminal of the clamping circuit; the voltage dividing sub-circuit divides the voltage of the clamping terminal to obtain the divided voltage, and provides the divided voltage to the the control terminal of the on-off sub-circuit;
  • the on-off sub-circuit is controlled by the divided voltage connected to the control terminal.
  • the control terminal of the clamping circuit is disconnected from the third voltage terminal, and the clamping circuit controls the connection between the clamping terminal and the clamping voltage terminal under the control of the control voltage signal connected to the control terminal of the clamping circuit. .
  • Embodiments of the present disclosure also provide a wide band gap semiconductor transistor and the above clamping module
  • the control electrode of the wide band gap semiconductor transistor is electrically connected to the clamping terminal.
  • the wide band gap semiconductor transistor is a silicon carbide field effect transistor or a gallium nitride field effect transistor.
  • control circuit includes an on-off sub-circuit; the clamping circuit and/or the on-off sub-circuit in the clamping module includes a silicon device.
  • Embodiments of the present disclosure also provide an electronic device, including the above-mentioned switch unit.

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Abstract

一种钳位模组、钳位方法、开关单元和电子设备。钳位模组，与钳位端（K）电连接，所述钳位端（K）与驱动电压端（P0）电连接，所述驱动电压端（P0）用于提供驱动电压信号；所述钳位模组包括钳位电路（11）和控制电路（12）；所述钳位电路（11）的控制端与所述控制电路（12）电连接，所述钳位电路（11）的第一端与钳位端（K）电连接，所述钳位电路（11）的第二端与钳位电压端（P1）电连接；所述控制电路（12）用于当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端（K）的电位下降为第二电压之后，通过控制所述钳位电路（11）的控制端的电位，以使得所述钳位电路（11）控制所述钳位端（K）与所述钳位电压端（P1）之间连通。

Description

钳位模组、钳位方法、开关单元和电子设备 技术领域
本公开涉及电压钳位技术领域，尤其涉及一种钳位模组、钳位方法、开关单元和电子设备。
背景技术
宽带隙半导体晶体管属于高速开关器件，一般在桥式电路中应用广泛。
当采用不具有米勒钳位的驱动IC(Integrated Circuit，集成电路)驱动宽带隙半导体晶体管时，则会产生由于无法对宽带隙半导体晶体管进行米勒钳位，而引起宽带隙半导体晶体管误开通，导致整体电路损耗大的问题。
发明内容
本公开的主要目的在于提供一种钳位模组、钳位方法、开关单元和电子设备。
在一个方面中，本公开实施例提供了一种钳位模组，与钳位端电连接，所述钳位端与驱动电压端电连接，所述驱动电压端用于提供驱动电压信号；所述钳位模组包括钳位电路和控制电路；
所述钳位电路的控制端与所述控制电路电连接，所述钳位电路的第一端与钳位端电连接，所述钳位电路的第二端与钳位电压端电连接；
所述控制电路用于当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端的电位下降为第二电压之后，通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间连通。
在第二个方面中，本公开实施例提供了一种钳位方法，应用于上述的钳位方法，所述钳位方法包括：
当驱动电压信号的电位由第一电压下降为第二电压之后，并钳位端的电位下降为第二电压之后，控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与钳位电压端之间连通。
在第三个方面中，本公开实施例还提供了一种开关单元，包括宽带隙半导体晶体管和上述的钳位模组；
所述宽带隙半导体晶体管的控制极与所述钳位端电连接。
在第四个方面中，本公开实施例还提供了一种电子设备，包括上述的开关单元。
附图说明
图1是本公开至少一实施例所述的钳位模组的结构图；
图2是本公开至少一实施例所述的钳位模组的结构图；
图3是本公开至少一实施例所述的钳位模组的结构图；
图4是本公开至少一实施例所述的钳位模组的电路图；
图5是本公开如图4所示的钳位模组的至少一实施例的第一工作时序图；
图6是本公开如图4所示的钳位模组的至少一实施例的第二工作时序图；
图7是本公开至少一实施例所述的钳位模组的电路图；
图8是本公开如图7所示的钳位模组的至少一实施例的第一工作时序图；
图9是本公开如图7所示的钳位模组的至少一实施例的第二工作时序图；
图10是本公开至少一实施例所述的钳位模组应用于的桥式电路的电路图；
图11是本公开至少一实施例所述的钳位模组的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所 述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开至少一实施例所述的钳位模组，与钳位端K电连接，所述钳位端K通过第一电阻R1与驱动电压端P0电连接，所述驱动电压端P0用于提供驱动电压信号；如图1所示，所述钳位模组包括钳位电路11和控制电路12；所述钳位电路11的控制端与所述控制电路12电连接，所述钳位电路11的第一端与钳位端K电连接，所述钳位电路11的第二端与钳位电压端P1电连接；
所述控制电路12用于当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端K的电位下降为第二电压之后，通过控制所述钳位电路11的控制端的电位，以使得所述钳位电路11控制所述钳位端K与所述钳位电压端P1之间连通；所述钳位电压端P1用于提供钳位电压；
所述钳位端K与第一控制端S1电连接，所述第一控制端S1与宽带隙(Wide Bandgap)半导体晶体管M1的栅极电连接，M1的源极可以与桥式电路中的高端(High Side)子电路包括的高端开关晶体管(图1中未示出)电连接，M1的漏极与地端GND电连接，M1可以为所述桥式电路中的低端(Low Side)子电路包括的低端开关晶体管。
在本公开至少一实施例中，如图1所示，所述驱动电压端P0可以与驱动集成电路10电连接，由所述驱动集成电路10向所述驱动电压端P0提供所述驱动电压信号，所述驱动电压信号可以为脉冲信号。
在本公开至少一实施例中，所述钳位端K可以为与宽带隙半导体晶体管的栅极电连接的节点。
可选的，所述第一电压可以为正电压，例如，所述第一电压可以为18V或16V，但不以此为限；
所述第二电压可以为地电压或负电压，但不以此为限。
在本公开至少一实施例中，所述宽带隙半导体晶体管M1可以为SiC(碳 化硅)场效应晶体管或GaN(氮化镓)场效应晶体管，但不以此为限。
本公开至少一实施例所述的钳位模组在工作时，当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端K的电位降为第二电压之后，所述控制电路12通过控制所述钳位电路11的控制端的电位，以使得所述钳位电路11控制所述钳位端K与所述钳位电压端P1之间连通；通过采用本公开至少一实施例所述的钳位模组，能够实现当所述驱动电压信号的电位由第一电压下降为第二电压之后，由于所述宽带隙半导体晶体管M1的动作反应速度比钳位电路11的动作反应速度快，因此所述钳位端K的电压通过第一电阻R1向所述驱动电压端P0放电，而并非通过所述钳位电路11放电，以提升放电速度，并可以通过调节R1的参数(例如可以为电阻值等)来控制所述钳位端K的放电速度等。
在本公开至少一实施例中，所述钳位电路可以包括Si(硅)器件，Si器件的动作反应速度较慢。
本公开至少一实施例当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端K的电位降为第二电压之后，通过钳位电路11控制所述钳位端K与所述钳位电压端P1之间连通，以使得所述宽带隙半导体晶体管M1的栅极的电位为钳位电压，能够保证所述宽带隙半导体晶体管M1关断，避免宽带隙半导体晶体管M1误开通的情况发生，降低电路损耗。
在具体实施时，当所述宽带隙半导体晶体管为N型晶体管时，所述钳位电压端可以为地端或负电压端，但不以此为限；
当所述宽带隙半导体晶体管为P型晶体管时，所述钳位电压端可以为正电压端，但不以此为限。
在具体实施时，所述控制电路12还用于在所述驱动电压信号的电位由第一电压下降之后，所述钳位端K的电位下降为第二电压之前，通过控制所述钳位电路11的控制端的电位，以使得所述钳位电路11控制所述钳位端K与所述钳位电压端P1之间断开。
本公开至少一实施例所述的钳位模组在工作时，在所述驱动电压信号的电位由第一电压下降之后，所述钳位端K的电位下降为第二电压之前，所述控制电路12通过控制所述钳位电路11的控制端的电位，以使得所述钳位电 路11控制所述钳位端K与所述钳位电压端P1之间断开，以保证所述钳位端K不会通过所述钳位电路11放电。
进一步的，所述控制电路12还用于在所述驱动电压信号的电位为第一电压时，通过控制所述钳位电路11的控制端的电位，以使得所述钳位电路11控制所述钳位端K与所述钳位电压端P1之间断开。
本公开至少一实施例所述的钳位模组在工作时，在所述驱动电压信号的电位为第一电压时，所述控制电路12通过控制所述钳位电路11的控制端的电位，使得钳位电路11控制所述钳位端K与钳位电压端P1之间断开，以保证所述宽带隙半导体晶体管能够打开。
在图1所示的钳位模组的至少一实施例中，所述钳位端K可以与所述驱动电压端P0之间可以直接电连接，或者，所述钳位端K可以与所述驱动电压端P0之间可以通过电容电连接。
在图1所示的钳位模组的至少一实施例中，所述第一电阻R1也可以设置于所述钳位端K与所述第一控制端S1之间。
可选的，所述钳位电路可以包括钳位晶体管；
所述钳位晶体管的控制极与所述控制电路电连接，所述钳位晶体管的第一极与所述钳位端电连接，所述钳位晶体管的第二极与钳位电压端电连接；
所述控制电路用于当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端的电位下降为第二电压之后，通过控制所述钳位晶体管的控制极的电位，以使得所述钳位晶体管导通。
根据一种具体实施方式，所述控制电路可以包括通断子电路、放电电阻和电压提供子电路；
所述电压提供子电路用于向所述钳位电路的控制端提供控制电压信号；
所述通断子电路的控制端通过所述放电电阻与所述驱动电压端电连接，所述通断子电路的第一端与所述钳位电路的控制端电连接，所述通断子电路的第二端与第三电压端电连接，所述通断子电路用于在其控制端的电位的控制下，控制所述钳位电路的控制端与所述第三电压端之间连通或断开。
在本公开至少一实施例中，所述通断子电路可以包括Si(硅)器件，Si器件的动作反应速度较慢。
如图2所示，在图1所示的钳位模组的至少一实施例的基础上，所述控制电路可以包括通断子电路21、放电电阻R0和电压提供子电路22；
所述电压提供子电路22与所述钳位电路11的控制端电连接，用于向所述钳位电路11的控制端提供控制电压信号；
所述通断子电路21的控制端通过所述放电电阻R0与所述驱动电压端P0电连接，所述通断子电路21的第一端与所述钳位电路11的控制端电连接，所述通断子电路21的第二端与第三电压端P3电连接，所述通断子电路21用于在其控制端的电位的控制下，控制所述钳位电路11的控制端与所述第三电压端V3之间连通或断开。
本公开如图2所示的钳位模组的至少一实施例在工作时，所述电压提供子电路22向所述钳位电路11的控制端提供控制电压信号；当驱动电压信号的电位由第一电压下降为第二电压之后，所述通断子电路21的控制端通过所述放电电阻R0向所述驱动电压端P0放电，在所述钳位端K的电位下降为第二电压之后，所述通断子电路21在其控制端的电位的控制下，控制所述钳位电路11的控制端与第三电压端V3之间断开，所述钳位电路11在其控制端接入的控制电压信号的控制下，控制所述钳位端K与钳位电压端P1之间连通。
在本公开至少一实施例中，所述通断子电路21的控制端可以直接与所述驱动电压端P0电连接，或者，所述通断子电路21的控制端可以通过放电电容等其他元器件与所述驱动电压端P0电连接。
在本公开至少一实施例中，所述放电电阻的电阻值可以为100欧姆～1000欧姆，在图2所示的实施例中，所述放电电阻的电阻值可以为200欧姆，但不以此为限。
在本公开至少一实施例中，所述第一电阻的电阻值可以为1欧姆～10欧姆，在图2所示的实施例中，第一电阻的电阻值可以为2欧姆，但不以此为限。
考虑到放电时间，在优选情况下，放电电阻的电阻值大于第一电阻的电阻值，更优选的，放电电阻的电阻值可以是第一电阻的电阻值的20-500倍。
在本公开至少一实施例中，当所述钳位电路11包括的钳位晶体管为N型晶体管时，所述第三电压端V3可以为地端或负电压端，但不以此为限；
当所述钳位晶体管为P型晶体管时，所述第三电压端V3可以为正电压端，但不以此为限。
在具体实施时，当所述控制电路包括通断子电路21、放电电阻R0和电压提供子电路22时，在驱动电压信号的电位由第一电压下降为第二电压之后，所述通断子电路21的控制端通过所述放电电阻R0向所述驱动电压端P0放电，以使得所述通断子电路21的控制端的电压的下降速度变小，从而使得在钳位端K的电位下降为第二电压之后，所述通断子电路22的控制端的电位才下降到预定电位，以能够使得所述通断子电路22控制所述钳位电路11的控制端与所述第三电压端V3之间断开，此时所述钳位电路11在所述电压提供子电路22提供的控制电压信号的控制下，控制所述钳位端K与所述钳位电压端P1之间连通，保证所述宽带隙半导体晶体管M1关断。
根据另一种具体实施方式，所述控制电路可以包括通断子电路、分压子电路和电压提供子电路；
所述电压提供子电路用于向所述钳位电路的控制端提供控制电压信号；
所述分压子电路用于对所述钳位端的电压进行分压，得到分压电压，并将所述分压电压提供至所述通断子电路的控制端；
所述通断子电路的第一端与所述钳位电路的控制端电连接，所述通断子电路的第二端与第三电压端电连接，所述通断子电路用于在其控制端的电位的控制下，控制所述钳位电路的控制端与所述第三电压端之间连通或断开。
如图3所示，在图1所示的钳位模组的至少一实施例的基础上，所述控制电路可以包括通断子电路21、分压子电路20和电压提供子电路22；
所述电压提供子电路22与所述钳位电路11的控制端电连接，用于向所述钳位电路11的控制端提供控制电压信号；
所述分压子电路20分别与所述钳位端K和所述通断子电路21的控制端电连接，用于对所述钳位端K的电压进行分压，得到分压电压，并将所述分压电压提供至所述通断子电路21的控制端；
所述通断子电路21的第一端与所述钳位电路11的控制端电连接，所述通断子电路21的第二端与第三电压端V3电连接，所述通断子电路21用于在其控制端的电位的控制下，控制所述钳位电路11的控制端与所述第三电压 端V3之间连通或断开。
本公开如图3所示的钳位模组的至少一实施例在工作时，所述电压提供子电路22向所述钳位电路11的控制端提供控制电压信号；所述分压子电路20用于对钳位端K的电压进行分压，得到分压电压，并将所述分压电压提供至所述通断子电路21的控制端；当驱动电压信号的电位由第一电压下降为第二电压之后，并钳位端K的电位下降为第二电压之后，所述通断子电路21在其控制端接入的分压电压的控制下，控制所述钳位电路11的控制端与第三电压端V3之间断开，所述钳位电路11在其控制端接入的控制电压信号的控制下，控制所述钳位端K与钳位电压端P1之间连通，保证所述宽带隙半导体晶体管M1关断。
在本公开至少一实施例中，当所述钳位电路11包括的钳位晶体管为N型晶体管时，所述第三电压端V3可以为地端或负电压端，但不以此为限；
当所述钳位晶体管为P型晶体管时，所述第三电压端V3可以为正电压端，但不以此为限。
可选的，所述分压子电路包括第一分压电阻和第二分压电阻；
所述第一分压电阻的第一端与所述钳位端电连接，所述第一分压电阻的第二端与所述通断子电路的控制端电连接；
所述第二分压电阻的第一端与所述第一分压电阻的第二端电连接，所述第二分压电阻的第二端与所述第三电压端电连接。
在具体实施时，所述控制电路还可以包括控制二极管，所述控制二极管的阳极与所述驱动电压端电连接，所述控制二极管的阴极与所述通断子电路的控制端电连接。
在本公开至少一实施例中，所述控制电路还可以包括控制二极管，当所述驱动电压端提供的驱动电压信号的电位由第二电压上升为第一电压后，所述驱动电压信号能够通过所述控制二极管快速的提升所述通断子电路的控制端的电位，以使得所述通断子电路能够控制所述钳位电路的控制端与所述第三电压端之间连通，以控制所述钳位电路使得所述钳位端与所述钳位电压端之间断开，使得所述宽带隙半导体晶体管能够快速打开。
可选的，所述通断子电路包括通断控制晶体管；
所述通断控制晶体管的控制极与所述通断子电路的控制端电连接，所述通断控制晶体管的第一极与所述钳位电路的控制端电连接，所述通断控制晶体管的第二极与所述第三电压端电连接。
在本公开至少一实施例中，所述电压提供子电路可以包括第二电阻和电压源；
所述电压源通过所述第二电阻与所述钳位电路的控制端电连接，所述电压源用于提供第四电压信号。
在具体实施时，当所述钳位电路包括的钳位晶体管为N型晶体管时，所述第四电压信号可以为正电压信号，例如，所述第四电压信号可以为18V电压信号，但不以此为限；
当所述钳位电路包括的钳位晶体管为P型晶体管时，所述第四电压信号可以为负电压信号，但不以此为限。
如图4所示，本公开至少一实施例所述的钳位模组与钳位端K电连接，所述钳位端K通过第一电阻R1与驱动电压端P0电连接，所述驱动电压端P0用于提供驱动电压信号；如图4所示，所述钳位模组包括钳位电路和控制电路；所述控制电路包括通断子电路、放电电阻R0、电压提供子电路和控制二极管D1；
所述钳位端K与第一控制端S1电连接，所述第一控制端S1与宽带隙(Wide Bandgap)半导体晶体管M1的栅极电连接，M1的源极与桥式电路中的高端子电路包括的高端开关晶体管(图4中未示出)电连接，M1的漏极与地端GND电连接；所述钳位电路包括钳位晶体管M2；所述通断子电路包括通断控制晶体管M3；所述电压提供子电路包括第二电阻R2和电压源S0；
所述钳位晶体管M2的栅极与所述控制电路电连接，所述钳位晶体管M2的源极与所述钳位端K电连接，所述钳位晶体管M2的漏极与地端GND电连接；
所述控制二极管D1的阳极与所述驱动电压端P0电连接，所述控制二极管D1的阴极与所述通断控制晶体管M3的栅极电连接；
M3的栅极通过所述放电电阻R0与所述驱动电压端P0电连接；
所述通断控制晶体管M3的源极与所述钳位晶体管M2的栅极电连接， 所述通断控制晶体管M3的漏极与地端GND电连接；
所述电压源S0通过所述第二电阻R2与所述钳位晶体管M2的栅极电连接，所述电压源S0用于提供18V电压信号，但不以此电压为限。
在本公开至少一实施例中，如图4所示，所述驱动电压端P0可以与驱动集成电路10电连接，由所述驱动集成电路10向所述驱动电压端P0提供所述驱动电压信号，所述驱动电压信号可以为脉冲信号。
在图4所示的至少一实施例中，所述钳位电压端为地端，所述第三电压端为地端，第四电压信号为18V电压信号，但不以此电压为限。
在图4所示的至少一实施例中，M1可以为N型Sic MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物-半导体场效应晶体管)，M2和M3可以都为Si材料的N型MOSFET，但不以此为限。
在图4所示的至少一实施例中，M1也可以为N型GaN MOSFET。
在图4所示的至少一实施例中，M1的开关速度比M2的开关速度快，M1的开关速度比M3的开关速度快，从而使得所述钳位端K的电压通过第一电阻R1向所述驱动电压端P0放电，而并非通过所述钳位电路11放电，从而可以通过调节R1的参数(所述参数例如可以为电阻值等)来控制所述钳位端K的放电速度。
在图4所示的至少一实施例中，R1的电阻值可以为2欧姆，R0的电阻值可以为200欧姆，R2的电阻值可以为800欧姆，但不以此为限。
在本公开至少一实施例中，所述放电电阻R0的电阻值可以为100欧姆～1000欧姆，所述第一电阻R1的电阻值可以为1欧姆～10欧姆，但不以此为限。
考虑到放电时间，在优选情况下，所述放电电阻R0的电阻值大于所述第一电阻R1的电阻值，更优选的，所述放电电阻R0的电阻值可以是第一电阻R1的电阻值的20-500倍。
如图5所示，本公开如图4所示的至少一实施例在工作时，在驱动电压端P0提供的驱动电压信号的电位由18V下降至0V后，M3的栅极的电位通过R0向所述驱动电压端P0放电，由于R0的电阻值较大，因此M3的栅极的电位的下降的速度较慢，在M1的栅极的电位下降为0V之后，M3关闭， M2的栅极的电位被S0拉高，M2的电位上升，M2打开，M1的栅极与地端GND连通；这样，可以使得M1的栅极是通过R1向所述驱动电压端P0放电，而不是通过M2放电，因此可以通过调节R1的电阻值来对放电速度进行调整。
在图5中，标示为S2的为M2的栅极的电位。
如上所述，本公开如图4所示的钳位模组的至少一实施例是以M1自身的关闭速度来控制整个电路的关闭动作，即本公开如图4所示的钳位模组的至少一实施例在需要关闭电路，尤其是检测到异常状态需要立即关闭电路时，可以维持M1的高速响应速度来关闭电路。
如图6所示，本公开如图4所示的钳位模组的至少一实施例在工作时，在驱动电压端P0提供的驱动电压信号的电位由0V上升至18V后，所述驱动电压信号通过R1和R0很快就能够提升M3的栅极的电位，以使得M3打开，M2的栅极与地端GND之间连通，M2关闭，M1的栅极的电位上升为高电压。
如上所述，本公开如图4所示的钳位模组的至少一实施例在开启电路的动作上，是先以通断控制晶体管M3的开关速度使得M3打开，以钳位晶体管M2的开关速度，使钳位晶体管M2关闭，然后再以宽带隙半导体晶体管M1的开关速度使宽带隙半导体晶体管M1开启，使整个电路导通。当宽带隙半导体晶体管M1是碳化硅晶体管或者氮化镓晶体管，通断控制晶体管M2和钳位晶体管M3中至少一个是硅晶体管时，由于碳化硅晶体管的开关速度和氮化镓晶体管的开关速度远快于硅晶体管的开关速度，这样，整个电路的动作速度就大致等同于硅晶体管的开关速度。
也就是说，P0提供的驱动电压由于外部噪声有小幅波动的时候，本公开如图4所示的钳位模组的至少一实施例不会像直接连接到M1那样产生误操作。
在本发明至少一实施例中，M1的栅极通过M2接地，因此可以抵御外部噪声。
如上所述，该整体电路的关闭动作的速度比开启动作的速度要快。
在图5和图6中，标号为S2的为M2的栅极的电位。并在图5和图6中，各波形图的横轴为时间t，单位是微秒。
如图7所示，本公开至少一实施例所述的钳位模组与钳位端K电连接， 所述钳位端K通过第一电阻R1与驱动电压端P0电连接，所述驱动电压端P0用于提供驱动电压信号；如图8所示，所述钳位模组包括钳位电路和控制电路；所述控制电路包括通断子电路、分压电路、电压提供子电路和控制二极管D1；
所述钳位端K与第一控制端S1电连接，所述第一控制端S1与宽带隙半导体晶体管M1的栅极电连接，M1的源极与桥式电路中的高端子电路包括的高端开关晶体管(图7中未示出)电连接，M1的漏极与地端GND电连接；所述钳位电路包括钳位晶体管M2；所述通断子电路包括通断控制晶体管M3；所述电压提供子电路包括第二电阻R2和电压源S0；所述分压电路包括第一分压电阻R3和第二分压电阻R4；
所述钳位晶体管M2的栅极与所述控制电路电连接，所述钳位晶体管M2的源极与所述钳位端K电连接，所述钳位晶体管M2的漏极与地端GND电连接；
所述控制二极管D1的阳极与所述驱动电压端P0电连接，所述控制二极管D1的阴极与所述通断控制晶体管M3的栅极电连接；
所述第一分压电阻R3的第一端与所述钳位端K电连接，所述第一分压电阻R3的第二端与所述通断控制晶体管M3的栅极电连接；
所述第二分压电阻R4的第一端与所述第一分压电阻R1的第二端电连接，所述第二分压电阻R2的第二端与地端GND电连接；
所述通断控制晶体管M3的源极与所述钳位晶体管M2的栅极电连接，所述通断控制晶体管M3的漏极与地端GND电连接；
所述电压源S0通过所述第二电阻R2与所述钳位晶体管M2的栅极电连接，所述电压源S0用于提供18V电压信号。
在本公开至少一实施例中，如图7所示，所述驱动电压端P0可以与驱动集成电路10电连接，由所述驱动集成电路10向所述驱动电压端P0提供所述驱动电压信号，所述驱动电压信号可以为脉冲信号。
在图7所示的至少一实施例中，所述钳位电压端为地端，所述第三电压端为地端，第四电压信号为18V电压信号。
在图7所示的至少一实施例中，M1可以为N型Sic MOSFET或N型GaN  MOSFET，M2和M3都为N型Si MOSFET，但不以此为限。
在图7所示的至少一实施例中，R1的电阻值可以为2欧姆，R2的电阻值可以为800欧姆，R3的电阻值可以为800欧姆，R4的电阻值可以为300欧姆，但不以此为限。
如图8所示，本公开如图7所示的钳位模组的至少一实施例在工作时，
当所述驱动电压端P0提供的驱动电压信号为18V电压信号时，R3和R4对S1的电压进行分压，以得到分压电压，此时M3打开，M2的栅极接地，M2关断，M1打开；
在驱动电压端P0提供的驱动电压信号的电位由18V下降至0V后，当S1的栅极的电位还未下降至预定电压时，R3和R4对S1的电压进行分压，以得到分压电压，该分压电压依旧能够控制M3打开，M2的栅极接地，M2关断，M1的栅极通过R1向所述驱动电压端P0放电；
在驱动电压端P0提供的驱动电压信号的电位由18V下降至0V后，当S1的栅极的电位下降至小于所述预定电压时，R3和R4对S1的电压进行分压，以得到分压电压，该分压电压控制M3关断，M2打开，以使得M1的栅极接地，保证M1关断；并由于R3和R4进行分压，并M3在分压电压的控制下关断需要一定时间，因此当M2打开时，S1的电压已经下降为0V；这样，可以使得M1的栅极是通过R1向所述驱动电压端P0放电，而不是通过M2放电，因此可以通过调节R1的电阻值来对放电速度进行调整。
如图9所示，本公开如图7所示的钳位模组的至少一实施例在工作时，在驱动电压端P0提供的驱动电压信号的电位由0V上升至18V后，所述驱动电压信号通过R1、R3和R4很快就能够提升M3的栅极的电位，以使得M3打开，M2的栅极与地端GND之间连通，M2关闭，M1的栅极的电位上升为高电压。
在图8和图9中，标号为S2的为M2的栅极的电位。并在图8和图9中，各波形图的横轴为时间t，单位是微秒。
本公开如图7所示的至少一实施例比本公开如图4所示的至少一实施例增加了由R3和R4组成的分压子电路，使电路能动作得更稳定，也使得整体电路的动作时间变得更加可控。
本公开如图7所示的至少一实施例在工作时，当P0提供的驱动电压信号的电位由高电压变成低电压，即输入关闭信号时，M3的栅极的电位也通过R4放电而变为低电压，使得M3关闭。而M3的关闭时间不仅基于M3自身的关闭速度，也由R4和M3的寄生电容决定，所以，调整R4的电阻值可以调整M3的关闭时间；
当P0提供的驱动电压信号的电位由低电压变为高电压时，即输入开启信号时，由于二极管的导通时间较慢，一开始的动作由R1、R3、R4的分压开启M3，所以，M3的开启速度由M3自身的开启速度、R4，以及，M3的寄生电容决定。
本公开至少一实施例所述的钳位方法，应用于上述的钳位方法，所述钳位方法包括：
当驱动电压信号的电位由第一电压下降为第二电压之后，并钳位端的电位下降为第二电压之后，控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与钳位电压端之间连通。
本公开至少一实施例当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端的电位降为第二电压之后，通过钳位电路控制所述钳位端与所述钳位电压端之间连通，以使得所述宽带隙半导体晶体管的栅极的电位为钳位电压，能够保证所述宽带隙半导体晶体管关断，避免宽带隙半导体晶体管误开通的情况发生，降低电路损耗。
在具体实施时，本公开至少一实施例所述的钳位方法还可以包括：
在所述驱动电压信号的电位由第一电压下降之后，所述钳位端的电位下降为所述第二电压之前，所述控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
在本公开至少一实施例所述的钳位方法中，在所述驱动电压信号的电位由第一电压下降之后，所述钳位端的电位下降为第二电压之前，所述控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开，以保证所述钳位端不会通过所述钳位电路放电。
进一步的，本公开至少一实施例所述的钳位方法还可以包括：在所述驱 动电压信号的电位为第一电压时，所述控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
在本公开至少一实施例所述的钳位方法中，在所述驱动电压信号的电位为第一电压时，所述控制电路通过控制所述钳位电路的控制端的电位，使得钳位电路控制所述钳位端与钳位电压端之间断开，以保证所述宽带隙半导体晶体管能够打开
根据一种具体实施方式，所述控制电路包括通断子电路和电压提供子电路；所述钳位方法包括：
所述电压提供子电路向所述钳位电路的控制端提供控制电压信号；
当驱动电压信号的电位由第一电压下降为第二电压之后，所述通断子电路的控制端向所述驱动电压端放电，在所述钳位端的电位下降为第二电压之后，所述通断子电路在其控制端的电位的控制下，控制所述钳位电路的控制端与第三电压端之间断开，所述钳位电路在其控制端接入的控制电压信号的控制下，控制所述钳位端与钳位电压端之间连通。
根据另一种具体实施方式，所述控制电路包括通断子电路、分压子电路和电压提供子电路；所述钳位方法包括：
所述电压提供子电路向所述钳位电路的控制端提供控制电压信号；所述分压子电路对钳位端的电压进行分压，得到分压电压，并将所述分压电压提供至所述通断子电路的控制端；
当驱动电压信号的电位由第一电压下降为第二电压之后，并钳位端的电位下降为第二电压之后，所述通断子电路在其控制端接入的分压电压的控制下，控制所述钳位电路的控制端与第三电压端之间断开，所述钳位电路在其控制端接入的控制电压信号的控制下，控制所述钳位端与钳位电压端之间连通。
本公开至少一实施例所述的开关单元包括宽带隙半导体晶体管和上述的钳位模组；
所述宽带隙半导体晶体管的控制极与所述钳位端电连接。
在具体实施时，本公开至少一实施例所述的开关单元可以应用于桥式电 路。
如图10所示，所述桥式电路可以包括高端子电路和低端子电路；
所述高端子电路包括高端开关晶体管M0、电源E、高端驱动电压源S11、电感L、控制电阻R01和第一控制二极管D01；所述低端子电路包括第一电阻R1、低端驱动电压源S12、第二控制二极管D02、宽带隙半导体晶体管M1和本公开实施例所述的钳位模组；
所述低端驱动电压源120提供的低端驱动电压信号即为所述电压信号端P0提供的驱动电压信号；
所述钳位模组包括钳位晶体管M2和所述控制电路12，所述控制电路12用于控制M2的栅极的电位。
在图10中，标号为C11的为M0的栅源寄生电容，标号为C12的为M0的栅漏寄生电容，标号为C21的为M1的栅源寄生电容，标号为C22的为M0的栅漏寄生电容；
所述宽带隙半导体晶体管M1为所述低端子电路包括的低端开关晶体管。
在图10所示的桥式电路的至少一实施例中，标号为GND的为地端。
在图10所示的桥式电路的至少一实施例中，M1可以为SiC MOSFET或GaN MOSFET。
在图10所示的桥式电路的至少一实施例中，所述低端驱动电压源S12提供的低压驱动电压信号可以由驱动IC提供，所述高端驱动电压源S11提供的高端驱动电压信号也可以由驱动IC提供。
如图10所示的桥式电路的至少一实施例在工作时，当高端驱动电压源110提供18V电压信号至M0的栅极，所述驱动电压端P0提供的驱动电压信号的电位为0V时，通过采用本公开至少一实施例所述的钳位模组，可以控制M1不会由于M1的寄生电容而误导通，能够保证M1的栅极通过M2接地，保证M1关断，以使得桥式电路能够正常工作。
本公开至少一实施例所述的电子设备包括上述的开关单元。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。
附录
如图11所示，本公开实施例提供了一种钳位模组，与钳位端K电连接，所述钳位端K与驱动电压端P0电连接，所述驱动电压端P0用于提供驱动电压信号；所述钳位模组包括钳位电路11和控制电路12；
所述钳位电路11的控制端与所述控制电路12电连接，所述钳位电路11的第一端与钳位端K电连接，所述钳位电路11的第二端与钳位电压端P1电连接；
所述控制电路12用于当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端K的电位下降为第二电压之后，通过控制所述钳位电路11的控制端的电位，以使得所述钳位电路11控制所述钳位端与所述钳位电压端P1之间连通。
本公开实施例所述的钳位模组在工作时，当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端K的电位降为第二电压之后，通过钳位电路11控制所述钳位端K与所述钳位电压端P1之间连通，以使得所述宽带隙半导体晶体管M1的栅极的电位为钳位电压，能够保证所述宽带隙半导体晶体管M1关断，避免宽带隙半导体晶体管M1误开通的情况发生，降低电路损耗。
可选的，所述钳位端直接与所述驱动电压端电连接；或者，所述钳位端通过电阻或电容与所述驱动电压端电连接；或者，所述驱动电压端提供的驱动电压信号为高频脉冲信号，所述钳位端通过电容与所述驱动电压端电连接。
可选的，所述控制电路还用于在所述驱动电压信号的电位由第一电压下降之后，所述钳位端的电位下降为第二电压之前，通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
可选的，所述控制电路还用于在所述驱动电压信号的电位为第一电压时，通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
可选的，所述控制电路包括通断子电路和电压提供子电路；
所述电压提供子电路用于向所述钳位电路的控制端提供控制电压信号；
所述通断子电路的控制端与所述驱动电压端电连接，所述通断子电路的第一端与所述钳位电路的控制端电连接，所述通断子电路的第二端与第三电压端电连接，所述通断子电路用于在其控制端的电位的控制下，控制所述钳位电路的控制端与所述第三电压端之间连通或断开。
可选的，所述通断子电路的控制端直接与所述驱动电压端电连接；或者，所述通断子电路的控制端通过放电电阻与所述驱动电压端电连接；或者，所述通断子电路的控制端通过放电电容与所述驱动电压端电连接。
可选的，所述控制电路包括通断子电路、分压子电路和电压提供子电路；
所述电压提供子电路用于向所述钳位电路的控制端提供控制电压信号；
所述分压子电路用于对所述钳位端的电压进行分压，得到分压电压，并将所述分压电压提供至所述通断子电路的控制端；
所述通断子电路的第一端与所述钳位电路的控制端电连接，所述通断子电路的第二端与第三电压端电连接，所述通断子电路用于在其控制端的电位的控制下，控制所述钳位电路的控制端与所述第三电压端之间连通或断开。
可选的，所述分压子电路包括第一分压电阻和第二分压电阻；
所述第一分压电阻的第一端与所述钳位端电连接，所述第一分压电阻的第二端与所述通断子电路的控制端电连接；
所述第二分压电阻的第一端与所述第一分压电阻的第二端电连接，所述第二分压电阻的第二端与所述第三电压端电连接。
可选的，所述控制电路还包括控制二极管，所述控制二极管的阳极与所述驱动电压端电连接，所述控制二极管的阴极与所述通断子电路的控制端电连接。
可选的，所述通断子电路包括通断控制晶体管；
所述通断控制晶体管的控制极与所述通断子电路的控制端电连接，所述通断控制晶体管的第一极与所述钳位电路的控制端电连接，所述通断控制晶体管的第二极与所述第三电压端电连接。
可选的，所述电压提供子电路包括第二电阻和电压源；
所述电压源通过所述第二电阻与所述钳位电路的控制端电连接，所述电 压源用于提供第四电压信号。
可选的，所述钳位电路包括钳位晶体管；
所述钳位晶体管的控制极与所述控制电路电连接，所述钳位晶体管的第一极与所述钳位端电连接，所述钳位晶体管的第二极与钳位电压端电连接；
所述控制电路用于当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端的电位下降为第二电压之后，通过控制所述钳位晶体管的控制极的电位，以使得所述钳位晶体管导通。
本公开实施例还提供了一种钳位方法，应用于上述的钳位方法，所述钳位方法包括：
当驱动电压信号的电位由第一电压下降为第二电压之后，并钳位端的电位下降为第二电压之后，控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与钳位电压端之间连通。
可选的，本公开至少一实施例所述的钳位方法还包括：
在所述驱动电压信号的电位由第一电压下降之后，所述钳位端的电位下降为所述第二电压之前，所述控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
可选的，本公开至少一实施例还包括：在所述驱动电压信号的电位为第一电压时，所述控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
可选的，所述控制电路包括通断子电路和电压提供子电路；所述钳位方法包括：
所述电压提供子电路向所述钳位电路的控制端提供控制电压信号；
当驱动电压信号的电位由第一电压下降为第二电压之后，所述通断子电路的控制端向所述驱动电压端放电，在所述钳位端的电位下降为第二电压之后，所述通断子电路在其控制端的电位的控制下，控制所述钳位电路的控制端与第三电压端之间断开，所述钳位电路在其控制端接入的控制电压信号的控制下，控制所述钳位端与钳位电压端之间连通。
可选的，所述控制电路包括通断子电路、分压子电路和电压提供子电路；所述钳位方法包括：
所述电压提供子电路向所述钳位电路的控制端提供控制电压信号；所述分压子电路对钳位端的电压进行分压，得到分压电压，并将所述分压电压提供至所述通断子电路的控制端；
当驱动电压信号的电位由第一电压下降为第二电压之后，并钳位端的电位下降为第二电压之后，所述通断子电路在其控制端接入的分压电压的控制下，控制所述钳位电路的控制端与第三电压端之间断开，所述钳位电路在其控制端接入的控制电压信号的控制下，控制所述钳位端与钳位电压端之间连通。
本公开实施例还提供了一种包括宽带隙半导体晶体管和上述的钳位模组；
所述宽带隙半导体晶体管的控制极与所述钳位端电连接。
可选的，所述宽带隙半导体晶体管为碳化硅场效应晶体管或氮化镓场效应晶体管。
可选的，所述控制电路包括通断子电路；所述钳位模组中的钳位电路和/或所述通断子电路包括硅器件。
本公开实施例还提供了一种电子设备，包括上述的开关单元。

Claims (21)

  1. 一种钳位模组，与钳位端电连接，所述钳位端与驱动电压端电连接，所述驱动电压端用于提供驱动电压信号；所述钳位模组包括钳位电路和控制电路；
    所述钳位电路的控制端与所述控制电路电连接，所述钳位电路的第一端与钳位端电连接，所述钳位电路的第二端与钳位电压端电连接；
    所述控制电路用于当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端的电位下降为第二电压之后，通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间连通。
  2. 如权利要求1所述的钳位模组，其中，所述钳位端直接与所述驱动电压端电连接；或者，所述钳位端通过电阻或电容与所述驱动电压端电连接。
  3. 如权利要求1所述的钳位模组，其中，所述控制电路还用于在所述驱动电压信号的电位由第一电压下降之后，所述钳位端的电位下降为第二电压之前，通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
  4. 如权利要求1所述的钳位模组，其中，所述控制电路还用于在所述驱动电压信号的电位为第一电压时，通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
  5. 如权利要求1所述的钳位模组，其中，所述控制电路包括通断子电路和电压提供子电路；
    所述电压提供子电路用于向所述钳位电路的控制端提供控制电压信号；
    所述通断子电路的控制端与所述驱动电压端电连接，所述通断子电路的第一端与所述钳位电路的控制端电连接，所述通断子电路的第二端与第三电压端电连接，所述通断子电路用于在其控制端的电位的控制下，控制所述钳位电路的控制端与所述第三电压端之间连通或断开。
  6. 如权利要求5所述的钳位模组，其中，所述通断子电路的控制端直接与所述驱动电压端电连接；或者，所述通断子电路的控制端通过放电电阻与 所述驱动电压端电连接；或者，所述通断子电路的控制端通过放电电容与所述驱动电压端电连接。
  7. 如权利要求1所述的钳位模组，其中，所述控制电路包括通断子电路、分压子电路和电压提供子电路；
    所述电压提供子电路用于向所述钳位电路的控制端提供控制电压信号；
    所述分压子电路用于对所述钳位端的电压进行分压，得到分压电压，并将所述分压电压提供至所述通断子电路的控制端；
    所述通断子电路的第一端与所述钳位电路的控制端电连接，所述通断子电路的第二端与第三电压端电连接，所述通断子电路用于在其控制端的电位的控制下，控制所述钳位电路的控制端与所述第三电压端之间连通或断开。
  8. 如权利要求7所述的钳位模组，其中，所述分压子电路包括第一分压电阻和第二分压电阻；
    所述第一分压电阻的第一端与所述钳位端电连接，所述第一分压电阻的第二端与所述通断子电路的控制端电连接；
    所述第二分压电阻的第一端与所述第一分压电阻的第二端电连接，所述第二分压电阻的第二端与所述第三电压端电连接。
  9. 如权利要求5至8中任一权利要求所述的钳位模组，其中，所述控制电路还包括控制二极管，所述控制二极管的阳极与所述驱动电压端电连接，所述控制二极管的阴极与所述通断子电路的控制端电连接。
  10. 如权利要求5至8中任一权利要求所述的钳位模组，其中，所述通断子电路包括通断控制晶体管；
    所述通断控制晶体管的控制极与所述通断子电路的控制端电连接，所述通断控制晶体管的第一极与所述钳位电路的控制端电连接，所述通断控制晶体管的第二极与所述第三电压端电连接。
  11. 如权利要求5至8中任一权利要求所述的钳位模组，其中，所述电压提供子电路包括第二电阻和电压源；
    所述电压源通过所述第二电阻与所述钳位电路的控制端电连接，所述电压源用于提供第四电压信号。
  12. 如权利要求1至5中任一权利要求所述的钳位模组，其中，所述钳 位电路包括钳位晶体管；
    所述钳位晶体管的控制极与所述控制电路电连接，所述钳位晶体管的第一极与所述钳位端电连接，所述钳位晶体管的第二极与钳位电压端电连接；
    所述控制电路用于当所述驱动电压信号的电位由第一电压下降为第二电压之后，并所述钳位端的电位下降为第二电压之后，通过控制所述钳位晶体管的控制极的电位，以使得所述钳位晶体管导通。
  13. 一种钳位方法，应用于如权利要求1至12中任一权利要求所述的钳位方法，所述钳位方法包括：
    当驱动电压信号的电位由第一电压下降为第二电压之后，并钳位端的电位下降为第二电压之后，控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与钳位电压端之间连通。
  14. 如权利要求13所述的钳位方法，其中，还包括：
    在所述驱动电压信号的电位由第一电压下降之后，所述钳位端的电位下降为所述第二电压之前，所述控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
  15. 如权利要求13所述的钳位方法，其中，还包括：在所述驱动电压信号的电位为第一电压时，所述控制电路通过控制所述钳位电路的控制端的电位，以使得所述钳位电路控制所述钳位端与所述钳位电压端之间断开。
  16. 如权利要求13所述的钳位方法，其中，所述控制电路包括通断子电路和电压提供子电路；所述钳位方法包括：
    所述电压提供子电路向所述钳位电路的控制端提供控制电压信号；
    当驱动电压信号的电位由第一电压下降为第二电压之后，所述通断子电路的控制端向所述驱动电压端放电，在所述钳位端的电位下降为第二电压之后，所述通断子电路在其控制端的电位的控制下，控制所述钳位电路的控制端与第三电压端之间断开，所述钳位电路在其控制端接入的控制电压信号的控制下，控制所述钳位端与钳位电压端之间连通。
  17. 如权利要求13所述的钳位方法，其中，所述控制电路包括通断子电路、分压子电路和电压提供子电路；所述钳位方法包括：
    所述电压提供子电路向所述钳位电路的控制端提供控制电压信号；所述 分压子电路对钳位端的电压进行分压，得到分压电压，并将所述分压电压提供至所述通断子电路的控制端；
    当驱动电压信号的电位由第一电压下降为第二电压之后，并钳位端的电位下降为第二电压之后，所述通断子电路在其控制端接入的分压电压的控制下，控制所述钳位电路的控制端与第三电压端之间断开，所述钳位电路在其控制端接入的控制电压信号的控制下，控制所述钳位端与钳位电压端之间连通。
  18. 一种开关单元，包括宽带隙半导体晶体管和如权利要求1至12中任一权利要求所述的钳位模组；
    所述宽带隙半导体晶体管的控制极与所述钳位端电连接。
  19. 如权利要求18所述的开关单元，其中，所述宽带隙半导体晶体管为碳化硅场效应晶体管或氮化镓场效应晶体管。
  20. 如权利要求18所述的开关单元，其中，所述控制电路包括通断子电路；所述钳位模组中的钳位电路和/或所述通断子电路包括硅器件。
  21. 一种电子设备，包括如权利要求18至20中任一权利要求所述的开关单元。
PCT/CN2021/085950 2021-04-08 2021-04-08 钳位模组、钳位方法、开关单元和电子设备 WO2022213323A1 (zh)

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CN212457333U (zh) * 2020-05-25 2021-02-02 珠海拓芯科技有限公司 一种钳位保护电路、驱动系统以及空调器

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