WO2022206078A1 - 驱动电路的控制开关、阵列基板和显示面板 - Google Patents

驱动电路的控制开关、阵列基板和显示面板 Download PDF

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Publication number
WO2022206078A1
WO2022206078A1 PCT/CN2021/143542 CN2021143542W WO2022206078A1 WO 2022206078 A1 WO2022206078 A1 WO 2022206078A1 CN 2021143542 W CN2021143542 W CN 2021143542W WO 2022206078 A1 WO2022206078 A1 WO 2022206078A1
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Prior art keywords
source
drain
branch
branches
thin film
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PCT/CN2021/143542
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English (en)
French (fr)
Inventor
何政航
康报虹
Original Assignee
绵阳惠科光电科技有限公司
惠科股份有限公司
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Application filed by 绵阳惠科光电科技有限公司, 惠科股份有限公司 filed Critical 绵阳惠科光电科技有限公司
Priority to JP2022548552A priority Critical patent/JP7372476B2/ja
Priority to KR1020227026702A priority patent/KR20220137011A/ko
Priority to EP21931918.3A priority patent/EP4113204A4/en
Publication of WO2022206078A1 publication Critical patent/WO2022206078A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136268—Switch defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present application relates to the field of display technology, and in particular, to a control switch of a driving circuit, an array substrate and a display panel.
  • display technology is widely used in the display of televisions, mobile phones and public information, and the display panels used for displaying pictures are also various, and can display colorful pictures. More and more display panels, such as Thin Film Transistor-Liquid Crystal Display (TFT-LCD), Organic Light Emitting Diode (OLED), etc., all need to use the array substrate row.
  • Drive Gate Driver on Array, GOA for short
  • GOA Gate Driver on Array
  • the source, drain and source leads in the thin film transistor are placed in the same layer and formed by etching at the same time, but the problem of uneven etching is prone to occur during the etching process; and with the integration of the GOA circuit
  • the present application provides a control switch of a driving circuit, an array substrate and a display panel, which can prevent the source and drain from being short-circuited due to uneven etching of the driving circuit.
  • the present application provides a control switch of a drive circuit
  • the control switch includes a thin film transistor
  • the drive circuit further includes a source lead connected to the thin film transistor
  • the thin film transistor includes a source, a drain electrode and a gate electrode
  • the source electrode includes at least two source electrode branches arranged in parallel, and a source electrode trunk connecting each of the source electrode branches, and the source electrode branch directly connected with the source electrode lead is a first source branch, the first source branch is connected to the end of the source trunk
  • the drain and the source are arranged in the same layer, including at least one drain branch, and each of the drains is connected a drain trunk of a pole branch, the drain branch and the source branch are arranged in parallel and alternately to form a channel, and the drain branch arranged adjacent to the first source branch is a first drain branch
  • the gate electrode is arranged corresponding to the source electrode and the drain electrode; wherein, the extension line of the source electrode lead is located between the first drain electrode branch and the source electrode trunk.
  • the present application also discloses an array substrate, the array substrate includes a drive circuit, a source lead and a scan line driven by the drive circuit, the control switch of the drive circuit includes a thin film transistor, and the thin film transistor includes a source electrode , a drain, and a gate, the source comprising at least two source branches arranged in parallel, and a source trunk connecting each of the source branches and the source branch directly connected to the source lead is a first source branch, the first source branch is connected to the end of the source trunk; the drain and the source are arranged in the same layer, including at least one drain branch, and connecting each of the a drain trunk of a drain branch, the drain branch and the source branch are arranged in parallel and alternately to form a channel, and the drain branch arranged adjacent to the first source branch is a first drain a pole branch; the gate is arranged corresponding to the source and the drain; wherein, the extension line of the source lead is located between the first drain branch and the source trunk.
  • the present application also discloses a display panel, the display panel includes an array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, the array substrate
  • the substrate includes a drive circuit, a source lead and a scan line driven by the drive circuit
  • the control switch of the drive circuit includes a thin film transistor
  • the thin film transistor includes a source electrode, a drain electrode and a gate electrode
  • the source electrode includes at least Two side-by-side source branches, and a source trunk connecting each of the source branches, and the source branch directly connected to the source lead is a first source branch, the first source The branch is connected to the end of the source trunk;
  • the drain and the source are arranged in the same layer, including at least one drain branch, and a drain trunk connecting each of the drain branches, the drain branch are arranged in parallel and alternately with the source branches to form a channel, and the drain branch arranged adjacent to the first source branch is the first drain branch;
  • the present application improves the thin film transistor and the source lead in the driving circuit, so that the extension line of the source lead is located between the first drain branch and the source trunk, and does not overlap with the drain branch;
  • the film layer where the drain and source leads are located is etched, even if there is a problem of uneven etching, which causes the top of the source lead to protrude from the first source branch, its protruding position will only extend to the first drain branch. and the source stem, without intersecting with the first drain branch, thus not causing a short circuit between the source and the drain.
  • 1 is a schematic plan view of an array substrate
  • Fig. 2 is a partial enlarged view of M position in Fig. 1;
  • FIG. 3 is a partial schematic diagram of a gate driving unit
  • FIG. 4 is a partial schematic diagram of another gate driving unit
  • Fig. 5 is a schematic diagram based on Fig. 3 in an ideal state
  • Fig. 6 is a schematic diagram based on Fig. 4 in an ideal state
  • FIG. 7 is a partial schematic diagram of a driving circuit including a first type of thin film transistor provided by an embodiment of the present application.
  • FIG. 8 is a partial schematic diagram of a driving circuit including a second type of thin film transistor provided by an embodiment of the present application.
  • FIG. 9 is a partial schematic diagram of a drive circuit including three types of thin film transistors provided by an embodiment of the present application.
  • FIG. 10 is a partial schematic diagram of a driving circuit including a thin film transistor of the first type provided by another embodiment of the present application.
  • FIG. 11 is a partial schematic diagram of a driving circuit including a second type of thin film transistor provided by another embodiment of the present application.
  • FIG. 12 is a schematic diagram of a display panel according to an embodiment of the present application.
  • first and second are only used for description purposes, and cannot be understood as indicating relative importance, or implicitly indicating the number of indicated technical features.
  • features defined as “first” and “second” may expressly or implicitly include one or more of the features; “plurality” means two or more.
  • the term “comprising” and any variations thereof mean non-exclusive inclusion, possibly the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection , it can also be an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or an internal connection between two components.
  • installed should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection , it can also be an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or an internal connection between two components.
  • FIG. 1 and FIG. 2 it is a schematic plan view of an array substrate.
  • Scan lines 300 are arranged in the display area of the array substrate 100
  • driving circuits 200 are arranged in the non-display area of the array substrate 100 .
  • the array substrate may be an array substrate.
  • a row driving circuit the driving circuit 200 includes a frame start signal line 205 (STV), a gate voltage control line 206 (VGL), a clock signal line 207 (CKV) and a plurality of gate driving units 270, the input of the gate driving unit 270
  • the terminal is connected to STV, VGL and CKV, the output terminal is connected to the scan line 300, and drives the scan line 300; wherein, the gate voltage control line 206 is connected to a thin film transistor 220 in the gate driving unit 270 through the source lead The thin film transistor 220 is charged.
  • the gate driving unit 270 includes a first thin film transistor 201 , a second thin film transistor 202 , a third thin film transistor 203 and a fourth thin film transistor 204 , and the source 230 of the first thin film transistor 201 passes through two
  • the source lead 210 is connected to the gate voltage control line 206 and the source 230 of the second thin film transistor 202
  • the drain 240 of the first thin film transistor 201 is respectively connected to the source of the third thin film transistor 203
  • the electrode 230 and the gate 260 of the fourth thin film transistor 204 are connected, the gate 260 of the first thin film transistor 201 is connected to the gate 260 of the second thin film transistor 202; the drain 240 of the second thin film transistor 202 connected to the source electrode 230 of the fourth thin film transistor 204; the gate electrode 260 of the second thin film transistor 202 is connected to the gate electrode 260 of the fourth thin film transistor 204; the drain electrode 240 of the third thin film transistor 203
  • the gate drive unit 270 shown in FIG. 2 there are four interconnected thin film transistors and other wirings. It can be seen in the figure that there are three blank areas, namely area A, area B and area C; Between the region B and the region C, the two thin film transistors 220 are connected through the source lead 210. Before the metal layer is etched into the source 230, the drain 240 and other metal line patterns, the source 230, the drain 240 and the The etching barrier layer is formed on the other metal line patterns, and then the barrier layer pattern is formed by the developer solution. Since the area of the region B and the region C is large, more developer solution needs to be consumed, so that the development energy consumed by the region D and the region E changes.
  • the barrier layers corresponding to the regions D and E are not easily etched completely, and finally, the problem of uneven etching occurs when the metal layer pattern is etched, resulting in a short circuit between the source electrodes 230 and the drain electrodes 240 corresponding to the regions D and E.
  • FIGS. 3 and 4 are partial schematic diagrams of two exemplary GOAs
  • the source leads 210 in FIGS. 3 and 4 will extend to the thin film transistors 220
  • the channel of the source 230 is even connected to the drain 240, resulting in a short circuit between the source 230 and the drain 240.
  • Figures 5 and 6 are respectively the schematic diagrams based on Figures 3 and 4 under ideal conditions, but this needs to consume a lot of developer to ensure that the barrier layers corresponding to the regions D and E are completely etched, so that subsequent etching is performed.
  • the source lead 210 does not protrude from the source 230 and does not extend into the channel of the source 230 .
  • the present application provides a control switch of the driving circuit 200 that does not cause the source electrode 230 and the drain electrode 240 to be short-circuited even when the etching is uneven.
  • the control switch includes a thin film transistor 220, the driving circuit 200 further includes a source lead 210 connected to the thin film transistor 220, the thin film transistor 220 includes a source electrode 230, a drain electrode 240 and a gate electrode 260, and the source electrode 230 includes At least two source branches 231 arranged in parallel, and a source trunk 234 connecting each source branch 231, and the source branch 231 directly connected to the source lead 210 is the first source branch 232, so
  • the first source branch 232 is connected to the end of the source trunk 234; the drain 240 and the source 230 are arranged in the same layer, and include at least one drain branch 241, and a drain branch 241 connected to each of the drain branches 241.
  • the drain trunk 244, the drain branches 241 and the source branches 231 are arranged in parallel and alternately to form a channel, and the drain branch 241 arranged adjacent to the first source branch 232 is the first Drain branch 242 ; the gate electrode 260 is arranged corresponding to the source electrode 230 and the drain electrode 240 ; wherein, the extension line of the source electrode lead 210 is located between the first drain electrode branch 242 and the source electrode trunk 234 .
  • the drain trunk 244 is a part of the drain branch 241 and is connected to other structures in the driving circuit 200 .
  • the gate electrode 260 may be located under the source electrode 230 and the drain electrode 240 to form a bottom gate structure in the thin film transistor 220 , and the gate electrode 260 may also be located above the source electrode 230 and the drain electrode 240 to form a top gate structure in the thin film transistor 220 gate structure.
  • the source lead 210 is usually vertically connected to the first source branch 232. Due to the higher and higher requirements for the integration of the driving circuit 200, the channel spacing between the source 230 and the drain 240 becomes smaller and smaller. , when the source electrode 230, the drain electrode 240 and the source electrode branch 231 are etched unevenly due to various reasons, for example in FIG. With more liquid, the etching liquid in the area D and the area E is insufficient, resulting in the problem of uneven etching of the metal pattern in the area D and the area E. At this time, the end of the source lead 210 is not etched cleanly, resulting in the end of the source lead 210 protruding from the first source branch 232.
  • the source lead 210 is connected to the drain 240 so that the source 230 and the drain 240 are short-circuited. Moreover, in the current design, since the width dimension of the source lead 210 is generally larger to increase the charging effect on the thin film transistor 220, the source lead 210 is more susceptible to the influence of uneven etching, and the first source branch 232 The protruding area in the middle is larger, which increases the risk of short circuit between the source electrode 230 and the drain electrode 240 .
  • the present application improves the thin film transistor 220 and the source lead 210 in the driving circuit 200, so that the extension line of the source lead 210 is located between the first drain branch 242 and the source trunk 234, and is not connected with the drain branch 241 overlap; when the film layer where the source electrode 230, the drain electrode 240 and the source electrode lead 210 are located is etched, even if there is a problem of uneven etching, the top of the source electrode lead 210 protrudes from the first source branch 232, which The protruding position also only extends between the first drain branch 242 and the source trunk 234 , and does not intersect the first drain branch 242 , so that the source 230 and the drain 240 are not short-circuited.
  • the channel widths of the source electrode 230 and the drain electrode 240 and the width of the source lead 210 are not limited. Therefore, the driving circuit 200 can be made to meet the advantages of high integration, high charging effect, and resistance to short circuit at the same time. Competitiveness among products of the same type.
  • one thin film transistor 220 is connected to two source leads 210 at the same time. At this time, there are two first source branches 232 and at least one first drain branch 242 . In FIGS. 10-11 , one thin film transistor 220 is only connected to one source lead 210. At this time, there is only one first source branch 232, at least one second source branch 233, and only one first drain branch 242. . These two connection situations can be applied to one drive circuit 200 or to different drive circuits 200 , which are specifically designed according to usage conditions.
  • the source 230 has only two first source branches 232 connected to the source leads 210 in a one-to-one correspondence, and the source trunk 234 connecting the two first source branches 232; the drain 240 has only one The first drain branch 242, the first drain branch 242 is located between the two first source branches 232; the two first source branches 232 are both between the first drain branch 242 and the source trunk 234, while There is no overlap with the first drain branch 242 .
  • the thin film transistor 220 adopts the simplest dual-channel structure, the shape of the source electrode 230 is similar to a U-shape, and two channels are formed between the first drain branch 242 and the two first source branches 232 . Since the two source leads 210 are compared with the same first drain branch 242 as long as they are not in contact with the first drain branch 242, the design of the etching pattern is simpler.
  • the source 230 includes two first source branches 232 , one second source branch 233 and one source trunk 234 , and the two first source branches 232 are respectively connected with the source trunk 234 .
  • the two ends are connected and are respectively connected with the two source leads 210 in a one-to-one correspondence.
  • the second source branch 233 is arranged in parallel between the two first source branches 232 and is connected to the middle of the source trunk 234 connected;
  • the drain 240 includes two first drain branches 242 and a drain trunk 244, and the two first drain branches 242 are respectively connected to both ends of the drain trunk 244; each drain branch 241 is located in between two adjacent first source branches 232 and second source branches 233 .
  • the shape of the source electrode 230 is similar to the W-shape
  • the shape of the drain electrode 240 is similar to the U-shape
  • each source lead 210 can be connected between the first source branch 232 and the adjacent second source branch 233 Therefore, when the problem of uneven etching is serious, there is enough fault tolerance space to prevent the source lead 210 from extending too long to cause the source 230 and the drain 240 short circuit.
  • the source 230 includes two first source branches 232 , two second source branches 233 and a source trunk 234 , and the two first source branches 232 are respectively connected to the source trunk 234 .
  • the two ends are connected to the two source leads 210 in a one-to-one correspondence, and the two second source branches 233 are arranged in parallel between the two first source branches 232 and are connected to the source trunk 234
  • the drain 240 includes two first drain branches 242, a second drain branch 243 and a drain trunk 244, the two first drain branches 242 are respectively connected to both ends of the drain trunk 244, and the second drain
  • the pole branches 243 are arranged in parallel between the two first drain branches 242 and are connected to the middle of the drain trunk 244; each of the first drain branches 242 is located in the adjacent two first source branches 232 and Between the second source branches 233 , the second drain branches 243 are located between two adjacent second source branches 233 .
  • the shape of the source electrode 230 is similar to three parallel U-shaped structures, and the shape of the drain electrode 240 is similar to the W-shaped structure.
  • the electrical performance of the thin film transistor 220 in FIG. 9 is better. OK; of course, the present application can continue to increase the number of the second source branch 233 and the second drain branch 243 on the basis of FIG. 9 , so that the electrical performance of the thin film transistor 220 is further improved.
  • the source electrode 230 has only a first source branch 232 connected to the source lead 210 , a second source branch 233 not connected to the source lead 210 , and the first source branch 232 and The source stem 234 of the second source branch 233;
  • the drain 240 has only one first drain branch 242, the first drain branch 242 is arranged in parallel between the first source branch 232 and the second source branch 233, and
  • the first source branch 232 and the second source branch 233 respectively form two channels;
  • the extension line of the source lead 210 is located between the first drain branch 242 and the source trunk 234, and is not connected to all the channels.
  • the first drain branches 242 overlap.
  • the thin film transistor 220 is also the simplest dual-channel type, but the difference from FIG. 7 is that since the thin film transistor in FIG. 10 is only connected to one source lead 210, the source lead has a larger extension space, and it is not easy to short-circuit with other structures.
  • the drain 240 includes a first source branch 232 connected to the source lead 210 , two second source branches 233 not connected to the source lead 210 , and connected to the first source
  • the drain 240 includes a first drain branch 242, a second drain branch 243 and a drain trunk 244, the first drain branch 242 and the second drain branch 243 are respectively connected with the drain Both ends of the trunk 244 are connected;
  • the first drain branch 242 is arranged in parallel between the adjacent first source branch 232 and the second source branch 233, and the second drain branch 243 is arranged in parallel between the adjacent two between the second source branches 233 .
  • the number of the second source branch 233 and the second drain branch 243 is arranged in parallel between the adjacent two between the second source branches 233
  • the distance between the first drain branch 242 and the source trunk 234 can be increased by shortening the length of the first drain branch 242, so that the extension line of the source lead 210 can achieve the first drain branch 242 and all the between the source trunks 234 and do not overlap with the first drain branch 242; the width of the source lead 210 can also be reduced, so that the extension line of the source lead 210 can achieve the first drain branch 242 and the first drain branch 242.
  • the extension line of the source lead 210 does not overlap the first drain branch 242; the width of the source trunk 234 can also be reduced so that the extension line of the source lead 210 When it is achieved between the first drain branch 242 and the source trunk 234, the extension line of the source lead 210 does not overlap with the first drain branch 242; two or more of the above methods can also be used. to achieve the same technical effect.
  • the distance between the first drain branch 242 and the source trunk 234 is increased by shortening the length of the first drain branch 242 ; this method will not affect the charging effect of the source lead 210 , It will not affect the electrical uniform effect of the source electrode 230 and the drain electrode 240, and compared with other methods, the length of the drain electrode 240 can be arbitrarily controlled in this method.
  • the distance between the first drain branch 242 and the source stem 234 is relatively large. In FIG. 9 and FIG. 11 , the length of the second drain branch 243 does not need to be changed.
  • the distance between the second drain branch 243 and the source stem 234 is smaller than that of the first drain
  • the distance between the branch 242 and the source stem 234; such a design reduces the length of the first drain branch 242, but the channel spacing between the source 230 and the drain 240 is not affected by The larger the influence, the smaller the influence on the thin film transistor 220.
  • the distance by which the first drain branch 242 is shortened can be equal to the width of the source lead 240 , that is, the difference between the lengths of the second drain branch 243 and the first drain branch 242 , and The widths of the source leads 210 are equal; wherein, the length direction of the first drain branch 242 and the second drain branch 243 is the extension direction of the first drain branch 242 and the second drain branch 243 .
  • Such a close arrangement makes full use of the blank area between the first drain branch 242 and the source trunk 234, which is beneficial to reduce the volume of the thin film transistor 220, and the second drain branch 243 and the top of the source lead 210 (close to the source The side of the pole trunk) is flush, which is convenient for the alignment design when making the pattern, thereby reducing the etching difficulty of the etching barrier layer pattern, and improving the etching of the metal layer where the source electrode 230, the drain electrode 240 and the source electrode lead 210 are located. uniform effect.
  • the two source leads 210 can be arranged on the same straight line, so that the shortening distance of the two first drain branches 242 can be the same, which is convenient to improve the thin film
  • the uniform effect of the source 230 and the drain 240 at both ends of the transistor 220 can also maximize the lengths of the two first drain branches 242 at the same time, so that one first drain branch 242 is long and one first drain branch is long. 242 is short, reducing the electrical performance of the thin film transistor 220.
  • the two source leads 210 may not be arranged on the same straight line, so as to prevent the two source leads 210 from being short-circuited, resulting in the risk of a short circuit.
  • all the source branches 231 and the drain branches 241 are strip-shaped structures, which can be rectangular, elliptical or other shapes.
  • the extension direction of the pole branch 241 and the extension direction of the drain trunk 244 are perpendicular to each other; of course, the angle between the extension direction of the source branch 231 and the extension direction of the source trunk 234 can form an acute angle, while the extension of the drain branch 241
  • the included angle between the direction and the extending direction of the drain stem 244 is also an acute angle.
  • the source lead 210 and the first source branch 232 can be arranged vertically or obliquely.
  • the widths of the source branch 231 , the source trunk 234 , the drain branch 241 and the drain trunk 244 are all equal, and the channel widths between the adjacent second source branches 233 and the drain branches 241 are also equal, thereby increasing the Conductivity of the thin film transistor 220 .
  • the present application only needs to reduce the length of the first drain branch 242 to overcome the short circuit of the source electrode 230 and the drain electrode 240 caused by uneven etching, the source electrode branch 231 and the drain branch 241 can be further reduced
  • the channel width between the second drain branches 243 and the source trunk 234 is reduced, and the distance between the source trunk 234 and the drain trunk 244 is reduced, so as to further improve the integration degree in the driving circuit 200,
  • the occupied area of the driving circuit 200 in the display panel is reduced, and the narrow frame of the display panel is further reduced.
  • FIG. 12 which is a schematic diagram of a display panel, as another embodiment of the present application, a display panel 400 is also disclosed.
  • the display panel 400 includes the array substrate 100 shown in FIG. A color filter substrate 500 disposed opposite the array substrate 100, and a liquid crystal layer 600 disposed between the array substrate 100 and the color filter substrate 500; the non-display area of the array substrate 100 includes the above-mentioned driving circuit 200.
  • the thin film transistor 220 in the present application is not only applicable to the row driving circuit of the array substrate in the non-display area, but also applicable to the active switch in the display area of the array substrate 100 .
  • the technical solution of the present application can be widely used in various display panels, such as TN (Twisted Nematic, twisted nematic) display panels, IPS (In-Plane Switching, in-plane switching) display panels, VA (Vertical Alignment, vertical alignment type) display panels ) display panel, MVA (Multi-Domain Vertical Alignment, multi-quadrant vertical alignment type) display panel, of course, other types of display panels are also applicable, and the above solutions can be applied.
  • TN Transmission Nematic, twisted nematic
  • IPS In-Plane Switching, in-plane switching
  • VA Very Alignment, vertical alignment type
  • MVA Multi-Domain Vertical Alignment, multi-quadrant vertical alignment type
  • inventive concept of the present application can form a large number of embodiments, but the length of the application documents is limited and cannot be listed one by one.
  • the technical features can be arbitrarily combined to form a new embodiment, and the original technical effect will be enhanced after each embodiment or technical feature is combined.

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Abstract

一种驱动电路（200）的控制开关、阵列基板（100）和显示面板（400），其中，控制开关包括薄膜晶体管（220），在薄膜晶体管（220）中，源极（230）包括至少两个源极分支（231），漏极（240）包括至少一个漏极分支（241），与源极引线（210）直接连接的源极分支（231）为第一源极分支（232）；与第一源极分支（232）相邻的漏极分支（241）为第一漏极分支（242），源极引线（210）的延长线位于第一漏极分支（241）和源极主干（234）之间。

Description

驱动电路的控制开关、阵列基板和显示面板
本申请要求于2021年3月29日提交中国专利局，申请号为CN2021103322238，申请名称为“一种驱动电路的控制开关、阵列基板和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种驱动电路的控制开关、阵列基板和显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
目前，显示技术被广泛应用于电视、手机以及公共信息的显示，用于显示画面的显示面板也多种多样，而且可以显示丰富多彩的画面。越来越多的显示面板，例如薄膜晶体管液晶显示面板(Thin Film Transistor-Liquid Crystal Display，简称TFT-LCD)，有机发光显示面板(Organic Light Emitting Diode，简称OLED)等，都需要利用阵列基板行驱动(Gate Driver on Array，简称GOA)技术，将阵列基板行驱动电路集成在显示面板中的阵列基板上，形成对显示面板的扫描驱动，从而可以从材料成本和制作工艺两方面降低产品成本。
通常在制作GOA电路时，将薄膜晶体管中的源极、漏极与源极引线同层设置且同时蚀刻形成，但是在进行蚀刻工艺时容易出现蚀刻不均匀的问题；而且随着GOA电路的集成度越来越高，使得源极和漏极之间的沟道间距越来越小，因此当蚀刻不均匀时，容易导致源极引线同时与源极、漏极连接，使得源极和漏极发生短路。
发明内容
本申请提供一种驱动电路的控制开关、阵列基板和显示面板，防止驱动电路在蚀刻不均匀时导致源极和漏极短路。
为实现上述目的，本申请提供了一种驱动电路的控制开关，所述控制开关包括薄膜晶体管，所述驱动电路还包括与所述薄膜晶体管连接的源极引线，所述薄膜晶体管包括源极、漏极和栅极，所述源极包括至少两个并列设置的源极分支，以及连接各个所述源极分支的源极主干，且与所述源极引线直接连接的所述源极分支为第一源极分支，所述第一源极分支与所述源极主干的端部连接；所述漏极与所述源极同层设置，包括至少一个漏极分支，以及连接各所述漏极分支的漏极主干，所述漏极分支与所述源极分支并列且交替设置以形成沟道，且 与所述第一源极分支相邻设置的所述漏极分支为第一漏极分支；所述栅极与所述源极、漏极对应设置；其中，所述源极引线的延长线位于所述第一漏极分支和所述源极主干之间。
本申请还公开了一种阵列基板，所述阵列基板包括驱动电路、源极引线和被所述驱动电路驱动的扫描线，所述驱动电路的控制开关包括薄膜晶体管，所述薄膜晶体管包括源极、漏极和栅极，所述源极包括至少两个并列设置的源极分支，以及连接各个所述源极分支的源极主干，且与所述源极引线直接连接的所述源极分支为第一源极分支，所述第一源极分支与所述源极主干的端部连接；所述漏极与所述源极同层设置，包括至少一个漏极分支，以及连接各个所述漏极分支的漏极主干，所述漏极分支与所述源极分支并列且交替设置以形成沟道，且与所述第一源极分支相邻设置的所述漏极分支为第一漏极分支；所述栅极与所述源极、漏极对应设置；其中，所述源极引线的延长线位于所述第一漏极分支和所述源极主干之间。
本申请还公开了一种显示面板，所述显示面板包括阵列基板，与所述阵列基板相对设置的彩膜基板，以及设置在所述阵列基板和彩膜基板之间的液晶层，所述阵列基板包括驱动电路、源极引线和被所述驱动电路驱动的扫描线，所述驱动电路的控制开关包括薄膜晶体管，所述薄膜晶体管包括源极、漏极和栅极，所述源极包括至少两个并列设置的源极分支，以及连接各个所述源极分支的源极主干，且与所述源极引线直接连接的所述源极分支为第一源极分支，所述第一源极分支与所述源极主干的端部连接；所述漏极与所述源极同层设置，包括至少一个漏极分支，以及连接各个所述漏极分支的漏极主干，所述漏极分支与所述源极分支并列且交替设置以形成沟道，且与所述第一源极分支相邻设置的所述漏极分支为第一漏极分支；所述栅极与所述源极、漏极对应设置；其中，所述源极引线的延长线位于所述第一漏极分支和所述源极主干之间。
本申请通过对驱动电路中薄膜晶体管和源极引线进行改进，使得源极引线的延长线位于第一漏极分支和所述源极主干之间，且不与漏极分支重叠；当对源极、漏极和源极引线所在的膜层进行蚀刻时，即使存在蚀刻不均匀的问题，导致源极引线的顶部突出于第一源极分支，其突出位置也只会延伸到第一漏极分支和所述源极主干之间，不会与第一漏极分支相交，因此不会导致源极和漏极短路。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是一种阵列基板的平面示意图；
图2是图1中M位置的局部放大图；
图3是一种栅极驱动单元局部示意图；
图4是另一种栅极驱动单元局部示意图；
图5是基于图3在理想状态下的示意图；
图6是基于图4在理想状态下的示意图；
图7是本申请一实施例提供的含有第一种类型薄膜晶体管的驱动电路的局部示意图；
图8是本申请一实施例提供的含有第二种类型薄膜晶体管的驱动电路的局部示意图；
图9是本申请一实施例提供的含有三种类型薄膜晶体管的驱动电路的局部示意图；
图10是本申请另一实施例提供的含有第一种类型薄膜晶体管驱动电路的局部示意图；
图11是本申请另一实施例提供的含有第二种类型薄膜晶体管驱动电路的局部示意图；
图12是本申请一实施例提供的一种显示面板的示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本申请作详细说明，需要说明的是,在不相冲突的前提下,以下描述的各实施例之间或各技术特征之间可以任意组合形成新的实施例。
如图1和图2所示，是一种阵列基板的平面示意图，在阵列基板100的显示区设有扫描 线300，在阵列基板100的非显示区设有驱动电路200，具体可为阵列基板行驱动电路，驱动电路200含有帧起始信号线205(STV)、栅电压控制线206(VGL)、时钟信号线207(CKV)和多个栅极驱动单元270，栅极驱动单元270的输入端与STV、VGL和CKV连接，输出端与扫描线300连接，对扫描线300驱动；其中，栅电压控制线206通过源极引线210与栅极驱动单元270中的一个薄膜晶体管220连接，对薄膜晶体管220充电。
具体的，所述栅极驱动单元270包括第一薄膜晶体管201、第二薄膜晶体管202、第三薄膜晶体管203和第四薄膜晶体管204，所述第一薄膜晶体管201的源极230分别通过两条所述源极引线210与所述栅电压控制线206、所述第二薄膜晶体管202的源极230连接，所述第一薄膜晶体管201的漏极240分别与所述第三薄膜晶体管203的源极230、第四薄膜晶体管204的栅极260连通，所述第一薄膜晶体管201的栅极260与所述第二薄膜晶体管202的栅极260连接；所述第二薄膜晶体管202的漏极240与所述第四薄膜晶体管204的源极230连接，所述第二薄膜晶体管202的栅极260与所述第四薄膜晶体管204的栅极260连接；所述第三薄膜晶体管203的漏极240与所述帧起始信号线205连通，所述第四薄膜晶体管204的漏极240与所述时钟信号线207连通。
在图2中示出的栅极驱动单元270中，含有四个相互连通的薄膜晶体管，以及其它的走线，图中可以看出有三个空白区域，即区域A、区域B和区域C；在区域B和区域C之间，两个薄膜晶体管220通过源极引线210连通，在将金属层蚀刻成源极230、漏极240和其它金属线图案前，需要在源极230、漏极240和其它金属线图案上形成蚀刻阻挡层，然后利用显影液形成阻挡层图案，由于区域B和区域C的面积较大，需要消耗较多的显影液，使得区域D和区域E吃到的显影能量变少，进而使区域D和区域E对应的阻挡层不易蚀刻完全，最后在蚀刻金属层图案时出现蚀刻不均匀的问题，导致区域D和区域E对应的源极230和漏极240发生短路。
如图3和图4所示，是两种示例性的GOA局部示意图，当区域D和区域E对应的金属图案未蚀刻均匀时，图3和图4中源极引线210会延伸到薄膜晶体管220的源极230沟道中，甚至是与漏极240连通，导致源极230和漏极240短路。
图5和图6分别是当理想状态下，基于图3和图4的示意图，但是这样需要消耗较多的显影液，以保证区域D和区域E对应的阻挡层蚀刻完全，从而使得后续在蚀刻金属图案时，源极引线210不会突出于源极230，不会延伸到源极230沟道中。
鉴于此，本申请提供一种在蚀刻不均匀时仍然不会导致源极230和漏极240短路的驱动电路200的控制开关，结合图1、图2、以及图7至图11所示，所述控制开关包括薄膜晶体管220，所述驱动电路200还包括与所述薄膜晶体管220连接的源极引线210，所述薄膜晶体管220含有源极230、漏极240和栅极260，源极230包括至少两个并列设置的源极分支 231，以及连接各源极分支231的源极主干234，且与所述源极引线210直接连接的所述源极分支231为第一源极分支232，所述第一源极分支232与所述源极主干234的端部连接；漏极240与所述源极230同层设置，包括至少一个漏极分支241，以及连接各所述漏极分支241的漏极主干244，所述漏极分支241与所述源极分支231并列且交替设置以形成沟道，且与所述第一源极分支232相邻设置的所述漏极分支241为第一漏极分支242；所述栅极260与源极230、漏极240对应设置；其中，所述源极引线210的延长线位于所述第一漏极分支242和所述源极主干234之间。
需要说明的是，当漏极分支241只有一条时，漏极主干244是漏极分支241的一部分，与驱动电路200中的其它结构连接。而且，栅极260可以位于源极230和漏极240的下方，在薄膜晶体管220中形成底栅结构，栅极260也可以位于源极230和漏极240的上方，在薄膜晶体管220中形成顶栅结构。
目前，源极引线210通常与第一源极分支232垂直连接，由于对驱动电路200的集成度要求越来越高，源极230和漏极240之间的沟道间距变得越来越小，当由于各种原因导致对源极230、漏极240和源极分支231所在的金属膜层蚀刻不均时，例如图2中由于区域B和区域C的空白区域较大，需要消耗的蚀刻液更多，使得区域D和区域E中的蚀刻液不足，导致区域D和区域E中金属图案出现蚀刻不均匀的问题。此时未将源极引线210的端部蚀刻干净，导致源极引线210的端部从第一源极分支232中突出，由于源极230和漏极240之间的沟道间距较小，容易使得源极引线210与漏极240连接，使得源极230和漏极240短路。而且，目前设计中由于源极引线210的宽度尺寸通常较大，以增加对薄膜晶体管220的充电效果，这样使得源极引线210更加容易受到蚀刻不均匀的影响，并且从第一源极分支232中突出的面积较大，增大了源极230和漏极240短路的风险。
本申请通过对驱动电路200中薄膜晶体管220和源极引线210进行改进，使得源极引线210的延长线位于第一漏极分支242和所述源极主干234之间，且不与漏极分支241重叠；当对源极230、漏极240和源极引线210所在的膜层进行蚀刻时，即使存在蚀刻不均匀的问题，导致源极引线210的顶部突出于第一源极分支232，其突出位置也只会延伸到第一漏极分支242和所述源极主干234之间，不会与第一漏极分支242相交，因此不会导致源极230和漏极240短路。本方案对源极230和漏极240沟道宽度，以及对源极引线210的宽度不做限定，因此可以同时使得驱动电路200满足高集成度、高充电效果、不易短路等优点，提高了在同类型产品中的竞争力。
在图7至图9中，一个薄膜晶体管220同时与两条源极引线210连接，此时，第一源极分支232有两条，第一漏极分支242至少有一条。在图10-11中，一个薄膜晶体管220只与一条源极引线210连接，此时，第一源极分支232只有一条，第二源极分支233至少有一条， 第一漏极分支242只有一条。这两种连接情况可以适用于一个驱动电路200中，也可以适用于不同驱动电路200中，具体根据使用情况进行设计。
如图7所示，源极230只有两条与源极引线210一一对应连接的第一源极分支232，以及连接两条第一源极分支232的源极主干234；漏极240只有一条第一漏极分支242，第一漏极分支242位于两条第一源极分支232之间；两个第一源极分支232都在第一漏极分支242和源极主干234之间，同时不与第一漏极分支242有重叠部。薄膜晶体管220采用最简单的双沟道结构，源极230的形状类似于U型，第一漏极分支242与两个第一源极分支232之间形成两个沟道。由于两个源极引线210都与同一条第一漏极分支242进行对比，只要不与第一漏极分支242接触即可，因此在对蚀刻图案的设计上更为简单。
如图8所示，此时源极230包括两条第一源极分支232、一条第二源极分支233和一条源极主干234，两个第一源极分支232分别与源极主干234的两端连接，且分别与两条源极引线210一一对应连接，第二源极分支233并列地设置在两条所述第一源极分支232之间，与所述源极主干234的中部连接；所述漏极240包括两条第一漏极分支242和一条漏极主干244，两条第一漏极分支242分别与漏极主干244的两端连接；每一条漏极分支241都位于相邻两条第一源极分支232和第二源极分支233之间。本实施例中，源极230的形状类似于W型，漏极240的形状类似与U型，每一条源极引线210都可在第一源极分支232与相邻的第二源极分支233之间形成的区域内延伸，而不会与其它结构接触；因此，当蚀刻不均匀的问题较为严重时，也有足够的容错空间，防止源极引线210延伸过长导致源极230和漏极240短路。
如图9所示，此时源极230包括两条第一源极分支232、两条第二源极分支233和一条源极主干234，两条第一源极分支232分别与源极主干234的两端连接，且分别与两条源极引线210一一对应连接，两条第二源极分支233并列地设置在两条所述第一源极分支232之间，与源极主干234连接；漏极240包括两条第一漏极分支242、一条第二漏极分支243和一条漏极主干244，两条第一漏极分支242分别与漏极主干244的两端连接，第二漏极分支243并列地设置在两条第一漏极分支242之间，与漏极主干244的中部连接；每条所述第一漏极分支242都位于相邻两条第一源极分支232和第二源极分支233之间，所述第二漏极分支243位于相邻两条第二源极分支233之间。本实施例中，源极230的形状类似于三个并列的U型结构，漏极240的形状类似于W型，相对于图7和图8而言，图9中薄膜晶体管220的电学性能更好；当然，本申请还可以在图9的基础上继续增加第二源极分支233和第二漏极分支243的数量，使得薄膜晶体管220的电学性能进一步提高。
如图10所示，源极230只有一个与源极引线210连接的第一源极分支232，一个不与源极引线210连接的第二源极分支233，以及连接第一源极分支232和第二源极分支233的 源极主干234；漏极240只有一个第一漏极分支242，第一漏极分支242并列设置在第一源极分支232和第二源极分支233之间，与第一源极分支232和第二源极分支233分别形成两个沟道；源极引线210的延长线位于所述第一漏极分支242和所述源极主干234之间，且不与所述第一漏极分支242重叠。本实施例中薄膜晶体管220同样为最简单的双沟道类型，但是与图7不同的是，由于图10中的薄膜晶体管只与一条源极引线210连接，因此源极引线具有较大的延伸空间，不容易与其它结构短接。
如图11所示，此时漏极240包括一条与源极引线210连接的第一源极分支232，两个不与源极引线210连接的第二源极分支233，以及连接第一源极分支232和第二源极分支233的源极主干234，其中一个第二源极分支233和第一源极分支232连接到源极主干234的两端，另一个第二源极分支233连接到源极主干234的中部；漏极240包括一条第一漏极分支242、一条第二漏极分支243和一条漏极主干244，第一漏极分支242和第二漏极分支243分别与漏极主干244的两端连接；第一漏极分支242并列地设置在相邻的第一源极分支232和第二源极分支233之间，第二漏极分支243并列地设置在相邻的两条第二源极分支233之间。为了进一步增加薄膜晶体管220的电学性能，还可以在图11的基础上进一步继续增加第二源极分支233和第二漏极分支243的数量。
本申请可以通过减短第一漏极分支242的长度来增加第一漏极分支242与源极主干234的间距，从而使得源极引线210的延长线可以做到第一漏极分支242和所述源极主干234之间，且不与所述第一漏极分支242重叠；还可以通过减小源极引线210的宽度，使得源极引线210的延长线做到第一漏极分支242和所述源极主干234之间时，源极引线210的延长线且不与所述第一漏极分支242重叠；也可以通过减小源极主干234的宽度，使得源极引线210的延长线做到第一漏极分支242和所述源极主干234之间时，源极引线210的延长线且不与所述第一漏极分支242重叠；也可以通过上述两种或两种以上方式的结合方式来达到相同的技术效果。
在图7至图11中，采用减短第一漏极分支242长度的方式，来增加第一漏极分支242与源极主干234的间距；此方式不会影响源极引线210的充电效果，也不会影响源极230和漏极240的电学均匀效果，而且相比于其他的方式而言，这一方式可以任意控制漏极240的长度，由于漏极240的长度较大，因此能够使得第一漏极分支242与源极主干234的间距较大。而在图9和图11中，第二漏极分支243的长度不需要改变，此时所述第二漏极分支243与所述源极主干234之间的距离，小于所述第一漏极分支242与所述源极主干234之间的距离；这样的设计使得虽然减小了第一漏极分支242的长度，但是源极230和漏极240之间的沟道间距并不会受到较大的影响，对薄膜晶体管220的影响较小。
具体的，可以使第一漏极分支242减短的距离与源极引线240的宽度相等，也就是说所 述第二漏极分支243与所述第一漏极分支242的长度之差，和所述源极引线210的宽度相等；其中，所述第一漏极分支242、第二漏极分支243的长度方向为所述第一漏极分支242、第二漏极分支243的延伸方向。这样的紧密排布充分利用第一漏极分支242与源极主干234之间的空白区域，有利于缩小薄膜晶体管220的体积，且第二漏极分支243与源极引线210的顶部(靠近源极主干的一侧)平齐，方便在制作图案时进行对准设计，从而减小蚀刻阻挡层图案的蚀刻难度，提高对源极230、漏极240和源极引线210所在的金属层进行蚀刻时的均匀效果。
而且，当薄膜晶体管220与两条源极引线210连接时，两条源极引线210可以设置在同一直线上，可以使得两条第一漏极分支242的减短距离相同，这样既方便提高薄膜晶体管220两端源极230和漏极240的均匀效果，又能够同时将两个第一漏极分支242的长度做到最大程度，以免一个第一漏极分支242长，一个第一漏极分支242短，降低薄膜晶体管220的电学性能。当然，两条源极引线210也可以不设置在同一直线上，防止两条源极引线210短接，做成短路的风险。
在本申请中，所有源极分支231和漏极分支241均为条状结构，可为矩形、椭圆形或其它形状，源极分支231的延伸方向与源极主干234的延伸方向相互垂直，漏极分支241的延伸方向与漏极主干244的延伸方向互相垂直；当然，源极分支231的延伸方向与源极主干234的延伸方向之间的夹角可以形成锐角，同时漏极分支241的延伸方向与漏极主干244的延伸方向之间的夹角也为锐角。源极引线210与第一源极分支232之间可以垂直设置，也可以倾斜设置。
另外，源极分支231、源极主干234、漏极分支241和漏极主干244的宽度都相等，相邻第二源极分支233与漏极分支241之间的沟道宽度也相等，从而提高薄膜晶体管220的导电性能。由于本申请只需要减小第一漏极分支242的长度就能够克服由于蚀刻不均匀所导致的源极230和漏极240短路的问题，因此可以进一步减小源极分支231和漏极分支241之间的沟道宽度，减小第二漏极分支243与源极主干234之间的间距，减小源极主干234和漏极主干244的间距，来进一步提高驱动电路200中的集成度，减小显示面板中驱动电路200的占用面积，进一步减小显示面板的窄边框。
如图12所示，是一种显示面板的示意图，作为本申请的另一实施例，还公开了一种显示面板400，所述显示面板400包括图1所示的阵列基板100，与所述阵列基板100相对设置的彩膜基板500，以及设置在所述阵列基板100和彩膜基板500之间的液晶层600；所述阵列基板100的非显示区含有上述驱动电路200。另外，本申请中的薄膜晶体管220不仅适用于非显示区中的阵列基板行驱动电路，同样适用于所述阵列基板100显示区中的主动开关。
本申请的技术方案可以广泛用于各种显示面板，如TN(Twisted Nematic，扭曲向列型)显示面板、IPS(In-Plane Switching，平面转换型)显示面板、VA(Vertical Alignment，垂直配向型)显示面板、MVA(Multi-Domain Vertical Alignment，多象限垂直配向型)显示面板，当然，也可以是其他类型的显示面板，均可适用上述方案。
需要说明的是,本申请的发明构思可以形成非常多的实施例，但是申请文件的篇幅有限，无法一一列出，因而，在不相冲突的前提下,以上描述的各实施例之间或各技术特征之间可以任意组合形成新的实施例，各实施例或技术特征组合之后，将会增强原有的技术效果。
以上内容是结合具体的可选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种驱动电路的控制开关，所述控制开关包括薄膜晶体管，所述驱动电路还包括与所述薄膜晶体管连接的源极引线，所述薄膜晶体管包括：
    源极，包括至少两个并列设置的源极分支，以及连接各个所述源极分支的源极主干，且与所述源极引线直接连接的所述源极分支为第一源极分支，所述第一源极分支与所述源极主干的端部连接；
    漏极，与所述源极同层设置，包括至少一个漏极分支，以及连接各个所述漏极分支的漏极主干，所述漏极分支与所述源极分支并列且交替设置以形成沟道，且与所述第一源极分支相邻设置的所述漏极分支为第一漏极分支；以及
    栅极，与所述源极、漏极对应设置；
    其中，所述源极引线的延长线位于所述第一漏极分支和所述源极主干之间。
  2. 如权利要求1所述的驱动电路的控制开关，其中，所述薄膜晶体管与两条所述源极引线连接，所述第一源极分支的数量有两条，两条所述第一源极分支分别连接到所述源极主干的两端，且与两条所述源极引线一一对应连接；
    所述第一漏极分支位于两条所述第一源极分支之间，两条所述源极引线的延长线均位于所述第一漏极分支和所述源极主干之间，且不与所述第一漏极分支重叠。
  3. 如权利要求2所述的驱动电路的控制开关，其中，不与所述源极引线直接连接的所述源极分支为第二源极分支，且所述第二源极分支并列设置在两条所述第一源极分支之间，与所述源极主干连接；
    不与所述第一源极分支相邻设置的所述漏极分支为第二漏极分支，所述第一漏极分支的数量有两条，且两条所述第一漏极分支分别与所述漏极主干的两端连接，所述第二漏极分支并列设置在两条所述第一漏极分支之间，与所述漏极主干连接；
    所述第一漏极分支设置在相邻所述第一源极分支和所述第二源极分支之间，所述第二漏极分支设置在相邻两条所述第二源极分支之间。
  4. 如权利要求3所述的驱动电路的控制开关，其中，当所述第二源极分支的数量只有一条时，所述第二漏极分支的数量为零，所述源极的形状为W形，所述漏极的形状为U形。
  5. 如权利要求3所述的驱动电路的控制开关，其中，所述源极包括两条所述第一源极分支、两条所述第二源极分支和一条所述源极主干，所述漏极包括两条所述第一漏极分支、一条所述第二漏极分支和一条所述漏极主干，每条所述第一漏极分支都位于相邻所述第一源极分支和所述第二源极分支之间，所述第二漏极分支位于相邻两条所述第二源极分支之间。
  6. 如权利要求3所述的驱动电路的控制开关，其中，所述第二漏极分支与所述源极主干之间的距离，小于所述第一漏极分支与所述源极主干之间的距离。
  7. 如权利要求2所述的驱动电路的控制开关，其中，当所述第一漏极分支的数量只有一条时，所述源极的形状为U形。
  8. 如权利要求2所述的驱动电路的控制开关，其中，两条所述源极引线位于同一直线上。
  9. 如权利要求2所述的驱动电路的控制开关，其中，两条所述源极引线不位于同一直线上。
  10. 如权利要求1所述的驱动电路的控制开关，其中，所述薄膜晶体管与一条所述源极引线连接，所述第一源极分支的数量只有一条；不与所述源极引线直接连接的所述源极分支为第二源极分支，所述第二源极分支的数量至少有一条；
    所述第一漏极分支设置在所述第一源极分支和所述第二源极分支之间，所述源极引线的延长线位于所述第一漏极分支和所述源极主干之间，且不与所述第一漏极分支重叠。
  11. 如权利要求10所述的驱动电路的控制开关，其中，不与所述第一源极分支相邻设置的所述漏极分支为第二漏极分支，所述第二漏极分支的数量至少有一条，所述第一漏极分支和一条所述第二漏极分支分别与所述漏极主干的两端连接；所述第二漏极分支设置在相邻两条所述第二源极分支之间。
  12. 如权利要求11所述的驱动电路的控制开关，其中，所述第二漏极分支与所述第一漏极分支的长度之差，和所述源极引线的宽度相等；
    其中，所述第一漏极分支、第二漏极分支的长度方向为所述第一漏极分支、第二漏极分支的延伸方向。
  13. 如权利要求1所述的驱动电路的控制开关，其中，所述源极分支和所述漏极分支的形状包括条状、矩形或椭圆形。
  14. 如权利要求1所述的驱动电路的控制开关，其中，所述源极分支的延伸方向与所述源极主干的延伸方向相互垂直，所述漏极分支的延伸方向与所述漏极主干的延伸方向互相垂直。
  15. 如权利要求1所述的驱动电路的控制开关，其中，所述源极分支的延伸方向与所述源极主干的延伸方向之间的夹角为锐角，所述漏极分支的延伸方向与所述漏极主干的延伸方向之间的夹角为锐角。
  16. 如权利要求1所述的驱动电路的控制开关，其中，所述源极分支、所述源极主干、所述漏极分支和所述漏极主干的宽度都相等。
  17. 一种阵列基板，包括驱动电路、源极引线和被所述驱动电路驱动的扫描线，所述驱动电路的控制开关包括薄膜晶体管，所述薄膜晶体管包括：
    源极，包括至少两个并列设置的源极分支，以及连接各个所述源极分支的源极主干，且与所述源极引线直接连接的所述源极分支为第一源极分支，所述第一源极分支与所述源极主干的端部连接；
    漏极，与所述源极同层设置，包括至少一个漏极分支，以及连接各个所述漏极分支的漏极主干，所述漏极分支与所述源极分支并列且交替设置以形成沟道，且与所述第一源极分支相邻设置的所述漏极分支为第一漏极分支；以及
    栅极，与所述源极、漏极对应设置；
    其中，所述源极引线的延长线位于所述第一漏极分支和所述源极主干之间。
  18. 如权利要求17所述的阵列基板，其中，所述驱动电路包括帧起始信号线、栅电压控制线、时钟信号线和多个栅极驱动单元，所述栅极驱动单元的输入端与所述帧起始信号线、栅电压控制线和时钟信号线连接，对所述扫描线驱动；所述栅电压控制线通过源极引线与栅极驱动单元中的一个薄膜晶体管连接。
  19. 如权利要求18所述的阵列基板，其中，所述栅极驱动单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管，所述第一薄膜晶体管的源极分别通过两条所述源极引线与所述栅电压控制线、所述第二薄膜晶体管的源极连接，所述第一薄膜晶体管的漏极分别与所述第三薄膜晶体管的源极、第四薄膜晶体管的栅极连接，所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极连接；所述第二薄膜晶体管的漏极与所述第四薄膜晶体管的源极连接，所述第二薄膜晶体管的栅极与所述第四薄膜晶体管的栅极连接；所述第三薄膜晶体管的漏极与所述帧起始信号线连通，所述第四薄膜晶体管的漏极与所述时钟信号线连通。
  20. 一种显示面板，包括阵列基板，与所述阵列基板相对设置的彩膜基板，以及设置在所述阵列基板和彩膜基板之间的液晶层，所述阵列基板包括驱动电路、源极引线和被所述驱动电路驱动的扫描线，所述驱动电路的控制开关包括薄膜晶体管，所述薄膜晶体管包括：
    源极，包括至少两个并列设置的源极分支，以及连接各个所述源极分支的源极主干，且与所述源极引线直接连接的所述源极分支为第一源极分支，所述第一源极分支与所述源极主干的端部连接；
    漏极，与所述源极同层设置，包括至少一个漏极分支，以及连接各个所述漏极分支的漏极主干，所述漏极分支与所述源极分支并列且交替设置以形成沟道，且与所述第一源极分支相邻设置的所述漏极分支为第一漏极分支；以及
    栅极，与所述源极、漏极对应设置；
    其中，所述源极引线的延长线位于所述第一漏极分支和所述源极主干之间。
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