WO2022201798A1 - 受光素子アレイおよびその製造方法 - Google Patents
受光素子アレイおよびその製造方法 Download PDFInfo
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- WO2022201798A1 WO2022201798A1 PCT/JP2022/001908 JP2022001908W WO2022201798A1 WO 2022201798 A1 WO2022201798 A1 WO 2022201798A1 JP 2022001908 W JP2022001908 W JP 2022001908W WO 2022201798 A1 WO2022201798 A1 WO 2022201798A1
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- layer
- light absorption
- absorption layer
- substrate
- light
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 230000031700 light absorption Effects 0.000 claims description 129
- 238000000926 separation method Methods 0.000 claims description 16
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 309
- 239000000463 material Substances 0.000 description 20
- 238000005530 etching Methods 0.000 description 13
- 238000000206 photolithography Methods 0.000 description 13
- 239000011701 zinc Substances 0.000 description 11
- 239000012535 impurity Substances 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 7
- 238000005259 measurement Methods 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1446—Devices controlled by radiation in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14694—The active layers comprising only AIIIBV compounds, e.g. GaAs, InP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
Definitions
- the present disclosure relates to a light receiving element array and its manufacturing method.
- Patent Document 1 discloses a light-receiving element array including a plurality of light-receiving elements, which includes an n-type substrate and a semiconductor stack formed on the n-type substrate.
- the semiconductor lamination consists of an absorption layer formed on an n-type substrate and an n-type semiconductor layer formed on the absorption layer.
- the semiconductor lamination has a plurality of p-type semiconductor regions for each device partition area.
- An object of the present disclosure is to provide a light receiving element array capable of reducing crosstalk and a method of manufacturing the same.
- One embodiment of the present disclosure includes a substrate and a semiconductor laminate structure formed on the substrate, wherein the semiconductor laminate structure includes a light absorption layer disposed above the substrate and a light absorption layer on the light absorption layer. a plurality of first-conductivity-type window layers spaced apart from each other, and the light absorbing layer is provided in each of the window layers from the surface of the window layer opposite to the light absorption layer.
- a first second-conductivity-type region extending in the light absorbing layer is formed in the light absorbing layer so as to surround each of the plurality of window layers in a plan view;
- One embodiment of the present disclosure includes a substrate and a semiconductor laminate structure formed on the substrate, wherein the semiconductor laminate structure includes a light absorption layer disposed above the substrate and a light absorption layer on the light absorption layer. a plurality of first-conductivity-type window layers spaced apart from each other, and the light absorbing layer is provided in each of the window layers from the surface of the window layer opposite to the light absorption layer.
- a second conductivity type region extending into the light absorption layer is formed, and the light absorption layer is arranged so as to surround each of the plurality of window layers in a plan view, and the substrate in the light absorption layer and the provides a light-receiving element array in which separation grooves extending from the opposite surface toward the substrate-side surface of the light-absorbing layer are formed.
- An embodiment of the present disclosure comprises forming, on a substrate, a semiconductor multilayer structure including a light absorbing layer and a plurality of window layers of a first conductivity type spaced apart from each other on the light absorbing layer; forming a first second conductivity type region extending into the light absorption layer from a surface of the window layer opposite to the light absorption layer for each window layer in the semiconductor laminated structure; a second window layer arranged to surround each of the plurality of window layers in plan view and extending from a surface of the light absorption layer opposite to the substrate toward a surface of the light absorption layer facing the substrate; and forming a biconductivity type region.
- FIG. 1A is a plan view for explaining the configuration of a light receiving element array according to the first embodiment of the present disclosure
- FIG. FIG. 1B is a partially enlarged plan view showing the IB portion of FIG. 1A.
- FIG. 2 is a schematic cross-sectional view along line II-II of FIG. 1B.
- FIG. 3 is a schematic cross-sectional view along line III-III in FIG. 1B.
- FIG. 4 shows that, in contrast to the light receiving element array shown in FIGS. 1 to 3, a window layer is integrally formed over almost the entire surface of the light absorption layer, and a second p-type region is formed in the light absorption layer.
- FIG. 4 is a cross-sectional view showing a light receiving element array that has not been formed;
- FIG. 5 is a graph showing measurement results of a first sample, which is a sample of the light receiving element array shown in FIG.
- FIG. 6 is a graph showing measurement results of a second sample, which is a sample of the light receiving element array shown in FIGS. 1A to 3.
- FIG. 7A is a cross-sectional view showing an example of the manufacturing process of the light-receiving element array shown in FIGS. 1A to 3, and is a cross-sectional view corresponding to the cross-sectional view of FIG.
- FIG. 7B is a cross-sectional view showing the next step of FIG. 7A.
- FIG. 7C is a cross-sectional view showing the next step of FIG. 7B.
- FIG. 7D is a cross-sectional view showing the next step of FIG. 7C.
- FIG. 7E is a cross-sectional view showing the next step of FIG. 7D.
- FIG. 7F is a cross-sectional view showing the next step of FIG. 7E.
- FIG. 7G is a cross-sectional view showing the next step after FIG. 7F.
- FIG. 7H is a cross-sectional view showing the next step of FIG. 7G.
- FIG. 7I is a cross-sectional view showing the next step after FIG. 7H.
- FIG. 7J is a cross-sectional view showing the next step after FIG. 7I.
- FIG. 7K is a cross-sectional view showing the next step of FIG. 7J.
- 8A is a cross-sectional view showing an example of the manufacturing process of the light-receiving element array shown in FIGS.
- FIG. 8B is a cross-sectional view showing the next step of FIG. 8A.
- FIG. 8C is a cross-sectional view showing the next step of FIG. 8B.
- FIG. 8D is a cross-sectional view showing the next step of FIG. 8C.
- FIG. 8E is a cross-sectional view showing the next step of FIG. 8D.
- FIG. 8F is a cross-sectional view showing the next step of FIG. 8E.
- FIG. 8G is a cross-sectional view showing the next step after FIG. 8F.
- FIG. 8H is a cross-sectional view showing the next step of FIG. 8G.
- FIG. 8I is a cross-sectional view showing the next step after FIG. 8H.
- FIG. 8J is a cross-sectional view showing the next step of FIG. 8I.
- FIG. 8K is a cross-sectional view showing the next step of FIG. 8J.
- FIG. 9 is a cross-sectional view for explaining the configuration of the light receiving element array according to the second embodiment of the present disclosure.
- FIG. 10 is a graph showing measurement results of a third sample, which is a sample of the photodetector array shown in FIG. 11A is a cross-sectional view showing an example of a manufacturing process of the light receiving element array shown in FIG. 9.
- FIG. 11B is a cross-sectional view showing the next step of FIG. 11A.
- FIG. 11C is a cross-sectional view showing the next step of FIG. 11B.
- FIG. 11D is a cross-sectional view showing the next step of FIG. 11C.
- FIG. 11E is a cross-sectional view showing the next step of FIG. 11D.
- FIG. 11F is a cross-sectional view showing the next step of FIG. 11E.
- FIG. 11G is a cross-sectional view showing the next step of FIG. 11F.
- FIG. 11H is a cross-sectional view showing the next step of FIG. 11G.
- One embodiment of the present disclosure includes a substrate and a semiconductor laminate structure formed on the substrate, wherein the semiconductor laminate structure includes a light absorption layer disposed above the substrate and a light absorption layer on the light absorption layer. a plurality of first-conductivity-type window layers spaced apart from each other, and the light absorbing layer is provided in each of the window layers from the surface of the window layer opposite to the light absorption layer.
- a first second-conductivity-type region extending in the light absorbing layer is formed in the light absorbing layer so as to surround each of the plurality of window layers in a plan view;
- the second second-conductivity-type region extends from the surface of the light absorbing layer opposite to the substrate halfway through the thickness of the light absorbing layer.
- the second second conductivity type region penetrates the light absorption layer.
- One embodiment of the present disclosure includes a substrate and a semiconductor laminate structure formed on the substrate, wherein the semiconductor laminate structure includes a light absorption layer disposed above the substrate and a light absorption layer on the light absorption layer. a plurality of first-conductivity-type window layers spaced apart from each other, and the light absorbing layer is provided in each of the window layers from the surface of the window layer opposite to the light absorption layer.
- a second conductivity type region extending into the light absorption layer is formed, and the light absorption layer is arranged so as to surround each of the plurality of window layers in a plan view, and the substrate in the light absorption layer and the provides a light-receiving element array in which separation grooves extending from the opposite surface toward the substrate-side surface of the light-absorbing layer are formed.
- the separation groove penetrates the light absorption layer in the thickness direction.
- an insulating film is formed on the light absorption layer so as to cover the plurality of window layers, and a plurality of second layers are provided for each of the window layers and arranged on the insulating film. and one electrode, each said first electrode being electrically connected to a corresponding said first second conductivity type region.
- an insulating film is formed on the light absorption layer so as to cover the plurality of window layers, and a plurality of second layers are provided for each of the window layers and arranged on the insulating film. and one electrode, each said first electrode being electrically connected to a corresponding said second conductivity type region.
- the insulating film is an antireflection film that prevents reflection of light with a preset wavelength.
- the first electrode is endless in plan view.
- An embodiment of the present disclosure includes a second electrode formed on the second main surface of the substrate.
- the plurality of window layers are arranged in a matrix in plan view.
- the semiconductor laminated structure includes a first conductivity type buffer layer formed between the substrate and the light absorption layer.
- the buffer layer has an exposed surface on a portion of the surface opposite to the substrate, and a third electrode is formed on the exposed surface.
- the substrate is an n-type InP substrate
- the light absorption layer is a non-doped InGaAs layer
- the window layer is an n-type InP layer.
- the substrate is an n-type InP substrate
- the buffer layer is an n-type InP layer
- the light absorption layer is a non-doped InGaAs layer
- the window layer is an n-type InP layer.
- An embodiment of the present disclosure comprises forming, on a substrate, a semiconductor multilayer structure including a light absorbing layer and a plurality of window layers of a first conductivity type spaced apart from each other on the light absorbing layer; forming a first second conductivity type region extending into the light absorption layer from a surface of the window layer opposite to the light absorption layer for each window layer in the semiconductor laminated structure; a second window layer arranged to surround each of the plurality of window layers in plan view and extending from a surface of the light absorption layer opposite to the substrate toward a surface of the light absorption layer facing the substrate; and forming a biconductivity type region.
- the step of forming the first second-conductivity-type region and the step of forming the second second-conductivity-type region are performed in the same step.
- FIG. 1A is a plan view for explaining the configuration of the light receiving element array according to the first embodiment of the present disclosure.
- FIG. 1B is a partially enlarged plan view showing the IB portion of FIG. 1A.
- FIG. 2 is a schematic cross-sectional view along line II-II of FIG. 1B.
- FIG. 3 is a schematic cross-sectional view along line III-III in FIG. 1B.
- the horizontal direction of the paper surface of FIG. 1A may be referred to as the horizontal direction
- the vertical direction of the paper surface of FIG. 1A may be referred to as the vertical direction
- the light receiving element array 1 has a rectangular parallelepiped shape.
- the light-receiving element array 1 has a square shape having two sides parallel to the horizontal direction and two sides parallel to the vertical direction.
- the light receiving element array 1 includes a substrate 2 having a first main surface (front surface) 2a and a second main surface (back surface) 2b on the opposite side, and a semiconductor laminated structure 20 formed on the first main surface 2a of the substrate 2.
- the semiconductor laminated structure 20 includes an n-type buffer layer 3 formed on the first main surface 2a of the substrate 2, and a non-doped light absorption layer 4 formed on the surface of the buffer layer 3 except for four corner portions.
- the semiconductor laminated structure 20 further includes a plurality of n-type window layers 5 spaced apart from each other in the central region of the surface of the light absorption layer 4, and a window layer group in the peripheral portion of the surface of the light absorption layer 4. and a surrounding n-type layer 6 .
- the semiconductor laminated structure 20 further includes a p-type contact layer 7 formed on each window layer 5 and in contact with a first p-type region 8 to be described later.
- a first p-type region 8 extending into the light absorption layer 4 from the surface of the window layer 5 opposite to the light absorption layer 4 is formed.
- the light absorption layer 4 it is arranged so as to surround each of the plurality of window layers 5 in plan view, and from the surface of the light absorption layer 4 opposite to the substrate 2 to the surface of the light absorption layer 4 on the side of the substrate 2 .
- a second p-type region 9 extending toward is formed. In FIG. 1B, the second p-type region 9 is indicated with dots for clarity.
- the light receiving element array 1 includes an insulating film 10 covering part of the exposed surface of the buffer layer 3, the exposed surface of the light absorbing layer 4, the exposed surface of the window layer 5, the exposed surface of the n-type layer 6 and the contact layer 7.
- the light receiving element array 1 also includes a plurality of first electrodes (p-side electrodes) 12 provided for each window layer 5 and arranged on the insulating film 10 .
- the light receiving element array 1 includes a second electrode (main n-side electrode) 13 formed on the second main surface 2b of the substrate 2 and a plurality of third electrodes formed on the four corner portions of the surface of the buffer layer 3.
- An electrode (sub n-side electrode) 14 is included.
- the light receiving element array 1 includes a plurality of bonding pads 15, wirings 16 and marks 17 and 18 formed on the insulating film 10. As shown in FIG.
- a light receiving element 30 composed of a PIN photodiode is formed in each region where the window layer 5 exists in plan view.
- a light receiving element 30 is formed for each first p-type region 8 in the light receiving element array 1 .
- the light receiving element array 1 includes 16 light receiving elements 30 arranged in 4 rows and 4 columns.
- Each light receiving element 30 includes a substrate 2 , a buffer layer 3 , a light absorption layer 4 , a window layer 5 , a contact layer 7 , an insulating film 10 , a first electrode 12 and a second electrode 13 .
- the four rows are referred to as the first, second, third and fourth rows from the top of the page of FIG.
- the plurality of light receiving elements 30 include 1 to 4 from the first to fourth columns in the first row, 5 to 8 from the first to fourth columns in the second row, and a third Identification numbers 9 to 12 are assigned from the 1st to 4th columns of the row, and 13 to 16 are assigned from the 1st to 4th columns of the 4th row, respectively.
- the substrate 2 consists of an n-type InP substrate in this embodiment.
- the n-type impurity is, for example, S (sulfur), and the impurity concentration is about 1 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 18 cm ⁇ 3 .
- the thickness of the substrate 2 is of the order of 180 ⁇ m.
- the substrate 2 may be a semi-insulating substrate.
- the buffer layer 3 is a buffer layer for relaxing strain caused by a difference between the lattice constant of the light absorption layer 4 formed on the buffer layer 3 and the lattice constant of the substrate 2 .
- the buffer layer 3 consists of an n-type InP layer in this embodiment.
- the n-type impurity is Si (silicon), for example, and the impurity concentration is about 1 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 18 cm ⁇ 3 .
- the thickness of the buffer layer 3 is approximately 100 nm to 200 nm.
- the light absorption layer 4 has chamfers 4a at four corners.
- the outer surface of the chamfered portion 4a is formed in an arcuate shape protruding inward in plan view.
- the light absorption layer 4 consists of a non-doped InGaAs layer in this embodiment.
- the thickness of the light absorption layer 4 is about 2 ⁇ m to 5 ⁇ m.
- the window layer 5 has a square shape in plan view in this embodiment.
- the plurality of window layers 5 are arranged in a matrix in plan view in this embodiment. More specifically, the plurality of window layers 5 are arranged side by side at regular intervals in the horizontal and vertical directions. In this embodiment, the plurality of window layers 5 includes 16 window layers 5 with 4 rows and 4 columns.
- the n-type layer 6 has chamfered portions 6 a at four corner portions corresponding to the four corner portions of the light absorbing layer 4 .
- the outer surface of the chamfered portion 6a is formed in an arcuate shape protruding inward in plan view.
- the window layer 5 and the n-type layer 6 consist of n-type InP layers in this embodiment.
- the n-type impurity is Si (silicon), for example, and the impurity concentration is about 1 ⁇ 10 16 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 .
- the thickness of window layer 5 and n-type layer 6 is about 0.5 ⁇ m to 1.5 ⁇ m.
- First p-type region 8 is formed by diffusing Zn (zinc) into window layer 5 and light absorbing layer 4 from the surface of window layer 5 opposite to light absorbing layer 4 .
- the concentration of Zn in the surface layer portion of the window layer 5 is approximately 2 ⁇ 10 18 cm ⁇ 3 .
- the first p-type region 8 has a circular shape in plan view in this embodiment. The first p-type region 8 extends halfway through the thickness of the light absorption layer 4 from the surface of the window layer 5 .
- the second p-type region 9 is formed by diffusing Zn (zinc) into the light absorbing layer 4 from the surface of the light absorbing layer 4 opposite to the substrate 2 .
- the concentration of Zn is about 2 ⁇ 10 18 cm ⁇ 3 in the surface layer of the light absorption layer 4 .
- the second p-type region 9 is formed in a grid pattern in plan view in the central region of the light absorption layer 4 . That is, in a plan view, the second p-type region 9 includes a plurality of first portions 91 extending in the horizontal direction at equal intervals in the vertical direction, and a plurality of first portions 91 extending in the vertical direction at equal intervals in the horizontal direction and extending in the horizontal direction.
- the plurality of first portions 91 and the plurality of second portions 92 form a plurality of endless (in this example, rectangular annular) second p-type regions 9 surrounding each of the window layers 5 in plan view. .
- the second p-type region 9 extends from the surface of the light absorption layer 4 halfway through the thickness of the light absorption layer 4 .
- the second p-type region 9 may extend from the surface of the light absorption layer 4 through the light absorption layer 4 to reach the buffer layer 3, as indicated by a chain double-dashed line 9A in FIG.
- the contact layer 7 consists of a p-type InGaAs layer in this embodiment.
- the p-type impurity is, for example, Zn (zinc), and the impurity concentration is about 1 ⁇ 10 19 cm ⁇ 3 to 2 ⁇ 10 19 cm ⁇ 3 .
- the thickness of the contact layer 7 is approximately 100 nm.
- the contact layer 7 is endless (annular in this example) in plan view, and is formed on the periphery of the surface of the first p-type region 8 . That is, the lower surface of contact layer 7 is in contact with the surface of first p-type region 8 .
- the insulating film 10 covers the exposed surface of the light absorption layer 4 , the exposed surface of the window layer 5 , the exposed surface of the n-type layer 6 and the contact layer 7 .
- the insulating film 10 further covers the exposed surfaces of the corners of the buffer layer 3 near the chamfered portions 4 a of the light absorbing layer 4 .
- the insulating film 10 is formed with a contact hole 11 that is annular in plan view and exposes the widthwise intermediate portion of the surface of the contact layer 7 that is annular in plan view over the entire periphery.
- Chamfered portions 10 a are formed at four corner portions of the insulating film 10 .
- the outer surface of the chamfered portion 10a is formed in an arcuate shape protruding inward in plan view.
- the insulating film 10 is made of a SiN film in this embodiment.
- the thickness of the insulating film 10 is set to about 200 nm so as to prevent reflection of light with a wavelength of 1500 nm. That is, in this embodiment, the insulating film 10 is an antireflection film that prevents reflection of light of a predetermined wavelength.
- the thickness of the insulating film 10 is set according to the wavelength of light whose reflection is to be prevented. The wavelength of light whose reflection should be prevented is set in advance.
- the first electrode 12 is endless in plan view (toroidal in this example), and is formed on the insulating film 10 so as to cover the contact hole 11 . A portion of the first electrode 12 enters the contact hole 11 and contacts the surface of the contact layer 7 within the contact hole 11 . Thereby, the first electrode 12 is electrically connected to the first p-type region 8 via the contact layer 7 .
- the first electrode 12 is composed of a Ti/Pt/Au laminated film in which a Ti film, a Pd film and an Au film are laminated in that order from the bottom.
- the second electrode 13 is electrically connected to the buffer layer 3 through the substrate 2 .
- the second electrode 13 is composed of a Ti/Pt/Au laminated film in which a Ti film, a Pd film and an Au film are laminated in that order on the second main surface 2b of the substrate 2 .
- the third electrodes 14 are formed on the exposed surfaces of the four corner portions of the buffer layer 3 respectively. That is, the third electrode 14 is electrically connected to the buffer layer 3 .
- the third electrode 14 may be used to check the characteristics of the light receiving elements 30 during the manufacturing process of the light receiving element array 1 .
- the third electrode 14 is composed of a Ti/Pt/Au laminated film in which a Ti film, a Pd film and an Au film are laminated in that order from the bottom.
- a plurality of bonding pads 15 are formed on the periphery of the surface of the insulating film 10 . Specifically, four bonding pads 15 are formed on each edge of the insulating film 10 corresponding to each side. A plurality of wirings 16 are formed on the surface of the insulating film 10 for connecting the first electrodes 12 of the plurality of light receiving elements 30 to different bonding pads 15, respectively.
- one first mark 17 having a + (plus sign) shape in plan view and an L-shaped mark in plan view are formed so that the identification number of each light receiving element 30 can be recognized. are formed.
- the first mark 17 is formed near the upper left corner portion of the surface of the insulating film 10
- the second marks are formed near the other three corner portions of the surface of the insulating film 10 .
- the bonding pad 15, wiring 16 and marks 17, 18 are made of the same material as the electrodes 12, 14 in this embodiment. As will be described later, the bonding pad 15, wiring 16, marks 17 and 18, first electrode 12 and third electrode 14 are formed in the same process.
- the light receiving element array 1 is used with external wiring connected between each bonding pad 15 and the second electrode 13 .
- a power supply for generating an internal electric field in the light absorption layer 4 is connected to the external wiring.
- the second p-type region 9 is formed in the light absorption layer 4 so as to surround each of the plurality of window layers 5 (light receiving elements 30) in plan view.
- the second p-type region 9 is formed in the light absorption layer 4 so as to surround each of the plurality of window layers 5 (light receiving elements 30) in plan view.
- FIG. 4 shows a structure in which a window layer 5 is integrally formed over substantially the entire surface of a light absorption layer 4 and a second layer is formed in the light absorption layer 4 in contrast to the light receiving element array 1 shown in FIGS. It shows a light receiving element array 101 in which the 2p-type region 9 is not formed. In the light receiving element array 101 as well, a light receiving element 30 is formed for each first p-type region 8 .
- the same reference numerals as in FIG. 2 denote the parts corresponding to the parts in FIG. 2 described above.
- the sample of the light receiving element array 101 shown in FIG. 4 may be referred to as the first sample. Also, the sample of the light receiving element array 1 shown in FIGS. 1 to 3 may be referred to as a second sample.
- first current I1 a current flowing through the light receiving element 30 when a light of 1 mW is incident on a certain light receiving element
- second current I2 a current flowing through a light receiving element adjacent to the light receiving element when the light is incident thereon and a dark current
- a dark current is a current that flows through a light receiving element when light is not incident on the light receiving element.
- FIG. 5 is a graph showing measurement results for the first sample
- FIG. 6 is a graph showing measurement results for the second sample.
- a straight line a is a graph showing the first current I1
- a straight line b is a graph showing the second current I2
- a circle dot group c is a graph showing dark current.
- the second current is significantly lower in the second sample than in the first sample.
- ⁇ (I2/I1) ⁇ 100 ⁇ is the crosstalk characteristic [%]
- the crosstalk characteristic of the first sample is 2.32%
- the crosstalk characteristic of the second sample is 0.13%.
- %Met it can be seen that crosstalk is significantly reduced in the second sample compared to the first sample. It can also be seen that the second sample has a lower dark current than the first sample.
- FIG. 7A to 7K are cross-sectional views for explaining an example of the manufacturing process of the light-receiving element array 1 described above, and are cross-sectional views corresponding to the cross-sectional plane of FIG. 8A to 8K are cross-sectional views for explaining an example of the manufacturing process of the light-receiving element array 1 described above, and are cross-sectional views corresponding to the cross-sectional plane of FIG.
- a buffer layer (eg, n-type InP layer) is formed on the first main surface 2a of the substrate (eg, n-type InP substrate) 2 by, eg, MOCVD (Metal Organic Chemical Vapor Deposition). 3 and a light absorption layer (eg, InGaAs layer) 4 are epitaxially grown in sequence. Further, a window material layer (for example, an n-type InP layer) 41 that is a material layer for the window layer 5 and the n-type layer 6 and a contact material layer (for example, p type InGaAs layer 42 is epitaxially grown in turn. As the substrate 2, a substrate thicker than the final thickness of the substrate 2 is used.
- photolithography and etching are used to remove regions of the contact material layer 42 other than the region corresponding to the region where the first p-type region 8 is to be formed. As a result, the contact material layer 42 remains only in the region where the first p-type region 8 is to be formed on the surface of the window material layer 41 .
- the window material layer 41 is patterned by photolithography and etching. Thereby, a plurality of window layers 5 and an n-type layer 6 are formed on the light absorption layer 4 .
- a plurality of window layers 5 are formed so as to be arranged in a matrix in the central region of the surface of the light absorption layer 4 .
- the n-type layer 6 is formed on the peripheral edge portion of the surface of the light absorption layer 4 excluding the four corner portions so as to surround the window layer group. As a result, the n-type layer 6 having the chamfered portions 6a at the corners corresponding to the four corners of the light absorbing layer 4 is obtained.
- a mask insulating film 43 is formed on the entire exposed surface by plasma CVD, LPCVD (Low Pressure CVD), MOCVD, sputtering, or the like. be.
- a portion of the insulating film 43 covering the surface (upper surface) of the contact material layer 42 and the surface of the light absorption layer 4 are subjected to photolithography and etching to form a second p-type layer.
- the part covering the area where the area 9 is to be formed is removed. Thereby, a first opening 43 a for forming the first p-type region 8 and a second opening 43 b for forming the second p-type region 9 are formed in the insulating film 43 .
- the contact material layer 42 is then patterned by photolithography and etching, as shown in FIGS. 7G and 8G.
- the contact layer 7 having an annular shape in plan view is formed on each of the first window layers 5 ⁇ /b>A so as to come into contact with the periphery of the surface of the first p-type region 8 .
- a semiconductor laminated structure 20 including the buffer layer 3, the light absorbing layer 4, the window layer 5 and the n-type layer 6, and the contact layer 7 is obtained.
- FIGS. 7H and 8H photolithography and etching are used to remove four corners of the light absorption layer 4 .
- chamfered portions 4a are formed at the four corner portions of the light absorption layer 4.
- an insulating material film 44 which is the material film of the insulating film 10, is formed on the entire exposed surface by plasma CVD, LPCVD, MOCVD, sputtering, or the like. be done.
- photolithography and etching are used to form contact holes 11 exposing a portion of the contact layer 7 in the insulating material film 44 for each window layer 5 .
- portions other than the vicinity of the chamfered portion 4a of the light absorption layer 4 are removed.
- the insulating film 10 having the chamfered portions 10a at the four corner portions is obtained.
- four corner portions of the surface of the buffer layer 3 are exposed.
- a first electrode 12, a third electrode 14, a bonding pad 15, a wiring 16 and a mark are formed by an electron beam evaporation method, a sputtering method, or the like so as to cover the exposed surface of the corner portion of the buffer layer 3 and the insulating film 10.
- Electrode films, which are material films of 17 and 18, are formed.
- the electrode film is patterned by photolithography and etching.
- FIGS. 7K and 8K a plurality of first electrodes 12, a plurality of bonding pads 15, a plurality of wirings 16 and a plurality of marks 17 and 18 are formed on the insulating film 10, and a buffer is formed.
- a third electrode 14 is formed at each of the four corners of layer 3 .
- the substrate 2 is thinned by grinding the substrate 2 from the second main surface 2b side. Then, the second electrode 13 is formed on the thinned second main surface 2b of the substrate 2 . As a result, a light receiving element array 1 as shown in FIGS. 1A to 3 is obtained.
- FIG. 9 is a cross-sectional view for explaining the configuration of the light receiving element array according to the second embodiment of the present disclosure.
- 9 is a cross-sectional view corresponding to the cross-sectional plane of FIG. 2.
- FIG. 9 the same reference numerals as in FIG. 2 denote the parts corresponding to the parts in FIG. 2 described above.
- the second p-type region 9 is not formed in the light absorption layer 4, and the separation groove 50 is formed in the light absorption layer 4 so as to surround the window layer 5 in plan view. 1A to 3 in that the inner surfaces (bottom and side surfaces) of the separation grooves 50 are covered with the insulating film 10.
- FIG. Other structures are the same as those of the light receiving element array 1 shown in FIGS. 1A to 3.
- FIGS. 1 and 1B are plan views of the light receiving element array 1 according to the second embodiment.
- the dashed line representing the second p-type region 9 in FIG. In other words, the areas where dots are added in FIG. 1B can be regarded as areas where the separation grooves 50 are formed.
- the separation grooves 50 are formed in a grid pattern in plan view in the central region of the light absorption layer 4 . That is, the separation groove 50 includes a plurality of first portions (portions indicated by reference numeral 50 in FIG. 9) extending in the horizontal direction at equal intervals in the vertical direction in a plan view, and a plurality of first portions (portions denoted by reference numeral 50 in FIG. 9) at equal intervals in the horizontal direction. It has a plurality of second portions (portions not shown in FIG. 9) extending longitudinally and intersecting the plurality of first portions. The plurality of first portions and the plurality of second portions form a plurality of rectangular ring-shaped separation grooves 50 surrounding each of the window layers 5 in plan view.
- the separation groove 50 extends from the surface of the light absorption layer 4 through the light absorption layer 4 to reach the buffer layer 3 .
- the separation groove 50 may extend from the surface of the light absorption layer 4 halfway through the thickness of the light absorption layer 4 .
- separation grooves 50 are formed in the light absorption layer 4 so as to surround each of the plurality of window layers 5 (light receiving elements 30) in plan view.
- the sample of the light receiving element array 1A shown in FIG. 9 may be referred to as the third sample.
- a current (first current I1) that flows through the light receiving element 30 when a light of 1 mW is incident on a certain light receiving element, and A current (second current I2) flowing through an adjacent light receiving element and a dark current were measured.
- FIG. 10 is a graph showing measurement results for the third sample.
- a straight line a is a graph showing the first current I1
- a straight line b is a graph showing the second current I2
- a circle dot group c is a graph showing dark current.
- the second current is significantly lower in the third sample than in the first sample.
- ⁇ (I2/I1) ⁇ 100 ⁇ is the crosstalk characteristic [%]
- the crosstalk characteristic of the first sample is 2.32%
- the crosstalk characteristic of the third sample is 0.12%. %Met. That is, it can be seen that crosstalk is significantly reduced in the third sample compared to the first sample. Also, it can be seen that the third sample has a lower dark current than the first sample.
- 11A to 11H are cross-sectional views for explaining an example of the manufacturing process of the light-receiving element array 1A described above, and are cross-sectional views corresponding to the cross-sectional plane of FIG.
- a mask insulating film 43 is formed on the entire exposed surface by plasma CVD, LPCVD, MOCVD, sputtering, or the like.
- a portion of the insulating film 43 covering the surface (upper surface) of the contact material layer 42 is removed by photolithography and etching.
- an opening 43 a for forming the p-type region 8 is formed in the insulating film 43 .
- the contact material layer 42 is patterned by photolithography and etching.
- the contact layer 7 having an annular shape in plan view is formed on each first window layer 5 ⁇ /b>A so as to be in contact with the peripheral portion of the surface of the p-type region 8 .
- a semiconductor laminated structure 20 including the buffer layer 3, the light absorbing layer 4, the window layer 5 and the n-type layer 6, and the contact layer 7 is obtained.
- an insulating material film 44 which is the material film of the insulating film 10, is formed on the entire exposed surface by plasma CVD, LPCVD, MOCVD, sputtering, or the like.
- contact holes 11 are formed in the insulating material film 44 for each window layer 5 by photolithography and etching, exposing a portion of the contact layer 7 . Further, of the insulating material film 44 on the four corner portions of the surface of the buffer layer 3, portions other than the vicinity of the chamfered portion 4a of the light absorption layer 4 are removed. As a result, the insulating film 10 having the chamfered portions 10a at the four corner portions is obtained. As a result, four corner portions of the surface of the buffer layer 3 are exposed.
- the substrate 2 is thinned by grinding the substrate 2 from the second main surface 2b side. Then, the second electrode 13 is formed on the thinned second main surface 2b of the substrate 2 . Thereby, a light receiving element array 1A as shown in FIG. 19 is obtained.
- the light receiving element arrays 1 and 1A include 16 light receiving elements 30, but the light receiving element arrays 1 and 1A only need to include a plurality of light receiving elements.
- the number of elements can be set arbitrarily.
- the plurality of light receiving elements 30 are arranged two-dimensionally, they may be arranged one-dimensionally.
- the first p-type region 8 has a circular shape in plan view, it may be a quadrangle (square, rectangle, etc.) or a polygon such as a regular hexagon in plan view.
- each conductivity type of the n-type substrate 2, the n-type buffer layer 3, the n-type window layer 5 and the n-type n-type layer 6, and the p-type contact The conductivity types of layer 7, p-type first p-type region 8 and p-type second p-type region 9 may be reversed. That is, the n-type portion may be p-type, and the p-type portion may be n-type.
- Reference Signs List 1 1A light receiving element array 2 substrate 3 buffer layer 4 light absorption layer 4a chamfered portion 5 window layer 6 n-type layer 6a chamfered portion 7 contact layer 8 first p-type region (p-type region) 9 second p-type region 10 insulating film 10a chamfered portion 11 contact hole 12 first electrode 13 second electrode 14 third electrode 15 bonding pad 16 wiring 17, 18 mark 20 semiconductor laminated structure 30 light receiving element 41 window material layer 42 contact material layer 43 insulating film 43 insulating material film 50 separation trench 91 first portion 92 second portion
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Abstract
Description
本開示の一実施形態は、基板と、前記基板上に形成された半導体積層構造とを含み、前記半導体積層構造は、前記基板の上方に配置された光吸収層と、前記光吸収層上に互いに離間して形成された複数の第1導電型の窓層とを含み、前記半導体積層構造内には、前記窓層毎に、当該窓層における前記光吸収層とは反対側の表面から前記光吸収層内に延びた第1の第2導電型領域が形成されており、前記光吸収層内には、平面視において前記複数の窓層の各々を取り囲むように配置され、前記光吸収層における前記基板とは反対側の表面から前記光吸収層における前記基板側の表面に向かって延びた第2の第2導電型領域が形成されている、受光素子アレイを提供する。
以下では、本開示の実施形態を、添付図面を参照して詳細に説明する。
2 基板
3 バッファ層
4 光吸収層
4a 面取り部
5 窓層
6 n型層
6a 面取り部
7 コンタクト層
8 第1p型領域(p型領域)
9 第2p型領域
10 絶縁膜
10a 面取り部
11 コンタクト孔
12 第1電極
13 第2電極
14 第3電極
15 ボンディングパッド
16 配線
17,18 マーク
20 半導体積層構造
30 受光素子
41 窓材料層
42 コンタクト材料層
43 絶縁膜
43 絶縁材料膜
50 分離溝
91 第1部分
92 第2部分
Claims (18)
- 基板と、
前記基板上に形成された半導体積層構造とを含み、
前記半導体積層構造は、
前記基板の上方に配置された光吸収層と、
前記光吸収層上に互いに離間して形成された複数の第1導電型の窓層とを含み、
前記半導体積層構造内には、前記窓層毎に、当該窓層における前記光吸収層とは反対側の表面から前記光吸収層内に延びた第1の第2導電型領域が形成されており、
前記光吸収層内には、平面視において前記複数の窓層の各々を取り囲むように配置され、前記光吸収層における前記基板とは反対側の表面から前記光吸収層における前記基板側の表面に向かって延びた第2の第2導電型領域が形成されている、受光素子アレイ。 - 前記第2の第2導電型領域は、前記光吸収層における前記基板とは反対側の表面から前記光吸収層の厚さ途中まで延びている、請求項1に記載の受光素子アレイ。
- 前記第2の第2導電型領域は、前記光吸収層を貫通している、請求項1に記載の受光素子アレイ。
- 基板と、
前記基板上に形成された半導体積層構造とを含み、
前記半導体積層構造は、
前記基板の上方に配置された光吸収層と、
前記光吸収層上に互いに離間して形成された複数の第1導電型の窓層とを含み、
前記半導体積層構造内には、前記窓層毎に、当該窓層における前記光吸収層とは反対側の表面から前記光吸収層内に延びた第2導電型領域が形成されており、
前記光吸収層には、平面視において前記複数の窓層の各々を取り囲むように配置され、前記光吸収層における前記基板とは反対側の表面から前記光吸収層における前記基板側の表面に向かって延びた分離溝が形成されている、受光素子アレイ。 - 前記分離溝は、前記光吸収層を厚さ方向に貫通している、請求項4に記載の受光素子アレイ。
- 前記光吸収層上に、前記複数の窓層を覆うように形成された絶縁膜と、
前記窓層毎に設けられ、前記絶縁膜上に配置された複数の第1電極とを含み、
前記各第1電極は、対応する前記第1の第2導電型領域に電気的に接続されている、請求項1~3のいずれか一項に記載の受光素子アレイ。 - 前記光吸収層上に、前記複数の窓層を覆うように形成された絶縁膜と、
前記窓層毎に設けられ、前記絶縁膜上に配置された複数の第1電極とを含み、
前記各第1電極は、対応する前記第2導電型領域に電気的に接続されている、請求項4または5に記載の受光素子アレイ。 - 前記絶縁膜が、予め設定される波長の光の反射を防止する光反射防止膜である、請求項6または7に記載の受光素子アレイ。
- 前記第1電極が平面視で無端状である、請求項6または7に記載の受光素子アレイ。
- 前記基板の第2主面上に形成された第2電極を含む、請求項1~9のいずれか一項に記載の受光素子アレイ。
- 前記複数の窓層は、平面視において、行列状に配置されている、請求項1~10のいずれか一項に記載の受光素子アレイ。
- 前記半導体積層構造は、前記基板と前記光吸収層との間に形成された第1導電型のバッファ層を含む、請求項1~11のいずれか一項に記載の受光素子アレイ。
- 前記バッファ層は、前記基板とは反対側の表面の一部に露出面を有しており、
前記露出面上に第3電極が形成されている、請求項12に記載の受光素子アレイ。 - 前記基板が、n型InP基板であり、
前記光吸収層がノンドープのInGaAs層であり、
前記窓層がn型InP層である、請求項1~12のいずれか一項に記載の受光素子アレイ。 - 前記基板が、n型InP基板であり、
前記バッファ層がn型InP層であり、
前記光吸収層がノンドープのInGaAs層であり、
前記窓層がn型InP層である、請求項12または13に記載の受光素子アレイ。 - 基板上に、光吸収層と前記光吸収層上に互いに離間して形成された複数の第1導電型の窓層とを含む半導体積層構造を形成する工程と、
前記半導体積層構造内に、前記窓層毎に、当該窓層における前記光吸収層とは反対側の表面から前記光吸収層内に延びた第1の第2導電型領域を形成する工程と、
平面視において前記複数の窓層の各々を取り囲むように配置され、前記光吸収層における前記基板とは反対側の表面から前記光吸収層における前記基板側の表面に向かって延びた第2の第2導電型領域を形成する工程とを含む、受光素子アレイの製造方法。 - 前記第1の第2導電型領域を形成する工程と前記第2の第2導電型領域を形成する工程とが、同一工程で実施される、請求項16に記載の受光素子アレイの製造方法。
- 前記光吸収層上に前記複数の窓層を覆うように、絶縁膜を形成する工程と、
前記窓層毎に、前記第1の第2導電型領域に電気的に接続される第1電極を前記絶縁膜上に形成する工程と、
前記基板における前記半導体積層構造とは反対側の表面に第2電極を形成する工程とをさらに含む、請求項16または17に記載の受光素子アレイの製造方法。
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JP2011137836A (ja) * | 2011-03-17 | 2011-07-14 | Sumitomo Electric Ind Ltd | 水分検出装置、生体中水分検出装置、自然産物中水分検出装置、および製品・材料中水分検出装置 |
JP2012244124A (ja) * | 2011-05-24 | 2012-12-10 | Sumitomo Electric Ind Ltd | 受光素子アレイ、その製造方法および検出装置 |
JP2014003083A (ja) * | 2012-06-15 | 2014-01-09 | Mitsubishi Electric Corp | フォトダイオードアレイ |
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JP2011137836A (ja) * | 2011-03-17 | 2011-07-14 | Sumitomo Electric Ind Ltd | 水分検出装置、生体中水分検出装置、自然産物中水分検出装置、および製品・材料中水分検出装置 |
JP2012244124A (ja) * | 2011-05-24 | 2012-12-10 | Sumitomo Electric Ind Ltd | 受光素子アレイ、その製造方法および検出装置 |
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