WO2022196435A1

WO2022196435A1 - Thin-film transistor and method for manufacturing thin-film transistor

Info

Publication number: WO2022196435A1
Application number: PCT/JP2022/009971
Authority: WO
Inventors: 達也戸田
Original assignee: Ａｇｃ株式会社
Priority date: 2021-03-15
Filing date: 2022-03-08
Publication date: 2022-09-22

Abstract

The present invention is a thin-film transistor having an oxide semiconductor layer. The oxide semiconductor layer has a ZnGaO-based oxide in which the molar ratio of Zn with respect to the total of Ga (gallium) and Zn (zinc) is 35% inclusive to 50% exclusive. If a crystal in which the Scherrer diameter L obtained by equation (1) is 5 nm or less is referred to as a nanocrystal in an X-ray diffraction measurement of the oxide semiconductor layer, the oxide semiconductor layer contains a nanocrystal with a ZnGa₂O₄ structure, and the (220) plane of the nanocrystal is oriented in a direction orthogonal to the thickness of the oxide semiconductor layer. (1): L = Kλ/(βcosθ) (here, K is the Scherrer constant, λ is the X-ray wavelength, β is the half-value width, and θ is the peak position)

Description

Thin film transistor and thin film transistor manufacturing method

The present invention relates to a thin film transistor and a method for manufacturing a thin film transistor.

In recent years, oxide semiconductors have attracted attention as a semiconductor material that can replace silicon. For example, InGaZnO-based oxide semiconductors (so-called IGZO) are characterized by being transparent and having high mobility, and are being applied as active layers in next-generation thin film transistors (TFTs). In addition, IGZO has a feature of low off-state current, and its application to low power consumption displays has also started.

On the other hand, IGZO is known to have a problem of photoleakage current, which increases off-state current, and a problem of negative shift in threshold voltage when a negative voltage is applied under light irradiation (for example, non-patent Reference 1). Therefore, for example, when IGZO is applied to a TFT, leakage current increases, which may cause problems such as poor display of the display.

In order to deal with such problems, ZnGaO-based materials typified by ZnGa ₂ O ₄ are newly attracting attention (for example, Patent Document 1).

WO2017/150351

In general, when forming a pattern of an oxide semiconductor layer in a TFT, a mask made of a resist is used to perform an etching process (first process) on the oxide semiconductor layer, and then a process of peeling off the resist (second process). 2 processing) is required.

The first treatment may be performed by dry etching using plasma treatment, but since it is performed in a vacuum apparatus, the process load is large, and wet etching using acid is industrially desirable. For example, IGZO is wet etched with oxalic acid. Also in the second process, the resist can be removed by oxygen plasma treatment, but the process load is large and resist residue is generated as in dry etching, so stripping with an organic stripping solution is desirable.

However, according to the findings of the inventors of the present application, the amorphous ZnGa ₂ O ₄ layer has poor chemical durability, and is easily etched with acid in the first treatment, but in the second treatment, the stripping solution There is a problem that it dissolves in Therefore, it is considered difficult to apply an amorphous ZnGa ₂ O ₄ layer as the active layer of a TFT.

In general, the chemical durability of thin films is improved by crystallization. Therefore, in order to deal with such problems, it is conceivable to crystallize the ZnGa ₂ O ₄ layer. Incidentally, ZnGa ₂ O ₄ has a spinel crystal structure.

However, ZnGa ₂ O ₄ crystals are known to have very high chemical durability. In fact, when the inventors of the present application attempted acid etching of a sufficiently crystallized ZnGa ₂ O ₄ layer, it was found that even if immersion in a heated aqua regia etchant (mixed acid of hydrochloric acid and nitric acid), let alone oxalic acid, , was hardly etched. Therefore, in Non-Patent Document 2, for example, the crystallized ZnGa ₂ O ₄ layer is etched by chlorine-based plasma treatment. As described above, the dry method imposes a large process load and is industrially undesirable.

Thus, assuming a practical manufacturing process, many problems remain in patterning a ZnGa ₂ O ₄ layer and applying it as an active layer of a TFT.

The present invention has been made in view of such a background, and an object of the present invention is to provide a TFT having a properly patterned ZnGaO-based oxide semiconductor layer. Another object of the present invention is to provide a method of manufacturing a TFT having a patterned ZnGaO-based oxide semiconductor layer by a practical process.

In the present invention, a thin film transistor having an oxide semiconductor layer,
The oxide semiconductor layer has a ZnGaO-based oxide in which the molar ratio of Zn to the total of Ga (gallium) and Zn (zinc) is 35% or more and less than 50%,
In the X-ray diffraction 2θ/θ measurement of the oxide semiconductor layer, when a crystal having a Scherrer diameter L of 5 nm or less determined by the following formula (1) is referred to as a nanocrystal,

L=Kλ/(β cos θ) (1) Equation (where K is the Scherrer constant, λ is the X-ray wavelength, β is the half width, and θ is the peak position)

The thin film transistor is provided, wherein the oxide semiconductor layer includes nanocrystals having a ZnGa ₂ O ₄ structure, and the (220) plane of the nanocrystals is oriented perpendicular to the thickness direction of the oxide semiconductor layer. .

Further, in the present invention, there is provided a method for manufacturing a thin film transistor having a patterned oxide semiconductor layer, comprising:
The oxide semiconductor layer is
(1) In an atmosphere with an oxygen concentration of more than 1 vol%, by sputtering using a ZnGaO-based oxide target, the molar ratio of Zn to the total of Ga (gallium) and Zn (zinc) is 35% or more and less than 50% ZnGaO (2) using a resist as a mask, wet etching the film to form a pattern of an oxide semiconductor layer; (3) using a stripping solution to wet the resist; A method of manufacture is provided, formed by removing.

The present invention can provide a TFT having a properly patterned ZnGaO-based oxide semiconductor layer. In addition, the present invention can provide a method of manufacturing a TFT having a patterned ZnGaO-based oxide semiconductor layer using a practical process.

FIG. 4 is a diagram schematically showing an example of steps up to forming a patterned oxide semiconductor layer on a substrate to be processed; FIG. 4 is a diagram schematically showing an example of steps up to forming a patterned oxide semiconductor layer on a substrate to be processed; FIG. 4 is a diagram schematically showing an example of steps up to forming a patterned oxide semiconductor layer on a substrate to be processed; 1 is a cross-sectional view schematically showing an example of the configuration of a TFT according to one embodiment of the present invention; FIG. 1 is a diagram schematically showing an example flow of a method for manufacturing a TFT according to an embodiment of the present invention; FIG. FIG. 4 is a diagram schematically showing one step of a method of manufacturing a TFT according to one embodiment of the present invention; FIG. 4 is a diagram schematically showing one step of a method of manufacturing a TFT according to one embodiment of the present invention; FIG. 4 is a diagram schematically showing one step of a method of manufacturing a TFT according to one embodiment of the present invention; FIG. 4 is a diagram schematically showing one step of a method of manufacturing a TFT according to one embodiment of the present invention; It is the figure which showed collectively the result of the X-ray-diffraction 2(theta)/(theta) measurement in each sample. It is the figure which showed an example of the TEM observation result in the surface of sample 1A. It is the figure which showed an example of the TEM observation result in the surface of sample 11A. It is the figure which showed an example of the electron-beam-diffraction-analysis result obtained in the surface of the sample 1A. It is the figure which showed an example of the electron-beam-diffraction-analysis result obtained in the surface of sample 11A. It is the figure which showed an example of the TEM observation result in the cross section of the sample 1A. It is the figure which showed an example of the TEM observation result in the cross section of sample 11A. It is the figure which showed an example of the electron beam diffraction analysis result obtained in the cross section of the sample 1A. It is the figure which showed an example of the electron beam diffraction analysis result obtained in the cross section of the sample 11A. FIG. 4 is a diagram showing TFT characteristics in a dark state obtained in element 1; FIG. 10 is a diagram showing TFT characteristics in a dark state obtained in element 12; FIG. 3 is a diagram showing changes in TFT characteristics in a negative gate bias thermal stress (NBTIS) test under light irradiation of device 1; FIG. 10 is a diagram showing changes in TFT characteristics in the NBTIS test of element 12;

An embodiment of the present invention will be described below with reference to the drawings.

In order to better understand the features of a TFT according to one embodiment of the present invention, first, conventional problems will be described with reference to FIGS. 1 to 3. FIG.

1 to 3 schematically show steps of forming a patterned oxide semiconductor layer on a substrate to be processed.

As shown in FIG. 1, when forming a patterned oxide semiconductor layer, first, an oxide semiconductor layer 2 before patterning is formed on a substrate 1 to be processed. Moreover, a resist 3 is provided on the oxide semiconductor layer 2 in a desired pattern.

Next, using the resist 3 as a mask, the oxide semiconductor layer 2 is etched (etching process). Thereby, a pattern of the resist 3 and the oxide semiconductor layer 2 is formed as shown in FIG.

Next, the resist 3 is peeled off (peeling step) to obtain the pattern of the oxide semiconductor layer 2 as shown in FIG.

Here, when a practical manufacturing process is taken into consideration, it is desirable that the etching process of the oxide semiconductor layer 2 and the stripping process of the resist 3 be performed by a wet method. This is because the dry method requires a vacuum apparatus with a complicated structure, and also has a large process load and a high production cost.

However, when the oxide semiconductor layer 2 is composed of an amorphous ZnGa ₂ O ₄ layer, the inventors of the present application have found that the ZnGa ₂ O ₄ layer dissolves in the stripping solution when the resist 3 is stripped. Noticed. Therefore, in the wet method, it is considered difficult to remove the resist 3 from the amorphous ZnGa ₂ O ₄ layer in the removing step.

In order to deal with such problems, it is conceivable to crystallize the ZnGa ₂ O ₄ layer. However, ZnGa ₂ O ₄ crystals, which have a spinel structure, are known to have very high chemical durability, and the inventors of the present application attempted acid etching of a well-crystallized ZnGa ₂ O ₄ layer. However, the ZnGa ₂ O ₄ crystal layer was not etched even by using aqua regia etchant (mixed acid of hydrochloric acid and nitric acid), which is a strong acid. Thus, the ZnGa ₂ O ₄ layer, whether amorphous or crystalline, has the problem that it is difficult to properly pattern it by a wet method. Therefore, it is considered difficult to manufacture a TFT having a ZnGa ₂ O ₄ layer by a practical manufacturing process including a wet method.

The inventors of the present application have noticed such a problem, and have devoted themselves to research and development on methods for patterning a ZnGaO-based oxide semiconductor layer using a wet method. The inventors of the present application have found that when the amount of zinc contained in the ZnGaO system is increased above the stoichiometric composition of ZnGa ₂ O ₄ (Zn = 33 mol%), the crystal size is refined, and We have found that strongly oriented ZnGa ₂ O ₄ nanocrystals can be obtained.

In addition, the inventors of the present application have found that such a layer containing nanocrystals can be properly etched by the wet etching process described above, and has significant resistance to stripping solutions in the stripping process described above. The invention of the present application has been achieved.

Therefore, in one embodiment of the invention,
A thin film transistor having an oxide semiconductor layer,
The oxide semiconductor layer has a ZnGaO-based oxide in which the molar ratio of Zn to the total of Ga (gallium) and Zn (zinc) is 35% or more and less than 50%,
In the X-ray diffraction 2θ/θ measurement of the oxide semiconductor layer, when a crystal having a Scherrer diameter L of 5 nm or less determined by the following formula (1) is referred to as a nanocrystal,

L=Kλ/(β cos θ) (1) Formula
The thin film transistor is provided, wherein the oxide semiconductor layer includes nanocrystals having a ZnGa ₂ O ₄ structure, and the (220) plane of the nanocrystals is oriented perpendicular to the thickness direction of the oxide semiconductor layer. .

In the above formula (1), K is the Scherrer constant, λ is the X-ray wavelength, β is the half width, and θ is the peak position. For example, when the X-ray wavelength λ is 0.154 nm, the Scherrer constant K is 0.9.

In the TFT according to one embodiment of the present invention, the oxide semiconductor layer has a molar ratio of Zn to the total of Ga (gallium) and Zn (zinc) (hereinafter expressed as "Zn/(Ga+Zn)") of 35% or more; Less than 50% ZnGaO based oxide is used.

By setting Zn/(Ga+Zn) to 35% or more in the ZnGaO-based oxide layer, nanocrystals in which the ZnGa ₂ O ₄ (220) planes are oriented perpendicular to the thickness direction can be obtained as described above.

An oxide semiconductor layer containing such nanocrystals can be properly etched with an etchant in a wet etching process.

Further, in one embodiment of the present invention, it is possible to significantly suppress the problem that the oxide semiconductor layer dissolves in the stripping solution in the wet stripping process described above.

Due to the above characteristics, the TFT according to one embodiment of the present invention can provide a TFT including a ZnGaO-based oxide semiconductor layer that is appropriately patterned by a wet method.

Note that in the TFT according to one embodiment of the present invention, Zn/(Ga+Zn) in the ZnGaO-based oxide semiconductor layer is suppressed to less than 50%. This is because, as will be described later, when Zn/(Ga+Zn) exceeds 50% in the oxide semiconductor layer, the characteristics of the TFT are degraded.

Also, in one embodiment of the present invention,
A method for manufacturing a thin film transistor having a patterned oxide semiconductor layer, comprising:
The oxide semiconductor layer is
(1) In an atmosphere with an oxygen concentration of more than 1 vol%, by sputtering using a ZnGaO-based oxide target, the molar ratio of Zn to the total of Ga (gallium) and Zn (zinc) is 35% or more and less than 50% ZnGaO (2) using a resist as a mask, wet etching the film to form a pattern of an oxide semiconductor layer; (3) using a stripping solution to wet the resist; A method of manufacture is provided, formed by removing.

In the manufacturing method according to one embodiment of the present invention, by setting Zn/(Ga+Zn) to 35% or more in the ZnGaO-based oxide film formed by sputtering, as described above, fine and crystal plane Oriented ZnGa ₂ O ₄ nanocrystals are obtained.

Therefore, this film can be properly patterned in the wet etching process through the resist. In addition, in the subsequent step of removing the resist using a stripping solution, the problem of dissolution of the film in the stripping solution can also be significantly suppressed.

In addition, in the manufacturing method according to one embodiment of the present invention, the ZnGaO-based oxide film is formed in an environment where the oxygen concentration exceeds 1 vol %. This is because the obtained film becomes amorphous when the film is formed under the condition that the oxygen concentration is 1 vol % or less. That is, by forming a ZnGaO-based oxide film under the condition that the oxygen concentration exceeds 1 vol %, a film containing nanocrystals can be properly obtained.

(TFT according to one embodiment of the present invention)
Next, one configuration example of a TFT according to one embodiment of the present invention will be described more specifically with reference to the drawings.

FIG. 4 schematically shows an example of a cross section of a TFT according to one embodiment of the present invention.

As shown in FIG. 4, a TFT (hereinafter referred to as a "first TFT") 100 according to one embodiment of the present invention includes a substrate 110, a barrier layer 120, a gate electrode 130, a gate insulating film 140, an oxide layer 140, and an oxide film. A semiconductor layer 150, a first electrode (source or drain) 160, a second electrode (drain or source) 162, and a passivation layer 180 are arranged.

The substrate 110 is, for example, an insulating substrate such as a glass substrate, a ceramic substrate, a plastic substrate, or a resin substrate. Substrate 110 may also be a transparent substrate.

The barrier layer 120 is composed of, for example, silicon oxide, silicon oxynitride, silicon nitride, alumina, or a combination thereof. Barrier layer 120 may be a multilayer structure.

However, the barrier layer 120 is not an essential component, and may be omitted if unnecessary.

The gate insulating film 140 is composed of an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, and alumina. The gate insulating film 140 may have a multilayer structure.

The oxide semiconductor layer 150 is composed of a ZnGaO-based oxide. The thickness of the oxide semiconductor layer 150 ranges, for example, from 30 nm to 90 nm.

The first and

second electrodes

160, 162 and the gate electrode 130 are composed of metals such as titanium, molybdenum, aluminum, copper and silver, or other conductive materials. The first and

second electrodes

160, 162 and the gate electrode 130 may be multilayer structures.

The passivation layer 180 has a role of protecting the device and is composed of, for example, silicon oxide, silicon oxynitride, silicon nitride, and alumina. Passivation layer 180 may be a multilayer structure.

Here, in the first TFT 100, the oxide semiconductor layer 150 has the characteristics described above.

That is, the oxide semiconductor layer 150 is a ZnGaO-based oxide layer with Zn/(Ga+Zn) of 35% or more and less than 50%, and is characterized by containing ZnGa ₂ O ₄ nanocrystals.

Therefore, the first TFT 100 can be manufactured by a practical process including a wet etching method. That is, the oxide semiconductor layer 150 can be patterned through a conventional wet etching process using lithographic methods and a conventional wet stripping process for photoresist.

Note that when a layer of ZnGa 2 O 4 having a stoichiometric composition of Zn/(Ga+Zn)=33%, that is, a layer of ZnGa ₂ O ₄ having a stoichiometric composition is formed as the oxide semiconductor layer, the crystal plane in the direction perpendicular to the thickness of the layer is ZnGa ₂ O ₄ Oriented in the [111] direction.

In contrast, in the first TFT 100, the crystal planes of the nanocrystals included in the oxide semiconductor layer 150 in the direction perpendicular to the thickness are oriented in the ZnGa ₂ O ₄ [220] direction.

(Method for manufacturing a TFT according to an embodiment of the present invention)
Next, a method of manufacturing a TFT according to an embodiment of the present invention will be described with reference to FIG.

FIG. 5 schematically shows the flow of a TFT manufacturing method (hereinafter referred to as "first manufacturing method") according to one embodiment of the present invention.

As shown in FIG. 5, the first manufacturing method includes:
a step of providing a gate electrode and a gate insulating film on the substrate (step S110);
placing an oxide semiconductor layer on the gate insulating film (step S120);
patterning the oxide semiconductor layer (step S130);
placing a first electrode and a second electrode on the patterned oxide semiconductor layer (step S140);
have

Each step will be explained below. Here, the above-described first TFT 100 is assumed as the TFT manufactured by the first manufacturing method. Therefore, the reference numerals shown in FIG. 4 are used when representing each member of the TFT.

(Step S110)
First, substrate 110 is prepared. The substrate 110 is not particularly limited, but may be, for example, a glass substrate.

A single-layer or multiple-layer barrier layer 120 may be provided on the substrate 110 . Barrier layer 120 may be composed of, for example, silicon nitride and/or silicon oxide.

Next, a material for the gate electrode is deposited on the substrate 110 (or barrier layer 120).

Materials for the gate electrode include, for example, chromium (Cr), molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), tantalum (Ta), titanium (Ti), or composite materials containing them and / or may be composed of an alloy.

The method of installing the material for the gate electrode is not particularly limited. The material for the gate electrode may be formed by conventional film forming methods such as sputtering and vapor deposition.

The gate electrode 130 is then formed by patterning the material for the gate electrode. Note that the gate electrode 130 may be a laminated film.

The thickness of the gate electrode 130 ranges, for example, from 30 nm to 600 nm.

Next, a gate insulating film 140 is formed on the gate electrode 130 . The gate insulating film 140 may be made of silicon oxide, silicon nitride, or the like.

The method of forming the gate insulating film 140 is not particularly limited. The gate insulating film 140 may be deposited using deposition techniques such as sputtering, pulse laser deposition, normal pressure CVD, low pressure CVD, and plasma CVD. The thickness of the gate insulating film 140 ranges, for example, from 30 nm to 600 nm.

After that, the gate insulating film 140 is processed into a predetermined pattern.

FIG. 6 schematically shows an example of the cross-sectional structure obtained after step S110.

(Step S120)
Next, an unpatterned oxide semiconductor layer (hereinafter referred to as “unprocessed film”) is provided on the gate insulating film 140 .

FIG. 7 schematically shows an example of a state in which an untreated film 149 is placed on the gate insulating film 140. FIG.

The untreated film 149 is composed of a ZnGaO-based material in which Zn/(Ga+Zn) is 35% or more and less than 50%, as described above.

The untreated film 149 is deposited using, for example, a sputtering method. As a sputtering target, for example, a ZnGaO-based material with Zn/(Ga+Zn) of 35% or more and less than 50% is used.

Here, the formation of the untreated film 149 may be performed while heating the substrate 110 to less than 100° C., or may be performed at room temperature without heating the substrate 110 .

Zinc in the ZnGaO-based oxide is easily volatilized, and when the untreated film 149 is formed while the substrate 110 is heated to 100° C. or higher, only the zinc component volatilizes. ) ratio becomes less than 35%, and a ZnGa ₂ O ₄ crystal layer, which is difficult to etch with acid, tends to precipitate. On the other hand, if the film formation is performed at room temperature while heating the substrate 110 to less than 100° C. or without heating, the nano-crystallized untreated film 149 can be stably obtained.

Also, the sputtering process is performed under a relatively high oxygen partial pressure, specifically in an atmosphere with an oxygen concentration of more than 1%.

This is because the unprocessed film 149 obtained by sputtering using the above target in an environment with a low oxygen partial pressure is an amorphous film. That is, by performing sputtering in an atmosphere with an oxygen concentration of more than 1%, a layer containing nanocrystals as described above can be obtained.

The oxygen concentration is preferably 5% or more, for example 10% or more.

As described above, in the untreated film 149 formed in this step, the crystal planes of the nanocrystals contained in the untreated film 149 are oriented in the ZnGa ₂ O ₄ [220] direction in the direction perpendicular to the thickness.

Although the thickness of the untreated film 149 is not particularly limited, it ranges from 30 nm to 90 nm, for example.

After forming the untreated film 149, the substrate 110 may be annealed at 300° C. or higher.

Annealing temperature of 350-400°C is desirable. This is because the annealing treatment at 350° C. or higher further improves the stripping solution resistance of the untreated film 149 in the stripping step of the next step S130. On the other hand, if the annealing temperature exceeds 400.degree. Annealing may be performed in air, oxygen, nitrogen, or vacuum, but from the viewpoint of production costs, it is desirable to perform annealing in a vacuum apparatus or in an air atmosphere that does not require atmosphere replacement.

(Step S130)
The untreated film 149 is then patterned. Thereby, an oxide semiconductor layer 150 having a predetermined pattern is obtained.

Here, the untreated film 149 has nanocrystals rather than an amorphous film.

Therefore, in the first manufacturing method, a wet method can be applied as the pattern processing of the unprocessed film 149 . That is, in the first manufacturing method, in the pattern processing of the unprocessed film 149, the etching process and the stripping process as shown in FIGS. 1 to 3 can be performed wet.

The etchant for the untreated film 149 is not particularly limited, but for example, an oxalic acid solution may be used. Also, a mixed solution of dimethylsulfoxide and N-methyl-2-pyrrolidone, for example, can be used as a photoresist stripping solution. These etchants and removers are commonly used in wet pattern processing methods using lithography.

FIG. 8 schematically shows a state in which the untreated film 149 is patterned and the oxide semiconductor layer 150 is formed.

(Step S140)
Next, a conductive film for the first electrode 160 and the second electrode 162 is placed on the oxide semiconductor layer 150 and patterned. The first electrode 160 and the second electrode 162 are, for example, drain and source electrodes, respectively, or vice versa.

The conductive films of the first electrode 160 and the second electrode 162 are placed and patterned so as to be in ohmic contact with at least a portion of the oxide semiconductor layer 150 .

Here, a combination of a general photolithography process/etching process can be used for pattern processing of the conductive film. This is because, as described above, the oxide semiconductor layer 150 has resistance to a general resist remover used in the process of electrode patterning.

In addition, for pattern processing of the conductive film, dry etching by plasma processing using a fluorine-based gas or chlorine-based gas, or wet etching using a weak acid etchant may be used. The weak acid etchant includes, for example, a mixed aqueous solution of hydrogen peroxide and an organic acid, or a mixed aqueous solution of hydrogen peroxide and an organic acid to which a trace amount of a fluorine compound (such as sodium fluoride) is added. The oxide semiconductor layer 150 obtained from the nano-crystallized untreated film 149 has resistance not only to the resist stripping solution but also to the weak acid etchant as described above.

The first electrode 160 and the second electrode 162 may each be chromium, molybdenum, aluminum, copper, silver, tantalum, titanium, or composite materials and/or alloys containing them. Also, the first electrode 160 and the second electrode 162 may be laminated films.

Note that the first electrode 160 and the second electrode 162 can also be made of a transparent conductive film, like the gate electrode 130 .

FIG. 9 schematically shows a state in which a first electrode 160 and a second electrode 162 are placed so as to be in contact with the oxide semiconductor layer 150 .

Then, if necessary, a passivation layer 180 is placed over the first electrode 160 and the second electrode 162 (see FIG. 4 above).

The passivation layer 180 may be deposited using deposition techniques such as sputtering, pulse laser deposition, normal pressure CVD, reduced pressure CVD, and plasma CVD.

The thickness of the passivation layer 180 ranges, for example, from 30 nm to 600 nm.

After that, if necessary, a contact hole 185 penetrating the passivation layer 180 and the gate insulating film 140 is formed so as to allow contact with the first electrode 160, the second electrode 162, and the gate electrode 130. good.

Through the above steps, the first TFT 100 can be manufactured.

In the first manufacturing method, a conventional wet method can be applied when patterning the oxide semiconductor layer 150 . Therefore, in the first manufacturing method, it is not necessary to apply a dry process to the patterning process of the oxide semiconductor layer 150, and the TFT can be manufactured by a process with higher productivity.

An embodiment of the present invention has been described above. However, the above description is merely an example, and the TFT and the manufacturing method thereof according to one embodiment of the present invention have different configurations as long as the ZnGaO-based oxide semiconductor having the characteristics described above is used. may

For example, in one embodiment of the present invention, a ZnGaO-based oxide semiconductor is applied to a bottom-gate TFT. However, the ZnGaO-based oxide semiconductor may be applied to, for example, top-gate TFTs.

In addition to this, various changes and modifications are possible.

Next, an embodiment of the present invention will be described. In the following description, Example 1C is an example. Example 12C, on the other hand, is a comparative example.

(Example 1)
A ZnGaO-based oxide layer was formed on a 20 mm square quartz substrate with a thickness of 0.7 mm by the following method.

In a chamber evacuated to 0.5 Pa, a ZnGaO-based oxide layer was formed on one surface of a quartz substrate by RF magnetron sputtering. A ZnGaO target with a diameter of 50.8 mm was used as the target. In the ZnGaO target, Zn/(Ga+Zn) was 40%.

The supplied gas was a mixed gas of oxygen and argon, and the oxygen partial pressure was 10 vol%. RF power was 200W. Note that the quartz substrate was not heated during the film formation.

The thickness of the ZnGaO-based oxide layer was set to 150 nm (target value).

After the film formation, a quartz substrate having a ZnGaO-based oxide layer (hereinafter referred to as "sample 1") was obtained.

(Example 11)
A quartz substrate having a ZnGaO-based oxide layer (hereinafter referred to as "Sample 11") was prepared in the same manner as in Example 1.

However, in this sample 11, ZnGaO with Zn/(Ga+Zn) of 33% was used as the target.

(Example 12)
A quartz substrate having a ZnGaO-based oxide layer (hereinafter referred to as "Sample 12") was prepared in the same manner as in Example 1.

However, in this sample 12, ZnGaO with 50% Zn/(Ga+Zn) was used as the target.

(Example 13)
A quartz substrate having a ZnGaO-based oxide layer (hereinafter referred to as "Sample 13") was prepared in the same manner as in Example 1.

However, in this sample 13, ZnGaO with 25% Zn/(Ga+Zn) was used as the target.

(Example 21)
A quartz substrate having a ZnGaO-based oxide layer (hereinafter referred to as "Sample 21") was prepared in the same manner as in Example 1.

However, in this sample 21, the oxygen partial pressure contained in the supplied mixed gas was set to 1 vol%.

(Example 22)
A quartz substrate having a ZnGaO-based oxide layer (hereinafter referred to as "Sample 22") was prepared in the same manner as in Example 11.

However, in this sample 22, the oxygen partial pressure contained in the supplied mixed gas was set to 1 vol%.

(Example 23)
A quartz substrate having a ZnGaO-based oxide layer (hereinafter referred to as "Sample 23") was prepared in the same manner as in Example 12.

However, in this sample 23, the oxygen partial pressure contained in the supplied mixed gas was set to 1 vol%.

(Example 24)
A quartz substrate having a ZnGaO-based oxide layer (hereinafter referred to as "Sample 24") was prepared in the same manner as in Example 13.

However, in this sample 24, the oxygen partial pressure contained in the supplied mixed gas was set to 1 vol%.

(X-ray diffraction analysis)
Using each sample prepared by the above method, X-ray diffraction 2θ/θ measurement was performed.

Fig. 10 summarizes the obtained diffraction results. In FIG. 10, the results are shown as a matrix so that the relationship between the composition of the sample and the partial pressure of oxygen during preparation of the sample can be grasped. In each result, the peak near 2θ of about 20° is due to the quartz substrate rather than the ZnGaO-based oxide layer.

From the results obtained, when the oxygen partial pressure is 10 vol%, a peak is observed in all samples, indicating that the layer contains a crystalline component.

All of the obtained peaks were derived from ZnGa ₂ O ₄ .

On the other hand, when the oxygen partial pressure is as low as 1 vol%, no significant peak is observed in any sample except for sample 23, indicating that the layer is amorphous. It was found that in sample 23 with a high Zn content (Zn/(Ga+Zn)=50%), the layer was crystallized even at an oxygen partial pressure of 1 vol %.

In sample 11, sharp peaks were observed at 2θ positions corresponding to the (111), (222), and (333) planes of ZnGa ₂ O ₄ from the low angle side. That is, in the Zn ₂ Ga ₄ O layer of sample 11, the crystal plane perpendicular to the thickness direction was found to be strongly oriented in the [111] direction. The Scherrer diameter of sample 11 calculated using the formula (1) was about 36 nm.

On the other hand, in

samples

1 and 12, which had a higher Zn ratio than in sample 11, a broad peak was detected near 2θ of 31°. This 2θ corresponds to the ZnGa ₂ O ₄ (220) plane. That is, in

Samples

1 and 12, the crystal plane perpendicular to the thickness direction of the oxide layer is oriented in the ZnGa ₂ O ₄ [220] direction, which is different from that in Sample 11. rice field. The Scherrer diameters of

samples

1 and 12 calculated in the same manner as for sample 11 were about 4 nm, indicating that nanocrystals were obtained.

Furthermore, in sample 13 having a Zn ratio lower than that of sample 11, a slight peak was detected at the 2θ position corresponding to ZnGa ₂ O ₄ [111] as in sample 11. That is, it can be said that sample 13 has low crystallinity although the orientation direction of crystals contained in the oxide layer is the same as that of sample 11.

From the above results, Sample 1 and Sample 11, which contain ZnGaO-based oxide layers with a Zn ratio higher than the stoichiometric composition, yield ZnGa ₂ O ₄ nanocrystals, and the nanocrystals increase the thickness of the oxide layer. It was confirmed that the crystal plane perpendicular to the direction was oriented in [220].

Table 1 below summarizes the preparation conditions of each sample and the results of X-ray diffraction analysis.

(Example 1A)
A ZnGaO-based oxide layer was formed on the substrate by the same method as in Example 1 described above.

However, in Example 1A, a Si substrate (thickness 0.6 mm, 25 mm square) with a thermal oxide film having a thickness of 150 nm was used as the substrate. The thickness of the ZnGaO-based oxide layer was set to 50 nm (target value).

The obtained sample is called "Sample 1A".

(Example 11A)
In Example 11A, a sample (referred to as "Sample 11A") was prepared in a manner similar to Example 1A.

However, in Example 11A, the conditions described in Example 11 above were adopted as the film forming conditions for the ZnGaO-based oxide. Accordingly, sample 11A differs from sample 11 only in the substrate and the film thickness of the ZnGaO-based oxide.

(Transmission electron microscope (TEM) observation and electron diffraction analysis)
TEM observation and electron diffraction analysis were performed using Sample 1A and Sample 11A.

11 and 12 show TEM images of the ZnGaO-based oxide layers of Sample 1A and Sample 11A, respectively, observed from the surface side.

13 and 14 show electron beam diffraction images corresponding to the surface TEM images of FIGS. 11 and 12, respectively. These electron beam diffraction images in the surface direction are obtained by interference on crystal planes perpendicular to the substrate surface (that is, parallel to the thickness direction).

15 and 16 show TEM images of the ZnGaO-based oxide layers of Sample 1A and Sample 11A, respectively, observed from the cross-sectional direction.

Furthermore, FIGS. 17 and 18 show electron beam diffraction images corresponding to the cross-sectional TEM images of the ZnGaO-based oxide layer shown in FIGS. 15 and 16, respectively. These cross-sectional electron beam diffraction images are obtained by interference on crystal planes perpendicular to the cross section (that is, parallel to the depth direction of the paper).

From FIG. 11, it can be seen that the surface of the ZnGaO-based oxide of sample 1A is relatively uniform and is composed of nanocrystals such that clear crystal grains and grain boundaries cannot be visually recognized even at this magnification. On the other hand, from FIG. 12, in the ZnGaO-based oxide layer of sample 11A, most of the surface is occupied by an amorphous region, and relatively large crystal grains (20 nm or more) are partially observed. That is, the surface of the ZnGaO-based oxide layer of sample 11A contains large crystals, and has lower crystallinity and uniformity than sample 1A.

Also, as shown in FIG. 13, a ring-shaped electron beam diffraction pattern (Debye ring) was obtained in the electron beam diffraction image from the surface direction of sample 1A. From this result, it was found that the crystal planes parallel to the thickness direction contained in the ZnGaO-based oxide layer of sample 1A were not oriented in a specific direction.

As shown in FIG. 14, a ring-shaped electron beam diffraction pattern was also obtained for sample 11A, and it was found that the crystal planes parallel to the thickness direction were non-oriented, similar to sample 1A. However, the distance from the transmitted light positioned at the center of the electron beam diffraction image to each ring, that is, the ring radius is different from that of sample 1A shown in FIG. This indicates that sample 1A and sample 11A differ in the distance between crystal planes included in the ZnGaO-based oxide layer, that is, in the plane orientation. Also, the ring shape in FIG. 14 is more discrete than the ring shape in FIG. This indicates that the ZnGaO-based oxide layer of sample 11A has lower crystallinity than the ZnGaO-based oxide layer of sample 1A, similar to the TEM observation results of FIG.

Next, as shown in the cross-sectional TEM image of FIG. 15, in sample 1A, dense nanocrystals are formed relatively uniformly from the initial stage of layer formation (near the interface with the thermally oxidized silicon film). I understand. On the other hand, as shown in FIG. 16, in sample 11A, an amorphous ZnGaO-based oxide layer was formed at the initial stage of film formation, and relatively large crystal grains grew after about half of the film thickness. It can be seen that

This is thought to be because crystallization was promoted due to the rise in substrate temperature associated with sputtering film formation. In other words, it can be said that the ZnGaO-based oxide layer of sample 1A with an increased Zn ratio is crystallized at a lower energy than the ZnGaO-based oxide layer of sample 11A. In other words, it is considered that the crystallization of the layer was promoted by increasing the Zn ratio, and as a result, a ZnGaO-based oxide layer containing dense nanocrystals was obtained.

Furthermore, as shown in FIG. 17, in the electron beam diffraction image of the cross section of sample 1A, a pair of strong diffraction spots was recognized in the vertical direction with the transmitted light positioned at the center interposed therebetween. This direction is the same as the film thickness direction of the ZnGaO-based oxide layer. It was also found that these diffraction spots correspond to the ZnGa ₂ O ₄ (220) plane. That is, in the ZnGaO-based oxide layer of sample 1A, the ZnGa ₂ O ₄ (220) plane is strongly oriented perpendicular to the film thickness direction. This result agrees with the XRD 2θ/θ measurement result of sample 1 formed under the same conditions. A strong orientation means that the directions of crystal planes included are aligned, that is, the crystallinity is uniform.

On the other hand, as shown in FIG. 18, in the cross-sectional electron beam diffraction image of sample 11A, diffraction spots corresponding to crystal planes in the ZnGa ₂ O ₄ [111] direction were observed, but sample 1A shown in FIG. No strong orientation as in the case of . It can be said that the ZnGaO-based oxide layer of Sample 11A has weaker orientation than the ZnGaO-based oxide layer of Sample 1A.

In sample 11 in which the ZnGaO-based oxide layer was formed under the same conditions as sample 11A, the crystal plane perpendicular to the film thickness direction of the ZnGaO-based oxide layer was strongly [111] oriented in the XRD 2θ/θ measurement as described above. , which is inconsistent with cross-sectional electron diffraction results. This is probably because the film thickness of the ZnGaO-based oxide layer is 150 nm in sample 11, whereas the film thickness is as thin as 50 nm in sample 11A. As shown in the cross-sectional TEM image of FIG. 16, in the sample 11A, the ZnGaO-based oxide layer was crystallized in the middle of the film formation, and it is expected that the ZnGaO-based oxide layer will grow in the [111] direction as the film thickness increases. be. That is, when a ZnGa ₂ O ₄ layer having a stoichiometric composition is crystallized by film formation at room temperature, the crystallinity greatly depends on the film thickness.

Thus, by increasing Zn/(Ga+Zn) from 33%, which is the stoichiometric composition of ZnGa ₂ O ₄ , to 40% or more, dense and homogeneous nanocrystals can be formed from the initial stage of film formation. confirmed. Such structural features of the ZnGaO-based oxide layer are important factors for obtaining the effects of the present invention.

(Example 1B)
A ZnGaO-based oxide layer was formed on the substrate by the same method as in Example 1 described above.

However, in Example 1B, a non-alkali glass substrate (0.7 mm thick, 40 mm square) was used as the substrate.

The obtained sample is called "Sample 1B".

(Example 11B to Example 13B)
In Examples 11B to 13B, samples (referred to as "Sample 11B" to "Sample 13B", respectively) were prepared in the same manner as in Example 1B.

However, in these Examples 11B to 13B, the conditions described in Examples 11 to 13 above were adopted as the film forming conditions for the ZnGaO-based oxide. The film thickness of the ZnGaO layer was set to 50 nm (target value). Furthermore, samples 11B to 13B were annealed in the air at 350° C. for 1 hour after film formation. Accordingly, the sample 11B differs from the sample 11 in the film thickness of the substrate and the ZnGaO-based oxide layer, and in the presence or absence of annealing treatment. The same is true for other samples 12B and 13B.

(Example 21B to Example 24B)
In Examples 21B-24B, samples (referred to as "Sample 21B"-"Sample 24B", respectively) were prepared in a manner similar to that of Example 1B.

However, in Examples 21B to 24B, the conditions described in Examples 11 to 14 above were adopted as the film forming conditions for the ZnGaO-based oxide.

(Evaluation of pattern processability)
Next, using Sample 1B, Samples 11B to 13B, and Samples 21B to 24B, a wet patterning process was performed by photolithography.

The pattern processing was performed according to the procedure shown in Figures 1 to 3 above.

That is, first, a patterned resist was placed on each sample, and wet etching was performed using this resist as a mask. Next, the resist was stripped by a wet method.

Wet etching was performed by immersing the sample in an oxalic acid solution (ITO-07N; manufactured by Kanto Kagaku Co., Ltd.) heated to 40°C. Moreover, the stripping process for stripping the resist was carried out by immersing the sample in stripping solution heated to 80°C. A mixture of dimethylsulfoxide (60 wt %) and N-methyl-2-pyrrolidone (40 wt %) (stripping solution 104; manufactured by Tokyo Ohka Kogyo Co., Ltd.) was used as the stripping solution.

After patterning, the state of the ZnGaO layer was evaluated with a microscope.

Table 2 below summarizes the results obtained for each sample. The column of "wet etching treatment" in Table 2 shows the result of evaluation by ◯ when the desired pattern was properly formed, and by × when not. In addition, in the column of "wet stripping treatment", the result of evaluation is indicated by x when disappearance or damage of the ZnGaO layer due to impregnation with the stripping solution is recognized, and by ◯ when not.

As shown in Table 2, samples 21B to 24B could be wet-etched into an appropriate shape regardless of the Zn/(Ga+Zn) value of the ZnGaO-based oxide layer. However, in Samples 21B to 24B, disappearance and partial damage due to dissolution of the ZnGaO-based oxide layer were confirmed by the subsequent wet stripping treatment.

As described above, in samples 21, 22, and 23, no diffraction peak was confirmed in the XRD 2θ/θ measurement. Therefore, the ZnGaO-based oxide layers of Samples 21B, 22B, and 23B formed under the same conditions are amorphous, and thus wet etching with acid is easy, but they do not have peeling solution resistance. On the other hand, since diffraction peaks were confirmed in the XRD 2θ/θ measurement for sample 24, the ZnGaO-based oxide layer of sample 24B is considered to contain crystalline material. However, in the ZnGaO-based oxide layer of sample 24B, although the pattern did not disappear after impregnation with the stripping solution, non-uniform film unevenness and surface roughness occurred. It is considered that this is because the ZnGaO-based oxide layer was insufficiently crystallized, and the uncrystallized amorphous region was partially eroded by the stripping solution.

In the sample 11B in which the ZnGaO-based oxide layer was formed at an oxygen partial pressure of 10 vol%, after the wet etching, the region that should be etched, that is, the region not covered with the resist 3 in FIG. Etching residue was confirmed. Further, after the wet peeling treatment, unevenness of the film and surface roughness occurred as in the sample 24B described above.

Furthermore, although not shown in Table 2, a sample (referred to as sample 11B') was prepared by increasing the thickness of the ZnGaO-based oxide layer of sample 11B, and the same pattern processing was performed. As a result, the ZnGaO-based oxide layer of sample 11B′ was impregnated with an aqua regia etchant (mixed acid ITO-02; manufactured by Kanto Kagaku Co., Ltd.) heated to 40° C. as well as an oxalic acid solution in wet etching. It was barely etched.

As mentioned above, the conventional ZnGa ₂ O ₄ spinel crystal layer has very high chemical durability and is difficult to etch by acid. In fact, sample 11B' could not be etched with strong acid either. On the other hand, as shown in the TEM image of sample 11A (FIG. 16), the ZnGaO-based oxide layer with Zn/(Ga+Zn)=33% is crystallized at room temperature, and the crystallinity varies depending on the film thickness. It becomes uneven in the direction. Therefore, in the ZnGaO-based oxide layer of sample 11B, which is thin and the surface layer is not sufficiently crystallized, the amorphous portion is selectively dissolved in the acid and the stripping solution during the patterning process, while the coarse portion is formed. It is considered that the ZnGa ₂ O ₄ crystal part was not dissolved, and the etching residue and surface roughness as described above occurred.

For samples 1B and 12B, the ZnGaO-based oxide layer was wet-etched normally, and neither dissolution nor damage due to the stripping liquid impregnation was observed, and an appropriate pattern was obtained. On the other hand, sample 13B could be wet-etched without any problem, but after the wet stripping process, non-uniform film unevenness and surface roughness were generated, similar to samples 11B and 24B.

As described above, it was confirmed that the "wet etching process" and "wet stripping process" could appropriately pattern the ZnGaO-based oxide layer only in samples 1B and 12B.

As described above, this result shows that dense and homogeneous nanocrystals can be obtained when Zn/(Ga+Zn) is increased from the stoichiometric composition of 33% to 40% or more and the film is formed at a high oxygen partial pressure. This is thought to be for the sake of

(Fabrication of TFT element: Example 1C)
A TFT element having a cross-sectional structure as shown in FIG. 4 was manufactured using the first manufacturing method described above.

Specifically, first, a glass substrate (non-alkali glass) with a length of 40 mm, a width of 40 mm, and a thickness of 0.5 mm was prepared. Next, a barrier film was formed on the glass substrate. The barrier film had a two-layer structure of silicon nitride (lower side) and silicon oxide (upper side) and was formed by plasma CVD. During film formation, the glass substrate was heated to 350°C. The thicknesses of the silicon nitride layer and the silicon oxide layer were both set to 100 nm (target value).

Next, a metal film for gate electrodes was formed on the barrier layer by a DC magnetron sputtering method. The metal film was made of metal titanium (Ti) and had a thickness of 100 nm (target value). After that, the metal film was dry-etched by normal photoresist method and CF ₄ /O ₂ plasma treatment to form a patterned gate electrode.

Next, a gate insulating film was formed on the gate electrode by plasma CVD. The gate insulating film was made of silicon oxide and had a thickness of 200 nm (target value). As a result, a layer structure as shown in FIG. 6 was obtained.

Next, an untreated oxide semiconductor film was formed on the gate insulating film by RF magnetron sputtering. The deposition conditions for the untreated film are the same as in Example 1 described above. Therefore, Zn/(Zn+Ga) in the untreated film is 40%. However, the thickness of the untreated film was set to 50 nm (target value).

After forming the untreated film, the glass substrate was annealed at 350°C for 1 hour in the air. As a result, a layer structure as shown in FIG. 7 was obtained.

Next, the untreated film was patterned to form an oxide semiconductor layer. Pattern processing was performed in the following procedure.

First, a photoresist layer was applied on the untreated film, and the photoresist layer was patterned through exposure and development processes.

Next, the glass substrate was immersed in an etching solution to wet etch the untreated film. An oxalic acid solution (ITO-07N; manufactured by Kanto Kagaku Co., Ltd.) at 40° C. was used as an etching solution. The immersion time was 2.5 minutes. Thereafter, the glass substrate was immersed in a stripping solution at 80° C. for 3 minutes, and further immersed in the same stripping solution at room temperature for 3 minutes to remove the photoresist.

A mixture of dimethyl sulfoxide (60 wt%) and N-methyl-2-pyrrolidone (40 wt%) (stripping solution 104; manufactured by Tokyo Ohka Kogyo Co., Ltd.) was used as the stripping solution.

A patterned oxide semiconductor layer such as that shown in FIG. 8 was obtained by the wet treatment described above.

Next, metal films for the first electrode and the second electrode were formed by DC magnetron sputtering so as to cover the oxide semiconductor layer. The metal film had a two-layer structure of metal aluminum (upper layer) and metal titanium (lower layer). The thickness of the upper layer was set to 150 nm (target value), and the thickness of the lower layer was set to 50 nm (target value).

After that, the photoresist layer placed on the metal film was patterned, and using this as a mask, the upper layer of the metal film was wet-etched. As an etching solution, a mixed acid solution of nitric acid, acetic acid and phosphoric acid (KSMF100; manufactured by Kanto Kagaku Co., Ltd.) was used. The lower layer of the metal film was patterned by dry etching using CF ₄ /O ₂ gas.

After that, the photoresist layer was removed using the aforementioned stripping solution. As a result, a layer structure having the first electrode and the second electrode as shown in FIG. 9 was obtained.

Next, a passivation layer was formed by a plasma CVD method so as to cover the first electrode, the second electrode, and the oxide semiconductor layer.

The passivation layer was made of silicon oxide and had a thickness of 300 nm (target value).

After that, a contact hole penetrating the passivation layer and the gate insulating film was formed by a general lithography method.

Through the above steps, a TFT element having the structure shown in FIG. 4 was manufactured. The obtained TFT element is hereinafter referred to as "element 1".

(Fabrication of TFT element: Example 12C)
A TFT device (hereinafter referred to as "device 12") was fabricated in the same manner as in Example 1C.

However, in this example 12C, Zn/(Zn+Ga) in the untreated film was set to 50%.

(Evaluation of TFT characteristics)
Using the element 1 and the element 12, the following evaluation was carried out.

(Characteristic evaluation in dark state)
Using a semiconductor parameter analyzer (B1500A; manufactured by Keysight), the TFT transfer characteristics of element 1 and element 12 were evaluated. The drain current value Id obtained by changing the gate voltage Vg stepwise from -15 V to +45 V was measured. The drain voltage Vd was set to 0.1V. The measurement was performed in the dark state inside the probe box, and the stage temperature was room temperature.

19 and 20 show the TFT transfer characteristics of element 1 and element 12, respectively.

From FIGS. 19 and 20, the threshold voltage Vth and the field effect mobility of the

elements

1 and 12 were calculated. The threshold voltage Vth was defined as the gate voltage Vg when the drain current Id was 1 nA.

As a result of the evaluation, the device 1 had a threshold voltage Vth of 7.8 V and a field effect mobility of 6.7 cm ² /V·sec. On the other hand, the device 12 had a threshold voltage Vth of 7.1 V and a field effect mobility of 4.6 cm ² /V·sec.

Thus, normal switching characteristics were obtained in both element 1 and element 12. That is, when a ZnGaO-based oxide having a Zn/(Ga+Zn) ratio of 40% or more was used for the active layer, it was confirmed that the TFT operated normally even if the active layer was patterned by a wet method. Moreover, since the field effect mobility of the device 12 is lower than that of the device 1, it was found that the field effect mobility is lowered when the active layer has a Zn/(Ga+Zn) ratio of 50% or more.

(Negative gate bias thermal stress test under light irradiation)
Next, the device 1 and the device 12 were subjected to a negative gate bias thermal stress (NBTIS) test under light irradiation.

In this NBTIS test, a negative voltage is applied to the gate electrodes of the

elements

1 and 12 under a temperature load environment with light irradiation for a predetermined time. In such an NBTIS test, it is possible to quickly evaluate the deterioration of the TFT characteristics in the actual driving state of the display.

Specifically, the test was conducted using the following method.

First, the initial characteristics of

Elements

1 and 12 under light irradiation are measured under the following conditions:
light irradiation on;
stage temperature 85°C;
drain voltage Vd=0.1V;
Sweep the gate voltage Vg stepwise from +45V to -15V;
A threshold voltage (Vth(0)) is obtained from the obtained relationship between the gate voltage Vg and the drain current Id.

Next, while maintaining the light irradiation on and the stage temperature at 85° C., the drain voltage Vd is set to 0 V and the gate voltage Vg is maintained at −30 V for 10 seconds.

After that, the TFT characteristics after stress load for 10 seconds are measured in the same manner as the initial characteristics measurement.

Similarly, the drain voltage Vd is set to 0 V and the gate voltage Vg is maintained at -30 V for 90 seconds. After that, the TFT characteristics are measured, and the TFT characteristics after the stress load for a total of 100 seconds are measured.

Such an operation is performed for cumulative stress times of 500 seconds and 1000 seconds, and the threshold voltage Vth (1000) in the TFT characteristics after 1000 seconds is obtained.

From the obtained results, the threshold voltage shift amount ΔVth in the cumulative 1000 NBTIS tests was calculated by the following formula (2):

ΔVth=Vth(1000)−Vth(0) Equation (2)
The aforementioned semiconductor parameter analyzer was used to measure the TFT characteristics and apply the stress voltage. A white LED light source was used as the light source, and the amount of light was adjusted so that the illuminance on the device surface was 10,000 lx, and the device was irradiated from the device surface side.

FIG. 21 shows changes in the TFT characteristics of element 1 in the NBTIS test. FIG. 22 also shows changes in the TFT characteristics of the element 12 in the NBTIS test.

The threshold voltage shift amount ΔV _th of the device 1 was -2.6 V in the NBTIS test for 1000 seconds. On the other hand, the threshold voltage shift amount ΔV _th of the element 12 was −4.3 V, and compared with the element 1, the threshold voltage shift amount of the element 12 by the NBTIS test, that is, the deterioration of the element was large.

Thus, it was found that increasing Zn/(Ga+Zn) to 50% in the ZnGaO-based oxide layer reduced the field effect mobility and deteriorated the TFT reliability under light irradiation.

From the above results, it can be said that (Zn)/(Zn+Ga) in the ZnGaO-based oxide semiconductor layer is preferably less than 50% when TFT characteristics are considered.

This application claims priority based on Japanese Patent Application No. 2021-041812 filed on March 15, 2021, and the entire contents of the same Japanese application are incorporated herein by reference.

1 substrate to be processed 2 oxide semiconductor layer (before patterning)
3 resist 100 first TFT
110 substrate 120 barrier layer 130 gate electrode 140 gate insulating film 149 untreated film 150 oxide semiconductor layer 160 first electrode 162 second electrode 180 passivation layer 185 contact hole

Claims

A thin film transistor having an oxide semiconductor layer,
The oxide semiconductor layer has a ZnGaO-based oxide in which the molar ratio of Zn to the total of Ga (gallium) and Zn (zinc) is 35% or more and less than 50%,
In the X-ray diffraction 2θ/θ measurement of the oxide semiconductor layer, when a crystal having a Scherrer diameter L of 5 nm or less determined by the following formula (1) is referred to as a nanocrystal,

L=Kλ/(β cos θ) (1) Equation (where K is the Scherrer constant, λ is the X-ray wavelength, β is the half width, and θ is the peak position)

The thin film transistor, wherein the oxide semiconductor layer includes nanocrystals having a ZnGa 2 O 4 structure, and (220) planes of the nanocrystals are oriented perpendicular to a thickness direction of the oxide semiconductor layer.
The thin film transistor according to claim 1, wherein the oxide semiconductor layer has a molar ratio of Zn to the total of Ga and Zn of 40% or more.
A method for manufacturing a thin film transistor having a patterned oxide semiconductor layer, comprising:
The oxide semiconductor layer is
(1) In an atmosphere with an oxygen concentration of more than 1 vol%, by sputtering using a ZnGaO-based oxide target, the molar ratio of Zn to the total of Ga (gallium) and Zn (zinc) is 35% or more and less than 50% ZnGaO (2) using a resist as a mask, the film is wet-etched with acid to form a pattern of an oxide semiconductor layer; (3) using a stripping solution, the resist is A manufacturing method formed by wet removing a
The film is formed on a substrate to be processed,
4. The manufacturing method according to claim 3, wherein the step (1) is performed while heating the substrate to be processed to less than 100[deg.]C.
In the X-ray diffraction measurement of the oxide semiconductor layer, when a crystal having a Scherrer diameter L of 5 nm or less determined by the following formula (1) is referred to as a nanocrystal,

L=Kλ/(β cos θ) (1) Equation (where K is the Scherrer constant, λ is the X-ray wavelength, β is the half width, and θ is the peak position)

5. The manufacturing method according to claim 3 , wherein said oxide semiconductor layer includes nanocrystals having a ZnGa2O4 structure.
The manufacturing method according to any one of claims 3 to 5, wherein the (220) planes of the nanocrystals of the oxide semiconductor layer are oriented in a direction perpendicular to the thickness.
The manufacturing method according to any one of claims 3 to 6, wherein the oxide semiconductor layer has a molar ratio of Zn to the total of Ga and Zn of 40% or more.