WO2022190984A1 - 半導体装置および機器 - Google Patents

半導体装置および機器 Download PDF

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Publication number
WO2022190984A1
WO2022190984A1 PCT/JP2022/008828 JP2022008828W WO2022190984A1 WO 2022190984 A1 WO2022190984 A1 WO 2022190984A1 JP 2022008828 W JP2022008828 W JP 2022008828W WO 2022190984 A1 WO2022190984 A1 WO 2022190984A1
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Prior art keywords
layer
semiconductor layer
transistor
semiconductor
substrate
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English (en)
French (fr)
Japanese (ja)
Inventor
広明 小林
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Canon Inc
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Canon Inc
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Priority to CN202280019241.3A priority Critical patent/CN116918075A/zh
Priority to JP2023505337A priority patent/JPWO2022190984A1/ja
Publication of WO2022190984A1 publication Critical patent/WO2022190984A1/ja
Priority to US18/461,990 priority patent/US20230411402A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • Patent Document 1 discloses a semiconductor device using a TFT having polysilicon and a TFT having an oxide semiconductor layer.
  • Patent Document 2 discloses a semiconductor device including a first top-gate thin film transistor having a polycrystalline silicon layer as a channel and a second top-gate thin film transistor having an oxide semiconductor layer as a channel. The semiconductor device of Patent Document 2 discloses that the source and drain of the first top-gate thin film transistor and the gate of the second top-gate thin film transistor are a common metal layer.
  • Patent Document 1 does not sufficiently consider cost reduction.
  • the technique of Patent Literature 2 can obtain effects only with a limited structure.
  • SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a technique that is advantageous in reducing the cost of a semiconductor device.
  • a first aspect of the semiconductor device is a substrate; a first semiconductor layer of a first transistor overlying the substrate; a first conductor layer provided on the substrate and overlapping the first semiconductor layer; a second semiconductor layer of a second transistor overlying the substrate; a second conductor layer provided on the substrate and overlapping the second semiconductor layer; with Among the group 12 to 16 elements contained in the first semiconductor layer, the first element having the highest concentration in the first semiconductor layer is the above group 12 to 16 elements contained in the second semiconductor layer. Unlike the second element with the highest concentration in the second semiconductor layer, Among the metal elements or metalloid elements contained in the first conductor layer, the third element having the highest concentration in the first conductor layer is the metal element or metalloid element contained in the second conductor layer. is the same as the fourth element having the highest concentration in the second conductor layer, the first conductor layer contacts the first semiconductor layer; the second conductor layer is insulated from the second semiconductor layer; It is characterized by
  • a second aspect of the semiconductor device according to the present invention is that the second conductor layer is provided between the second semiconductor layer and the substrate.
  • the third conductor layer provided in and overlapping the second conductor layer does not contact the second semiconductor layer and is insulated from the second conductor layer.
  • the first transistor is P-type and the second transistor is N-type.
  • 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams for explaining types of transistors; 1A and 1B are schematic diagrams for explaining types of transistors; 1A and 1B are schematic diagrams for explaining types of transistors; 1A and 1B are schematic diagrams for explaining types of transistors; 1A and 1B are schematic diagrams for explaining types of transistors; 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams illustrating a semiconductor device; 1A and 1B are schematic diagrams illustrating a semiconductor
  • FIG. 1A is a schematic plan view of a semiconductor device AP.
  • a semiconductor device AP suitable for this embodiment can include a pixel region 2 in which a plurality of pixel circuits PX are arranged and a peripheral region 3 around the pixel region 2 .
  • a pixel region 2 is a region surrounded by a one-dot chain line
  • a peripheral region 3 is a region sandwiched between a one-dot chain line and a two-dot chain line.
  • a semiconductor device AP having a pixel region 2 can be used as a display device or an imaging device.
  • the present embodiment can also be applied to a semiconductor device AP that does not have the pixel region 2 or the peripheral region 3, and may be, for example, an arithmetic device, a memory device, or a communication device.
  • FIG. 1B is a schematic cross-sectional view of the semiconductor device AP.
  • a semiconductor device AP includes a substrate 1 , a transistor 10 provided on the substrate 1 , and a transistor 20 provided on the substrate 1 .
  • 2A to 2D are cross-sectional schematic diagrams showing the configuration of the transistor 10 or the transistor 20.
  • FIG. Transistor 10 includes a semiconductor layer 11 provided over substrate 1
  • transistor 20 includes a semiconductor layer 21 provided over substrate 1 .
  • Each of the semiconductor layer 11 and the semiconductor layer 21 is composed of at least one group 12-16 element.
  • the semiconductor layers 11 and 21 may contain an element other than Group 12 to Group 16 (for example, hydrogen).
  • the transistor 10 can be provided in at least one of the pixel region 2 and the peripheral region 3.
  • the transistor 20 can be provided in at least one of the pixel region 2 and the peripheral region 3 .
  • the transistor 30 is provided in the peripheral region 3 together with the transistor 10 .
  • Transistor 10 in peripheral region 3 and transistor 30 in peripheral region 3 together may form a complementary integrated circuit such as a CMOS circuit.
  • transistor 10 can be a P-type transistor and transistor 30 can be an N-type transistor.
  • transistor 10 can be an N-type transistor and transistor 30 can be a P-type transistor.
  • Transistor 10 may be an N-type transistor or a P-type transistor, but preferably transistor 10 is an N-type transistor because electrons generally have higher mobility than holes.
  • Transistor 20 may be an N-type transistor or a P-type transistor, but preferably transistor 20 is an N-type transistor because electrons generally have higher mobility than holes.
  • a functional element 200 may be provided on the transistor 20 (and the transistor 10) in the pixel region 2.
  • the functional element 200 is an element that can generally constitute a pixel, such as a liquid crystal element, a light emitting element, or a photoelectric conversion element.
  • the functional element 200 is connected to a transistor included in the pixel circuit PX, and the transistor to which the functional element 200 is connected is the transistor 20 or the transistor 10, for example.
  • An insulator 40 is provided on the substrate 1, as shown in FIG. 1B.
  • the insulator 40 can be used in various ways, such as the gate insulating films of the transistors 10, 20, and 30, interlayer insulating films around the transistors 10, 20, and 30, planarization films, diffusion prevention films, protective films, and sealing films. It is a laminate of insulating films having a function.
  • FIG. 1C shows one pixel circuit PX when the semiconductor device AP is an imaging device.
  • the pixel circuit PX includes a functional element 200 that is a photoelectric conversion element and an amplification transistor 104 that amplifies the signal generated by the functional element 200 .
  • a functional element 200 which is a photoelectric conversion element, includes a first electrode 201, a second electrode 209, a functional layer 205 disposed between the first electrode 201 and the second electrode 209, and a functional layer 205. and an insulating layer 207 disposed between the second electrode 209 .
  • the functional layer 205 is a photoelectric conversion layer made of an organic material, an inorganic material, or a hybrid material of an organic material and an inorganic material.
  • a hybrid material may be a quantum dot material.
  • a functional device 200 that is a photoelectric conversion device can include a blocking layer 203 disposed between a functional layer 205 and a first electrode 201 .
  • the blocking layer 203 is provided to prevent charges of the same conductivity type as signal charges accumulated in the functional layer 205 from being injected from the first electrode 201 into the functional layer 205 .
  • the blocking layer 203 and the insulating layer 207 may be omitted.
  • the photoelectric conversion unit can accumulate charges generated by incident light as signal charges. Further, by controlling the voltage supplied to the pixel circuit PX, the signal from the photoelectric conversion element (functional element 200) can be read.
  • the pixel PX includes a reset transistor 102, a capacitor 103, an amplification transistor 104, and a selection transistor 105.
  • a drain of the reset transistor 102 is connected to a node supplied with the reset voltage Vres.
  • a node A including the first electrode 201 of the functional element 200 is supplied with the power supply voltage Vs.
  • the source of reset transistor 102 is connected to the second electrode 209 of functional element 200 and the gate of amplification transistor 104 . With such a configuration, the reset transistor 102 can reset the voltage of the node B to the reset voltage Vres. That is, the reset transistor 102 is a reset unit that supplies the reset voltage Vres to the second electrode 209 .
  • the node B including the second electrode 209 of the functional element 200 becomes electrically floating.
  • Node C is capacitively coupled with node B via capacitor 103 .
  • a first terminal of capacitor 103 is connected to node B.
  • a voltage Vd from the voltage supply unit 410 is supplied to the node C to which the second terminal of the capacitor 103 is connected.
  • Node B includes the gate of amplifying transistor 104 .
  • Amplification transistor 104 is the amplification section, and the gate of amplification transistor 104 is the input node of the amplification section. That is, the second electrode 209 of the functional element 200 is electrically connected to the amplifier section.
  • the amplifying section can amplify and output a signal generated by the functional element 200 (photoelectric conversion element).
  • a drain of the amplification transistor 104 is connected to a node supplied with a power supply voltage.
  • a source of the amplification transistor 104 is connected to the output line 130 via the selection transistor 105 .
  • a current source 160 is connected to the output line 130 .
  • Amplifying transistor 104 and current source 160 form a source follower circuit, which outputs a signal based on charges generated by functional element 200 to output line 130 .
  • a column circuit 140 is further connected to the output line 130 .
  • a signal from the pixel circuit PX output to the output line 130 is input to the column circuit 140 .
  • FIG. 1D shows one pixel circuit PX when the semiconductor device AP is a display device.
  • the pixel PX includes a functional element 200, which is an organic EL element, and the functional element 200 is arranged between a first electrode 201, a second electrode 209, and between the first electrode 201 and the second electrode 209. a functional layer 205;
  • the functional layer 205 is a light-emitting layer made of an organic material or an inorganic material.
  • the first electrode 201 is for example a cathode and the second electrode 209 is for example an anode.
  • the luminescent color of the luminescent layer of the functional element 200, which is an organic EL element may be red, green, or blue for each sub-pixel.
  • the pixel circuit PX includes a selection transistor 107, a drive transistor 106, and a capacitor 108.
  • the power supply voltage Vd is supplied to the drive transistor 106 from the power supply line PL, and the power supply voltage Vs is supplied to the first electrode 201 .
  • the power supply voltage Vs can be a voltage lower than the power supply voltage Vd.
  • the select transistor 107 outputs the data signal applied to the data line DL in response to the scan signal applied to the scan line GL.
  • Capacitor 108 charges a voltage corresponding to the data signal received via select transistor 107 .
  • a node D is connected to the source or drain of the select transistor 107 . Also, the node D is connected to the gate of the drive transistor 106 .
  • Drive transistor 106 is connected to node E.
  • the drive transistor 106 is connected to the second electrode 209 of the functional element 200 .
  • One of the source and drain of drive transistor 106 is connected to node E, and the other of the source and drain of drive transistor 106 is connected to second electrode 209 .
  • a voltage Vd is supplied to the node E from the voltage supply unit.
  • a first terminal of capacitor 108 is connected to node D.
  • the second terminal of the capacitor 108 is connected to the node E, and the node E is capacitively coupled with the node D via the capacitor 108 .
  • the capacitor 108 may be connected not to the node E but to the node to which the second electrode 209 is connected.
  • the drive transistor 106 controls the drive current flowing through the functional element 200 according to the amount of charge stored in the capacitor.
  • the functional element 200 as a light emitting element emits light with luminance according to the data level of the data signal.
  • the pixel circuit PX described in FIGS. 1C and 1D is merely an example, and is not limited to this.
  • the pixel PX may further include a plurality of transistors and may include a greater number of capacitors.
  • the capacitors 103 and 108 may be of the MIS type in which a dielectric layer is sandwiched between conductor layers and semiconductor layers, or may be of the MIM type in which a dielectric layer is sandwiched between conductor layers. It may have a structure in which a dielectric layer is sandwiched between layers.
  • the selection transistor 105, the reset transistor 102, and the selection transistor 107 can be switch transistors. These switch transistors can be the transistors 20 described above.
  • the amplification transistor 104 and the driving transistor 106 output a potential correlated to the potential input to the gate, and are different from the switch transistor in that these transistors are the transistor 10 described above. sell.
  • the capacitors 103 and 108 have a common function in that they hold the amount of charge corresponding to the signal level of the pixel.
  • the transistor 10 is preferably used as the reset transistor 102 and the selection transistor 107 which are directly connected to the capacitor 103 and the capacitor 108 .
  • the amplifying transistor 104 and the driving transistor 106 directly connected to the capacitor 103 and the capacitor 108 can also be used as the transistor 20 .
  • FIGS. 2A to 2D are schematic cross-sectional views showing the configuration of the transistor 10 or the transistor 20.
  • FIG. Four different configurations of transistor 10 or transistor 20 are shown in FIGS. 2A-2D, but first what is common to each configuration will be described.
  • the transistor 10 includes a semiconductor layer 11 , a gate electrode 12 , a source electrode 13 , a drain electrode 14 and a gate insulating film 15 provided on the substrate 1 .
  • the gate electrode 12 , the source electrode 13 and the drain electrode 14 overlap the semiconductor layer 11 .
  • the gate electrode 12 is insulated from the semiconductor layer 11 by the gate insulating film 15 , and the source electrode 13 and the drain electrode 14 are in contact with the semiconductor layer 11 .
  • the gate electrode 12 is provided on the channel of the semiconductor layer 11 and the gate insulating film 15 is provided between the semiconductor layer 11 and the gate electrode 12 .
  • the source electrode 13 is provided on the source of the semiconductor layer 11 and the drain electrode 14 is provided on the drain of the semiconductor layer 11 .
  • the transistor 20 includes a semiconductor layer 21 , a gate electrode 22 , a source electrode 23 , a drain electrode 24 and a gate insulating film 25 provided on the substrate 1 .
  • the gate electrode 22 , the source electrode 23 and the drain electrode 24 overlap the semiconductor layer 21 .
  • the gate electrode 22 is insulated from the semiconductor layer 21 by the gate insulating film 25 , and the source electrode 23 and the drain electrode 24 are in contact with the semiconductor layer 21 .
  • the gate electrode 22 is provided on the semiconductor layer 21 and the gate insulating film 25 is provided between the semiconductor layer 21 and the gate electrode 22 .
  • the source electrode 23 is provided on the source of the semiconductor layer 21 and the drain electrode 24 is provided on the drain of the semiconductor layer 21 .
  • element S1 be the element with the highest concentration in the semiconductor layer 11 among the 12th to 16th group elements contained in the semiconductor layer 11 .
  • An element having the highest concentration in the semiconductor layer 21 among elements belonging to Groups 12 to 16 contained in the semiconductor layer 21 is an element S2.
  • element S1 is different from element S2.
  • the semiconductor layers 11 and 21 may be group IV semiconductors such as Si, Ge, fullerene, carbon nanotubes, etc. In that case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be group 14 elements.
  • the semiconductor layers 11 and 21 may be group II-VI compound semiconductors such as ZnSe, CdS and ZnO, in which case the elements S1 and S2 in the semiconductor layers 11 and 21 are group 12 elements or group 16 elements. sell.
  • the semiconductor layers 11 and 21 may be oxide semiconductors such as InGaZnO and InSnZnO, in which case the elements S1 and S2 in the semiconductor layers 11 and 21 may be oxygen (group 16 elements) or elements 12-14.
  • the concentration of oxygen in the oxide semiconductor is, for example, 50 at % or more, 70 at % or less, 67 at % or less, and 60 at %.
  • the semiconductor layers 11 and 21 may be group III-V compound semiconductors such as GaAs, InP and GaN, in which case the elements S1 and S2 in the semiconductor layers 11 and 21 are group 13 elements or group 15 elements. sell.
  • the semiconductor layers 11 and 21 may be group IV compound semiconductors such as SiC and SiGe, in which case the elements S1 and S2 in the semiconductor layers 11 and 21 may be group 14 elements.
  • the semiconductor layers 11, 21 may be organic semiconductors, in which case the elements S1, S2 in the semiconductor layers 11, 21 may be carbon (group 14 element).
  • the semiconductor layers 11 and 21 are at least one of a single crystal layer, a polycrystalline layer and an amorphous layer.
  • the semiconductor layers 11 and 21 may be multilayer bodies of multiple types of layers selected from a single crystal layer, a polycrystalline layer, and an amorphous layer.
  • the semiconductor layers 11 and 21 are preferably thin film transistors (TFTs) using polycrystalline layers or amorphous layers.
  • Each of the gate electrodes 12, 22, the source electrodes 13, 23, and the drain electrodes 14, 24 consists of at least one conductive layer.
  • the gate electrodes 12 and 22 have a multi-layered structure composed of a plurality of conductor layers
  • the bottom or top conductor layer of the gate electrodes 12 and 22 is in contact with the gate insulating films 15 and 25 .
  • the source electrodes 13 and 23 and the drain electrodes 14 and 24 have a multi-layer structure composed of a plurality of conductor layers
  • the lowermost or uppermost conductor layer of the source electrodes 13 and 23 and the drain electrodes 14 and 24 is a semiconductor. contact layers 11 and 21;
  • the conductor layer is a conductor closest to the semiconductor layers 11 and 21. There can be layers.
  • a conductor member overlapping the semiconductor layer 11 and insulated from the semiconductor layer 11 may be provided on the substrate 1 .
  • a conductor member 28 (described later) that overlaps with the semiconductor layer 21 and is insulated from the semiconductor layer 21 may be provided on the substrate 1 .
  • the conductor member 28 can be used as an auxiliary electrode, wiring, light blocking member, height difference adjusting member, etc. for the transistor 20 .
  • Another conductor layer may exist between the conductor member 28 and the semiconductor layer 21, but another conductor layer may not exist between the conductor member 28 and the semiconductor layer 21. .
  • Each of the conductor layers of the source electrode 13 and the drain electrode 14 is composed of at least one metal element or metalloid element.
  • the element with the highest concentration in the source electrode 13 and the drain electrode 14 is defined as an element M1.
  • the conductor layer of the gate electrode 22 is composed of at least one metal element or metalloid element.
  • the element M2 is the element with the highest concentration in the gate electrode 22 among the metal elements or metalloid elements contained in the gate electrode 22 .
  • the conductor layer of the gate electrode 12 is composed of at least one metal element or metalloid element.
  • An element having the highest concentration in the conductor layer of the gate electrode 12 among metal elements or metalloid elements contained in the conductor layer of the gate electrode 12 is an element M3.
  • the conductor layers of the source electrode 23 and the drain electrode 24 are composed of at least one metal element or metalloid element.
  • the element M4 is the element with the highest concentration in the gate electrode 22 among the metal elements or metalloid elements contained in the conductive layers of the source electrode 23 and the drain electrode 24 .
  • the element M3, which is a metal element or metalloid element contained in the gate electrode 12, may be different from the element S2 contained in the semiconductor layer 21.
  • the element M4, which is a metal element or a metalloid element included in the gate electrode 22, may be different from the element S1 included in the semiconductor layer 11.
  • the conductor layer of the conductor member 28 overlaps the semiconductor layer 21 and is insulated from the semiconductor layer 21 .
  • the conductor layer of the conductor member 28 is composed of at least one metal element or metalloid element other than the gate electrode 22 .
  • the element M5 be the element with the highest concentration in the conductor member 28 among the metal elements or metalloid elements contained in the conductor layer of the conductor member 28 .
  • the element M1 which is a metal element or metalloid element contained in the source electrode 13 and the drain electrode 14, may be different from the element S2 contained in the semiconductor layer 21.
  • the element M2 which is a metal element or metalloid element contained in the gate electrode 22, may be different from the element S1 contained in the semiconductor layer 11.
  • the element M3, which is a metal element or metalloid element contained in the gate electrode 12, may be different from the element S2 contained in the semiconductor layer 21.
  • the element M4 which is a metal element or metalloid element contained in the gate electrode 22, may be different from the element S1 contained in the semiconductor layer 11.
  • the element M5, which is a metal element or metalloid element contained in the conductor member 28, may be different from the element S1 contained in the semiconductor layer 11.
  • the characteristics of the electrodes of the transistors 10 and 20 are advantageous for the characteristics of the electrodes of the transistors 10 and 20 to differ from each other in the main constituent elements of the gate electrode of one of the transistors 10 and 20 and the semiconductor layer of the other of the transistors 10 and 20 .
  • the elements M1 to M4 are elements of Groups 3 to 13, and may be elements of Groups 3 to 9.
  • the elements M1-M4 are gold (Au), silver (Ag), copper (Cu), platinum (Pt), molybdenum (Mo), tungsten (W), tantalum (Ta), titanium (Ti).
  • Au gold
  • Mo molybdenum
  • W tungsten
  • Ta tantalum
  • Ti titanium
  • Cu Copper
  • Mo molybdenum
  • W tungsten
  • Ti titanium
  • the element M1 and the element M2 may be the same.
  • the same element means that the atomic number of the element is the same.
  • the element M1 and the element M5 may be the same.
  • the same element means that the atomic number of the element is the same.
  • FIG. 2A to 2D omit the illustration of the insulator 40 on the substrate 1 shown in FIG. 1B.
  • An insulator film may be provided as at least part of insulator 40 .
  • the semiconductor layer 11 is provided between the substrate 1 and the gate electrode 12 in the T-type transistor 10 shown in FIGS. 2A and 2D. Also, in the T-type transistor 20 , a semiconductor layer 21 is provided between the substrate 1 and the gate electrode 22 .
  • the gate electrode 12, the source electrode 13, and the drain electrode 14 of the transistor 10 are located on the substrate 1 side and the side opposite to the substrate 1 side with respect to the semiconductor layer 11. is located on one side of the In the example of FIG. 2A, the gate electrode 12, the source electrode 13, and the drain electrode 14 are provided on the opposite side of the semiconductor layer 11 from the substrate 1 side. In the example of FIG. 2B , the gate electrode 12 , the source electrode 13 and the drain electrode 14 are provided on the substrate 1 side with respect to the semiconductor layer 11 . In a C-type transistor 10 , a gate electrode 12 may be provided between a source electrode 13 and a drain electrode 14 .
  • the gate electrode 22, the source electrode 23, and the drain electrode 24 of the transistor 20 are located on the substrate 1 side and the side opposite to the substrate 1 side with respect to the semiconductor layer 21. is located on one side of the In the example of FIG. 2A, the gate electrode 22, the source electrode 23, and the drain electrode 24 are provided on the opposite side of the semiconductor layer 11 from the substrate 1 side. 2B, the gate electrode 22, the source electrode 23, and the drain electrode 24 are provided on the substrate 1 side with respect to the semiconductor layer 21. In the example of FIG. In a C-type transistor 20 , a gate electrode 22 may be provided between a source electrode 23 and a drain electrode 24 .
  • the gate electrode 12 is provided between the substrate 1 and the semiconductor layer 11 .
  • a gate electrode 22 is provided between the substrate 1 and the semiconductor layer 21 .
  • the semiconductor layer 11 is provided between the gate electrode 12 and the source electrode 13 .
  • the semiconductor layer 11 is provided between the gate electrode 12 and the drain electrode 14 .
  • the semiconductor layer 21 is provided between the gate electrode 22 and the source electrode 23 .
  • the semiconductor layer 21 is provided between the gate electrode 22 and the drain electrode 24 .
  • both the transistor 10 and the transistor 20 provided on the same substrate 1 are T-type.
  • both the transistor 10 and the transistor 20 are preferably C-type, and it is also preferable that both the transistor 10 and the transistor 20 are S-type.
  • transistor 10 may be one of the C-type and S-type and transistor 20 may be the other of the C-type and S-type.
  • both the transistor 10 and the transistor 20 provided on the same substrate 1 are B-type transistors.
  • both the transistor 10 and the transistor 20 are preferably C-type, and it is also preferable that both the transistor 10 and the transistor 20 are S-type.
  • transistor 10 may be one of the C-type and S-type and transistor 20 may be the other of the C-type and S-type.
  • both the transistor 10 and the transistor 20 provided on the same substrate 1 are C-type transistors.
  • both the transistor 10 and the transistor 20 are preferably T-type, and it is also preferable that both the transistor 10 and the transistor 20 are B-type.
  • transistor 10 may be one of the T-type and B-type and transistor 20 may be the other of the T-type and B-type.
  • both the transistor 10 and the transistor 20 provided on the same substrate 1 are S-type transistors.
  • both the transistor 10 and the transistor 20 are preferably T-type, and it is also preferable that both the transistor 10 and the transistor 20 are B-type.
  • transistor 10 may be one of the T-type and B-type and transistor 20 may be the other of the T-type and B-type.
  • both the transistor 10 and the transistor 20 provided on the same substrate 1 the same type, the configuration of the semiconductor device AP is simplified, and the design and manufacture of the semiconductor device AP are simplified. can reduce the cost required for
  • the element M2 contained in the gate electrode 22 is the same as the element M4 contained in the source electrode 23 and the drain electrode 24. Cost can be reduced by using the same element for the three electrodes of the transistor 20 .
  • the element M3 included in the gate electrode 12 is the same as the element M1 included in the source electrode 13 and the drain electrode 14 . Cost can be reduced by using the same element for the three electrodes of the transistor 10 .
  • the gate electrode 22 has a conductor layer containing the same element M4 as the element M1 contained in the source electrode 13 and the drain electrode .
  • the conductive layer of gate electrode 22 may be continuous with the conductive layer of source electrode 13 or drain electrode 14 .
  • the conductive layer containing the element M4 of the gate electrode 22 may be discontinuous with the conductive layer containing the element M1 of the source electrode 13 or the drain electrode 14 .
  • the conductor member 28 has a conductor layer containing the same element M5 as the element M1 contained in the source electrode 13 and the drain electrode 14 .
  • a semiconductor layer 21 is provided between the gate electrode 22 and a conductor member 28 (a conductor layer containing the element M5).
  • the conductor member 28 is a conductor layer containing the same element M5 as the element M1.
  • the conductor layer containing the element M5 of the conductor member 28 may be continuous with the conductor layer containing the element M1 of the source electrode 13 or the drain electrode 14 .
  • the conductor layer of the conductor member 28 may be discontinuous with the conductor layer containing the element M1 of the source electrode 13 or the drain electrode 14 .
  • the potential of the conductor member 28 (the conductor layer containing the element M5) is the same as the potential of any one of the gate electrode 12, the source electrode 13, the drain electrode 14, the gate electrode 22, the source electrode 23, and the drain electrode 24. good too.
  • the potential of the conductor member 28 (the conductor layer containing the element M5) may be the same as the potential of the gate electrode 22 . Therefore, the gate electrode 22 and the conductor member 28 may be electrically connected to each other.
  • the conductor layer containing the element M2 of the gate electrode 22 and the conductor layer containing the element M5 of the conductor member 28 may be in contact with each other, or the two may be electrically connected through another conductor layer (for example, a via). may be physically connected.
  • the electric field applied to the semiconductor layer 21 can be controlled by the gate electrode 22 and the conductor member 28 located on both sides of the semiconductor layer 21 .
  • the potential of the conductor member 28 (the conductor layer containing the element M5) may be different from any of the potentials of the gate electrode 12, the source electrode 13, the drain electrode 14, the gate electrode 22, the source electrode 23, and the drain electrode 24. However, it may be at a floating potential.
  • the element M3, which is a metal element or a metalloid element contained in the gate electrode 12, may be different from the element M2, which is a metal element or a metalloid element contained in the gate electrode 22. Differentiating the main metal element or semi-metal element contained in the gate electrodes 12 and 22 is advantageous for improving the characteristics of the transistors 10 and 20 .
  • the element S3 has the second highest concentration in the semiconductor layer 11 after the element S1 among the 12th to 16th group elements contained in the semiconductor layer 11 .
  • the semiconductor layer 11 is a binary compound semiconductor
  • the semiconductor layer 11 is a compound of the element S1 and the element S3.
  • the element having the second highest concentration in the semiconductor layer 21 after the element S2 is defined as an element S4.
  • the semiconductor layer 21 is a binary compound semiconductor
  • the semiconductor layer 21 is a compound of the element S2 and the element S4.
  • the element S3 contained in the semiconductor layer 21 may be different from the element S4 contained in the semiconductor layer 21 .
  • the elements S3 and S4 can be zinc (Zn).
  • the concentration of zinc can be 10-30 at %, 10-20 at %, eg, 16 at %.
  • the elements S3 and S4 may be indium (In). The concentration of indium may be 5-20 at %, for example 14 at %.
  • the concentration of gallium (Ga) and tin (Sn) may be lower than the concentration of zinc (Zn).
  • the concentration of gallium (Ga) and tin (Sn) may be lower than the concentration of indium (In).
  • the concentration of gallium (Ga) and tin (Sn) can be 5 to 20 at %, eg, 10 at %.
  • the conductor layer containing the same element (for example, the element M2 or the element M5) as the element M1 contained in the conductor layer of the source electrode 13 or the drain electrode 14 is the conductive layer of the source electrode 13 or the drain electrode 14 . It can be in the same layer as the body layer.
  • the same layer means a layer formed from a single film. Even if the layers are the same, the heights of the two layers from the substrate 1 may be different due to the height difference of the underlying layer during film formation. Also, if they are the same layer, the two layers can have approximately the same thickness.
  • substantially the same thickness means that the thickness of one is 90 to 110% of the thickness of the other.
  • Table 1 lists 32 types of combinations of the transistors 10 and 20.
  • T is written in column TB
  • B is written in column TB
  • B is written in column TB
  • C is written in the CS column
  • S is written in the CS column.
  • G is written in the M column.
  • N is described in the M column.
  • No. 01-04 and No. 09 to 12 correspond to the second embodiment.
  • No. 21-24 and No. 29 to 32 correspond to the third embodiment.
  • No. 01, 02, 05, 06 and No. 17, 18, 21 and 22 correspond to the fourth embodiment.
  • No. 11, 12, 15, 16 and no. 27, 28, 31 and 32 correspond to the fifth embodiment.
  • the odd-numbered example with G in the M column corresponds to the eighth embodiment.
  • the odd-numbered example with N in the M column corresponds to the ninth embodiment.
  • FIG. 3A No. 1 in Table 1 is shown using a dashed line.
  • 1 illustrates a cross-sectional view of a semiconductor device AP having the configuration of FIG.
  • the dashed line in FIG. 3A indicates that the members connected by the dashed line are in the same layer, that is, the source electrode 13 (and the drain electrode 14) are in the same layer as the gate electrode 22.
  • FIG. 3A illustrates a cross-sectional view of a semiconductor device AP having the configuration of FIG.
  • the dashed line in FIG. 3A indicates that the members connected by the dashed line are in the same layer, that is, the source electrode 13 (and the drain electrode 14) are in the same layer as the gate electrode 22.
  • FIG. 1 illustrates a cross-sectional view of a semiconductor device AP having the configuration of FIG.
  • the dashed line in FIG. 3A indicates that the members connected by the dashed line are in the same layer, that is, the source electrode 13 (and the drain electrode 14) are in the
  • FIG. 3B No. 1 in Table 1 is shown using a dashed line.
  • 1 illustrates a cross-sectional view of a semiconductor device AP having a configuration of 31.
  • FIG. The dashed line in FIG. 3B indicates that the members connected by the dashed lines are in the same layer, that is, the source electrode 13 (and the drain electrode 14) are in the same layer as the gate electrode 22.
  • FIG. 3B indicates that the members connected by the dashed lines are in the same layer, that is, the source electrode 13 (and the drain electrode 14) are in the same layer as the gate electrode 22.
  • FIG. 4A No. 1 in Table 1 is shown using a dashed line.
  • 02 illustrates a cross-sectional view of a semiconductor device AP having the configuration of FIG.
  • the dashed-dotted line in FIG. 4A indicates the case where the members connected by the dashed-dotted line are in the same layer, that is, the case where the source electrode 13 (and the drain electrode 14) is in the same layer as the conductive member 28.
  • the No. 1 illustrates a cross-sectional view of a semiconductor device AP having the configuration of FIG.
  • the two-dot chain line in FIG. 4A indicates the case where the members connected by the two-dot chain line are in the same layer, that is, the case where the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are in the same layer.
  • FIG. 4B No. 1 in Table 1 is shown using a dashed line. 1 illustrates a cross-sectional view of a semiconductor device AP having 32 configurations.
  • the dashed-dotted line in FIG. 4B indicates that the members connected by the dashed-dotted line are in the same layer, that is, the source electrode 13 (and the drain electrode 14) are in the same layer as the conductor member 28 .
  • the No. 1 illustrates a cross-sectional view of a semiconductor device AP having a configuration of 31.
  • FIG. The two-dot chain line in FIG. 4B indicates the case where the members connected by the two-dot chain line are in the same layer, that is, the case where the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are in the same layer.
  • FIG. 5A No. 1 in Table 1 is shown using a dashed line. 1 illustrates a cross-sectional view of a semiconductor device AP having the configuration of FIG.
  • the dashed-dotted line in FIG. 5A indicates that the members connected by the dashed-dotted line are in the same layer, that is, the source electrode 13 (and the drain electrode 14) are in the same layer as the conductor member 28.
  • the No. 1 illustrates a cross-sectional view of a semiconductor device AP having the configuration of FIG.
  • the two-dot chain line in FIG. 5A indicates the case where the members connected by the two-dot chain line are in the same layer, that is, the case where the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are in the same layer.
  • FIG. 5B No. 1 in Table 1 is shown using a dashed line. 1 illustrates a cross-sectional view of a semiconductor device AP having a configuration of 27.
  • FIG. A dashed line in FIG. 5B indicates that the source electrode 13 (and the drain electrode 14) are in the same layer as the gate electrode 22. As shown in FIG.
  • FIG. 6A illustrates a cross-sectional view of the T/C transistor shown in FIG. 2A.
  • FIG. 6A shows the size relationship between the thickness and distance of each layer.
  • transistor 20 gate electrode 22, source electrode 23, and drain electrode 24 have thickness T1.
  • the semiconductor layer 21 has a thickness T2 that is smaller than the thickness T1 (T1>T2).
  • Gate insulating film 25 has a thickness T3 smaller than thickness T1 (T1>T3).
  • thickness T3 may be less than thickness T2 (T3 ⁇ T2), but thickness T3 may be greater than thickness T2 (T2>T3).
  • the distance between the conductor member 28 and the semiconductor layer 21 is greater than the distance (thickness of the gate insulating film 25) between the gate electrode 22 and the semiconductor layer 21.
  • An interlayer insulating film 26 is arranged between the conductor member 28 and the semiconductor layer 21 .
  • An interlayer insulating film 27 is arranged between the semiconductor layer 21 and the source electrode 23 .
  • the interlayer insulating film 27 is the same layer as the gate insulating film 25 .
  • An interlayer insulating film 29 is provided to cover the transistor 20 .
  • the gate insulating film 25 has a portion that extends outward from between the gate electrode 22 and the semiconductor layer 21 (a portion that does not overlap with the gate electrode 22). A convex portion reflecting the portion that does not overlap with the gate electrode 22 is provided.
  • Such a structure of the transistor 20 shown in FIG. 6A can also be applied to the transistor 10.
  • the interlayer insulating film 16 is arranged below the semiconductor layer 11
  • the interlayer insulating film 17 is arranged above the semiconductor layer 11
  • the semiconductor layer 11 is formed between the interlayer insulating film 16 and the interlayer insulating layer 17 . placed in between.
  • An interlayer insulating film 19 is provided to cover the transistor 10 .
  • the conductor member 28 does not have to extend between the semiconductor layer 11 and the substrate 1 . Any one of the interlayer insulating films 16, 17, 19 overlapping the transistor 10 and any one of the interlayer insulating films 26, 27, 29 overlapping the transistor 20 may be the same layer.
  • interlayer insulating film 19 and the interlayer insulating film 26 may be the same layer.
  • Interlayer insulating film 17 may be the same layer as gate insulating film 15 .
  • the conductor member 28 is provided between the semiconductor layer 21 and the substrate 1 , and the interlayer insulation film provided between the conductor member 28 and the substrate 1 is at least one of the interlayer insulation film 17 and the gate insulation film 15 . may be in the same layer as
  • FIG. 6B illustrates a cross-sectional view of the B/S transistor shown in FIG. 2A.
  • FIG. 6B shows the magnitude relationship between the thickness and distance of each layer.
  • the gate insulating film 25 has a thickness T4 larger than the thickness T2 (T4>T2).
  • the interlayer insulating film 16 is arranged below the semiconductor layer 11
  • the interlayer insulating film 17 is arranged above the semiconductor layer 11
  • the semiconductor layer 11 is formed between the interlayer insulating film 16 and the interlayer insulating layer 17. placed in between.
  • FIGS. 7A to 7D A method for manufacturing the semiconductor device AP will be described with reference to FIGS. 7A to 7D.
  • FIG. 7A A first example of the manufacturing method is shown in FIG. 7A.
  • the semiconductor layer 11 is formed on the substrate 1 in step S11.
  • a conductor film 18 is formed on the substrate 1 to cover the semiconductor layer 11 .
  • the conductor film 18 contacts the semiconductor layer 11 .
  • the conductor film 18 is patterned.
  • wet etching or dry etching can be used for patterning, wet etching is preferable in order to suppress damage to the semiconductor layer 11 .
  • a source electrode 13 and a drain electrode 14 are formed from the conductor film 18 by patterning.
  • the gate electrode 22 or the conductor member 28 is formed from the conductor film 18 by patterning.
  • step S ⁇ b>14 a semiconductor layer 21 insulated from the gate electrode 22 or the conductor member 28 is formed on the gate electrode 22 or the conductor member 28 .
  • the gate electrode 22 or conductor member 28 is formed in the same layer as the source electrode 13 and drain electrode 14 .
  • FIG. 7B A second example of the manufacturing method is shown in FIG. 7B.
  • a conductor film 18 is formed on the substrate 1 in step S21.
  • the conductor film 18 is patterned. Wet etching or dry etching can be used for patterning.
  • a source electrode 13 and a drain electrode 14 are formed from the conductor film 18 by patterning.
  • the gate electrode 22 or the conductor member 28 is formed from the conductor film 18 by patterning.
  • step S23 the semiconductor layer 11 covering the source electrode 13 and the drain electrode 14 is formed. At this time, the semiconductor layer 11 contacts the source electrode 13 and the drain electrode 14 .
  • step S ⁇ b>14 a semiconductor layer 21 insulated from the gate electrode 22 or the conductor member 28 is formed on the gate electrode 22 or the conductor member 28 .
  • the gate electrode 22 or conductor member 28 is formed in the same layer as the source electrode 13 and drain electrode 14 .
  • FIG. 7C A third example of the manufacturing method is shown in FIG. 7C.
  • the semiconductor layer 11 is formed on the substrate 1 in step S31.
  • a semiconductor layer 21 is formed on the substrate 1 in step S32.
  • a conductor film 18 covering the semiconductor layers 11 and 21 is formed on the substrate 1 .
  • the conductor film 18 is in contact with the semiconductor layer 11 and an insulating film is provided between part of the conductor film 18 and the semiconductor layer 21 .
  • the conductor film 18 is patterned.
  • wet etching or dry etching can be used for patterning, wet etching is preferable in order to suppress damage to the semiconductor layers 11 and 21 .
  • a source electrode 13 and a drain electrode 14 are formed from the conductor film 18 by patterning. Further, the gate electrode 22 or the conductor member 28 is formed from the conductor film 18 by patterning. The gate electrode 22 or the conductor member 28 is insulated from the semiconductor layer 21 by the insulating film provided in step S34. Thus, the gate electrode 22 or conductor member 28 is formed in the same layer as the source electrode 13 and drain electrode 14 .
  • FIG. 7D A fourth example of the manufacturing method is shown in FIG. 7D.
  • the semiconductor layer 21 is formed on the substrate 1 in step S41.
  • a semiconductor layer 11 is formed on the substrate 1 in step S42.
  • a conductor film 18 covering the semiconductor layers 11 and 21 is formed on the substrate 1 .
  • the conductor film 18 is in contact with the semiconductor layer 11 and an insulating film is provided between part of the conductor film 18 and the semiconductor layer 21 .
  • the conductor film 18 is patterned. Although wet etching or dry etching can be used for patterning, wet etching is preferable in order to suppress damage to the semiconductor layers 11 and 21 .
  • a source electrode 13 and a drain electrode 14 are formed from the conductor film 18 by patterning. Further, the gate electrode 22 or the conductor member 28 is formed from the conductor film 18 by patterning. The gate electrode 22 or the conductor member 28 is insulated from the semiconductor layer 21 by the insulating film provided in step S44. Thus, the gate electrode 22 or conductor member 28 is formed in the same layer as the source electrode 13 and drain electrode 14 .
  • the conductor film 18 is formed before the semiconductor layer 21 is formed. Steps occurring in the conductor film 18 can be reduced as compared with the example and the fourth example of FIG. 7D. Therefore, in the first example shown in FIG. 7A and the second example shown in FIG. 7B, patterning of the conductor film 18 can be performed better than in the third example shown in FIG. 7C and the fourth example shown in FIG. 7D.
  • the semiconductor layer 11 can be formed by the CVD method
  • the semiconductor layer 21 can be formed by the PVD method
  • the conductor film 18 can be formed by the PVD method
  • the insulator film can be formed by the CVD method. can be formed.
  • the distance D1 between the semiconductor layer 11 and the substrate 1 may be different from the distance D2 between the semiconductor layer 21 and the substrate 1.
  • the characteristics of the transistors 10 and 20 can be made more appropriate than when the distances D1 and D2 are equal.
  • the semiconductor layers 11 and 21 are affected by the substrate 1 , and the semiconductor layers 11 and 21 are affected by members existing on the side opposite to the substrate 1 with respect to the semiconductor layers 11 and 21 .
  • the characteristics of the transistors 10 and 20 can be made more appropriate.
  • the distance D3 between the substrate 1 and the gate electrode 12 may be different from the distance D4 between the substrate 1 and the gate electrode 22. That is, the influence of the substrate 1 on the gate electrodes 12 and 22 and the influence of the members existing on the side opposite to the substrate 1 side with respect to the gate electrodes 12 and 22 on the gate electrodes 12 and 22 are determined by the transistors 10 and 20. characteristics can be made more appropriate.
  • the distance D3 between the substrate 1 and the gate electrode 12 may be different from the distance D2 between the substrate 1 and the semiconductor layer 21.
  • the distance D4 between the substrate 1 and the gate electrode 22 may be different from the distance D1 between the substrate 1 and the semiconductor layer 11 .
  • the distance D5 between the semiconductor layer 11 and the gate electrode 12 may be different from the distance D6 between the semiconductor layer 21 and the gate electrode 22.
  • a distance D 5 between the semiconductor layer 11 and the gate electrode 12 corresponds to the thickness of the gate insulating film 15
  • a distance D 6 between the semiconductor layer 21 and the gate electrode 22 corresponds to the thickness of the gate insulating film 25 .
  • the conductor layers in the same layer be discontinuous between the transistor 10 and the transistor 20 .
  • another conductor layer may be used for connection.
  • the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are electrically connected in the same layer and discontinuously, at least one of the gate electrode 12 and the source electrode 23 (drain electrode 24) The two may be connected by a conductor layer included in the .
  • the element S1 contained in the semiconductor layer 11 can be a group 14 element, and the element S2 contained in the semiconductor layer 21 can be a group 12, 13, 15 or 16 element.
  • the element S1 included in the semiconductor layer 11 may be silicon (Si), and the element S2 included in the semiconductor layer 21 may be oxygen (O).
  • the semiconductor layer 11 may be a polycrystalline layer or an amorphous layer, and the semiconductor layer 21 may be an oxide semiconductor layer.
  • Semiconductor layer 11 may be a polycrystalline silicon layer.
  • the element S4 may be indium (In). By using indium (In) as the element S4, the mobility of the semiconductor layer 21 can be increased.
  • the semiconductor layer 21 may contain gallium (Ga).
  • the semiconductor layer 21 may contain tin (Sn). By including tin (Sn) in the semiconductor layer 21, the mobility of the semiconductor layer 21 can be increased.
  • the substrate 1 may be an insulator substrate such as glass or resin, but may be a semiconductor substrate such as silicon or a conductor substrate such as metal.
  • a substrate is prepared by forming a resin film such as polyimide on a base material such as glass, and the transistors 10 and 20 are formed on the resin film of the substrate. Thereafter, the base material and the resin film are separated using a laser or the like, and this resin film can be used as the substrate 1 (resin substrate).
  • the resin substrate may be a flexible substrate.
  • the substrate 1 is a semiconductor substrate, at least one of the semiconductor layers 11 and 21 may be a single crystal semiconductor layer epitaxially grown on the substrate 1, which is a single crystal semiconductor, in conformity with the crystal structure of the substrate 1.
  • the substrate 1 is a semiconductor substrate
  • at least one of the semiconductor layers 11 and 21 has a structure (SOI (Semiconductor On Insulator) structure) formed on the substrate 1, which is a single crystal semiconductor, with an insulator layer interposed therebetween.
  • SOI semiconductor On Insulator
  • Transistor 10 may be a P-type transistor or an N-type transistor.
  • Transistor 10 preferably forms a CMOS circuit together with transistor 30, preferably transistor 10 is a P-type transistor and transistor 30 is an N-type transistor.
  • Transistor 10 may be an N-type transistor and transistor 30 may be a P-type transistor.
  • An element having the highest concentration in the semiconductor layer 31 among elements belonging to Groups 12 to 16 contained in the semiconductor layer 31 of the transistor 30 is an element S5.
  • Element S5 may be the same as element S1 contained in semiconductor layer 11 .
  • An element S6 is an element having the second highest concentration in the semiconductor layer 31 after the element S5 among the elements of Groups 12 to 16 contained in the semiconductor layer 31 of the transistor 30 .
  • Element S6 may be different from element S3 contained in semiconductor layer 11 .
  • element S1 and element S5 may be silicon (Si)
  • element S3 may be boron (B)
  • element S6 may be phosphorus (P).
  • the transistor 10 is an N-type transistor and the transistor 30 is a P-type transistor
  • the element S3 may be phosphorus (P) and the element S6 may be boron (B).
  • the semiconductor layer 11 of the transistor 10 or the semiconductor layer 31 of the transistor 30 is a polycrystalline semiconductor layer, it is suitable for speeding up switching due to high carrier mobility.
  • the semiconductor layer 11 of the transistor 10 and the semiconductor layer 31 of the transistor 30 are polycrystalline semiconductor layers, the gate voltage can be lowered due to high carrier mobility compared to an amorphous semiconductor, and thus the power consumption of the transistors can be reduced. It is suitable for
  • the transistor 20 may be a P-type transistor or an N-type transistor.
  • Transistor 20 is preferably an N-type transistor because electrons generally have higher mobility than holes.
  • Transistor 20 is also preferably a switch transistor. High-speed switching is possible if the transistor 20 is an N-type switch transistor. If the semiconductor layer 21 of the transistor 20 is an oxide semiconductor, leakage current can be reduced due to a wide bandgap, which is suitable for reducing leakage current of the switching transistor.
  • the diagonal length is preferably 1 cm or more, more preferably 2.5 cm or more.
  • Semiconductor layer 11 of transistor 10 may be a single crystal layer if the diagonal length is less than 2.5 cm.
  • the transistor 10 may be formed on the substrate 1 made of single crystal silicon, and the transistor 20 which is a thin film transistor may be formed on the substrate 1 .
  • the diagonal length of the substrate 1 may be 5 cm or more.
  • the transistor 10 is preferably a thin film transistor, and the semiconductor layer 11 can be a polycrystalline layer or an amorphous layer.
  • the semiconductor layer 11 is a polycrystalline layer or an amorphous layer, even if the diagonal length of the substrate 1 is 5 cm or more, sufficient uniformity in the characteristics of the transistor 10 can be ensured.
  • the diagonal length of substrate 1 is less than 75 cm, semiconductor layer 11 of transistor 10 is preferably a polycrystalline layer. If the semiconductor layer 11 of the transistor 10 is a polycrystalline layer, the diagonal length of the substrate 1 may be 20 cm or more, 25 cm or more, or 30 cm or more. When the diagonal length of the substrate 1 is 20 cm or more, it is preferable to dispose the transistor 10 using a polycrystalline layer as the semiconductor layer 11 in the pixel circuit PX.
  • the diagonal length of the substrate 1 is preferably less than 50 cm from the viewpoint of improving image quality. If the diagonal length of the substrate 1 is less than 50 cm, sufficient uniformity in the characteristics of the transistor 10 can be ensured.
  • the semiconductor layer 11 of the transistor 10 is preferably an amorphous layer. Regardless of the diagonal length of the substrate 1, the semiconductor layer 21 of the transistor 20 is preferably an oxide semiconductor layer.
  • the diagonal length of the substrate 1 has been described here, the same applies to the diagonal length of the pixel region 2 , and the diagonal length of the substrate 1 may be read as the diagonal length of the pixel region 2 .
  • the diagonal length of the pixel region 2 is preferably 1 cm or more, preferably 2.5 cm or more, preferably 5 cm or more, and may be 20 cm or more, 25 cm or more, or 30 cm or more. , less than 75 cm.
  • the fifteenth embodiment is a combination of the eleventh and fourteenth embodiments, and the distance D1 between the semiconductor layer 11 and the substrate 1 is longer than the distance D2 between the semiconductor layer 21 and the substrate 1. Small is preferred.
  • the semiconductor layer 11 is a polycrystalline layer, control of crystallinity is important. By arranging the semiconductor layer 11 closer to the substrate 1 than the semiconductor layer 21, the flatness of the semiconductor layer 11 can be improved and the uniformity of crystallinity can be improved. Further, by forming the semiconductor layer 11 before the semiconductor layer 21 is formed, it is possible to suppress the semiconductor layer 21 from being affected by the heat treatment for forming the semiconductor layer 11 . In other words, an appropriate heat treatment can be performed on the semiconductor layer 11 before the semiconductor layer 21 is formed. Therefore, the crystallinity of the semiconductor layer 11 can be easily controlled.
  • the sixteenth embodiment is a combination of the twelfth embodiment and the fourteenth embodiment, and the distance D3 between the substrate 1 and the gate electrode 12 is longer than the distance D4 between the substrate 1 and the gate electrode 22. Small is preferred.
  • the seventeenth embodiment is a combination of the twelfth embodiment and the fifteenth embodiment, and the distance D5 between the semiconductor layer 11 and the gate electrode 12 is the distance D6 between the semiconductor layer 21 and the gate electrode 22.
  • a distance D 5 between the semiconductor layer 11 and the gate electrode 12 corresponds to the thickness of the gate insulating film 15
  • a distance D 6 between the semiconductor layer 21 and the gate electrode 22 corresponds to the thickness of the gate insulating film 25 .
  • the distance D5 may be 200-400 nm and the distance D6 may be 50-200 nm.
  • the eighteenth embodiment relates to the capacitor C provided on the substrate 1.
  • the capacitor C can be applied to the capacitors 103 and 108 shown in FIGS. 1C and 1D, for example, but it can also be applied to the integrated circuit in the peripheral region 3 as well as the capacitor in the pixel circuit PX.
  • at least one of a lower gate electrode 221 and an upper gate electrode 222 is provided on the substrate 1 as the gate electrode 22 overlapping the semiconductor layer 21 .
  • both the lower gate electrode 221 and the upper gate electrode 222 are shown in FIG. 8 for convenience, one of them may be omitted.
  • the lower gate electrode 221 is provided on the substrate 1 side with respect to the semiconductor layer 21 , and the lower gate electrode 221 is positioned between the semiconductor layer 21 and the substrate 1 .
  • the lower gate electrode 221 corresponds to the gate electrode 22 in the B-type transistor 20 shown in FIGS. 2B, 2C, 3B, 4B, 5B, and 6B.
  • the upper gate electrode 222 is provided on the side opposite to the substrate 1 with respect to the semiconductor layer 21 , and the semiconductor layer 21 is positioned between the upper gate electrode 222 and the substrate 1 .
  • the upper gate electrode 222 corresponds to the gate electrode 22 in the T-type transistor 20 shown in FIGS. 2A, 2D, 3A, 4A, 5A, and 6A.
  • the lower gate electrode 221 and/or the upper gate electrode 222 overlap the semiconductor layer 21, and the gate insulating film 25 is provided between the lower gate electrode 221 and the semiconductor layer 21 and/or between the upper gate electrode 222 and the semiconductor layer 21. is provided.
  • the lower gate electrode 221 can overlap either the source electrode 23 or the drain electrode 24 .
  • the lower gate electrode 221 constitutes the source electrode 23 or the drain electrode 24 together with the capacitance Ce.
  • the upper gate electrode 222 can overlap either the source electrode 23 or the drain electrode 24 .
  • the lower gate electrode 221 forms a capacitor Ch together with the source electrode 23 or the drain electrode 24 .
  • the capacitors Ce and Ch are MIM type capacitors in which a dielectric layer is sandwiched between conductor layers.
  • the lower gate electrode 221 and the upper gate electrode 222 may be electrically connected to each other.
  • the conductor layer of the lower gate electrode 221 and the conductor layer of the upper gate electrode 222 may be in contact with each other, or may be electrically connected through another conductor layer (for example, via). good.
  • the element M2 of the conductor layer of at least one of the lower gate electrode 221 and the upper gate electrode 222 is preferably the same as the element M1 of the conductor layer of at least one of the source electrode 13 and the drain electrode .
  • the conductive layer containing the element M2 of either one of the lower gate electrode 221 and the upper gate electrode 222 may be the same layer as the conductive layer containing the element M1 of at least one of the source electrode 13 and the drain electrode 14. preferable.
  • the 19th embodiment also relates to the capacitor C provided on the substrate 1.
  • the capacitor C can be applied to the capacitors 103 and 108 shown in FIGS. 1C and 1D, for example, but it can also be applied to the integrated circuit in the peripheral region 3 as well as the capacitor in the pixel circuit PX. Description of the same points as those of the eighteenth embodiment is omitted.
  • a lower capacitor electrode 281 and an upper capacitor electrode 282 can be provided on the substrate 1 as the conductor member 28 . Although both the lower capacitor electrode 281 and the upper capacitor electrode 282 are shown in FIG. 8 for convenience, one of them may be omitted, or both the lower capacitor electrode 281 and the upper capacitor electrode 282 may be omitted. good too.
  • the lower capacitor electrode 281 overlaps with at least one of the lower gate electrode 221 , the source electrode 23 , the drain electrode 24 , the upper gate electrode 222 and the upper capacitor electrode 282 .
  • the lower capacitive electrode 281 is located between the substrate 1 and an electrode overlapping the lower capacitive electrode 281 .
  • the lower capacitive electrode 281 and at least one of the electrodes overlapping the lower capacitive electrode 281 constitute an MIM type capacitor in which a dielectric layer is sandwiched between conductor layers.
  • the dielectric layer of the capacitor is the interlayer insulating film 26 .
  • the lower capacitor electrode 281 constitutes the lower gate electrode 221 and the capacitor Cf.
  • the lower capacitor electrode 281 constitutes the source electrode 23 or the drain electrode 24 and the capacitor Ci.
  • the lower capacitor electrode 281 constitutes the upper gate electrode 222 and the capacitor Cj.
  • the lower capacitor electrode 281 and the upper capacitor electrode 282 form a capacitor Ca.
  • the upper capacitor electrode 282 overlaps with at least one of the lower capacitor electrode 281 , the lower gate electrode 221 , the source electrode 23 , the drain electrode 24 and the upper gate electrode 222 .
  • the electrode overlapping the upper capacitive electrode 282 is positioned between the upper capacitive electrode 282 and the substrate 1 .
  • the upper capacitive electrode 282 and at least one of the electrodes overlapping the upper capacitive electrode 282 constitute an MIM type capacitor in which a dielectric layer is sandwiched between conductor layers.
  • the dielectric layer of the capacitor is the interlayer insulating film 26 .
  • the upper capacitor electrode 282 forms a capacitor Ca together with the lower capacitor electrode 281 .
  • the upper capacitor electrode 282 constitutes the lower gate electrode 221 and the capacitor Cb.
  • the upper capacitor electrode 282 forms a capacitor Cd together with the source electrode 23 or the drain electrode 24 .
  • the upper capacitor electrode 282 and the upper gate electrode 222 form a capacitor Cg.
  • FIG. 8 shows an example in which the lower capacitive electrode 281 and the upper capacitive electrode 282 overlap the semiconductor layer 21 .
  • a lower capacitive electrode 281 is located between the semiconductor layer 21 and the substrate 1 .
  • the semiconductor layer 21 is positioned between the upper capacitive electrode 282 and the substrate 1 .
  • the lower capacitive electrode 281 and the upper capacitive electrode 282 need only overlap with the counterpart electrodes forming the capacity, and do not necessarily overlap with the semiconductor layer 21 .
  • the element M5 of the conductor layer of at least one of the lower capacitive electrode 281 and the upper capacitive electrode 282 is preferably the same as the element M1 of the conductor layer of at least one of the source electrode 13 and the drain electrode 14 .
  • the conductive layer containing the element M5 in either one of the lower capacitor electrode 281 and the upper capacitor electrode 282 is the same layer as the conductive layer containing the element M1 in at least one of the source electrode 13 and the drain electrode 14. preferable.
  • At least one of the two electrodes forming the capacitor C is the gate electrode 22 or the conductor member 28 (capacitor electrode) that does not contact the semiconductor layer 21 .
  • the other of the two electrodes forming the capacitor C is the gate electrode 22 or the conductor member 28 (capacitor electrode) that does not contact the semiconductor layer 21, or the source electrode 13 or the drain electrode 14 that contacts the semiconductor layer 21. is.
  • the electrode (the gate electrode 22 or the conductor member 28 (capacitor electrode)) not in contact with the semiconductor layer 21 forms the capacitance C with the dielectric layer (interlayer insulating film 26). It is insulated from the other of the two electrodes that connect.
  • the capacitors 103 and 108 shown in FIGS. 1C and 1D are connected to the source or drain of the reset transistor 102 serving as the transistor 20, the source or drain of the select transistor 107, and the source or drain of the drive transistor 106.
  • the capacitor electrodes electrically connected to the semiconductor layers 11 and 21 of the transistors 10 and 20 are indirectly connected via other conductor layers (such as vias) so as not to contact the semiconductor layers 11 and 21. can be connected to the semiconductor layers 11 and 21 at the same time. By doing so, metal contamination of the semiconductor layers 11 and 21 can be suppressed.
  • the elements M1 to M5 are copper (Cu), which is easily diffused, it is preferable to prevent the conductive layer (copper layer) made of copper from contacting the semiconductor layers 11 and 21 .
  • the gate electrode 22 can correspond to the upper gate electrode 222 shown in FIG. 8, and the conductor member 28 can correspond to the lower capacitor electrode 281 shown in FIG.
  • the gate electrode 22 and the conductor member 28 can form the capacitance Cj shown in FIG.
  • This capacitor Cj can be used, for example, as the capacitors 103 and 108 shown in FIGS. 1C and 1D.
  • the gate electrode 22 can correspond to the lower gate electrode 221 shown in FIG. 8, and the conductor member 28 can correspond to the upper capacitive electrode 282 shown in FIG.
  • the gate electrode 22 and the conductor member 28 can form the capacitance Cb shown in FIG.
  • This capacitance Cb can be used, for example, as the capacitances 103 and 108 shown in FIGS. 1C and 1D.
  • FIG. 9A No. 1 in Table 1 is shown using a dashed line. 1 illustrates a cross-sectional view of a semiconductor device AP having the configuration of FIG.
  • the dashed-dotted line in FIG. 9A indicates that the members connected by the dashed-dotted line are in the same layer, that is, the source electrode 13 (and the drain electrode 14) are in the same layer as the gate electrode 22.
  • the No. 02 illustrates a cross-sectional view of a semiconductor device AP having the configuration of FIG.
  • the two-dot chain line in FIG. 9A indicates the case where the members connected by the two-dot chain line are in the same layer, that is, the case where the source electrode 13 (and the drain electrode 14) is in the same layer as the conductive member 28.
  • the gate electrode 22 corresponds to the upper gate electrode 222 shown in FIG. 8, and the conductor member 28 corresponds to the upper capacitor electrode 282 shown in FIG.
  • Gate electrode 22 and conductive member 28 form capacitance Cg shown in FIG.
  • This capacitance Cg can be used, for example, as the capacitances 103 and 108 shown in FIGS. 1C and 1D.
  • FIG. 9B No. 1 in Table 1 is shown using a dashed line. 1 illustrates a cross-sectional view of a semiconductor device AP having 17 configurations.
  • the dashed-dotted line in FIG. 9B indicates that the members connected by the dashed-dotted line are in the same layer, that is, the source electrode 13 (and the drain electrode 14) are in the same layer as the gate electrode 22.
  • the No. 1 illustrates a cross-sectional view of a semiconductor device AP having 18 configurations.
  • the two-dot chain line in FIG. 9B indicates the case where the members connected by the two-dot chain line are in the same layer, that is, the case where the source electrode 13 (and the drain electrode 14) is in the same layer as the conductive member 28.
  • the gate electrode 22 corresponds to the lower gate electrode 221 shown in FIG. 8
  • the conductor member 28 corresponds to the lower capacitor electrode 281 shown in FIG.
  • Gate electrode 22 and conductive member 28 form capacitance Cf shown in FIG.
  • This capacitance Cf can be used, for example, as the capacitances 103 and 108 shown in FIGS. 1C and 1D.
  • the insulator 40 as shown in FIG. 1B is provided on the substrate 1, and the interlayer insulating film included in the insulator 40 is provided around the semiconductor layers 11 and 21.
  • An insulating film such as a gate insulating film is provided.
  • FIGS. 3A to 9B illustration of at least part of these insulators 40 is omitted.
  • FIG. 10A shows an equipment EQP including a semiconductor device AP.
  • the equipment EQP may comprise a display device DSPL, an imaging device IS, an audio device AUDIO, a control device CTRL and/or a communication device IF.
  • either the display device DSPL or the imaging device IS has the structure of the semiconductor device AP described above.
  • the audio device AUDIO, the control device CTRL and the communication device IF may have the structure of the semiconductor device AP described above.
  • the audio device AUDIO has a microphone and a speaker.
  • the communication device IF performs wired communication and wireless communication.
  • the communication device IF may communicate in a frequency band of 3.5-5.0 GHz, or may communicate in a frequency band of 24-53 GHz.
  • the communication device IF may communicate not only with microwaves and millimeter waves, but also with terahertz waves.
  • the control device CTRL can be composed of a wiring board and a plurality of components mounted on the wiring board.
  • the control device CTRL may include a semiconductor device manufactured under a 65-5 nm process rule, or may include a semiconductor device manufactured under a 1-4 nm process rule.
  • An EUV exposure apparatus, an electron beam exposure apparatus, a nanoimprint lithography apparatus, or the like may be used for manufacturing these devices.
  • the control device CTRL is connected to the display device DSPL.
  • the control device CTRL can supply power and signals to the driving circuit. If the display device DSPL does not have a driving circuit for driving the pixel circuits in the peripheral region 3, the control device CTRL has a driving circuit for driving the pixel circuits.
  • the control device CTRL is connected to the imaging device IS.
  • the control device CTRL controls the imaging mode of the imaging device IS and processes signals output from the imaging device IS.
  • the imaging device IS may be an image sensor, an infrared sensor, or a distance measuring sensor.
  • the equipment EQP can include an optical member OPT provided on the display device DSPL, which is the semiconductor device AP.
  • the optical members OPT are lenses, covers, and filters. If the semiconductor device AP is a top emission display device DSPL, a semiconductor layer 21 can be provided between the substrate 1 of the semiconductor device AP and the optical member OPT. If the semiconductor device AP is a bottom emission display device DSPL, the substrate 1 can be provided between the semiconductor layer 21 of the semiconductor device AP and the optical member OPT.
  • the equipment EQP may comprise an imaging device IS and a display device DSPL.
  • the image captured by the imaging device IS can be displayed on the display device DPSL.
  • the low frame rate is 10 fps or less, further 5 fps or less, such as 1 fps
  • the high frame rate is, for example, 100 fps or more, further 200 fps or more, such as 240 fps. It may be possible to switch between display at a low refresh rate by the display device DSPL and display at a high refresh rate higher than the low refresh rate.
  • a low refresh rate is 10 Hz or less, even 5 Hz or less, such as 1 Hz
  • a high refresh rate is, for example, 100 Hz or more, or even 200 Hz or more, such as 240 Hz.
  • both the frame rate unit fps and the refresh rate unit Hz can be expressed as “frames/second” or “times/second”. It may also be switchable for the display device DSPL to display at a medium frame rate between a low frame rate and a high frame rate. For example, the medium frame rate is 20-80 fps. It may also be switchable for the display device DSPL to display at a medium refresh rate between a low refresh rate and a high refresh rate.
  • a medium refresh rate is 20-80 Hz. Since an oxide semiconductor layer has low leakage current, the use of an oxide semiconductor layer for the selection transistor 107 suppresses charge leakage from the capacitor 108 and facilitates driving at a low frame rate. In addition, since the polycrystalline semiconductor layer has higher mobility than the amorphous semiconductor layer, the use of the polycrystalline semiconductor layer for the selection transistor 107 enables high-speed selection and facilitates driving at a high frame rate and refresh rate. be. In addition, since the polycrystalline semiconductor layer has higher mobility than the amorphous semiconductor layer, the use of the polycrystalline semiconductor layer for the driving transistor 106 can lower the gate voltage and facilitates driving with low power consumption. .
  • the imaging device IS can shoot at a middle frame rate between the above-described low frame rate and high frame rate.
  • the imaging device IS can shoot at a middle frame rate between the above-described low refresh rate and high refresh rate.
  • the imaging device IS can shoot at a frame rate of 20-80 fps.
  • the shooting here is not limited to saving an image, and includes shooting only for temporary display such as live view.
  • the frame rate of the display device DSPL when displaying an image captured by the imaging device IS at a medium frame rate is preferably a medium frame rate or a high frame rate.
  • the refresh rate of the display device DSPL when displaying an image captured by the imaging device IS at a medium frame rate is preferably a medium refresh rate or a high refresh rate.
  • the refresh rate of the display device DSPL is preferably 60 frames/second or 120 frames/second.
  • Device EQPs can be electronic devices such as smartphones, tablet terminals, laptop personal computers, digital cameras, and wearable terminals.
  • the device EQP may comprise batteries such as lithium-ion batteries, solid-state batteries, fuel cells, and the like. Since the power consumption of the imaging device IS and the display device DSPL can be reduced, they can be driven by a battery for a long time.
  • FIG. 10B shows a head mounted display HMD as a wearable terminal.
  • the main body having the display device DSPL and the imaging device IS can be worn on the head by the mounting means WR.
  • the present invention can be applied to various devices such as transportation devices, industrial devices, medical devices, and analytical devices.

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014075699A (ja) * 2012-10-04 2014-04-24 Canon Inc 動画再生装置、表示制御方法、プログラム及び記憶媒体
JP2015156486A (ja) * 2014-02-19 2015-08-27 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 有機発光ディスプレイ装置
JP2018006733A (ja) * 2016-03-18 2018-01-11 株式会社半導体エネルギー研究所 半導体装置、該半導体装置を有する表示装置
JP2018018068A (ja) * 2016-07-15 2018-02-01 株式会社半導体エネルギー研究所 表示装置、表示モジュール、電子機器、及び表示装置の作製方法
JP2018025777A (ja) * 2016-08-03 2018-02-15 株式会社半導体エネルギー研究所 表示装置および電子機器
CN112289744A (zh) * 2020-11-13 2021-01-29 武汉华星光电技术有限公司 阵列基板及其制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014075699A (ja) * 2012-10-04 2014-04-24 Canon Inc 動画再生装置、表示制御方法、プログラム及び記憶媒体
JP2015156486A (ja) * 2014-02-19 2015-08-27 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 有機発光ディスプレイ装置
JP2018006733A (ja) * 2016-03-18 2018-01-11 株式会社半導体エネルギー研究所 半導体装置、該半導体装置を有する表示装置
JP2018018068A (ja) * 2016-07-15 2018-02-01 株式会社半導体エネルギー研究所 表示装置、表示モジュール、電子機器、及び表示装置の作製方法
JP2018025777A (ja) * 2016-08-03 2018-02-15 株式会社半導体エネルギー研究所 表示装置および電子機器
CN112289744A (zh) * 2020-11-13 2021-01-29 武汉华星光电技术有限公司 阵列基板及其制作方法

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