WO2022188507A1 - 一种数字电路和电子装置 - Google Patents

一种数字电路和电子装置 Download PDF

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Publication number
WO2022188507A1
WO2022188507A1 PCT/CN2021/140352 CN2021140352W WO2022188507A1 WO 2022188507 A1 WO2022188507 A1 WO 2022188507A1 CN 2021140352 W CN2021140352 W CN 2021140352W WO 2022188507 A1 WO2022188507 A1 WO 2022188507A1
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Prior art keywords
switching device
voltage
state
turned
signal
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PCT/CN2021/140352
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English (en)
French (fr)
Inventor
王翠翠
王临春
臧大军
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华为技术有限公司
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Publication of WO2022188507A1 publication Critical patent/WO2022188507A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Definitions

  • the present application relates to the field of circuits, and more particularly, to a digital circuit and an electronic device.
  • Digital information storage devices are the most basic logic units that constitute various sequential circuits, and are also important devices in digital integrated circuits.
  • digital information storage devices for example, D flip-flops
  • MOSFETs metal oxide semiconductor field effect transistors
  • the present application provides a digital circuit and an electronic device capable of realizing non-volatile storage of digital information.
  • the present application provides a digital circuit, the digital circuit comprising:
  • control circuit and a first device, the control circuit includes an input end, a first output end and a clock control end, the clock control end is connected with a first clock signal, and the control circuit is used for:
  • the threshold voltage of the first device is controlled according to the first signal received by the input terminal, and different states of the first signal correspond to the threshold voltage of the first device. Different threshold voltages;
  • the on-off state of the first device is controlled according to the threshold voltage of the first device, and according to the on-off state of the first device, A third signal is output, the third signal being a signal related to the first signal.
  • the third signal is a signal in the same state as the first signal.
  • the digital circuit of the present application can control the threshold voltage of the first device according to the value of the data signal received by the input terminal when the first clock signal is in the first state.
  • the current threshold voltage of the first device will affect the on-off state of the first device, and the first Different states of a device can cause the output to output different signals.
  • the digital circuit of the present application can transmit the data signal at the input end to the output end, so that the output end outputs a signal related to the digital signal.
  • the digital circuit of the present application can realize the non-volatile storage of the data signal while realizing that the data signal of the input end is transmitted to the output end through a complete clock cycle.
  • control circuit is further configured to:
  • a second signal is output through the first output terminal, and the second signal is the last signal after the first clock signal changes from the first state to the second state The signal output by the first output terminal.
  • the first output terminal when the first clock signal is in the first state, the first output terminal outputs the signal output by the first output terminal after the last time the first clock signal changes from the first state to the second state, that is, the control circuit according to When the first information controls the threshold voltage of the first device, the control circuit can keep outputting the last "saved" digital information until the first clock signal changes to the second state.
  • the digital circuit of the present application can realize the non-volatile storage of the data signal while realizing the function of the D flip-flop.
  • the first state of the first signal corresponds to the first state of the threshold voltage
  • the first state of the threshold voltage A state corresponds to a first state of the third signal
  • a second state of the first signal corresponds to a second state of the threshold voltage
  • the second state of the threshold voltage corresponds to a second state of the third signal second state.
  • the high level of the first signal corresponds to the high threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the high level of the third signal.
  • the high level of the first signal corresponds to the low threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the high level of the third signal.
  • the low level of the first signal corresponds to the high threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the low level of the third signal.
  • a low level of the first signal corresponds to a low threshold voltage of the threshold voltage
  • a high threshold voltage corresponds to a low level of the third signal.
  • the high level of the first signal corresponds to the high threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the low level of the third signal.
  • the high level of the first signal corresponds to the low threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the low level of the third signal.
  • the low level of the first signal corresponds to the high threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the high level of the third signal.
  • a low level of the first signal corresponds to a low threshold voltage of the threshold voltage
  • a high threshold voltage corresponds to a high level of the third signal.
  • the first device includes a gate electrode, a source electrode and a drain electrode, and the on-off state is the first device The on-off state between the source and drain.
  • the first device further includes a substrate; the control circuit is specifically configured to: control the gate and all the At least one of a voltage between the source, a voltage between the gate and the drain, and a voltage between the gate and the substrate controls the threshold voltage.
  • the level of the gate when the first clock signal is in the first state, the level of the gate is the same as the level of the source. The level is opposite, and/or the level of the gate is opposite to that of the drain, and/or the level of the gate is opposite to that of the substrate.
  • the level of the gate of the first device is opposite to the level of the source, and/or the level of the gate is opposite to the level of the drain, and/or the level of the gate is opposite
  • the level of the level is opposite to that of the substrate, so that the first device changes the polarity according to the voltage difference between the gate and at least one of the source, the drain, and the substrate, so as to realize the change of the threshold voltage of the first device, that is, the first device.
  • a signal is "stored" in the first device.
  • the control circuit includes a first switching device and an inverting circuit; the input terminal is connected to the first switching device through the first switching device. the gate is connected, the input terminal is connected to at least one of the source, the drain and the substrate through the first switching device and the inverting circuit, the first switching device
  • the control terminal of the device is connected to the first clock signal, and the inverting circuit is used for inverting the first signal; when the first clock signal is in the first state, the first switching device conducts the first signal is input to the gate, and is input to at least one of the source, the drain and the substrate after inversion processing by the inverter circuit, so as to control the first signal
  • the threshold voltage of a device when the first clock signal is in the second state, the first switching device is turned off.
  • the first signal is input to the gate of the first device, and at the same time, the first signal is input to at least one of the source, drain and substrate of the first device through inversion processing, so that the first device can be
  • the level of the gate is opposite to that of the source, and/or the level of the gate is opposite to that of the drain, and/or the level of the gate is opposite to that of the substrate.
  • the control circuit includes a first switching device and an inverting circuit; the input terminal passes through the first switching device and The reverse circuit is connected to the gate, and the input terminal is connected to at least one of the source, the drain and the substrate through the first switching device, the first switching device
  • the control terminal of the device is connected to the first clock signal, and the inverting circuit is used for inverting the first signal; when the first clock signal is in the first state, the first switching device conducts the first signal is input to at least one of the source electrode, the drain electrode and the substrate, and is input to the gate after inversion processing by the inverter circuit, so as to control the first signal
  • the threshold voltage of a device when the first clock signal is in the second state, the first switching device is turned off.
  • the first signal is input to the gate of the first device through inversion processing, while the first signal is input to at least one of the source, drain and substrate of the first device, so that the first device can be realized
  • the level of the gate is opposite to that of the source, and/or the level of the gate is opposite to that of the drain, and/or the level of the gate is opposite to that of the substrate.
  • the inverter circuit includes at least one first inverter.
  • the inverter circuit further includes at least one second switching device, the at least one first inverter is connected to the at least one second switch device is in one-to-one correspondence, a control terminal of the second switch device is connected to the first clock signal, the second switch device is turned on when the first clock signal is in a first state, and It is turned off when the first clock signal is in the second state.
  • control circuit includes a third switching device, and a control end of the third switching device is connected to the first clock signal connected, the gate is connected to a first voltage through the third switching device, and the source is connected to a second voltage;
  • the third switching device When the first clock signal is in the first state, the third switching device is turned off;
  • the third switching device When the first clock signal is in the second state, the third switching device is turned on, the voltage of the gate is the first voltage, and the voltage of the source is the second voltage;
  • the first device tube is turned on
  • the first device is turned off.
  • the first clock signal when the first clock signal is in the second state, a voltage is applied to the gate and source of the first device, and its current threshold voltage will affect its on-off state, that is, it can be realized according to the current state of the first device.
  • the threshold voltage changes its on-off state.
  • control circuit further includes a fourth switching device, and a control end of the fourth switching device is connected to the first clock a signal connection, the source is connected to the second voltage through the fourth switching device;
  • the fourth switching device When the first clock signal is in the first state, the fourth switching device is turned off;
  • the fourth switching device When the first clock signal is in the second state, the fourth switching device is turned on.
  • control circuit further includes a fifth switching device, and a control end of the fifth switching device is connected to the first clock a signal connection, the substrate is connected to the second voltage through the fifth switching device;
  • the fifth switching device When the first clock signal is in the first state, the fifth switching device is turned off;
  • the fifth switching device is turned on.
  • the circuit between the first output end and the third voltage is turned on ; If the first device is turned off, the circuit between the first output terminal and the second voltage is turned on.
  • the on-off state of the first device affects the voltage signal connected to the first output terminal, so that the first output terminal outputs a third signal related to the first signal.
  • the control circuit includes a sixth switching device, a seventh switching device, an eighth switching device, a ninth switching device, and a storage device.
  • energy device wherein the drain is connected to the third voltage through the sixth switch device, the first output terminal is connected to the third voltage through the energy storage device, and the seventh switch
  • the device is connected to the third voltage, and is connected to the second voltage through the eighth switching device and the ninth switching device, and the control terminal of the seventh switching device and the control terminal of the eighth switching device pass through
  • the sixth switching device is connected to the third voltage, the control terminal of the sixth switching device and the control terminal of the ninth switching device are connected to the first clock signal, and the second voltage corresponds to a high level, the third voltage corresponds to a low level;
  • the ninth switching device When the first clock signal is in the first state, the ninth switching device is turned off, the sixth switching device is turned on, so that the seventh switching device is turned off, and the eighth switching device is turned on, the first output terminal outputs the second signal;
  • the ninth switching device When the first clock signal is in the second state, the ninth switching device is turned on, and the sixth switching device is turned off;
  • the seventh switching device is turned on, and the eighth switching device is turned off, so that the voltage of the first output terminal is the third voltage and the energy storage device is discharged ;
  • the seventh switching device is turned off, and the eighth switching device is turned on, so that the voltage of the first output terminal is the second voltage and the energy storage device Charge.
  • the charging or discharging of the first output terminal can be controlled to complete the reading or transmission of data.
  • a tenth switch device is further included between the drain and the sixth switch device, and the tenth switch device The control terminal of the device is connected to the first clock signal, and the tenth switch device is turned off when the first clock signal is in a first state, and turned on when the first clock signal is in a second state.
  • the tenth switching device when the first clock signal is in the first state, the tenth switching device is turned off, so that the drain of the first device can be separated from the third voltage, which helps to avoid the drain of the first device. affected by the third voltage.
  • the tenth switching device When the first clock signal is in the second state, the tenth switching device is turned on, which does not affect the transmission of the data signal.
  • the control circuit includes a sixth switching device, a seventh switching device, an eighth switching device, a ninth switching device, a Ten switching devices and energy storage devices, the drain is connected to the third voltage through the sixth switching device and the tenth switching device, the first output terminal is connected to the second voltage through the energy storage device, The seventh switching device is connected to the third voltage, and the eighth switching device and the ninth switching device are connected to the second voltage.
  • the control terminal of the seventh switching device and the The control terminal of the eighth switching device is connected to the third voltage through the sixth switching device, the control terminal of the sixth switching device is connected to the third voltage, and the control terminal of the ninth switching device is connected to the third voltage.
  • the first clock signal is connected, the second voltage corresponds to a low level, and the third voltage corresponds to a high level;
  • the ninth switching device When the first clock signal is in the first state, the ninth switching device is turned off, the sixth switching device is turned on, so that the seventh switching device is turned off, and the eighth switching device is turned on, the first output terminal outputs the second signal;
  • the ninth switching device When the first clock signal is in the second state, the ninth switching device is turned on;
  • the seventh switching device is turned on, and the eighth switching device is turned off, so that the voltage of the first output terminal is the third voltage and the energy storage device Charge;
  • the seventh switching device is turned off, and the eighth switching device is turned on, so that the voltage of the first output terminal is the second voltage and the energy storage device is discharged .
  • the charging or discharging of the first output terminal can be controlled to complete the reading or transmission of data.
  • the energy storage device is a capacitor.
  • control circuit further includes an eleventh switch device; the control end of the seventh switch device passes through the tenth switch device.
  • a switch device is connected to the third voltage; when the digital circuit is powered on, the first clock signal is in the second state, and the eleventh switch device is turned on.
  • the first clock signal is in the second state when the flip-flop is powered on, which can prevent the data information stored in the first device from being rewritten when the flip-flop is powered off.
  • the eleventh switch device is turned on, so that the data information stored in the first device when the power is turned off can be read out.
  • the control circuit further includes a clock signal generating circuit for generating the first clock signal; the clock signal generating The circuit specifically includes a second output terminal, a thirteenth switching device and a fourteenth switching device, the second output terminal is used to output the first clock signal, and the control terminal of the thirteenth switching device is connected to the third signal , the first terminal of the thirteenth switching device is grounded, the control terminal of the fourteenth switching device is connected to the fourth signal, the first terminal of the fourteenth switching device is connected to the second clock signal, and the tenth switching device is connected to the second clock signal.
  • the second terminal of the three switching device and the second terminal of the fourteenth switching device are connected to the second output terminal, and the thirteenth switching device is turned on when the third signal is in the first state, and is turned on when the third signal is in the first state.
  • the third signal is turned off when the second state is in the second state, the fourteenth switching device is turned on when the fourth signal is in the second state, and is turned off when the fourth signal is in the first state;
  • the third signal is in the first state in the first time period, the fourth signal is in the first state in the second time period, and the start times of the first time period and the second time period are all When the digital circuit is powered on, the duration of the first time period is less than or equal to the duration of the second time period.
  • control circuit further includes a level recovery circuit; the level recovery circuit is configured to be used when the first signal is In the case of the high level, before the next time the first clock signal changes from the first state to the second state, the first output terminal is controlled to maintain the high level.
  • the level recovery circuit includes a twelfth switching device and a second inverter; the first output terminal passes through The twelfth switching device is connected to the second voltage, and the second voltage corresponds to a high level; or, the first output terminal is connected to the third voltage through the twelfth switching device, The third voltage corresponds to a high level; the first output terminal is connected to the control terminal of the twelfth switching device through the second inverter.
  • the first state of the first clock signal is a high level, and the second state of the first clock signal is low level; or, the first state of the first clock signal is a low level, and the second state of the first clock signal is a high level.
  • the first device is a ferroelectric field effect transistor.
  • ferroelectric field effect transistor For a ferroelectric field effect transistor, changing the voltage applied to its ferroelectric layer can change its polarity, thereby changing its threshold voltage. And the on-off state of the ferroelectric field effect transistor is affected by its threshold voltage. Therefore, the ferroelectric field effect transistor can be used as a nonvolatile device to realize the digital circuit of the present application.
  • the digital circuit is a D flip-flop.
  • the present application provides an electronic device, including the digital circuit described in the first aspect or any possible implementation manner thereof.
  • FIG. 1 is a schematic structural diagram of a MOS transistor.
  • FIG. 2 is a schematic structural diagram of a ferroelectric field effect transistor.
  • FIG. 3 is a schematic diagram of the working principle of a ferroelectric field effect transistor.
  • FIG. 4 is a schematic structural diagram of an improved ferroelectric field effect transistor.
  • FIG. 5 is a schematic diagram of the working principle of the improved ferroelectric field effect transistor.
  • FIG. 6 is a schematic structural diagram of a digital circuit provided by the present application.
  • FIG. 7 is a schematic structural diagram of the first device provided in the present application.
  • FIG. 8 is a schematic structural diagram of a flip-flop provided by the present application.
  • FIG. 9 is a schematic diagram of a possible usage manner of the trigger of the present application.
  • FIG. 10 is an example of a trigger provided by the present application.
  • FIG. 11 is another example of a trigger provided by the present application.
  • FIG. 12 is another example of a trigger provided by the present application.
  • FIG. 13 is another example of a trigger provided by the present application.
  • FIG. 14 is another example of a trigger provided by the present application.
  • Figure 15 is another example of a trigger provided by the present application.
  • FIG. 16 is a schematic diagram of a possible clock signal generation circuit of the present application.
  • Figure 17 is a timing control diagram of a flip-flop with a data recall function.
  • Figure 18 is another example of a trigger provided by the present application.
  • Figure 19 is another example of a trigger provided by the present application.
  • a metal-oxide-semiconductor field-effect transistor generally may include a gate (gate, G), a source (source, S), a drain (drain, D) and a substrate (bulk, B), The on-off state between the source and the drain can be changed by applying a control signal between the gate and the source.
  • the MOS tube can be regarded as a 3-terminal device or a 4-terminal device. When the MOS tube is used as a 3-terminal device, the source electrode and the substrate are connected together, and even the substrate may not be drawn out. When the MOS tube is used as a 4-terminal device, the substrate and source can be independently controlled.
  • FIG. 1 is a schematic structural diagram of a MOS transistor. As shown in Figure 1, MOS tubes can be divided into two types: P-channel MOS tubes and N-channel MOS tubes.
  • the P-channel MOS transistor has two P+ regions on the N-type silicon substrate, which are used as source and drain, respectively, and there is no conduction between the two electrodes.
  • the N-type silicon surface under the gate presents a P-type inversion layer, which becomes a channel connecting the source and drain.
  • Changing the gate voltage can change the voltage in the channel.
  • Hole density, thereby changing the resistance of the channel this MOS tube is called a P-channel enhancement type field effect transistor. If there is no gate voltage on the surface of the N-type silicon substrate, there is already a P-type inversion layer channel. With the appropriate bias, the resistance of the channel can be increased or decreased.
  • This MOS tube is called P-channel. Depletion Mode Field Effect Transistor.
  • the P-channel enhancement type field effect transistor and the P-channel depletion type field effect transistor may be collectively referred to as PMOS transistors (hereinafter referred to as PMOS transistors).
  • the N-channel MOS transistor and the P-channel MOS transistor are similar in structure, the difference is the doping type of the substrate and the source and drain, and the PMOS is the substrate of the N-type silicon.
  • a P-type doped region is formed by doping as a source and drain region, while NMOS is formed on a P-type silicon substrate by doping to form an N-type doped region as a source and drain region.
  • MOS transistor For a more detailed description of the MOS transistor, reference may be made to the prior art, which will not be repeated here.
  • the ferro-electric field effect transistor is a new type of non-volatile memory device.
  • One ferro-electric field effect transistor can realize 1-bit information storage, which may replace Flash memory in the future, or Used to implement non-volatile static random access memory (static random access memory, SRAM), etc.
  • FIG. 2 is a schematic structural diagram of a ferroelectric field effect transistor.
  • the ferroelectric field effect transistor is very similar to the MOS transistor, except that a ferroelectric (FE) layer is added between the gate and the dielectric layer (insulator), and its polarity can be changed by changing the voltage applied to the FE layer. , so as to change the threshold voltage (V T ) of the ferroelectric field effect transistor, and realize the functions of storing "0" and "1".
  • FE ferroelectric
  • V T threshold voltage
  • ferroelectric field effect transistors are also divided into two types: N-type FEFET and P-type FEFET, which can also be used as 3-terminal devices or 4-terminal devices.
  • FIG. 3 is a schematic diagram of the working principle of a ferroelectric field effect transistor.
  • Figure 3 takes N-type FEFET as an example.
  • the working principle of ferroelectric field effect transistor is as follows:
  • the source and/or drain drain is grounded, and the polarization direction of the ferroelectric layer is changed by controlling the voltage at the gate, or by controlling the gate and The voltage difference between the source and/or the voltage difference between the gate and the drain changes the polarization direction of the ferroelectric layer.
  • the source and/or drain drain to ground and controlling the voltage of the gate to change the polarization direction of the ferroelectric layer as an example, if the voltage of the gate is positive, a negative voltage is induced on the surface of the channel, and V T decreases. If the gate voltage is negative, a positive voltage will be induced on the surface of the channel, V T will increase, and it will show high impedance during readout.
  • V T For use as a 4-terminal device, in addition to changing V T by changing the voltage between gate and source and/or between gate and drain, it is also possible to change the voltage between gate and substrate by changing the voltage to change the polarization direction of the ferroelectric layer. If the voltage between the gate and the substrate V GB > 0, a negative voltage is induced on the surface of the channel, and V T decreases; if V GB ⁇ 0, a positive charge is induced on the surface of the channel, and V T increases.
  • V T change is just the opposite.
  • FIG. 4 is a schematic structural diagram of an improved ferroelectric field effect transistor. Since the ferroelectric field effect transistor shown in FIG. 3 can be erased and written to a relatively limited number of times, it is in the order of 10 ⁇ 5. In order to improve the rewritable times of the ferroelectric field effect transistor, some people propose to superimpose a ferroelectric capacitor on the top of the MOS transistor, so that the rewritable times of the ferroelectric field effect transistor can be increased to the order of 10 ⁇ 12-14. A schematic structural diagram of the improved ferroelectric field effect transistor can be shown in FIG. 4 .
  • FIG. 5 is a schematic diagram of the working principle of the improved ferroelectric field effect transistor.
  • Figure 4 takes the P-type FEFET as an example.
  • the threshold voltage V T of the ferroelectric field effect transistor is controlled by controlling the potential between the gate and the substrate.
  • the working principle of the ferroelectric field effect transistor is as follows:
  • the source or drain can be open, or the substrate and the source/drain can be zero-biased or forward-biased to ensure the PN junction is reverse-biased.
  • the substrate is connected to 0 potential and the gate is connected to a high potential, negative charges are induced on the surface of the channel, and the V T of the ferroelectric field effect transistor increases; when the substrate is connected to a high potential and the gate is connected to 0 potential, the surface of the channel is induced The positive charge is discharged, and the V T of the ferroelectric field effect transistor decreases.
  • each pole and the threshold state during the operation of the P-type FEFET may be as shown in Table 1, where V H is a high level or a positive level, and V DD is a power supply voltage.
  • the low threshold voltage and the high threshold voltage can refer to the two threshold states of the FEFET after being polarized and biased.
  • the specific values of the high threshold voltage and the low threshold voltage are based on the fact that the two states can be effectively differentiated .
  • D flip-flop is an information storage device with memory function and two stable states. It is the most basic logic unit that constitutes various sequential circuits, and it is also an important device in digital integrated circuits. Generally, the master-slave structure is adopted, and the digital information can be transmitted to the output terminal after one beat and remain stable until the next data writing.
  • the present application provides a digital circuit capable of realizing non-volatile storage of digital information.
  • FIG. 6 is a schematic structural diagram of a digital circuit provided by the present application.
  • the digital circuit 500 includes: a control circuit 510 and a first device 520, the control circuit 510 includes an input end 5101, a first output end 5102 and a clock control end 5103, the clock control end 5103 and the first The clock signal 530 is connected.
  • the control circuit 510 is configured to control the threshold voltage of the first device 520 according to the first signal received by the input terminal 5101 when the first clock signal 530 is in the first state, and the first Different states of a signal correspond to different threshold voltages of the first device 520 ; when the first clock signal 530 changes from the first state to the second state, the threshold voltage of the first device 520 is controlled to control the The on-off state of the first device 520, and according to the on-off state of the first device 520, a third signal is output, and the third signal is a signal related to the first signal.
  • the third signal is a signal with the same state as the first signal, or the third signal is a signal with an opposite state to the first signal.
  • control circuit 510 is further configured to output a second signal through the first output terminal 5102 when the first clock signal 530 is in the first state, and the second signal is the last signal
  • the first clock signal is a signal output from the first output terminal 5102 after the first clock signal changes from the first state to the second state.
  • the first state of the first signal corresponds to the first state of the threshold voltage of the first device 520
  • the first state of the threshold voltage corresponds to the first state of the third signal
  • the second state of the first signal corresponds to For the second state of the threshold voltage of the first device 520
  • the second state of the threshold voltage corresponds to the second state of the third signal.
  • the present application does not specifically limit the first and second states of the first signal, the first and second states of the threshold voltage of the first device 520, and the first and second states of the third signal.
  • the high level of the first signal corresponds to the high threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the high level of the third signal.
  • the high level of the first signal corresponds to the low threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the high level of the third signal.
  • the low level of the first signal corresponds to the high threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the low level of the third signal.
  • a low level of the first signal corresponds to a low threshold voltage of the threshold voltage
  • a high threshold voltage corresponds to a low level of the third signal.
  • the high level of the first signal corresponds to the high threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the low level of the third signal.
  • the high level of the first signal corresponds to the low threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to the low level of the third signal.
  • a low level of the first signal corresponds to a high threshold voltage of the threshold voltage
  • the high threshold voltage corresponds to a high level of the third signal.
  • a low level of the first signal corresponds to a low threshold voltage of the threshold voltage
  • a high threshold voltage corresponds to a high level of the third signal.
  • the first device is a device with a variable threshold voltage, or a programmable threshold voltage device.
  • the variable threshold voltage can also be equivalent, replaced or described as variable impedance state, etc., which is not limited in this application.
  • the first device may be a 2-terminal device.
  • the first device may include a gate electrode, a source electrode and a drain electrode, or may include a gate electrode, a source electrode, a drain electrode and a substrate, that is, the first device may be a 3-terminal device or a 4-terminal device,
  • the first device may include one or more FEFETs.
  • the specific device structure of the FEFET is not limited to the above-mentioned forms or structures, and may also be FEFETs of other structures or forms, as long as the threshold value can be changed by controlling the polarization direction. voltage will do.
  • FIG. 7 shows several structural forms of the first device. As shown in Fig.
  • the first device is a 3-terminal N-type FEFET; as shown in Fig. 7(b), the first device includes two 3-terminal N-type FEFETs, FEFET1 and FEFET2.
  • the FEFETs are connected in parallel, wherein two gates are connected, two drains are connected, and two drains are connected; as shown in (c) of FIG. 7 , the first device includes FEFET1-FEFETn, and n FEFETs are 3 Similarly, N FEFETs are connected in parallel, wherein n gates are connected, n drains are connected, and n drains are connected.
  • the plurality of FEFETs included in the first device may also be regarded as one FEFET, which is not limited in this application.
  • control circuit 510 is specifically configured to control the voltage between the gate and the source, the voltage between the gate and the drain, and the voltage between the gate and the substrate of the first device 520 At least one of the voltages of the first device 520 is used to control the threshold voltage of the first device 520, and this application does not limit the specific implementation.
  • the control circuit 510 controls the level of the gate of the first device 520 to be opposite to the level of the source, and/or the level of the gate is different from that of the drain The level is opposite, and/or the level of the gate is opposite to the level of the substrate, thereby enabling the threshold voltage of the first device 520 to be changed.
  • the control circuit 510 may include a third switching device, the control terminal of the third switching device is connected to the first clock signal 530, and the gate of the first device 520 passes through the first clock signal 530.
  • the three-switch device is connected to the first voltage, and the source of the first device 520 is connected to the second voltage.
  • the third switching device When the first clock signal 530 is in the first state, the third switching device is turned off; when the first clock signal 530 is in the second state, the third switching device is turned on, and the first switching device is turned on.
  • the voltage of the gate of the device 520 is the first voltage, and the voltage of the source is the second voltage.
  • the first device 520 is turned on; if the first voltage, the first device 520 If the two voltages and the threshold voltage of the first device 520 do not satisfy the turn-on condition, the first device 520 is turned off.
  • the first clock signal 530 is in the second state, a voltage is applied to the gate and source of the first device 520, and its current threshold voltage will affect its on-off state, that is, according to the current state of the first device 520 can be realized.
  • the threshold voltage changes its on-off state.
  • the circuit between the first output terminal 5102 and the third voltage is turned on; if the first device 520 is turned off, the first The circuit between the output terminal 5102 and the second voltage is turned on.
  • the voltage signal connected to the first output terminal 5102 is affected by the on-off state of the first device, so that the first output terminal 5102 outputs a third signal related to the first signal.
  • the source of the first device may be an electrode corresponding to one end that provides carriers
  • the drain may be an electrode corresponding to one end that collects carriers
  • the gate may be an electrode that controls the on-off of the first device.
  • the substrate may refer to electrodes drawn from the substrate material.
  • the gate electrode, source electrode, drain electrode and substrate here are only a common description method. In fact, different devices may have different names, and the names of the above-mentioned electrodes do not limit the application.
  • the above-mentioned threshold voltage may be the input voltage corresponding to the midpoint of the transition region where the output current changes sharply with the input voltage in the transfer characteristic curve is called the threshold voltage, which has different parameters when describing different devices.
  • the threshold voltage is usually defined as the voltage between the gate and the source when the electron concentration at the interface is equal to the multi-sub concentration (hole concentration) of the P-type substrate.
  • the threshold voltage is usually defined as the voltage between the gate and the source when the hole concentration at the interface is equal to the multi-sub concentration (electron concentration) of the N-type substrate.
  • the on-off state of the first device may be the on-off state between the source electrode and the drain electrode of the first device.
  • control circuit will be divided into a plurality of sub-circuits such as a writing circuit, a reading circuit, and an output circuit, and each sub-circuit will be described in detail separately. It should be noted that the division of the control circuit below is only for the convenience of description, and does not constitute a limitation on the technical solutions of the present application. For example, the control circuit may not be divided, or other division methods may be adopted.
  • FIG. 8 is a schematic structural diagram of a flip-flop provided by the present application.
  • the flip-flop 600 includes: a writing circuit 610 , a reading circuit 620 , an output circuit 630 and a non-volatile device 640 .
  • the writing circuit 610 includes a signal input terminal 6101 for receiving signals
  • the output circuit 630 includes a signal output terminal 6301 for outputting signals.
  • the writing circuit 610 , the reading circuit 620 and the output circuit 630 are connected to the first clock signal 650 , in other words, the writing circuit 610 , the reading circuit 620 and the output circuit 630 are controlled by the first clock signal 650 .
  • the writing circuit 610 is configured to control the threshold voltage of the non-volatile device 640 according to the first signal received by the signal input terminal 6101 .
  • the output circuit 630 is used for outputting the second signal.
  • the second signal is the signal output by the output circuit 630 after the first clock signal 650 changes from the first state to the second state last time.
  • the readout circuit 630 is used to control the on-off state of the non-volatile device 640 according to the threshold voltage of the non-volatile device 640 .
  • the output circuit 630 is configured to output the first signal according to the on-off state of the non-volatile device 640 .
  • the first clock signal 650 changes from the first state to the second state, which may refer to the change of the first clock signal 650 from the first state to the second state, that is, the first clock signal is the second state, or it may refer to
  • the process in which the first clock signal 650 changes from the first state to the second state is not specifically limited in this application. That is to say, the flip-flop of the present application may be an edge-triggered flip-flop, or a level-triggered flip-flop.
  • the first state of the first clock signal is a high level
  • the second state of the first clock signal is a low level
  • the first state of the first clock signal is a low level
  • the first state of the first clock signal is a low level
  • the second state is a high level, which is not specifically limited in this application.
  • the flip-flop 600 can control the threshold voltage of the non-volatile device 640 according to the value of the data signal received by the signal input terminal 6101 when the first clock signal 650 is in the first state. It can be understood that the flip-flop writes the data signal to Into the non-volatile device 640, different threshold voltages represent different values.
  • the first clock signal 650 changes from the first state to the second state or after the first clock signal 650 changes from the first state to the second state
  • the current threshold voltage of the non-volatile device 640 will affect the non-volatile device The on-off state of 640, and the different states of the non-volatile device 640 can cause the output circuit 630 to output different signals.
  • the flip-flop 600 can transmit the data signal of the signal input terminal 6101 to the signal output terminal 6301, and keep it until the next data writing is completed, and since the flip-flop 600 stores the data signal to the non-volatile In the volatile device 640, the flip-flop 600 has the characteristic of data non-volatile, and the data before power-off can be recalled. Therefore, the flip-flop 600 can realize the non-volatile storage of the data signal while realizing the function of the D flip-flop.
  • non-volatile device 640 as an FEFET as an example.
  • the writing circuit 610 includes a first switching device and an inverting circuit
  • the signal input terminal 6101 is connected to the gate of the FEFET through the first switching device
  • the signal input terminal 6101 is connected through the first switching device and the inverting circuit.
  • the control terminal of the first switching device is connected to the first clock signal
  • the inverting circuit is used for inverting the first signal.
  • the first clock signal is in the first state
  • the first switching device is turned on, and the first signal is input to the gate of the FEFET and to the source, drain and substrate of the FEFET after inversion processing by the inverter circuit.
  • the writing circuit 610 includes a first switching device and an inverting circuit; the signal input terminal 6101 is connected to the gate of the FEFET through the first switching device and the inverting circuit, while the signal input terminal 6101 is connected to the gate of the FEFET through the first switching device and the inverting circuit.
  • the device is connected to at least one of the source electrode, the drain electrode and the substrate of the FEFET, the control terminal of the first switching device is connected to the first clock signal, and the inverting circuit is used for inverting the first signal.
  • the first switching device When the first clock signal is in the first state, the first switching device is turned on, and the first signal is input to at least one of the source, drain and substrate of the FEFET, and is input to the FEFET after reverse processing by the inverter circuit.
  • the gate is used to control the threshold voltage of the FEFET; when the first clock signal is in the second state, the first switching device is turned off.
  • the above-mentioned inverter circuit includes at least one first inverter.
  • the above-mentioned inverter circuit includes at least one first inverter and at least one second switching device, wherein the at least one first inverter corresponds to the at least one second switching device one-to-one, and the second switching device has a one-to-one correspondence.
  • the control terminal is connected to the first clock signal, and the second switch device is turned on when the first clock signal is in the first state, and turned off when the first clock signal is in the second state.
  • the readout circuit 620 includes a third switching device, the control terminal of the third switching device is connected to the first clock signal, the gate of the FEFET is connected to the first voltage through the third switching device, and the source of the FEFET is connected to the first clock signal.
  • the second voltage connection is connected.
  • the third switching device When the first clock signal is in the first state, the third switching device is turned off; when the first clock signal is in the second state, the third switching device is turned on, the voltage of the gate of the FEFET is the first voltage, and the source of the FEFET The voltage of the pole is the second voltage; if the current threshold voltage of the FEFET is a low voltage, the FEFET is turned on; if the current threshold voltage of the FEFET is a high voltage, the FEFET is turned off.
  • the readout circuit 620 may further include a fourth switching device, the control terminal of the fourth switching device is connected to the first clock signal, and the source of the FEFET is connected to the second voltage through the fourth switching device.
  • the fourth switching device When the first clock signal is in the first state, the fourth switching device is turned off; when the first clock signal is in the second state, the fourth switching device is turned on.
  • the readout circuit 620 may further include a fifth switching device, the control terminal of the fifth switching device is connected to the first clock signal, and the substrate of the FEFET is connected to the second voltage through the fifth switching device.
  • the fifth switching device When the first clock signal is in the first state, the fifth switching device is turned off; when the first clock signal is in the second state, the fifth switching device is turned on.
  • the above-mentioned first voltage is a voltage that can turn on the third switching device when the first clock signal is in the second state, and a voltage that can distinguish between high and low impedance states of the FEFET in cooperation with the second voltage.
  • the first voltage and the second voltage may both be the first power supply voltage, for example, the first voltage and the second voltage may both be V DD .
  • the first voltage and the second voltage may both be the second power supply voltage.
  • the first voltage and the second voltage may both be V SS or a ground voltage (Ground, GND).
  • the first voltage is VR and the second voltage is the second power supply voltage.
  • the output circuit 630 may include a sixth switching device, a seventh switching device, an eighth switching device, a ninth switching device, and an energy storage device.
  • the drain of the FEFET is connected to the third voltage through the sixth switching device
  • the signal output terminal 6301 is connected to the third voltage through the energy storage device
  • the seventh switching device is connected to the third voltage
  • the eighth switching device and the third voltage are connected through the seventh switching device.
  • the nine switching device is connected to the second voltage
  • the control terminal of the seventh switching device and the control terminal of the eighth switching device are connected to the third voltage through the sixth switching device, the control terminal of the sixth switching device and the control terminal of the ninth switching device connected to the first clock signal.
  • the ninth switching device When the first clock signal is in the first state, the ninth switching device is turned off, the sixth switching device is turned on, so that the seventh switching device is turned off, the eighth switching device is turned on, and the signal output terminal 6301 outputs the second signal; when When the first clock signal is in the second state, the ninth switching device is turned on, and the sixth switching device is turned off. If the FEFET is turned on, the seventh switching device is turned on, and the eighth switching device is turned off, so that the voltage of the signal output terminal 6301 is the third voltage and the energy storage device is discharged; if the FEFET is turned off, the seventh switching device is turned off , the eighth switching device is turned on, so that the voltage of the signal output terminal 6301 is the second voltage, and the energy storage device is charged.
  • a tenth switching device may be further included between the drain of the FEFET and the sixth switching device.
  • the control terminal of the tenth switch device is connected to the first clock signal, and the tenth switch device is turned off when the first clock signal is in the first state and turned on when the first clock signal is in the second state.
  • the second voltage corresponds to a high level
  • the third voltage corresponds to a low level
  • the second voltage is V DD and the third voltage is GND or V SS .
  • the second voltage is GND
  • the third voltage is V SS .
  • the output circuit 630 may include a sixth switching device, a seventh switching device, an eighth switching device, a ninth switching device, a tenth switching device, and an energy storage device.
  • the drain is connected to the third voltage through the sixth switching device and the tenth switching device
  • the signal output terminal 6301 is connected to the second voltage through the energy storage device
  • the seventh switching device is connected to the third voltage
  • the eighth switching device and The ninth switching device is connected to the second voltage
  • the control terminal of the seventh switching device and the control terminal of the eighth switching device are connected to the third voltage through the sixth switching device
  • the control terminal of the sixth switching device is connected to the third voltage
  • the sixth switching device is connected to the third voltage.
  • the control terminal of the nine-switch device is connected to the first clock signal.
  • the ninth switching device When the first clock signal is in the first state, the ninth switching device is turned off, the sixth switching device is turned on, so that the seventh switching device is turned off, the eighth switching device is turned on, and the signal output terminal 6301 outputs the second signal;
  • the ninth switching device is turned on; if the FEFET is turned on, the seventh switching device is turned on, and the eighth switching device is turned off, so that the voltage of the signal output terminal 6301 is the third voltage, and The energy storage device is discharged; if the FEFET is turned off, the seventh switching device is turned off, and the eighth switching device is turned on, so that the voltage of the signal output terminal 6301 is the second voltage, and the energy storage device is charged.
  • the second voltage corresponds to a low level
  • the third voltage corresponds to a high level
  • the second voltage is V SS and the third voltage is V DD or GND.
  • the second voltage is GND
  • the third voltage is V DD .
  • the above-mentioned energy storage device may be a capacitor.
  • the flip-flops of the above-mentioned embodiments use the non-volatile device FEFET to store data information
  • the data can be stored after power-off.
  • the first clock signal is at a high level and then at a low level when the flip-flop is powered on again
  • the data information stored in the FEFET during power-off may be rewritten. In this way, some data information cannot be recalled.
  • the flip-flop may further include an eleventh switch device for data recall, and use a clock signal whose level state is the second state when the flip-flop is powered on again. Triggers with data recall function will be described below with specific examples.
  • the flip-flop may further include a level recovery circuit.
  • the level recovery circuit is used to control the signal output terminal 6301 to maintain a high level before the next time the first clock signal changes from the first state to the second state when the first signal is at a high level.
  • each switching device for example, a MOS transistor, a bipolar junction transistor (BJT) or other types of switching devices can be used to implement.
  • the present application also does not specifically limit the N-type or P-type of each switching device.
  • MOS tube Take MOS tube as an example.
  • the first switching device, the second switching device, the sixth switching device, etc. may be NMOS transistors, and the third switching device may be an NMOS transistor.
  • the fourth switching device, the fifth switching device, and the ninth switching device, etc. can be PMOS transistors.
  • the first switching device, the second switching device, the sixth switching device, etc. may be PMOS transistors, and the third switch The device, the fourth switching device, the fifth switching device, the ninth switching device, etc. may be NMOS transistors.
  • the flip-flop of the present application can also be controlled by multiple clock signals, which is not limited.
  • the first switching device, the second switching device, the sixth switching device, etc. use one clock signal
  • the third switching device, the fourth switching device, the fifth switching device, the ninth switching device, etc. use one clock signal.
  • the flip-flops provided in this application can be applied to any scenario or product that requires D flip-flops or non-volatile D flip-flops.
  • the flip-flops provided in this application can be applied to chips, central processing units (CPUs) ), processors, mobile phones, computers, routers, switches, Internet of things (IoT) products, etc.
  • CPUs central processing units
  • processors mobile phones
  • computers routers
  • switches Internet of things
  • IoT Internet of things
  • multiple flip-flops can realize parallel-to-serial conversion of digital signals in the form of series or parallel, or flip-flops cooperate with combinatorial logic (CL) to achieve required logic and operation functions.
  • CL combinatorial logic
  • FIG. 9 shows a possible use of the trigger of the present application.
  • FIG. 9 is an example of a circuit symbol of the flip-flop of the present application, which includes a signal input terminal (IN), a signal output terminal (OUT), and a clock control terminal (CLK).
  • (b) of FIG. 9 is a usage mode of the flip-flop of the present application, that is, a plurality of flip-flops can be connected in series to realize serial-to-parallel conversion of signals.
  • (c) of FIG. 9 is another way of using the flip-flop of the present application, that is, the flip-flop cooperates with the CL to realize the required logic and operation functions.
  • FIG. 10 is an example of a trigger provided by the present application.
  • the flip-flop includes a P-type FEFET, a writing circuit, a reading circuit, and an output circuit.
  • the FEFET is used as a 4-terminal device.
  • the relevant description of FIG. 5 above which will not be repeated here.
  • the writing circuit includes a signal input terminal, NMOS transistors T1-T2, and an inverter 1 .
  • the signal input terminal is connected to the gate of the FEFET through T1 and to the substrate of the FEFET through T1, inverter 1 and T2.
  • the control terminals of T1 and T2 are connected to the clock signal.
  • the readout circuit includes PMOS transistors T3-T5, and the control terminals of T3-T5 are connected to the clock signal.
  • the gate of the FEFET is connected to V DD through T3, the source is connected to V DD through T4, and the substrate is connected to V DD through T5.
  • the output circuit includes NMOS transistors T6-T7, PMOS transistors T8-T9, and a capacitor C S .
  • the drain of FEFET , the control terminal of T7, and the control terminal of T8 are grounded through T6 respectively, the signal output terminal is grounded through T7 and CS respectively, and the signal output terminal is connected to V DD through T8 and T9, and the control terminals of T6 and T9 are connected to the ground respectively. Connect the clock signal.
  • T1, T2 and T6 are turned on, and T3, T4, T5 and T9 are turned off, the voltage at point A is pulled down, T7 is turned off, and C S saves the original data, that is, the signal output terminal Keep outputting the data written during the last data writing process.
  • the flip-flop transmits the data signal D at the signal input end to the signal output end, and keeps it until the next data writing is completed.
  • T1 and T2 can also be replaced with transmission gates, so as to pass the data signal to the gate and substrate of the FEFET losslessly.
  • the flip-flop shown in Figure 10 controls the voltage between the gate and the substrate of the FEFET according to the value of the data signal D, thereby changing the threshold voltage of the FEFET, so that the FEFET is in the data transfer (or read)
  • the impedance state of the FEFET will affect the on-off state of the FEFET, thereby affecting the charging and discharging of the signal output terminal, and the control signal output terminal outputs the value of the data signal D.
  • the D flip-flop can be made to have the data non-volatile characteristic, and the data before power down can be recalled. Therefore, the flip-flop shown in FIG. 10 can realize the non-volatile storage of the D flip-flop while realizing the function of the D flip-flop.
  • FIG. 11 is another example of a trigger provided by the present application. Similar to the flip-flop in FIG. 10 , the difference is that a PMOS transistor T10 is added to the flip-flop in FIG. 11 .
  • the flip-flop shown in FIG. 11 adds a PMOS transistor T10 between the drain of the FEFET and T6.
  • T10 is turned off, so that the drain of the FEFET can be separated from GND, so as to prevent the drain of the FEFET from being pulled down to 0 potential during the data writing phase.
  • T10 is turned on and does not affect the transfer of data signals.
  • both the source and drain of the FEFET are floating, and there is only a bias voltage between the gate and the substrate. According to its bias voltage, the FEFET's The threshold voltage will change accordingly.
  • the threshold voltage of the FEFET can be changed by controlling the voltage between the gate and the substrate of the FEFET as an example.
  • the voltage between at least one of the drains changes the threshold voltage of the FEFET, and the operation principle of the flip-flop is similar to that of the flip-flop shown in FIG. 10 , and details are not repeated here.
  • FIG. 12 is another example of a trigger provided by the present application.
  • the flip-flop includes a P-type FEFET, a writing circuit, a reading circuit, and an output circuit.
  • the FEFET is used as a three-terminal device.
  • the writing circuit includes a signal input terminal, NMOS transistors T1-T2, and an inverter 1 .
  • the signal input is connected to the gate of the FEFET through T1 and to the source of the FEFET through T1, inverter 1 and T2.
  • the control terminals of T1 and T2 are connected to the clock signal.
  • the readout circuit includes PMOS transistors T3-T4, and the control terminals of T3-T4 are connected to a clock signal.
  • the gate of the FEFET is connected to V DD through T3 and the source is connected to V DD through T4.
  • the output circuit includes NMOS transistors T6-T7, PMOS transistors T8-T9, and a capacitor C S .
  • the control terminal of T7 and the control terminal of T8 are grounded through T6 respectively, the signal output terminal is grounded through T7 and CS respectively, and the signal output terminal is connected to V DD through T8 and T9, and the control terminals of T6 and T9 are connected to the clock signal.
  • T10 is placed between T6 and the drain of the FEFET to isolate the drain of the FEFET from GND during the data writing phase. It should be noted that T10 is an optional device, and the drain of the FEFET can also be grounded only through T6.
  • the voltage of the gate of the FEFET is 1, the voltage of the source is 0, the threshold voltage VT of the FEFET is high, and it shows a high impedance in the data transfer (or readout) stage, and the FEFET is erased.
  • the flip-flop transmits the data signal D at the signal input end to the signal output end, and keeps it until the next data writing is completed.
  • T1 and T2 can also be replaced with transmission gates to pass the data signal to the gate and source of the FEFET losslessly.
  • the flip-flop shown in Figure 12 controls the voltage between the gate and the source of the FEFET according to the value of the data signal D in the data writing phase, thereby changing the threshold voltage of the FEFET, so that the FEFET is in the data transfer (or read) In the data transmission (or readout) stage, the impedance state of the FEFET will affect the on-off state of the FEFET, thereby affecting the charging and discharging of the signal output terminal, and the control signal output terminal outputs the value of the data signal D. And since the data signal is stored in the non-volatile device FEFET in Example 3, the D flip-flop can be made to have the data non-volatile characteristic, and the data before power down can be recalled. Therefore, the flip-flop shown in FIG. 12 can realize the non-volatile storage of the D flip-flop while realizing the function of the D flip-flop.
  • the threshold voltage of the FEFET is only changed by controlling the voltage between the gate and the drain of the FEFET as an example. In fact, the voltage between the gate and the drain of the FEFET can also be changed. Threshold voltage (as shown in Figure 13, the gate and drain of the FEFET are connected to the NMOS transistor T15 through the inverter 2, and the control terminal of T15 is connected to the clock signal), or it can be simultaneously controlled by the gate and the drain of the FEFET.
  • the voltage between the source and the voltage between the gate and drain of the FEFET changes the threshold voltage of the FEFET (as shown in Figure 14, the gate and source of the FEFET are connected through inverters 1 and T2 , the gate and drain of the FEFET are connected through the inverter 2 and T15, and the control terminals of T2 and T15 are connected with the clock signal).
  • the working principle of the trigger is similar and will not be repeated here.
  • the threshold voltage of the FEFET is changed by controlling the voltage between the gate and the source of the FEFET and the voltage between the gate and the drain of the FEFET at the same time, in addition to the Inverter 1 and T2 connect T1 and the source, and connect T1 and the drain through inverter 2 and T15. It is also possible to connect T1 and the source of the FEFET through inverter 1 and T2, or through the inverter.
  • the source and drain of FEFET are connected through an NMOS transistor, which is turned on in the data writing stage and turned off in the data transfer (or read) stage. break.
  • Figure 15 is another example of a trigger provided by the present application.
  • the flip-flop shown in FIG. 15 is similar to the flip-flop shown in FIG. 10 , the difference is that the flip-flop shown in FIG. 15 adds a data recall function.
  • the flip-flop shown in Example 4 adds an NMOS transistor T11 for recalling data.
  • T11 is set between the control terminal of T7 and GND, and the control terminal of T11 is connected to the recall signal (recall, RC), and the clock signal (CLK1 in FIG. 15 ) is the clock signal generated by the clock signal generating circuit shown in FIG. 16 .
  • T11 can be a small size tube.
  • FIG. 16 is a schematic diagram of a possible clock signal generation circuit of the present application.
  • the clock signal generation circuit includes an NMOS transistor T13 and a transmission gate T14, wherein the control end of T13 is connected to the recall signal, and the control end of T14 is connected to BL (block) and T13 is turned on when the recall signal is high, and turned off when the recall signal is low.
  • T14 is turned on when BL is high, and turned off when BL is low.
  • the present application does not specifically limit the form of the clock signal generating circuit, as long as the first clock signal can be made to be at a low level when the data is recalled.
  • Figure 17 is a timing control diagram of a flip-flop with a data recall function.
  • the recall signal RC is at a low level and BL is at a high level, so that the path where T13 is located is disconnected, the path where T14 is located is connected, and the clock signal generation circuit outputs the clock signal CLK2;
  • the clock signal generation circuit has no signal output; during power-on (or data recall phase), RC is high level, BL is low level, so the path where T13 is connected is connected, and the path where T14 is located is connected is disconnected, the clock signal generation circuit outputs a low level. In this way, it can be ensured that the clock signal is at a low level when the power is turned on, and the data information stored in the FEFET can be prevented from being rewritten when the power is turned off.
  • T1 When powered on, RC is high and CLK1 is low, then T1, T2 and T6 are turned off, and T3-T5, T9, and T11 are turned on.
  • Point A is still charged to a high level, so that T7 is turned on, T8 is turned off, Cs is discharged to GND, and the voltage of the signal output terminal is low level, that is, the data transmitted to the signal output terminal is the stored data 0.
  • a pulse signal RC can read out the data signal stored in the FEFET.
  • the clock signal generation circuit shown in FIG. 16 does not need to be equipped with one flip-flop, but only needs to be equipped with one for a group of flip-flops that need to be controlled at the same time, that is, the clock signal generation circuit can be A plurality of flip-flops are shared, so that adding the clock signal generating circuit shown in FIG. 16 will not introduce excessive power consumption to the flip-flop unit.
  • the power consumption of the flip-flop shown in FIG. 15 can still be considered to be 19 gates.
  • the trigger shown in Figure 15 can be applied to the collective power-down scenario.
  • the trigger shown in Figure 15 can be used to power off temporarily unused threads or registers in the core. , and then collectively call for the next use, which helps to save power consumption.
  • the flip-flop shown in FIG. 15 can be used for data backup of logic circuits, SRAM circuits, flip-flops and other units.
  • FIG. 15 only takes the addition of the data recall function on the basis of the trigger shown in FIG. 10 as an example.
  • the data recall function can be applied to any trigger provided by this application. This is not limited.
  • the flip-flop of the present application does not have a T11 tube and a clock generation circuit.
  • the recall of the data signal stored in the FEFET can also be achieved in the case of .
  • Figure 18 is another example of a trigger provided by the present application.
  • the flip-flop shown in Figure 18 is similar to the flip-flop shown in Figure 10, the difference is that the flip-flop shown in Figure 18 adds a level recovery function to maintain the high level of the signal output.
  • the level recovery circuit includes a PMOS transistor T12 and an inverter 3, wherein the signal output terminal is connected to V DD through T12, and is connected to V DD through the inverter. Phaser 3 is connected to the control terminal of T12.
  • the signal output terminal outputs a high level, but due to the leakage of CS charge (for example, CS is relatively small), the voltage of the signal output terminal is reduced, and the high level of the signal output terminal changes to a low level through the inverter 3, so that T12 is turned on to realize the charging of CS, so that the signal output terminal maintains a high level.
  • CS leakage of CS charge
  • the signal output terminal outputs a low level, it means that the FEFET is turned on to charge point A , and then T7 is turned on, and the conduction of T7 will discharge CS to a low level, so that T12 is turned off, and the level recovery circuit does not work.
  • FIG. 18 only takes the addition of the level recovery function on the basis of the flip-flop shown in FIG. 10 as an example.
  • the level recovery function can be applied to any flip-flop provided by this application. There is no restriction on this.
  • the circuit division in the above examples is for convenience of description. In fact, the embodiment of the present application does not limit the specific division form of the circuit.
  • T6 can also be divided in the write circuit.
  • T10 can also be divided into the write circuit.
  • the level recovery circuit may also be divided into an output circuit or the like.
  • Examples 1 to 5 are described by taking a P-type FEFET as an example.
  • the flip-flop of the present application can also be implemented by using an N-type FEFET.
  • Figure 19 is another example of a trigger provided by the present application.
  • the flip-flop includes an N-type FEFET, a writing circuit, a reading circuit, and an output circuit.
  • the FEFET is used as a three-terminal device.
  • the writing circuit includes a signal input terminal, NMOS transistors T1-T2, and an inverter 1 .
  • the signal input terminal is connected to the gate of the FEFET through T1 and to the drain of the FEFET through T1, inverter 1 and T2.
  • the control terminals of T1 and T2 are connected to the clock signal.
  • the readout circuit includes a PMOS transistor T3, and the control end of T3 is connected to a clock signal.
  • the gate of the FEFET is connected to VR through T3 and the source is connected to GND through T3.
  • T3 is a depletion transistor
  • VR can be equal to 0, that is, the gate of FEFET is connected to GND through T3;
  • T3 is an enhancement transistor, VR can turn on T3 and can distinguish Voltage for the high and low impedance states of the FEFET.
  • the output circuit includes an NMOS transistor T6, an NMOS transistor T8, a PMOS transistor T7, PMOS transistors T9-T10, and a capacitor C S .
  • the drain of the FEFET is connected to V DD through T10 and T6, the control terminal of T7 and the control terminal of T8 are connected to V DD through T6, respectively, and the signal output terminal is connected to GND through CS , to V DD through T7, and through T9.
  • T8 is connected to GND, the control terminal of T6 is connected to V DD , and the control terminal of T9 is connected to the clock signal.
  • T6 can be a small size tube.
  • T11 is used to recall data when the flip-flop is powered on, T11 is set between the control terminal of T7 and V DD , the control terminal of T11 is connected to the recall signal RC, and the clock signal (CLK1 in Figure 19) is shown in Figure 16
  • the clock signal generated by the clock signal generation circuit can be a small size tube. It should be noted that if the data recall function is not required, the trigger may not include T11, or T11 may not work.
  • T1 and T2 are turned on, T3, T9 and T10 are turned off, and T6 is continuously turned on, then point A is charged to a high level, so that T7 is turned off, T8 is turned on, and C S keeps the original Data, that is, the signal output terminal keeps outputting the data written in the last data writing process.
  • the flip-flop transmits the data signal D at the signal input end to the signal output end, and keeps it until the next data writing is completed.
  • T1 and T2 can also be replaced with transmission gates to pass the data signal to the gate and drain of the FEFET losslessly.
  • the flip-flop shown in Figure 19 only needs 11 MOS transistors and one FEFET to implement the D flip-flop function and data recall function. Therefore, the flip-flop shown in Figure 19 has lower power consumption and footprint.
  • FIG. 19 is only an example of using an N-type FEFET to implement the flip-flop of the present application, and in fact, there may be more implementations.
  • the threshold voltage of the FEFET can also be controlled by controlling the voltage between the gate and the source and/or the voltage between the gate and the substrate of the FEFET, and a level recovery circuit as shown in Figure 18 can also be provided,
  • a switching device T4 can also be set between the source of the FEFET and GND. T4 is turned off when CLK1 is at a high level and turned on when CLK1 is at a low level, and T11 for recalling data may not be set, and so on.
  • the present application also provides an electronic device comprising at least one of the possible triggers described above.
  • the electronic device can be a chip, a system on chip (SOC), an integrated circuit, a digital circuit, a sequential circuit, a CPU, a processor, a mobile phone, a computer, a router, a switch, an IoT product, a terminal, a network device, a computer, Air conditioners, refrigerators, printers, or fax machines, anything that requires D-flip-flops or non-volatile D-flip-flops.
  • SOC system on chip
  • a device when a device is “connected” to another device, it may be directly connected to another device, or an intermediate device may also exist between the two. "Connected” can also be replaced with “electrically connected”, “coupled”, etc., without limitation.

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Abstract

本申请提供了一种数字电路和电子装置，该数字电路包括控制电路和第一器件，控制电路与时钟信号连接。当时钟信号为第一状态时，控制电路根据其输入端接收的第一信号，控制第一器件的阈值电压。当时钟信号由第一状态变为第二状态，控制电路根据第一器件的阈值电压，控制第一器件的通断状态，并根据第一器件的通断状态，输出与第一信号相关的第三信号。由于本申请通过改变第一器件的阈值电压来"存储"数字信息，当数字电路掉电，"存储"在其中的数字信息并不会丢失，使得本申请的数字电路具备非易失特性。

Description

一种数字电路和电子装置
本申请要求于2021年03月12日提交中国专利局、申请号为202110271002.4、申请名称为“一种数字电路和电子装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路领域，并且更具体地，涉及一种数字电路和电子装置。
背景技术
数字信息存储器件是构成多种时序电路的最基本逻辑单元，也是数字集成电路中的重要器件。当前，数字信息存储器件(例如，D触发器)均采用金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor，MOSFET)实现，在掉电后其存储的数字信息会丢失。
目前，对于便携式设备，为了节省功耗，希望设备在不活动周期被置于断电或待机模式，不执行任何操作，但又希望下次唤醒设备时某些数据寄存器中的状态保持不变，快速恢复到原来状态。另外，对于多核、多线程处理器，希望在不访问某些核和线程时可以掉电以减少功耗，但有希望访问时又可立刻召回原状态。对于这类应用场景，都需要用到具有非易失性功能的数字信息存储器件，当前的数字信息存储器件不能满足这类场景的需求。
发明内容
本申请提供一种数字电路和电子装置，能够实现数字信息的非易失性存储。
第一方面，本申请提供了一种数字电路，该数字电路包括：
控制电路和第一器件，所述控制电路包括输入端、第一输出端和时钟控制端，所述时钟控制端与第一时钟信号连接，所述控制电路用于：
当所述第一时钟信号为第一状态时，根据所述输入端接收的第一信号，控制所述第一器件的阈值电压，所述第一信号的不同状态对应于所述第一器件的不同阈值电压；
当所述第一时钟信号由第一状态变为第二状态，根据所述第一器件的阈值电压，控制所述第一器件的通断状态，以及根据所述第一器件的通断状态，输出第三信号，所述第三信号为与所述第一信号相关的信号。
可选地，第三信号为与第一信号状态相同的信号。
本申请的数字电路在第一时钟信号为第一状态时可以根据输入端接收的数据信号的数值，控制第一器件的阈值电压。在第一时钟信号由第一状态变为第二状态时或第一时钟信号由第一状态变为第二状态后，第一器件当前的阈值电压会影响第一器件的通断状态，而第一器件的不同状态可以使得输出端输出不同的信号。这样，经过一个完整的时钟周期，本申请的数字电路可以将输入端的数据信号传递到了输出端，使得输出端输出与该数字信 号相关的信号。并且由于本申请通过改变第一器件的阈值电压来“存储”数字信息，当数字电路掉电，“存储”在其中的数字信息并不会丢失，使得本申请的数字电路具备非易失特性，掉电前的数据可以召回。因此，本申请的数字电路可以在实现经过一个完整的时钟周期将输入端的数据信号传递到了输出端的同时实现数据信号的非易失性存储。
结合第一方面，在一种可能的实现方式中，所述控制电路还用于：
在所述第一时钟信号为第一状态时通过所述第一输出端输出第二信号，所述第二信号为上一次所述第一时钟信号由第一状态变为第二状态后所述第一输出端输出的信号。
在上述技术方案中，在第一时钟信号为第一状态时第一输出端输出上一次第一时钟信号由第一状态变为第二状态后第一输出端输出的信号，即在控制电路根据第一信息控制第一器件的阈值电压时，控制电路可以保持输出上一次“保存”的数字信息，直到第一时钟信号变为第二状态。这样，本申请的数字电路可以在实现D触发器的功能的同时实现数据信号的非易失性存储。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述第一信号的第一状态对应于所述阈值电压的第一状态，所述阈值电压的第一状态对应于所述第三信号的第一状态；所述第一信号的第二状态对应于所述阈值电压的第二状态，所述阈值电压的第二状态对应于所述第三信号的第二状态。
例如，第一信号的高电平对应于阈值电压的高阈值电压，高阈值电压对应于第三信号的高电平。又例如，第一信号的高电平对应于阈值电压的低阈值电压，高阈值电压对应于第三信号的高电平。又例如，第一信号的低电平对应于阈值电压的高阈值电压，高阈值电压对应于第三信号的低电平。又例如，第一信号的低电平对应于阈值电压的低阈值电压，高阈值电压对应于第三信号的低电平。又例如，第一信号的高电平对应于阈值电压的高阈值电压，高阈值电压对应于第三信号的低电平。又例如，第一信号的高电平对应于阈值电压的低阈值电压，高阈值电压对应于第三信号的低电平。又例如，第一信号的低电平对应于阈值电压的高阈值电压，高阈值电压对应于第三信号的高电平。又例如，第一信号的低电平对应于阈值电压的低阈值电压，高阈值电压对应于第三信号的高电平。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述第一器件包括栅极、源极和漏极，所述通断状态为所述第一器件的源极和漏极之间的通断状态。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述第一器件还包括衬底；所述控制电路具体用于：通过控制所述栅极与所述源极之间的电压、所述栅极与所述漏极之间的电压、以及所述栅极与所述衬底之间的电压中的至少一个，控制所述阈值电压。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，当所述第一时钟信号为第一状态时，所述栅极的电平与所述源极的电平相反，和/或，所述栅极的电平与所述漏极的电平相反，和/或，所述栅极的电平与所述衬底的电平相反。
在上述技术方案中，通过使第一器件的栅极的电平与源极的电平相反，和/或，栅极的电平与漏极的电平相反，和/或，栅极的电平与衬底的电平相反，使得第一器件根据栅极与源极、漏极和衬底中的至少一个之间的电压差改变极性，从而实现改变第一器件的阈值电压，即将第一信号“存储”在第一器件中。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路包括第一开关器件和反相电路；所述输入端通过所述第一开关器件与所述栅极连接，所述输入端通过所述第一开关器件和所述反相电路与所述源极、所述漏极和所述衬底中的至少一个连接，所述第一开关器件的控制端与所述第一时钟信号连接，所述反相电路用于对所述第一信号进行反相处理；当所述第一时钟信号为第一状态时，所述第一开关器件导通，所述第一信号输入所述栅极、以及经过所述反相电路的反向处理后输入所述源极、所述漏极和所述衬底中的至少一个，以便控制所述第一器件的阈值电压；当所述第一时钟信号为第二状态时，所述第一开关器件关断。
在上述技术方案中，第一信号输入第一器件的栅极，同时第一信号经过反相处理输入至第一器件的源极、漏极和衬底中的至少一个，可以实现第一器件的栅极的电平与源极的电平相反，和/或，栅极的电平与漏极的电平相反，和/或，栅极的电平与衬底的电平相反。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路包括第一开关器件和反相电路；所述输入端通过所述第一开关器件和所述反向电路与所述栅极连接，所述输入端通过所述第一开关器件与所述源极、所述漏极和所述衬底中的至少一个连接，所述第一开关器件的控制端与所述第一时钟信号连接，所述反相电路用于对所述第一信号进行反相处理；当所述第一时钟信号为第一状态时，所述第一开关器件导通，所述第一信号输入所述源极、所述漏极和所述衬底中的至少一个、以及经过所述反相电路的反向处理后输入所述栅极，以便控制所述第一器件的阈值电压；当所述第一时钟信号为第二状态时，所述第一开关器件关断。
在上述技术方案中，第一信号经过反相处理输入至第一器件的栅极，同时第一信号输入至第一器件的源极、漏极和衬底中的至少一个，可以实现第一器件的栅极的电平与源极的电平相反，和/或，栅极的电平与漏极的电平相反，和/或，栅极的电平与衬底的电平相反。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述反相电路包括至少一个第一反相器。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述反相电路还包括至少一个第二开关器件，所述至少一个第一反相器与所述至少一个第二开关器件一一对应，所述第二开关器件的控制端与所述第一时钟信号连接，所述第二开关器件在所述第一时钟信号为第一状态时导通，以及在所述第一时钟信号为第二状态时关断。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路包括第三开关器件，所述第三开关器件的控制端与所述第一时钟信号连接，所述栅极通过所述第三开关器件与第一电压连接，所述源极与第二电压连接；
当所述第一时钟信号为第一状态时，所述第三开关器件关断；
当所述第一时钟信号为第二状态时，所述第三开关器件导通，所述栅极的电压为所述第一电压，所述源极的电压为所述第二电压；
若所述第一电压、所述第二电压和所述阈值电压满足导通条件，所述第一器件管导通；
若所述第一电压、所述第二电压和所述阈值电压不满足所述导通条件，所述第一器件关断。
在上述技术方案中，当第一时钟信号为第二状态时，对第一器件的栅极和源极施加电 压，其当前的阈值电压会影响其通断状态，即可以实现根据第一器件当前的阈值电压改变其通断状态。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路还包括第四开关器件，所述第四开关器件的控制端与所述第一时钟信号连接，所述源极通过所述第四开关器件与所述第二电压连接；
当所述第一时钟信号为第一状态时，所述第四开关器件关断；
当所述第一时钟信号为第二状态时，所述第四开关器件导通。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路还包括第五开关器件，所述第五开关器件的控制端与所述第一时钟信号连接，所述衬底通过所述第五开关器件与所述第二电压连接；
当所述第一时钟信号为第一状态时，所述第五开关器件关断；
当所述第一时钟信号为第二状态时，所述第五开关器件导通。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，若所述第一器件导通，则所述第一输出端与第三电压之间的电路导通；若所述第一器件关断，则所述第一输出端与第二电压之间的电路导通。
在上述技术方案中，第一器件的通断状态会影响第一输出端所连接的电压信号，从而实现第一输出端输出与第一信号相关的第三信号。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路包括第六开关器件、第七开关器件、第八开关器件、第九开关器件和储能器件，其中，所述漏极通过所述第六开关器件与所述第三电压连接，所述第一输出端通过所述储能器件与所述第三电压连接、通过所述第七开关器件与所述第三电压连接、以及通过所述第八开关器件和所述第九开关器件与第二电压连接，所述第七开关器件的控制端、所述第八开关器件的控制端通过所述第六开关器件与所述第三电压连接，所述第六开关器件的控制端和所述第九开关器件的控制端与所述第一时钟信号连接，所述第二电压对应于高电平，所述第三电压对应于低电平；
当所述第一时钟信号为第一状态时，所述第九开关器件关断，所述第六开关器件导通，使得所述第七开关器件关断，所述第八开关器件导通，所述第一输出端输出所述第二信号；
当所述第一时钟信号为第二状态时，所述第九开关器件导通，所述第六开关器件关断；
若所述第一器件导通，则所述第七开关器件导通，所述第八开关器件关断，使得所述第一输出端的电压为所述第三电压、以及所述储能器件放电；
若所述第一器件关断，则所述第七开关器件关断，所述第八开关器件导通，使得所述第一输出端的电压为所述第二电压、以及为所述储能器件充电。
在上述技术方案中，根据第一器件的通断状态，并配合各开关器件，可以控制第一输出端的充电或放电，完成数据的读出或传递。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述漏极与所述第六开关器件之间还包括第十开关器件，所述第十开关器件的控制端与所述第一时钟信号连接，所述第十开关器件在所述第一时钟信号为第一状态时关断、以及在所述第一时钟信号为第二状态时导通。
在上述技术方案中，在第一时钟信号为第一状态时，第十开关器件关断，从而可以将 第一器件的漏极和第三电压隔开，有助于避免第一器件的漏极受到第三电压的影响。在第一时钟信号为第二状态时，第十开关器件导通，不影响数据信号的传递。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路包括第六开关器件、第七开关器件、第八开关器件、第九开关器件、第十开关器件和储能器件，所述漏极通过所述第六开关器件和所述第十开关器件与第三电压连接，所述第一输出端通过所述储能器件与第二电压连接、通过所述第七开关器件与所述第三电压连接、以及通过所述第八开关器件和所述第九开关器件与所述第二电压连接，所述第七开关器件的控制端和所述第八开关器件的控制端通过所述第六开关器件与所述第三电压连接，所述第六开关器件的控制端与所述第三电压连接，所述第九开关器件的控制端与所述第一时钟信号连接，所述第二电压对应于低电平，所述第三电压对应于高电平；
当所述第一时钟信号为第一状态时，所述第九开关器件关断，所述第六开关器件导通，使得所述第七开关器件关断，所述第八开关器件导通，所述第一输出端输出所述第二信号；
当所述第一时钟信号为第二状态时，所述第九开关器件导通；
若所述第一器件导通，则所述第七开关器件导通，所述第八开关器件关断，使得所述第一输出端的电压为所述第三电压、以及为所述储能器件充电；
若所述第一器件关断，则所述第七开关器件关断，所述第八开关器件导通，使得所述第一输出端的电压为所述第二电压、以及所述储能器件放电。
在上述技术方案中，根据第一器件的通断状态，并配合各开关器件，可以控制第一输出端的充电或放电，完成数据的读出或传递。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述储能器件为电容。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路还包括第十一开关器件；所述第七开关器件的控制端通过所述第十一开关器件与所述第三电压连接；在所述数字电路上电时，所述第一时钟信号为第二状态，所述第十一开关器件导通。
在上述技术方案中，第一时钟信号在触发器上电时为第二状态，可以避免掉电时保存在第一器件中的数据信息被改写。并且在第一时钟信号为第二状态时，第十一开关器件导通，可以实现将掉电时保存在第一器件中的数据信息的读出。这样通过采用本申请的数字电路可以实现将暂时不用的线程或核里的寄存器下电，待下次使用时再集体召回，有助于节省功耗。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路还包括时钟信号生成电路，用于生成所述第一时钟信号；所述时钟信号生成电路具体包括第二输出端、第十三开关器件和第十四开关器件，所述第二输出端用于输出所述第一时钟信号，所述第十三开关器件的控制端连接第三信号，所述第十三开关器件的第一端接地，所述第十四开关器件的控制端连接第四信号，所述第十四开关器件的第一端连接第二时钟信号，所述第十三开关器件的第二端和所述第十四开关器件的第二端连接所述第二输出端，所述第十三开关器件在所述第三信号为第一状态时导通、以及在所述第三信号为第二状态时关断，所述第十四开关器件在所述第四信号为第二状态时导通、以及在所述第四信号为第一状态时关断；所述第三信号在第一时间段内为第一状态，所述第四信号在第 二时间段内为第一状态，所述第一时间段和所述第二时间段的起始时刻为所述数字电路上电的时刻，所述第一时间段的时长小于或者等于所述第二时间段的时长。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述控制电路还包括电平恢复电路；所述电平恢复电路用于在所述第一信号为高电平的情况下，在下一次所述第一时钟信号由第一状态变为第二状态之前，控制所述第一输出端维持高电平。
在上述技术方案中，通过增加电平恢复电路可以保证第一输出端应该输出高电平时维持输出高电平。有助于避免由于储能器件的电荷发生泄露导致的信号输出错误。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述电平恢复电路包括第十二开关器件和第二反相器；所述第一输出端通过所述第十二开关器件与所述第二电压连接，所述第二电压对应于高电平；或者，所述第一输出端通过所述第十二开关器件与所述第三电压连接，所述第三电压对应于高电平；所述第一输出端通过所述第二反相器与所述第十二开关器件的控制端连接。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述第一时钟信号的第一状态为高电平，所述第一时钟信号的第二状态为低电平；或者，所述第一时钟信号的第一状态为低电平，所述第一时钟信号的第二状态为高电平。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述第一器件为铁电场效应晶体管。
对于铁电场效应晶体管，改变加在其铁电层上的电压即可改变其极性，从而改变其阈值电压。并且铁电场效应晶体管的通断状态会受到其阈值电压的影响。因此，可以采用铁电场效应晶体管作为非易失性器件来实现本申请的数字电路。
结合第一方面或上述任意一种可能的实现方式，在另一种可能的实现方式中，所述数字电路为D触发器。
第二方面，本申请提供了一种电子装置，包括第一方面或其任意一种可能的实现方式中所述的数字电路。
附图说明
图1是MOS管的示意性结构图。
图2是铁电场效应晶体管的示意性结构图。
图3是铁电场效应晶体管的工作原理的示意图。
图4是改进的铁电场效应晶体管的示意性结构图。
图5是改进的铁电场效应晶体管的工作原理的示意图。
图6是本申请提供的数字电路的示意性结构图。
图7是本申请提供的第一器件的示意性结构图。
图8是本申请提供的触发器的示意性结构图。
图9是本申请的触发器的可能的使用方式的示意图。
图10是本申请提供的触发器的一个示例。
图11是本申请提供的触发器的另一个示例。
图12是本申请提供的触发器的另一个示例。
图13是本申请提供的触发器的另一个示例。
图14是本申请提供的触发器的另一个示例。
图15是本申请提供的触发器的另一个示例。
图16是本申请的一种可能的时钟信号生成电路的示意图。
图17是带有数据召回功能的触发器的时序控制图。
图18是本申请提供的触发器的另一个示例。
图19是本申请提供的触发器的另一个示例。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
为了便于理解，首先给出与本申请相关的概念的说明。
1、金属氧化物半导体场效应晶体管
金属氧化物半导体场效应晶体管(MOSFET，下文简称MOS管)通常可以包括栅极(gate，G)、源极(source，S)、漏极(drain，D)和衬底(bulk，B)，可以通过在栅极和源极间加控制信号改变源极和漏极间的通断状态。MOS管可以是看作是3端器件，也可以看作是4端器件。当MOS管作为3端器件使用时，源极和衬底连接在一起，甚至衬底可以不引出。当MOS管作为4端器件使用时，衬底和源极可独立控制。
图1是MOS管的示意性结构图。如图1所示，MOS管可以分为P沟道MOS管与N沟道MOS管两类。
如图1的(a)图所示，P沟道MOS管在N型硅衬底上有两个P+区，分别作为源极和漏极，两极之间不通导。源极上加有足够的正电压(栅极接地)时，栅极下的N型硅表面呈现P型反型层，成为连接源极和漏极的沟道，改变栅压可以改变沟道中的空穴密度，从而改变沟道的电阻，这种MOS管称为P沟道增强型场效应晶体管。如果N型硅衬底表面不加栅压就已存在P型反型层沟道，加上适当的偏压，可使沟道的电阻增大或减小，这种MOS管称为P沟道耗尽型场效应晶体管。P沟道增强型场效应晶体管和P沟道耗尽型场效应晶体管可以统称为PMOS晶体管(下文简称为PMOS管)。
如图1的(b)图所示，N沟道MOS管和P沟道MOS管在结构上相似，所不同的是衬底和源漏的掺杂类型，PMOS是在N型硅的衬底上，通过掺杂形成P型的掺杂区，作为源漏区，而NMOS是在P型硅的衬底上，通过掺杂形成N型的掺杂区，作为源漏区。
对于MOS管更详细的描述可以参考现有技术，在此不再赘述。
2、铁电场效应晶体管
铁电场效应晶体管(ferro-electric field effect transistor，FEFET)是一种新型的非易失性存储器件，一个铁电场效应晶体管即可实现1比特(bit)的信息存储，未来可能替代Flash存储器，或用于实现非易失性静态随机存储器(static random access memory，SRAM)等。
图2是铁电场效应晶体管的示意性结构图。铁电场效应晶体管与MOS管非常相似，只是在栅极和介质层(insulator)之间添加了铁电(ferro-electric，FE)层，通过改变加在FE层上的电压即可改变其极性，从而改变铁电场效应晶体管的阈值电压(V T)，实现存“0”和存“1”的功能。与MOS管类似，铁电场效应晶体管也分为N型FEFET和P型 FEFET两种类型，同样可以作为3端器件或4端器件使用。
图3是铁电场效应晶体管的工作原理的示意图。图3以N型FEFET为例，铁电场效应晶体管的工作原理如下：
1)对于作为3端器件使用的情况，在写入过程中，将源极和/或漏极漏接地，通过控制栅极的电压来改变铁电层的极化方向，或者通过控制栅极和源极之间的电压差和/或栅极和漏极之间的电压差改变铁电层的极化方向。以将源极和/或漏极漏接地、控制栅极的电压来改变铁电层的极化方向为例，如果栅极的电压为正值，则沟道表面感应出负电压，V T减小，在读出过程中会表现出低阻抗；如果栅极的电压为负值，则沟道表面感应出正电压，V T增大，在读出过程中会表现为高阻抗。在读出过程中，栅极和源极之间的电压V GS＝0或某一可识别阈值高低的电压，漏极和源极之间的电压V DS>0，根据写入时不同的状态，铁电场效应晶体管处于导通或关断状态，从而实现信息的存储和读出。
2)对于作为4端器件使用的情况，除了可以通过改变栅极和源极的电压和/或栅极和漏极之间的电压来改变V T，还可以通过改变栅极和衬底之间的电压来改变铁电层的极化方向。如果栅极和衬底之间的电压V GB>0，沟道表面感应出负电压，V T减小；如果V GB<0，沟道表面感应出正电荷，V T增大。
此外，对于P型晶体管来说，V T变化正好相反。
图4是改进的铁电场效应晶体管的示意性结构图。由于图3所示的铁电场效应晶体管可擦写次数比较有限，约在10^5量级。为了改善铁电场效应晶体管的可擦写次数，有人提出在MOS管的上方叠加铁电电容，这样可以将铁电场效应晶体管的可擦写次数提高到10^12-14量级。改进的铁电场效应晶体管的示意性结构图可以如图4所示。
图5是改进的铁电场效应晶体管的工作原理的示意图。图4以P型FEFET为例，通过控制栅极和衬底之间的电位来控制铁电场效应晶体管的阈值电压V T，铁电场效应晶体管的工作原理如下：
在写入过程中，源极或漏极可以开路(open)，或者可以使衬底和源极/漏极之间零偏或正偏，以保证PN结反偏。当衬底接0电位，栅极接高电位时，沟道表面感应出负电荷，铁电场效应晶体管的V T增大；当衬底接高电位，栅极接0电位时，沟道表面感应出正电荷，铁电场效应晶体管的V T减小。在读出过程中，栅极和源极之间的电压V GS＝0或某一可识别阈值高低的电压，栅极和衬底之间的电压V GB＝0，根据写入时不同的状态，铁电场效应晶体管处于导通或关断状态，从而实现信息的存储和读出。
示例性地，P型FEFET工作过程中各极的状态以及阈值状态可以如表1所示，其中，V H为高电平或正电平，V DD为电源电压。
表1
状态 栅极 源极 漏极 衬底 V T
写入1 0 开路 0 V H 低阈值电压
写入0 V H 开路 0 0 高阈值电压
读出 V DD V DD   V DD  
需要说明的是，低阈值电压和高阈值电压可以指FEFET受极化偏置后的两种阈值状态，高阈值电压和低阈值电压的具体数值以在实际应用中能够有效区分两种状态为准。
在本申请中，将着重结合P型FEFET对本申请的触发器进行描述，需要说明的是， 任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，例如，结合N型FEFET实现本申请的触发器，都应涵盖在本申请的保护范围之内。
3、D触发器
D触发器是一个具有记忆功能的、具有两个稳定状态的信息存储器件，是构成多种时序电路的最基本逻辑单元，也是数字集成电路中的重要器件。一般采用主从式结构，经过一拍可以将数字信息传递到输出端并保持稳定到下一次数据写入。
目前，对于便携式设备，为了节省功耗，希望设备在不活动周期被置于断电或待机模式，不执行任何操作，但又希望下次唤醒设备时某些数据寄存器中的状态保持不变，快速恢复到原来状态。另外，对于多核、多线程处理器，希望在不访问某些核和线程时可以掉电以减少功耗，但有希望访问时又可立刻召回原状态。对于这类应用场景，都需要用到具有非易失性功能的数字信息存储器件。但是，当前大部分数字信息存储器件，例如，D触发器，均采用MOS管实现，在掉电后存储的数字信息会丢失，不能满足这类场景的需求。
针对上述问题，本申请提供了一种数字电路，能够实现数字信息的非易失性存储。
图6是本申请提供的数字电路的示意性结构图。如图6所示，数字电路500包括：控制电路510和第一器件520，所述控制电路510包括输入端5101、第一输出端5102和时钟控制端5103，所述时钟控制端5103与第一时钟信号530连接。
其中，所述控制电路510，用于当所述第一时钟信号530为第一状态时，根据所述输入端5101接收的第一信号，控制所述第一器件520的阈值电压，所述第一信号的不同状态对应于所述第一器件520的不同阈值电压；当所述第一时钟信号530由第一状态变为第二状态，根据所述第一器件520的阈值电压，控制所述第一器件520的通断状态，以及根据所述第一器件520的通断状态，输出第三信号，所述第三信号为与所述第一信号相关的信号。
可选地，第三信号为与第一信号的状态相同的信号，或者第三信号为与第一信号的状态相反的信号。
在一些实现方式中，所述控制电路510，还用于在所述第一时钟信号530为第一状态时通过所述第一输出端5102输出第二信号，所述第二信号为上一次所述第一时钟信号由第一状态变为第二状态后所述第一输出端5102输出的信号。
在本申请中，第一信号的第一状态对应于第一器件520的阈值电压的第一状态，阈值电压的第一状态对应于第三信号的第一状态，第一信号的第二状态对应于第一器件520的阈值电压的第二状态，阈值电压的第二状态对应于第三信号的第二状态。本申请对于第一信号的第一状态和第二状态、第一器件520的阈值电压的第一状态和第二状态、第三信号的第一状态和第二状态不作具体限定。
例如，第一信号的高电平对应于阈值电压的高阈值电压，高阈值电压对应于第三信号的高电平。又例如，第一信号的高电平对应于阈值电压的低阈值电压，高阈值电压对应于第三信号的高电平。又例如，第一信号的低电平对应于阈值电压的高阈值电压，高阈值电压对应于第三信号的低电平。又例如，第一信号的低电平对应于阈值电压的低阈值电压，高阈值电压对应于第三信号的低电平。又例如，第一信号的高电平对应于阈值电压的高阈值电压，高阈值电压对应于第三信号的低电平。又例如，第一信号的高电平对应于阈值电压的低阈值电压，高阈值电压对应于第三信号的低电平。又例如，第一信号的低电平对应 于阈值电压的高阈值电压，高阈值电压对应于第三信号的高电平。又例如，第一信号的低电平对应于阈值电压的低阈值电压，高阈值电压对应于第三信号的高电平。
在本申请中，第一器件为阈值电压可变的器件，或者说阈值电压可编程器件。阈值电压可变也可以等效、替换或描述为阻抗状态可变等，本申请不予限制。
可选地，第一器件可以为2端器件。
可选地，第一器件可以包括栅极、源极和漏极，也可以包括栅极、源极、漏极和衬底，即第一器件可以为3端器件，也可以为4端器件，本申请不予限制。例如，第一器件可以包括一个或多个FEFET，FEFET具体的器件结构不限于上文所述的形式或结构，也可以是其他结构或形式的FEFET，只要满足可以通过控制极化方向改变其阈值电压即可。以第一器件采用FEFET实现为例，图7示出了第一器件的几种结构形式。如图7的(a)图所示，第一器件为一个3端的N型FEFET；如图7的(b)图所示，第一器件包括FEFET1和FEFET2两个3端的N型FEFET，两个FEFET并联，其中，两个栅极相连接，两个漏极相连接，两个漏极相连接；如图7的(c)图所示，第一器件包括FEFET1-FEFETn，n个FEFET为3端的N型FEFET，同样，N个FEFET并联，其中，n个栅极相连接，n个漏极相连接，n个漏极相连接。需要指出的是，第一器件包括的多个FEFET也可以被看作一个FEFET，本申请不予限制。
在一些实现方式中，所述控制电路510，具体用于通过控制第一器件520的栅极与源极之间的电压、栅极与漏极之间的电压、以及栅极与衬底之间的电压中的至少一个，控制第一器件520的阈值电压，本申请对于具体的实现方式不作限定。
作为一个示例，当第一时钟信号为第一状态时，控制电路510控制第一器件520的栅极的电平与源极的电平相反，和/或，栅极的电平与漏极的电平相反，和/或，栅极的电平与衬底的电平相反，从而实现改变第一器件520的阈值电压。
在一些实现方式中，所述控制电路510可以包括第三开关器件，所述第三开关器件的控制端与所述第一时钟信号530连接，所述第一器件520的栅极通过所述第三开关器件与第一电压连接，所述第一器件520的源极与第二电压连接。当所述第一时钟信号530为第一状态时，所述第三开关器件关断；当所述第一时钟信号530为第二状态时，所述第三开关器件导通，所述第一器件520的栅极的电压为所述第一电压、源极的电压为所述第二电压。此时，若所述第一电压、所述第二电压和所述第一器件520的阈值电压满足导通条件，所述第一器件520管导通；若所述第一电压、所述第二电压和所述第一器件520的阈值电压不满足导通条件，所述第一器件520关断。这样，当第一时钟信号530为第二状态时，对第一器件520的栅极和源极施加电压，其当前的阈值电压会影响其通断状态，即可以实现根据第一器件520当前的阈值电压改变其通断状态。
在一些实现方式中，若所述第一器件520导通，则所述第一输出端5102与第三电压之间的电路导通；若所述第一器件520关断，则所述第一输出端5102与第二电压之间的电路导通。通过第一器件的通断状态影响第一输出端5102所连接的电压信号，从而实现第一输出端5102输出与第一信号相关的第三信号。
需要说明的是，上述第一器件的源极可以是提供载流子的一端对应的电极，漏极可以是收集载流子的一端对应的电极，栅极可以是控制第一器件通断的电极，衬底可以是指从衬底材料中引出的电极。这里的栅极、源极、漏极和衬底只是一种常用的描述方式，实际 上对于不同的器件可能有不同的名称，上述各个电极的名称对本申请不构成限定。还需要说明的是，上述阈值电压可以为将传输特性曲线中输出电流随输入电压改变而急剧变化转折区的中点对应的输入电压称为阈值电压，在描述不同的器件时具有不同的参数。以NMOS为例，阈值电压通常定义为界面处的电子浓度等于P型衬底的多子浓度(空穴浓度)时栅极和源极之间的电压。以PMOS为例，阈值电压通常定义为界面处的空穴浓度等于N型衬底的多子浓度(电子浓度)时栅极和源极之间的电压。还需要说明的是，上述第一器件的通断状态可以是第一器件的源极和漏极之间的通断状态。
下面将结合图8至图19，以数字电路为D触发器为例，对本申请的技术方案进行更描述。并且为了描述方便，下文会将控制电路分为写入电路、读出电路和输出电路等多个子电路，并分别对各个子电路进行详细描述。需要说明的是，下文对于控制电路的划分仅为描述方便，并不对本申请的技术方案构成限定。例如，控制电路还可以不做划分、或者采用其他的划分方式。
图8是本申请提供的触发器的示意性结构图。如图8所示，触发器600包括：写入电路610、读出电路620、输出电路630和非易失性器件640。其中，写入电路610包括用于接收信号的信号输入端6101，输出电路630包括用于输出信号的信号输出端6301。写入电路610、读出电路620和输出电路630与第一时钟信号650连接，换句话说，写入电路610、读出电路620和输出电路630由第一时钟信号650控制。
下面对触发器的各个部分进行描述。
1)当第一时钟信号650为第一状态时，写入电路610用于根据信号输入端6101接收的第一信号，控制非易失性器件640的阈值电压。输出电路630用于输出第二信号。其中，第二信号为上一次第一时钟信号650由第一状态变为第二状态之后输出电路630输出的信号。
2)当第一时钟信号650由第一状态变为第二状态，读出电路630用于根据非易失性器件640的阈值电压，控制非易失性器件640的通断状态。输出电路630用于根据非易失性器件640的通断状态，输出第一信号。
这里所说的第一时钟信号650由第一状态变为第二状态，可以指第一时钟信号650由第一状态变为第二状态后，即第一时钟信号为第二状态，也可以指第一时钟信号650由第一状态变为第二状态的过程中，对此本申请不作具体限定。也就是说，本申请的触发器可以为边沿触发的触发器，也可以为电平触发的触发器。
可选地，第一时钟信号的第一状态为高电平，第一时钟信号的第二状态为低电平，或者，第一时钟信号的第一状态为低电平，第一时钟信号的第二状态为高电平，本申请不作具体限定。
这样，触发器600在第一时钟信号650为第一状态时可以根据信号输入端6101接收的数据信号的数值，控制非易失性器件640的阈值电压，可以理解为，触发器将数据信号写入到非易失性器件640，不同的阈值电压表示不同的数值。在第一时钟信号650由第一状态变为第二状态时或第一时钟信号650由第一状态变为第二状态后，非易失性器件640当前的阈值电压会影响非易失性器件640的通断状态，而非易失性器件640的不同状态可以使得输出电路630输出不同的信号。这样，经过一个完整的时钟周期，触发器600可以将信号输入端6101的数据信号传递到了信号输出端6301，并保持到下一次完成数据写入， 并且由于触发器600将数据信号存储到非易失性器件640中，使得触发器600具备数据非易失特性，掉电前的数据可以召回。因此，触发器600可以在实现D触发器的功能的同时实现数据信号的非易失性存储。
下面将以非易失性器件640为FEFET为例进行描述。
在一些实现方式中，写入电路610包括第一开关器件和反相电路，信号输入端6101通过第一开关器件与FEFET的栅极连接，同时信号输入端6101通过第一开关器件和反相电路与FEFET的源极、漏极和衬底中的至少一个连接，第一开关器件的控制端与第一时钟信号连接，反相电路用于对第一信号进行反相处理。当第一时钟信号为第一状态时，第一开关器件导通，第一信号输入FEFET的栅极、以及经过反相电路的反向处理后输入FEFET的源极、漏极和衬底中的至少一个，以便控制FEFET的阈值电压；当第一时钟信号为第二状态时，第一开关器件关断。
在另一些实现方式中，写入电路610包括第一开关器件和反相电路；信号输入端6101通过第一开关器件和反向电路与FEFET的栅极连接，同时信号输入端6101通过第一开关器件与FEFET的源极、漏极和衬底中的至少一个连接，第一开关器件的控制端与第一时钟信号连接，反相电路用于对所述第一信号进行反相处理。当第一时钟信号为第一状态时，第一开关器件导通，第一信号输入FEFET的源极、漏极和衬底中的至少一个、以及经过反相电路的反向处理后输入FEFET的栅极，以便控制FEFET的阈值电压；当第一时钟信号为第二状态时，第一开关器件关断。
可选地，上述反相电路包括至少一个第一反相器。
可选地，上述反相电路包括至少一个第一反相器、以及至少一个第二开关器件，其中，至少一个第一反相器与至少一个第二开关器件一一对应，第二开关器件的控制端与第一时钟信号连接，第二开关器件在第一时钟信号为第一状态时导通，以及在第一时钟信号为第二状态时关断。
在一些实现方式中，读出电路620包括第三开关器件，第三开关器件的控制端与第一时钟信号连接，FEFET的栅极通过第三开关器件与第一电压连接，FEFET的源极与第二电压连接。当第一时钟信号为第一状态时，第三开关器件关断；当第一时钟信号为第二状态时，第三开关器件导通，FEFET的栅极的电压为第一电压，FEFET的源极的电压为第二电压；若FEFET当前的阈值电压为低电压，FEFET导通；若FEFET当前的阈值电压为高电压，FEFET关断。
可选地，读出电路620还可以包括第四开关器件，第四开关器件的控制端与第一时钟信号连接，FEFET的源极通过第四开关器件与第二电压连接。当第一时钟信号为第一状态时，第四开关器件关断；当第一时钟信号为第二状态时，第四开关器件导通。
可选地，读出电路620还可以包括第五开关器件，第五开关器件的控制端与第一时钟信号连接，FEFET的衬底通过第五开关器件与第二电压连接。当第一时钟信号为第一状态时，第五开关器件关断；当第一时钟信号为第二状态时，第五开关器件导通。
需要指出的是，上述第一电压为在第一时钟信号为第二状态时可使第三开关器件导通的电压，以及与第二电压配合可以区分出FEFET的高低阻抗状态的电压。
可选地，若FEFET为P型FEFET，第一电压和第二电压可以均为第一电源电压，例如，第一电压和第二电压可以均为V DD。
可选地，若FEFET为N型FEFET，第一电压和第二电压可以均为第二电源电压，例如，第一电压和第二电压可以均为V SS或地线电压(Ground，GND)。或者，第一电压为V R，第二电压为第二电源电压。
在一些实现方式中，若FEFET为P型FEFET，输出电路630可以包括第六开关器件、第七开关器件、第八开关器件、第九开关器件和储能器件。其中，FEFET的漏极通过第六开关器件与第三电压连接，信号输出端6301通过储能器件与第三电压连接、通过第七开关器件与第三电压连接、以及通过第八开关器件和第九开关器件与第二电压连接，第七开关器件的控制端和第八开关器件的控制端通过第六开关器件与第三电压连接，第六开关器件的控制端和第九开关器件的控制端与第一时钟信号连接。当第一时钟信号为第一状态时，第九开关器件关断，第六开关器件导通，使得第七开关器件关断，第八开关器件导通，信号输出端6301输出第二信号；当第一时钟信号为第二状态时，第九开关器件导通，第六开关器件关断。若FEFET导通，则第七开关器件导通，第八开关器件关断，使得信号输出端6301的电压为第三电压、以及储能器件放电；若FEFET关断，则第七开关器件关断，第八开关器件导通，使得信号输出端6301的电压为第二电压、以及为储能器件充电。
可选地，FEFET的漏极与第六开关器件之间还可以包括第十开关器件。第十开关器件的控制端与第一时钟信号连接，第十开关器件在第一时钟信号为第一状态时关断、以及在第一时钟信号为第二状态时导通。
可选地，第二电压对应于高电平，第三电压对应于低电平。例如，第二电压为V DD，第三电压为GND或V SS。又例如，第二电压为GND，第三电压为V SS。
在另一些实现方式中，若FEFET为N型FEFET，输出电路630可以包括第六开关器件、第七开关器件、第八开关器件、第九开关器件、第十开关器件和储能器件，FEFET的漏极通过第六开关器件和第十开关器件与第三电压连接，信号输出端6301通过储能器件与第二电压连接、通过第七开关器件与第三电压连接、以及通过第八开关器件和第九开关器件与第二电压连接，第七开关器件的控制端和第八开关器件的控制端通过第六开关器件与第三电压连接，第六开关器件的控制端与第三电压连接，第九开关器件的控制端与第一时钟信号连接。当第一时钟信号为第一状态时，第九开关器件关断，第六开关器件导通，使得第七开关器件关断，第八开关器件导通，信号输出端6301输出第二信号；当第一时钟信号为第二状态时，第九开关器件导通；若FEFET导通，则第七开关器件导通，第八开关器件关断，使得信号输出端6301的电压为第三电压、以及储能器件放电；若FEFET关断，则第七开关器件关断，第八开关器件导通，使得信号输出端6301的电压为第二电压、以及为储能器件充电。
可选地，第二电压对应于低电平，第三电压对应于高电平。例如，第二电压为V SS，第三电压为V DD或GND。又例如，第二电压为GND，第三电压为V DD。
可选地，在一些实现方式中，上述储能器件可以为电容。
由于上述各实施例的触发器中使用了非易失性器件FEFET来保存数据信息，因此可以实现掉电保存数据。但是若在触发器重新上电时，第一时钟信号先为高电平再为低电平，那么掉电时保存在FEFET中的数据信息就有可能被改写。这样，会导致部分数据信息不能被召回。针对该问题，在另一些实现方式中，触发器还可以包括用于数据召回的第十一开关器件，并使用在触发器重新上电时电平状态为第二状态的时钟信号。对具有数据召回 功能的触发器，将在下文将结合具体示例进行描述。
对于信号输出端6301应该输出高电平的情况，由于储能器件有可能电荷发生泄露，因此有可能会导致信号输出端6301的电压降低，造成信号输出错误。针对该问题，在另一些实现方式中，触发器还可以包括电平恢复电路。电平恢复电路用于在第一信号为高电平的情况下，在下一次第一时钟信号由第一状态变为第二状态之前，控制信号输出端6301维持高电平。对于电平恢复电路，将在下文将结合具体示例进行描述。
需要说明的是，本申请对各开关器件的类型不做具体限定，例如，可以采用MOS管、双极结型晶体管(bipolar junction transistor，BJT)或其他类型的开关器件实现。本申请对于各开关器件的N型或P型也不作具体限定。以MOS管为例。例如，当第一时钟信号的第一状态为高电平、第二状态为低电平时，上述第一开关器件、第二开关器件、第六开关器件等可以为NMOS管，上述第三开关器件、第四开关器件、第五开关器件和第九开关器件等可以为PMOS管。又例如，当第一时钟信号的第一状态为高电平、第二状态为低电平时，上述第一开关器件、第二开关器件、第六开关器件等可以为PMOS管，上述第三开关器件、第四开关器件、第五开关器件和第九开关器件等可以为NMOS管。
还需要说明的是，本申请的触发器还可以通过多个时钟信号进行控制，不予限制。例如，上述第一开关器件、第二开关器件、第六开关器件等使用一个时钟信号，上述第三开关器件、第四开关器件、第五开关器件和第九开关器件等使用一个时钟信号。
本申请提供的触发器可以应用在任何需要D触发器或者非易失性D触发器的场景或产品中，例如，本申请提供的触发器可以应用于芯片、中央处理单元(central processing unit，CPU)、处理器、手机、电脑、路由器、交换机、物联网(internet of things，IoT)产品等等。在使用过程中，多个触发器可以通过串联或并联的形式实现数字信号的并、串转换，或者触发器配合组合逻辑(combinatorial logic，CL)实现所需要的逻辑和运算功能。
图9示出了本申请的触发器的可能的使用方式。
图9的(a)图为本申请的触发器的电路符号的一个示例，其包括信号输入端(IN)、信号输出端(OUT)以及时钟控制端(CLK)。图9的(b)图为本申请的触发器的一种使用方式，即可以将多个触发器串联，以实现信号的串并转换。图9的(c)图为本申请的触发器的另一种使用方式，即触发器配合CL实现所需要的逻辑和运算功能。
下面结合具体的例子，对本申请的触发器进行描述。
示例1
图10是本申请提供的触发器的一个示例。如图10所示，触发器包括：P型FEFET、写入电路、读出电路、以及输出电路，在图10中将FEFET作为4端器件使用。P型FEFET的工作原理可以参考上文图5的相关描述，在此不再赘述。
1)写入电路
写入电路包括信号输入端、NMOS管T1-T2、以及反相器1。信号输入端通过T1与FEFET的栅极连接，并且通过T1、反相器1和T2连接至FEFET的衬底。T1和T2的控制端连接时钟信号。
2)读出电路
读出电路包括PMOS管T3-T5，T3-T5的控制端连接时钟信号。FEFET的栅极通过T3连接至V DD，源极通过T4连接至V DD，衬底通过T5连接至V DD。
3)输出电路
输出电路包括NMOS管T6-T7、PMOS管T8-T9、以及电容C S。FEFET的漏极、T7的控制端、以及T8的控制端分别通过T6接地，信号输出端分别通过T7和C S接地，同时信号输出端通过T8和T9连接至V DD，T6和T9的控制端连接时钟信号。
下面对图10所示的触发器的工作原理进行描述。
1)数据写入阶段
当时钟信号CLK1为高电平时，T1、T2和T6导通，T3、T4、T5和T9关断，则A点的电压被拉低，T7关断，C S保存原来数据，即信号输出端保持输出上一次数据写入过程中写入的数据。
此时，若D＝1，则FEFET的栅极的电压为1，衬底的电压为0，根据上文的表1，FEFET的阈值电压V T为高，在数据传递(或读出)阶段表现为高阻抗，FEFET擦除(erase)；若D＝0，则FEFET的栅极的电压为0，衬底的电压为1，根据上文的表1，FEFET的阈值电压V T为低，在数据传递(或读出)阶段表现为低阻抗，FEFET编程(program)。
2)数据传递(或读出)阶段
当CLK1由高电平变为低电平或CLK1为低电平时，T1、T2和T6关断，T3、T4、T5和T9导通，FEFET的栅极、源极和衬底的电压均为V DD，FEFET的栅极和源极之间的电压V GS＝0，栅极和衬底之间的电压V GB＝0。
此时，若在数据写入阶段D＝1，FEFET的V T为高，则FEFET不导通，A点电位依然使T8导通、T7关断，C S被充电，信号输出端输出1；若在数据写入阶段D＝0，FEFET的V T为低，则FEFET会导通，A点电位被充电至高电平，使得T8关断、以及T7导通，从而将信号输出端的电压下拉为低电平，C S放电，信号输出端输出0。
这样，经过一个完整的时钟周期，触发器将信号输入端的数据信号D传递到了信号输出端，并保持到下一次完成数据写入。
此外，为了获得更高的极化偏置电压，T1和T2还可以被替换为传输门，以便无损的将数据信号传递到FEFET的栅极和衬底。
图10所示的触发器在数据写入阶段，根据数据信号D的数值，控制FEFET的栅极和衬底之间的电压，从而改变FEFET的阈值电压，使得FEFET在数据传递(或读出)阶段处于不同的阻抗状态；在数据传递(或读出)阶段，FEFET的阻抗状态会影响FEFET的通断状态，从而影响信号输出端的充放电，控制信号输出端输出数据信号D的数值。并且由于在示例1中将数据信号存储到非易失性器件FEFET中，因此可以使得D触发器具备数据非易失特性，掉电前的数据可以召回。因此，图10所示的触发器可以在实现D触发器的功能的同时实现D触发器的非易失性存储。
此外，图10所示的触发器只需要11个MOS管(反相器需要两个MOS管)和1个FEFET即可实现D触发器功能，因此，图10所示的触发器的功耗为7*2+5＝19门，具有较低的功耗和占用面积。
示例2
图11是本申请提供的触发器的另一个示例。与图10中的触发器类似，不同的地方在于，图11中的触发器增加了一个PMOS管T10。
对于图10所示的触发器，在数据写入阶段，由于T6是导通的，FEFET的漏极的电 压会一直被下拉至0电压，会影响FEFET的FE层的极化，从而影响数据信号D的存储。
为了避免FEFET的漏极在数据写入阶段被下拉至0电位，图11所示的触发器在FEFET的漏极与T6之间增加了一个PMOS管T10。在数据写入阶段，T10关断，从而可以隔开FEFET的漏极和GND，避免FEFET的漏极在数据写入阶段被下拉至0电位。在数据传递(或读出)阶段，T10导通，不影响数据信号的传递。
这样，对于图11所示的触发器，在数据写入阶段，FEFET的源极和漏极都是悬空的，只有栅极和衬底之间有偏置电压，根据其偏置电压，FEFET的阈值电压会相应改变。
关于图11中的触发器的更详细描述可以参考图10，在此不再赘述。
需要说明的是，图10和图11中仅以通过控制FEFET的栅极和衬底之间的电压改变FEFET的阈值电压为例，实际上可以通过控制FEFET的栅极与衬底、源极和漏极中的至少一个之间的电压改变FEFET的阈值电压，触发器的工作原理与图10所示的触发器的工作原理类似，在此不再赘述。
示例3
图12是本申请提供的触发器的另一个示例。如图12所示，触发器包括：P型FEFET、写入电路、读出电路、以及输出电路，在图12中将FEFET作为3端器件使用。
1)写入电路
写入电路包括信号输入端、NMOS管T1-T2、以及反相器1。信号输入端通过T1与FEFET的栅极连接，并且通过T1、反相器1和T2连接至FEFET的源极。T1和T2的控制端连接时钟信号。
2)读出电路
读出电路包括PMOS管T3-T4，T3-T4的控制端连接时钟信号。FEFET的栅极通过T3连接至V DD，源极通过T4连接至V DD。
3)输出电路
输出电路包括NMOS管T6-T7、PMOS管T8-T9、以及电容C S。T7的控制端和T8的控制端分别通过T6接地，信号输出端分别通过T7和C S接地，同时信号输出端通过T8和T9连接至V DD，T6和T9的控制端连接时钟信号。
4)PMOS管T10
T10设置在T6与FEFET的漏极之间，用于在数据写入阶段将FEFET的漏极和GND隔开。需要说明的是，T10为可选器件，FEFET的漏极也可以仅通过T6接地。
下面对图12所示的触发器的工作原理进行描述。
1)数据写入阶段
当CLK1为高电平时，T1、T2和T6导通，T3、T4、T9和T10关断，则A点的电压被拉低，FEFET的漏极开路，T7关断，C S保存原来数据，即信号输出端保持输出上一次数据写入过程中写入的数据。
此时，若D＝1，则FEFET的栅极的电压为1，源极的电压为0，FEFET的阈值电压V T为高，在数据传递(或读出)阶段表现为高阻抗，FEFET擦除；若D＝0，则FEFET的栅极的电压为0，源极的电压为1，FEFET的阈值电压V T为低，在数据传递(或读出)阶段表现为低阻抗，FEFET编程。
2)数据传递(或读出)阶段
当CLK1由高电平变为低电平或CLK1为低电平时，T1、T2和T6关断，T3、T4、T9和T10导通，FEFET的栅极和源极的电压均为V DD，栅极和源极之间的电压V GS＝0。
此时，若在数据写入阶段D＝1，FEFET的V T为高，则FEFET不导通，A点电位依然使T8导通、T7关断，C S被充电，信号输出端输出1；若在数据写入阶段D＝0，FEFET的V T为低，则FEFET会导通，A点电位被充电至高电平，使得T8关断、以及T7导通，从而将信号输出端的电压下拉为低电平，C S放电，信号输出端输出0。
这样，经过一个完整的时钟周期，触发器将信号输入端的数据信号D传递到了信号输出端，并保持到下一次完成数据写入。
同样，为了获得更高的极化偏置电压，T1和T2还可以被替换为传输门，以便无损的将数据信号传递到FEFET的栅极和源极。
图12所示的触发器在数据写入阶段，根据数据信号D的数值，控制FEFET的栅极和源极之间的电压，从而改变FEFET的阈值电压，使得FEFET在数据传递(或读出)阶段处于不同的阻抗状态；在数据传递(或读出)阶段，FEFET的阻抗状态会影响FEFET的通断状态，从而影响信号输出端的充放电，控制信号输出端输出数据信号D的数值。并且由于在示例3中将数据信号存储到非易失性器件FEFET中，因此可以使得D触发器具备数据非易失特性，掉电前的数据可以召回。因此，图12所示的触发器可以在实现D触发器的功能的同时实现D触发器的非易失性存储。
此外，图12所示的触发器只需要11个MOS管(反相器需要两个MOS管)和1个FEFET即可实现D触发器功能，因此，图12所示的触发器的功耗为7*2+5＝19门，具有较低的功耗和占用面积。
需要说明的是，图12中仅通过控制FEFET的栅极和漏极之间的电压改变FEFET的阈值电压为例，实际上也可以通过控制FEFET的栅极和漏极之间的电压改变FEFET的阈值电压(如图13所示，FEFET的栅极和漏极之间通过反相器2和NMOS管T15连接，T15的控制端与时钟信号连接)，或者还可以同时通过控制FEFET的栅极和源极之间的电压、以及FEFET的栅极和漏极之间的电压，来改变FEFET的阈值电压(如图14所示，FEFET的栅极和源极之间通过反相器1和T2连接，FEFET的栅极和漏极之间通过反相器2和T15连接，T2和T15的控制端与时钟信号连接)，图13和图14所示的触发器的工作原理与图12所示的触发器的工作原理类似，在此不再赘述。
还需要说明的是，若同时通过控制FEFET的栅极和源极之间的电压、以及FEFET的栅极和漏极之间的电压来改变FEFET的阈值电压，除了可以如图14所示的通过反相器1和T2连接T1与源极、通过反相器2和T15连接T1与漏极，还可以在通过反相器1和T2连接T1与FEFET的源极的基础上、或通过反相器2和T15连接T1与FEFET的漏极的基础上，将FEFET的源极和漏极通过一个NMOS管连接，该NMOS管在数据写入阶段导通，在数据传递(或读出)阶段关断。
示例4
图15是本申请提供的触发器的另一个示例。图15所示的触发器与图10所示的触发器类似，不同的是，图15所示的触发器增加了数据召回功能。
对于示例1至示例3所示的触发器，由于使用了非易失性器件FEFET来保存数据信息，因此可以实现掉电保存数据。但是若重新上电时，时钟信号先为高电平再为低电平， 那么掉电时保存在FEFET中的数据信息就有可能被改写。为了避免由此带来的误操作，示例4所示的触发器增加了用于召回数据的NMOS管T11，T11设置在T7的控制端与GND之间，T11的控制端连接召回信号(recall，RC)，并且时钟信号(图15中的CLK1)为由图16所示的时钟信号生成电路生成的时钟信号。其中，T11可以为小尺寸管。
图16是本申请的一种可能的时钟信号生成电路的示意图。如图16所示，该时钟信号生成电路包括NMOS管T13和传输门T14，其中，T13的控制端连接召回信号，T14的控制端连接BL(block)和
Figure PCTCN2021140352-appb-000001
T13在召回信号为高电平时导通，在召回信号为低电平时关断，T14在BL为高电平时导通，在BL为低电平时关断。本申请对于时钟信号生成电路的形式不作具体限定，只要可以使得第一时钟信号在数据召回时为低电平即可。
图17是带有数据召回功能的触发器的时序控制图。如图17所示，在正常情况下，召回信号RC为低电平，BL为高电平，这样T13所在通路是断开的，T14所在通路是联通的，时钟信号生成电路输出时钟信号CLK2；在掉电的情况下，时钟信号生成电路无信号输出；在上电时(或称数据召回阶段)，RC为高电平，BL为低电平，这样T13所在通路是连通的，T14所在通路是断开的，时钟信号生成电路输出低电平。这样，可以保证在上电时时钟信号为低电平，避免掉电时保存在FEFET中的数据信息被改写。
下面对图15所示的触发器的数据召回功能的工作原理进行描述。
1)在正常情况下，RC为低电平，T11关断，图15所示的触发器的工作原理与示例1相同，不再赘述。
2)若电路发生掉电，FEFET最后的状态被存储了起来，如果D＝0，FEFET的阈值电压为低，表现为低阻态，如果D＝1，FEFET的阈值电压为高，表现为高阻态。
3)上电时，RC为高电平，CLK1为低电平，则T1、T2和T6关断，T3-T5、T9、T11导通。若D＝1，FEFET的阈值电压为高，则FEFET关断，则A点被下拉到低电平，使得T7关断，T8导通，Cs被充电至高电平，信号输出端的电压为高电平，即传递给信号输出端的数据即为存储的数据1；若D＝0，FEFET的阈值电压为低，则FEFET导通，虽然T11和FEFET同时导通，但是由于FEFET的驱动能力强，因此A点仍被充电到高电平，使得T7导通，T8关断，Cs被放电至GND，信号输出端的电压为低电平，即传递给信号输出端的数据即为存储的数据0。这样，一个脉冲信号RC即可将存储在FEFET中的数据信号读出。
需要说明的是，在一些实现方式中，图16所示的时钟信号生成电路不需要每个触发器配备一个，需要同时控制的一组触发器配备一个即可，即该时钟信号生成电路可以是多个触发器共享的，这样，增加图16所示的时钟信号生成电路不会给触发器单元引入过多的功耗。并且，考虑到不会持续进行数据召回，因此图15所示的触发器的功耗可以认为仍为是19门。
图15所示的触发器除了可以应用于集体掉电的场景，在多线程、多核处理器场景中，通过图15所示的触发器，可以实现将暂时不用的线程或核里的寄存器下电，待下次使用时再集体召，有助于节省功耗。图15所示的触发器可以用于逻辑电路、SRAM电路、触发器等单元的数据备份。
还需要说明的是，图15仅以在图10所示的触发器的基础上增加数据召回功能为例，实际上数据召回功能可以应用于本申请提供的任意一种触发器上，本申请对此不予限制。
还需要说明的是，若可以很好地控制时钟信号在上电的时候先维持一段时间的低电平，再变为高电平，则本申请的触发器在不设置T11管和时钟生成电路的情况下也可以实现存储在FEFET中的数据信号的召回。
示例5
图18是本申请提供的触发器的另一个示例。图18所示的触发器与图10所示的触发器类似，不同的是，图18所示的触发器增加了电平恢复功能，以便维持信号输出端的高电平。
如图18所示，在信号输出端与V DD之间增加了电平恢复电路，电平恢复电路包括PMOS管T12和反相器3，其中，信号输出端通过T12连接至V DD，通过反相器3与T12的控制端连接。
下面对图18所示的电平恢复电路的工作原理进行描述。
若信号输出端输出高电平，但是由于C S电荷发生泄露(例如，C S比较小时)，导致信号输出端的电压降低，信号输出端的高电平经过反相器3变为低电平，使得T12导通，实现C S的充电，从而使得信号输出端维持高电平。
若信号输出端输出低电平，则表明FEFET导通为A点充电，进而T7导通，T7导通会将C S放电至低电平，使得T12关断，电平恢复电路不起作用。
需要说明的是，图18仅以在图10所示的触发器的基础上增加电平恢复功能为例，实际上电平恢复功能可以应用于本申请提供的任意一种触发器上，本申请对此不予限制。
在本申请中，上述各个示例中对于电路的划分均为了方便描述，实际上，本申请实施例并不限定电路的具体划分形式。例如，T6也可以被划分在写入电路。又例如，T10也可以被划分到写入电路。又例如，电平恢复电路也可以被划分到输出电路等。
示例6
示例1至示例5中均以P型FEFET为例进行说明，实际上，本申请的触发器同样可以采用N型FEFET来实现。
图19是本申请提供的触发器的另一个示例。如图19所示，触发器包括：N型FEFET、写入电路、读出电路、以及输出电路，在图19中将FEFET作为3端器件使用。
1)写入电路
写入电路包括信号输入端、NMOS管T1-T2、以及反相器1。信号输入端通过T1与FEFET的栅极连接，并且通过T1、反相器1和T2连接至FEFET的漏极。T1和T2的控制端连接时钟信号。
2)读出电路
读出电路包括PMOS管T3，T3的控制端连接时钟信号。FEFET的栅极通过T3连接至V R，源极通过连接至GND。其中，如果T3为耗尽型晶体管，则V R可以等于0，即FEFET的栅极通过T3连接至GND；如果T3是增强型晶体管，则V R为可使T3管导通，并且能够区分出FEFET的高低阻抗状态的电压。
3)输出电路
输出电路包括NMOS管T6、NMOS管T8、PMOS管T7、PMOS管T9-T10、以及电容C S。FEFET的漏极通过T10和T6连接至V DD，T7的控制端和T8的控制端分别通过T6连接至V DD，信号输出端通过C S连接至GND、通过T7连接至V DD、以及通过T9和 T8连接至GND，T6的控制端连接至V DD，T9的控制端连接时钟信号。其中，T6可以为小尺寸管。
4)NMOS管T11
T11用于在触发器上电时召回数据，T11设置在T7的控制端与V DD之间，T11的控制端连接召回信号RC，并且时钟信号(图19中的CLK1)为由图16所示的时钟信号生成电路生成的时钟信号。其中，T11可以为小尺寸管。需要说明的是，若不需要数据召回功能，触发器可以不包括T11，或者T11不工作。
下面对图19所示的触发器的工作原理进行描述。
1)数据写入阶段
当时钟信号CLK1为高电平时，T1和T2导通，T3、T9和T10关断，T6持续导通，则A点被充电至高电平，使得T7关断、T8导通，C S保存原来数据，即信号输出端保持输出上一次数据写入过程中写入的数据。
此时，若D＝1，则FEFET的栅极的电压为1，漏极的电压为0，FEFET的阈值电压V T为低，在数据传递(或读出)阶段表现为低阻抗；若D＝0，则FEFET的栅极的电压为0，衬底的电压为1，FEFET的阈值电压V T为高，在数据传递(或读出)阶段表现为高阻抗。
2)数据传递(或读出)阶段
当CLK1由高变为低电平或CLK1为低电平时，T1和T2关断，T3、T6、T9和T10导通，FEFET的栅极的电压为V R，FEFET的源极的电压为GND，FEFET的栅极和源极之间的电压V GS＝V R。
此时，若在数据写入阶段D＝1，FEFET的V T为低，则FEFET导通，由于T6是小尺寸管，A点仍然放电至低电平，使得T8关断、以及T7导通，从而为C S充电，信号输出端输出1；若在数据写入阶段D＝0，FEFET的V T为高，则FEFET不导通，A点电位依然使T8导通、T7关断，C S放电，从而将信号输出端的电压下拉为低电平，C S放电，信号输出端输出0。
这样，经过一个完整的时钟周期，触发器将信号输入端的数据信号D传递到了信号输出端，并保持到下一次完成数据写入。
此外，图19所示的触发器的数据召回功能的工作原理与图15所示的触发器类似，可以参考图15的相关描述，在此不再赘述。
为了获得更高的极化偏置电压，T1和T2还可以被替换为传输门，以便无损的将数据信号传递到FEFET的栅极和漏极。
图19所示的触发器只需要11个MOS管和1个FEFET即可实现D触发器功能和数据召回功能，因此，图19所示的触发器具有较低的功耗和占用面积。
需要说明的是，图19仅是采用N型FEFET实现本申请的触发器的一个示例，实际上可以有更多的实现方式。例如，还可以通过控制FEFET的栅极和源极之间的电压和/或栅极与衬底之间的电压来控制FEFET的阈值电压，还可以具有如图18所示的电平恢复电路，还可以在FEFET的源极于GND之间设置开关器件T4，T4在CLK1为高电平时关断、以及在CLK1为低电平时导通，还可以不设置用于召回数据的T11等等。
此外，本申请还提供了一种电子装置，所述电子装置包括至少一个上文描述的任意一 种可能的触发器。所述电子设备可以是芯片、片上系统(system on chip，SOC)、集成电路、数字电路、时序电路、CPU、处理器、手机、电脑、路由器、交换机、IoT产品、终端、网络设备、计算机、空调、冰箱、打印机、或传真机等任何需要D触发器或者非易失性D触发器的产品。
需要说明的是，在本申请的实施例中，当一器件与另一器件“连接”，可以是直接与另一器件连接，或者两者之间也可以存在居中的器件。“连接”也可以替换为“电连接”、“耦合”等，不予限制。
除非另有说明，本申请实施例所使用的所有技术和科学术语与本申请的技术领域的技术人员通常理解的含义相同。本申请中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请的范围。应理解，上述为举例说明，上文的例子仅仅是为了帮助本领域技术人员理解本申请实施例，而非要将申请实施例限制于所示例的具体数值或具体场景。本领域技术人员根据上文所给出的例子，显然可以进行各种等价的修改或变化，这样的修改和变化也落入本申请实施例的范围内。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种数字电路，其特征在于，包括：控制电路和第一器件，所述控制电路包括输入端、第一输出端和时钟控制端，所述时钟控制端与第一时钟信号连接，所述控制电路用于：
    当所述第一时钟信号为第一状态时，根据所述输入端接收的第一信号，控制所述第一器件的阈值电压，所述第一信号的不同状态对应于所述第一器件的不同阈值电压；
    当所述第一时钟信号由第一状态变为第二状态，根据所述第一器件的阈值电压，控制所述第一器件的通断状态，以及根据所述第一器件的通断状态，输出第三信号，所述第三信号为与所述第一信号相关的信号。
  2. 根据权利要求1所述的数字电路，其特征在于，
    所述控制电路还用于：
    在所述第一时钟信号为第一状态时通过所述第一输出端输出第二信号，所述第二信号为上一次所述第一时钟信号由第一状态变为第二状态后所述第一输出端输出的信号。
  3. 根据权利要求1或2所述的数字电路，其特征在于，
    所述第一信号的第一状态对应于所述阈值电压的第一状态，所述阈值电压的第一状态对应于所述第三信号的第一状态；
    所述第一信号的第二状态对应于所述阈值电压的第二状态，所述阈值电压的第二状态对应于所述第三信号的第二状态。
  4. 根据权利要求1至3中任一项所述的数字电路，其特征在于，所述第一器件包括栅极、源极和漏极，所述通断状态为所述第一器件的源极和漏极之间的通断状态。
  5. 根据权利要求4所述的数字电路，其特征在于，所述第一器件还包括衬底；
    所述控制电路具体用于：
    通过控制所述栅极与所述源极之间的电压、所述栅极与所述漏极之间的电压、以及所述栅极与所述衬底之间的电压中的至少一个，控制所述阈值电压。
  6. 根据权利要求5所述的数字电路，其特征在于，
    当所述第一时钟信号为第一状态时，所述栅极的电平与所述源极的电平相反，和/或，所述栅极的电平与所述漏极的电平相反，和/或，所述栅极的电平与所述衬底的电平相反。
  7. 根据权利要求6所述的数字电路，其特征在于，
    所述控制电路包括第一开关器件和反相电路；
    所述输入端通过所述第一开关器件与所述栅极连接，所述输入端通过所述第一开关器件和所述反相电路与所述源极、所述漏极和所述衬底中的至少一个连接，所述第一开关器件的控制端与所述第一时钟信号连接，所述反相电路用于对所述第一信号进行反相处理；
    当所述第一时钟信号为第一状态时，所述第一开关器件导通，所述第一信号输入所述栅极、以及经过所述反相电路的反向处理后输入所述源极、所述漏极和所述衬底中的至少一个，以便控制所述第一器件的阈值电压；
    当所述第一时钟信号为第二状态时，所述第一开关器件关断。
  8. 根据权利要求7所述的数字电路，其特征在于，所述反相电路包括至少一个第一反相器。
  9. 根据权利要求8所述的数字电路，其特征在于，所述反相电路还包括至少一个第二开关器件，所述至少一个第一反相器与所述至少一个第二开关器件一一对应，所述第二开关器件的控制端与所述第一时钟信号连接，所述第二开关器件在所述第一时钟信号为第一状态时导通，以及在所述第一时钟信号为第二状态时关断。
  10. 根据权利要求4至9中任一项所述的数字电路，其特征在于，
    所述控制电路包括第三开关器件，所述第三开关器件的控制端与所述第一时钟信号连接，所述栅极通过所述第三开关器件与第一电压连接，所述源极与第二电压连接；
    当所述第一时钟信号为第一状态时，所述第三开关器件关断；
    当所述第一时钟信号为第二状态时，所述第三开关器件导通，所述栅极的电压为所述第一电压，所述源极的电压为所述第二电压；
    若所述第一电压、所述第二电压和所述阈值电压满足导通条件，所述第一器件管导通；
    若所述第一电压、所述第二电压和所述阈值电压不满足所述导通条件，所述第一器件关断。
  11. 根据权利要求10所述的数字电路，其特征在于，
    所述控制电路还包括第四开关器件，所述第四开关器件的控制端与所述第一时钟信号连接，所述源极通过所述第四开关器件与所述第二电压连接；
    当所述第一时钟信号为第一状态时，所述第四开关器件关断；
    当所述第一时钟信号为第二状态时，所述第四开关器件导通。
  12. 根据权利要求10或11所述的数字电路，其特征在于，
    所述控制电路还包括第五开关器件，所述第五开关器件的控制端与所述第一时钟信号连接，所述衬底通过所述第五开关器件与所述第二电压连接；
    当所述第一时钟信号为第一状态时，所述第五开关器件关断；
    当所述第一时钟信号为第二状态时，所述第五开关器件导通。
  13. 根据权利要求4至12中任一项所述的数字电路，其特征在于，
    若所述第一器件导通，则所述第一输出端与第三电压之间的电路导通；
    若所述第一器件关断，则所述第一输出端与第二电压之间的电路导通。
  14. 根据权利要求13所述的数字电路，其特征在于，
    所述控制电路包括第六开关器件、第七开关器件、第八开关器件、第九开关器件和储能器件，其中，所述漏极通过所述第六开关器件与所述第三电压连接，所述第一输出端通过所述储能器件与所述第三电压连接、通过所述第七开关器件与所述第三电压连接、以及通过所述第八开关器件和所述第九开关器件与第二电压连接，所述第七开关器件的控制端、所述第八开关器件的控制端通过所述第六开关器件与所述第三电压连接，所述第六开关器件的控制端和所述第九开关器件的控制端与所述第一时钟信号连接，所述第二电压对应于高电平，所述第三电压对应于低电平；
    当所述第一时钟信号为第一状态时，所述第九开关器件关断，所述第六开关器件导通，使得所述第七开关器件关断，所述第八开关器件导通，所述第一输出端输出所述第二信号；
    当所述第一时钟信号为第二状态时，所述第九开关器件导通，所述第六开关器件关断；
    若所述第一器件导通，则所述第七开关器件导通，所述第八开关器件关断，使得所述第一输出端的电压为所述第三电压、以及所述储能器件放电；
    若所述第一器件关断，则所述第七开关器件关断，所述第八开关器件导通，使得所述第一输出端的电压为所述第二电压、以及为所述储能器件充电。
  15. 根据权利要求14所述的数字电路，其特征在于，所述漏极与所述第六开关器件之间还包括第十开关器件，所述第十开关器件的控制端与所述第一时钟信号连接，所述第十开关器件在所述第一时钟信号为第一状态时关断、以及在所述第一时钟信号为第二状态时导通。
  16. 根据权利要求13所述的数字电路，其特征在于，
    所述控制电路包括第六开关器件、第七开关器件、第八开关器件、第九开关器件、第十开关器件和储能器件，所述漏极通过所述第六开关器件和所述第十开关器件与第三电压连接，所述第一输出端通过所述储能器件与第二电压连接、通过所述第七开关器件与所述第三电压连接、以及通过所述第八开关器件和所述第九开关器件与所述第二电压连接，所述第七开关器件的控制端和所述第八开关器件的控制端通过所述第六开关器件与所述第三电压连接，所述第六开关器件的控制端与所述第三电压连接，所述第九开关器件的控制端与所述第一时钟信号连接，所述第二电压对应于低电平，所述第三电压对应于高电平；
    当所述第一时钟信号为第一状态时，所述第九开关器件关断，所述第六开关器件导通，使得所述第七开关器件关断，所述第八开关器件导通，所述第一输出端输出所述第二信号；
    当所述第一时钟信号为第二状态时，所述第九开关器件导通；
    若所述第一器件导通，则所述第七开关器件导通，所述第八开关器件关断，使得所述第一输出端的电压为所述第三电压、以及为所述储能器件充电；
    若所述第一器件关断，则所述第七开关器件关断，所述第八开关器件导通，使得所述第一输出端的电压为所述第二电压、以及所述储能器件放电。
  17. 根据权利要求14至16中任一项所述的数字电路，其特征在于，所述储能器件为电容。
  18. 根据权利要求14至17中任一项所述的数字电路，其特征在于，
    所述控制电路还包括第十一开关器件；
    所述第七开关器件的控制端通过所述第十一开关器件与所述第三电压连接；
    在所述数字电路上电时，所述第一时钟信号为第二状态，所述第十一开关器件导通。
  19. 根据权利要求18所述的数字电路，其特征在于，所述控制电路还包括时钟信号生成电路，用于生成所述第一时钟信号；
    所述时钟信号生成电路具体包括第二输出端、第十三开关器件和第十四开关器件，所述第二输出端用于输出所述第一时钟信号，所述第十三开关器件的控制端连接第三信号，所述第十三开关器件的第一端接地，所述第十四开关器件的控制端连接第四信号，所述第十四开关器件的第一端连接第二时钟信号，所述第十三开关器件的第二端和所述第十四开关器件的第二端连接所述第二输出端，所述第十三开关器件在所述第三信号为第一状态时导通、以及在所述第三信号为第二状态时关断，所述第十四开关器件在所述第四信号为第二状态时导通、以及在所述第四信号为第一状态时关断；
    所述第三信号在第一时间段内为第一状态，所述第四信号在第二时间段内为第一状态，所述第一时间段和所述第二时间段的起始时刻为所述数字电路上电的时刻，所述第一时间段的时长小于或者等于所述第二时间段的时长。
  20. 根据权利要求14至19中任一项所述的数字电路，其特征在于，
    所述控制电路还包括电平恢复电路；
    所述电平恢复电路用于在所述第一信号为高电平的情况下，在下一次所述第一时钟信号由第一状态变为第二状态之前，控制所述第一输出端维持高电平。
  21. 根据权利要求20所述的数字电路，其特征在于，
    所述电平恢复电路包括第十二开关器件和第二反相器；
    所述第一输出端通过所述第十二开关器件与所述第二电压连接，所述第二电压对应于高电平；或者，所述第一输出端通过所述第十二开关器件与所述第三电压连接，所述第三电压对应于高电平；
    所述第一输出端通过所述第二反相器与所述第十二开关器件的控制端连接。
  22. 根据权利要求1至21中任一项所述的数字电路，其特征在于，
    所述第一时钟信号的第一状态为高电平，所述第一时钟信号的第二状态为低电平；或者，
    所述第一时钟信号的第一状态为低电平，所述第一时钟信号的第二状态为高电平。
  23. 根据权利要求1至22中任一项所述的数字电路，其特征在于，所述第一器件为铁电场效应晶体管。
  24. 根据权利要求1至23中任一项所述的数字电路，其特征在于，所述数字电路为D触发器。
  25. 一种电子装置，其特征在于，包括如权利要求1至24中任选一项所述的数字电路。
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Citations (4)

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Publication number Priority date Publication date Assignee Title
CN202357595U (zh) * 2011-11-24 2012-08-01 珠海天威技术开发有限公司 时钟信号延时电路及芯片
CN110164352A (zh) * 2019-04-28 2019-08-23 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路和显示面板
US20190355433A1 (en) * 2018-01-02 2019-11-21 Chongqing Boe Optoelectronics Technology Co., Ltd. Shift register unit, gate drive circuit, display device and drive method
CN111162785A (zh) * 2020-01-15 2020-05-15 广东药科大学 一种模数转换器时分复用采样电路及方法

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CN202357595U (zh) * 2011-11-24 2012-08-01 珠海天威技术开发有限公司 时钟信号延时电路及芯片
US20190355433A1 (en) * 2018-01-02 2019-11-21 Chongqing Boe Optoelectronics Technology Co., Ltd. Shift register unit, gate drive circuit, display device and drive method
CN110164352A (zh) * 2019-04-28 2019-08-23 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路和显示面板
CN111162785A (zh) * 2020-01-15 2020-05-15 广东药科大学 一种模数转换器时分复用采样电路及方法

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