WO2022183474A1 - 共振隧穿二极管及其制作方法 - Google Patents

共振隧穿二极管及其制作方法 Download PDF

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WO2022183474A1
WO2022183474A1 PCT/CN2021/079264 CN2021079264W WO2022183474A1 WO 2022183474 A1 WO2022183474 A1 WO 2022183474A1 CN 2021079264 W CN2021079264 W CN 2021079264W WO 2022183474 A1 WO2022183474 A1 WO 2022183474A1
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barrier layer
layer
resonant tunneling
potential well
tunneling diode
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PCT/CN2021/079264
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English (en)
French (fr)
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程凯
刘凯
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苏州晶湛半导体有限公司
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Priority to CN202180094220.3A priority Critical patent/CN116868352A/zh
Priority to PCT/CN2021/079264 priority patent/WO2022183474A1/zh
Priority to US17/788,967 priority patent/US20230290892A1/en
Publication of WO2022183474A1 publication Critical patent/WO2022183474A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/88—Tunnel-effect diodes
    • H01L29/882—Resonant tunneling diodes, i.e. RTD, RTBD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66219—Diodes with a heterojunction, e.g. resonant tunneling diodes [RTD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a resonant tunneling diode and a manufacturing method thereof.
  • the resonant tunneling diode can generate negative differential resistance by using the resonant tunneling phenomenon to prepare a terahertz radiation source, which has received extensive attention.
  • GaN-based resonant tunneling diodes have the advantages of high electron rate, high breakdown field strength, large adjustable band gap, radiation resistance, etc. unique to group III nitride semiconductor materials, and are expected to achieve high terahertz at room temperature. power transmission.
  • the current nitride-based resonant tunneling diodes face problems such as poor device stability and low peak-to-valley current ratio, which greatly limit practical applications.
  • the purpose of the present invention is to provide a resonant tunneling diode and a manufacturing method thereof, which can improve device stability and peak-to-valley current ratio.
  • a first aspect of the present invention provides a resonant tunneling diode, comprising:
  • a first barrier layer, a second barrier layer and a potential well layer between the first barrier layer and the second barrier layer the material of the first barrier layer is Al x In y N 1-xy , 1>x>0, 1>y>0, and/or the material of the second barrier layer is Al m In n N 1-mn , 1>m>0, 1>n>0;
  • the material of the potential well layer contains Ga element.
  • the material of the potential well layer is at least one of InGaN, GaN, and AlInGaN.
  • the material of the first barrier layer is Al x In y N 1-xy , y ⁇ 45%, and/or the material of the second barrier layer is Al m In n N 1-mn , n ⁇ 45%.
  • the material of the first barrier layer is Al x In y N 1-xy , y ⁇ 30%; when the material of the second barrier layer is Al m In n N 1-mn , n ⁇ 30%.
  • a first isolation layer is provided between the first barrier layer and the potential well layer, and/or a second isolation layer is provided between the second barrier layer and the potential well layer .
  • the material of the first isolation layer and/or the second isolation layer is AlN.
  • the thickness of the first isolation layer ranges from 0.1 nm to 2 nm; and/or the thickness of the second isolation layer ranges from 0.1 nm to 2 nm.
  • the resonant tunneling diode further includes a collector and an emitter, the collector is close to the first barrier layer, and the emitter is close to the second barrier layer; the collector is connected to the second barrier layer.
  • a third isolation layer is provided between the first barrier layers, and/or a fourth isolation layer is provided between the emitter and the second barrier layer.
  • the materials of the collector and the emitter are GaN-based materials.
  • the material of the third isolation layer and/or the fourth isolation layer is AlN.
  • a second aspect of the present invention provides a method for fabricating a resonant tunneling diode, comprising:
  • the material of the first barrier layer is Al x In y N 1-xy , 1>x>0, 1>y>0, and /or the material of the second barrier layer is Al m In n N 1-mn , 1>m>0, 1>n>0; the material of the potential well layer contains Ga element.
  • the material of the potential well layer is at least one of InGaN, GaN, and AlInGaN.
  • the material of the first barrier layer is Al x In y N 1-xy , y ⁇ 30%, and/or the material of the second barrier layer is Al m In n N 1-mn , n ⁇ 30%.
  • the epitaxial growth temperature range of the first barrier layer is 600° C. ⁇ 900° C.
  • the temperature range of the epitaxial growth of the second barrier layer is 600° C. ⁇ 900° C.
  • the method for fabricating the resonant tunneling diode further includes: before epitaxially growing the potential well layer, epitaxially growing a first isolation layer on the first potential barrier layer; and/or epitaxially growing the second isolation layer Before the barrier layer, a second isolation layer is epitaxially grown on the well layer.
  • the collector electrode is epitaxially grown on the side of the first barrier layer away from the potential well layer, or the collector electrode is epitaxially grown before the first barrier layer is epitaxially grown;
  • the emitter is epitaxially grown on a side of the barrier layer away from the potential well layer.
  • the method for fabricating the resonant tunneling diode further includes: before the collector electrode is epitaxially grown on the side of the first barrier layer that is far away from the potential well layer, before the first potential barrier layer is far away from the potential well layer. epitaxially growing a third isolation layer on one side of the potential well layer; or after epitaxially growing the collector, and before the first potential barrier layer, epitaxially growing a third isolation layer;
  • the materials of the collector and the emitter are GaN-based materials.
  • the material of the first isolation layer and/or the second isolation layer is AlN.
  • the thickness of the first isolation layer ranges from 0.1 nm to 2 nm; and/or the thickness of the second isolation layer ranges from 0.1 nm to 2 nm.
  • In-containing AlN material as the first barrier layer and/or the second barrier layer correspondingly reduces the growth temperature of the first barrier layer and the second barrier layer, thereby avoiding high-temperature processes. Avoiding high temperature process can prevent Ga atoms in the well layer from diffusing to the first barrier layer and the second barrier layer caused by high temperature, ensure the uniform composition of the first barrier layer and the second barrier layer, and prevent the effective thickness from becoming thinner , thereby improving device stability and peak-to-valley current ratio.
  • the first isolation layer and the second isolation layer are used to prevent the Ga atoms in the well layer from diffusing to the first and second barrier layers, so as to ensure that the compositions of the first and second barrier layers are uniform. , Prevent the effective thickness from thinning, thereby improving device stability and peak-to-valley current ratio.
  • FIG. 1 is a flowchart of a method for manufacturing a resonant tunneling diode according to a first embodiment of the present invention
  • Fig. 2 is the intermediate structure schematic diagram corresponding to the process flow in Fig. 1;
  • FIG. 3 is a schematic cross-sectional structure diagram of the resonant tunneling diode according to the first embodiment of the present invention.
  • FIG. 4 is a flowchart of a method for manufacturing a resonant tunneling diode according to a second embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional structure diagram of a resonant tunneling diode according to a third embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram of a resonant tunneling diode according to a fourth embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional structure diagram of a resonant tunneling diode according to a fifth embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional structural diagram of a resonant tunneling diode according to a sixth embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional structure diagram of a resonant tunneling diode according to a seventh embodiment of the present invention.
  • the first barrier layer 11 The second barrier layer 12
  • the second isolation layer 15 The third isolation layer 16
  • FIG. 1 is a flowchart of a method for fabricating a resonant tunneling diode according to a first embodiment of the present invention
  • FIG. 2 is a schematic diagram of an intermediate structure corresponding to the process in FIG. 1
  • 3 is a schematic cross-sectional structural diagram of a resonant tunneling diode according to the first embodiment of the present invention.
  • the first barrier layer 11 , the potential well layer 13 and the second barrier layer 12 are epitaxially grown in sequence.
  • the material of the potential well layer 13 includes Ga element, the second potential
  • the material of the barrier layer 12 is Al m In n N 1-mn , 1>m>0, 1>n>0.
  • the first barrier layer 11 may be epitaxially grown on the substrate 10 .
  • the material of the substrate 10 may include: at least one of sapphire, silicon carbide, silicon and SOI substrates, or at least one of sapphire, silicon carbide, silicon and SOI substrates and group III nitride materials thereon, Or a group III nitride epitaxial layer in an integrated device, which is not limited in this embodiment.
  • the epitaxial growth process of the first barrier layer 11, the potential well layer 13 and the second barrier layer 12 may include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), Or Molecular Beam Epitaxy (MBE, Molecular Beam Epitaxy), or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or metal Organic Compound Chemical Vapor Deposition (MOCVD, Metal-organic Chemical Vapor Deposition), or a combination thereof.
  • ALD Atomic layer deposition
  • CVD Chemical Vapor Deposition
  • MBE Molecular Beam Epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal-organic Chemical Vapor Deposition
  • the material of the first barrier layer 11 is AlGaN, and the epitaxial growth temperature of the first barrier layer 11 is in the range of 900°C to 1300°C when MOCVD is used for epitaxial growth.
  • a certain material is represented by a chemical element, but the molar ratio of each chemical element in the material is not limited.
  • the AlGaN material contains three elements of Al, Ga, and N, but the respective mass percentages are not limited.
  • the forbidden band width of the well layer 13 is smaller than that of the first barrier layer 11 .
  • the material of the potential well layer 13 is GaN, and the forbidden band width is 3.4 eV.
  • the epitaxial growth temperature of the potential well layer 13 is in the range of 800°C to 1200°C.
  • the material of the second barrier layer 12 may be Al m In n N 1-mn , m is the percentage of the mass of the Al element to the sum of the mass of the Al element, the In element and the N element, and n is the mass of the In element in the Al element The percentage of the sum of the masses of , In and N elements.
  • the lower the epitaxial growth temperature of the second barrier layer 12 is, the more Ga atoms in the potential well layer 13 can be prevented from diffusing into the first barrier layer 11 and the second barrier layer 12 respectively.
  • the forbidden band width of the second barrier layer 12 is larger than that of the potential well layer 13 .
  • the forbidden band width of AlN is 6.2 eV, and the higher the In content in the AlInN material, the smaller the forbidden band width of the AlInN material.
  • n ⁇ 45% the second barrier layer 12 and the potential well layer 13 made of GaN can form a quantum well with higher tunneling efficiency.
  • MOCVD epitaxial growth when n ⁇ 45%, the epitaxial growth temperature range of the second barrier layer 12 is 600°C to 900°C; when 30% ⁇ n ⁇ 45%, the epitaxial growth temperature range of the second barrier layer 12 is 600° C. ⁇ 800° C.; when n ⁇ 30%, the temperature range of the epitaxial growth of the second barrier layer 12 is 700° C. ⁇ 900° C.
  • the material of the potential well layer 13 is InGaN or AlInGaN, and the forbidden band width of InGaN ranges from 0.7eV to 3.4eV.
  • the forbidden band width of AlInGaN ranges from 0.7eV to 6.2eV.
  • the material of the second barrier layer 12 is Al m In n N 1-mn , and n ⁇ 45%, and a quantum well with higher tunneling efficiency can also be formed with the potential well layer 13 of InGaN. Preferably, n ⁇ 30%.
  • the use of In-containing AlN material as the second barrier layer 12 can reduce the growth temperature of the second barrier layer 12, thereby avoiding high-temperature processes, thereby preventing Ga atoms in the potential well layer 13 from being caused by high temperature to the first barrier layer.
  • 11 and the second barrier layer 12 are diffused to ensure that the compositions of the first barrier layer 11 and the second barrier layer 12 are uniform and prevent the effective thickness from being thinned, thereby improving device stability and peak-to-valley current ratio.
  • the substrate 10 is removed.
  • the substrate 10 can be removed by a laser lift-off method or a chemical etching method.
  • the substrate 10 may not be removed. In other words, the substrate 10 remains in the resonant tunneling diode 1 .
  • the resonant tunneling diode 1 includes:
  • the first barrier layer 11 , the potential well layer 13 and the second barrier layer 12 form a double-barrier quantum well structure.
  • the forbidden band width of the well layer 13 is smaller than that of the first barrier layer 11 and the second barrier layer 12 .
  • the material of the potential well layer 13 may be GaN.
  • the material of the second barrier layer 12 is Al m In n N 1-mn , and n ⁇ 45%, and can form a quantum well with higher tunneling efficiency with the potential well layer 13 of GaN material. Preferably, n ⁇ 30%.
  • the material of the potential well layer 13 is InGaN or AlInGaN.
  • the material of the second barrier layer 12 is Al m In n N 1-mn , and n ⁇ 45%, and can form a quantum well with higher tunneling efficiency with the potential well layer 13 of InGaN. Preferably, n ⁇ 30%.
  • FIG. 4 is a flowchart of a method for fabricating a resonant tunneling diode according to a second embodiment of the present invention.
  • the resonant tunneling diode of the second embodiment and the fabrication method thereof are substantially the same as the resonant tunneling diode 1 of the first embodiment and the fabrication method thereof, the only difference being that: step S1 ′ is performed on the substrate 10 in sequence.
  • the second barrier layer 12 , the potential well layer 13 and the first barrier layer 11 are epitaxially grown.
  • the material of the potential well layer 13 contains Ga element, and the material of the first barrier layer 11 is Al x In y N 1-xy , 1 >x>0, 1>y>0.
  • the material of the second barrier layer 12 may be AlGaN.
  • the material of the potential well layer 13 may be at least one of InGaN, GaN, and AlInGaN.
  • the material of the first barrier layer 11 is Al x In y N 1-xy , x is the percentage of the mass of the Al element in the sum of the mass of the Al element, the In element and the N element, y is the mass of the In element in the Al element, The percentage of the sum of the masses of In and N elements.
  • the lower the epitaxial growth temperature of the first barrier layer 11 is, the more Ga atoms in the well layer 13 can be prevented from diffusing into the first barrier layer 11 and the second barrier layer 12 respectively.
  • the first barrier layer 11 and the potential well layer 13 made of GaN can form a quantum well with higher tunneling efficiency.
  • the epitaxial growth temperature range of the first barrier layer 11 is 600°C to 900°C; when 30% ⁇ y ⁇ 45%, the epitaxial growth temperature range of the first barrier layer 11 is 600° C. ⁇ 800° C.; when y ⁇ 30%, the temperature range of the epitaxial growth of the first barrier layer 11 is 700° C. ⁇ 900° C.
  • y ⁇ 30% the epitaxial growth temperature of the first barrier layer 11 is 700° C. ⁇ 900° C.
  • the use of In-containing AlN material as the first barrier layer 11 can reduce the growth temperature of the first barrier layer 11 , thereby avoiding high-temperature processes, thereby avoiding high temperature causing Ga atoms in the well layer 13 to move toward the first barrier layer respectively.
  • 11 and the second barrier layer 12 are diffused to ensure that the compositions of the first barrier layer 11 and the second barrier layer 12 are uniform and prevent the effective thickness from being thinned, thereby improving device stability and peak-to-valley current ratio.
  • the material of the first barrier layer 11 is AlxInyN1 -xy , 1>x>0, 1>y>0.
  • the material of the potential well layer 13 may be GaN.
  • the material of the first barrier layer 11 is AlxInyN1 -xy , y ⁇ 45%, and a quantum well with higher tunneling efficiency can be formed with the potential well layer 13 of GaN. Preferably, y ⁇ 30%.
  • the material of the potential well layer 13 is InGaN or AlInGaN.
  • the material of the first barrier layer 11 is AlxInyN1 -xy , y ⁇ 45%, and can form a quantum well with higher tunneling efficiency with the potential well layer 13 of InGaN. Preferably, y ⁇ 30%.
  • the material of the second barrier layer 12 epitaxially grown on the substrate 10 may be Al m In n N 1-mn , 1>m>0, 1>n>0; or on the substrate 10
  • the material of the epitaxially grown first barrier layer 11 is AlxInyN1 -xy , 1>x>0, 1>y>0.
  • FIG. 5 is a schematic cross-sectional structure diagram of a resonant tunneling diode according to a third embodiment of the present invention.
  • the resonant tunneling diode 2 of the third embodiment is substantially the same as the resonant tunneling diode 1 of the first and second embodiments, the only difference being that a A second isolation layer 15 is provided between the first isolation layer 14 , the second barrier layer 12 and the potential well layer 13 .
  • the arrangement of the first isolation layer 14 can further block the diffusion of Ga atoms in the potential well layer 13 to the first barrier layer 11 , ensure that the composition of the first barrier layer 11 is uniform, and prevent the effective thickness from becoming thinner, thereby improving the resonance tunneling effect.
  • the material of the first isolation layer 14 may be AlN.
  • the thickness of the first isolation layer 14 may range from 0.1 nm to 2 nm.
  • the arrangement of the second isolation layer 15 can further prevent the Ga atoms in the well layer 13 from diffusing to the second barrier layer 12 , ensure the uniform composition of the second barrier layer 12 and prevent the effective thickness from becoming thinner, thereby improving the resonance tunneling effect.
  • the material of the second isolation layer 15 may be AlN.
  • the thickness of the second isolation layer 15 may range from 0.1 nm to 2 nm.
  • the fabrication method of the resonant tunneling diode 2 of the third embodiment is substantially the same as the fabrication method of the resonant tunneling diode 1 of the first and second embodiments, and the difference is only that: before the potential well layer 13 is epitaxially grown, the first potential A first isolation layer 14 is epitaxially grown on the barrier layer 11 ; before the second barrier layer 12 is epitaxially grown, a second isolation layer 15 is epitaxially grown on the well layer 13 .
  • the epitaxial growth process of the first isolation layer 14 and the second isolation layer 15 may refer to the epitaxial growth process of the first barrier layer 11 , the well layer 13 and the second barrier layer 12 .
  • FIG. 6 is a schematic cross-sectional structure diagram of a resonant tunneling diode according to a fourth embodiment of the present invention.
  • the resonant tunneling diode 3 of the fourth embodiment and the fabrication method thereof are substantially the same as the resonant tunneling diode 2 of the third embodiment and the fabrication method thereof, except that the second isolation layer 15 is omitted and the first Two steps of isolation layer 15 .
  • FIG. 7 is a schematic cross-sectional structure diagram of a resonant tunneling diode according to a fifth embodiment of the present invention.
  • the resonant tunneling diode 4 of the fifth embodiment and the fabrication method thereof are substantially the same as the resonant tunneling diode 2 of the third embodiment and the fabrication method thereof, except that the first isolation layer 14 is omitted and the first isolation layer 14 is omitted. an isolation layer 14 step.
  • FIG. 8 is a schematic cross-sectional structure diagram of a resonant tunneling diode according to a sixth embodiment of the present invention.
  • the resonant tunneling diode 5 of the sixth embodiment is substantially the same as the resonant tunneling diodes 1, 2, 3, and 4 of the first to fifth embodiments, and the difference is only that the collector 20 and the emitter 30 are also included,
  • the collector electrode 20 is close to the first barrier layer 11
  • the emitter electrode 30 is close to the second barrier layer 12 .
  • the materials of the collector electrode 20 and the emitter electrode 30 are group III nitrides, such as GaN-based materials, more specifically, GaN.
  • the fabrication method of this embodiment is substantially the same as the fabrication method of the previous embodiment, the only difference being that step S2 is performed after step S1 : the collector is epitaxially grown on the side of the first barrier layer 11 away from the potential well layer 13 . 20 , epitaxially growing the emitter 30 on the side of the second barrier layer 12 away from the potential well layer 13 .
  • the materials of the collector electrode 20 and the emitter electrode 30 are group III nitrides.
  • step S1 before epitaxially growing the first barrier layer 11, the collector electrode 20 is epitaxially grown on the substrate 10; and/or the liner is removed Performed before bottom 10 : emitter 30 is epitaxially grown on second barrier layer 12 .
  • the epitaxial growth process of the collector electrode 20 and the emitter electrode 30 may refer to the epitaxial growth process of the first barrier layer 11 , the potential well layer 13 and the second barrier layer 12 .
  • FIG. 9 is a schematic cross-sectional structure diagram of a resonant tunneling diode according to a seventh embodiment of the present invention.
  • the resonant tunneling diode 6 of the seventh embodiment is substantially the same as the resonant tunneling diode 5 of the sixth embodiment, except that a third isolation is provided between the collector electrode 20 and the first barrier layer 11 .
  • a fourth isolation layer 17 is provided between the layer 16 , the emitter 30 and the second barrier layer 12 .
  • the third isolation layer 16 can prevent Ga atoms in the collector electrode 20 from diffusing into the first barrier layer 11 .
  • the fourth isolation layer 17 can prevent Ga atoms in the emitter 30 from diffusing into the second barrier layer 12 .
  • the materials of the third isolation layer 16 and the fourth isolation layer 17 may be AlN.
  • the thickness of the third isolation layer 16 may range from 0.1 nm to 2 nm.
  • the thickness of the fourth isolation layer 17 may range from 0.1 nm to 2 nm.
  • the third isolation layer 16 and the fourth isolation layer 17 may alternatively be provided.
  • the fabrication method of this embodiment is substantially the same as the fabrication method of the previous embodiment, the only difference being that: in step S1: before the collector electrode 20 is epitaxially grown on the side of the first barrier layer 11 away from the potential well layer 13, a The third isolation layer 16 is epitaxially grown on the side of the first barrier layer 11 away from the potential well layer 13 ; or after the collector electrode 20 is epitaxially grown on the substrate 10 and before the first barrier layer 11 , the third isolation layer 16 is epitaxially grown ;
  • step S1 before epitaxially growing the emitter 30 on the side of the second barrier layer 12 away from the potential well layer 13, epitaxially growing a fourth isolation layer on the side of the second barrier layer 12 away from the potential well layer 13 17.
  • the epitaxial growth process of the third isolation layer 16 and the fourth isolation layer 17 may refer to the epitaxial growth process of the first isolation layer 14 and the second isolation layer 15 .

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Abstract

本申请提供了一种共振隧穿二极管及其制作方法，共振隧穿二极管包括：第一势垒层，第二势垒层以及位于第一势垒层与第二势垒层之间的势阱层，第一势垒层的材料为Al xIn yN 1-x-y，1>x>0，1>y>0，和/或第二势垒层的材料为Al mIn nN 1-m-n，1>m>0，1>n>0；势阱层的材料包含Ga元素。采用含In的AlN材料作为第一势垒层和/或第二势垒层，对应降低第一势垒层、第二势垒层的生长温度，从而避免高温制程。避免高温制程可避免高温引起势阱层中的Ga原子向第一势垒层与第二势垒层扩散，保证第一势垒层与第二势垒层的组分均一、防止有效厚度变薄，从而改善器件稳定性及峰谷电流比。

Description

共振隧穿二极管及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种共振隧穿二极管及其制作方法。
背景技术
太赫兹技术作为一门新兴的科学技术，在安全检测、物质识别、保密通讯、宇宙探测、高精度雷达、组织活检、瞬态光谱研究等方面具有重要的应用前景。共振隧穿二极管作为一种两端器件，能够利用共振隧穿现象产生负微分电阻从而用于制备太赫兹辐射源，得到了广泛的关注。
目前比较成熟的RTD技术主要是基于GaAs材料，由于材料固有的性能限制，目前功率只达到微瓦量级。而基于GaN的共振隧穿二极管，具有III族氮化物半导体材料所特有的高电子速率、高击穿场强、大禁带宽度可调范围、耐辐射等优点，有望实现室温下太赫兹的高功率发射。
然而，目前氮化物基共振隧穿二极管面临器件稳定性差，峰谷电流比低等难题，大大限制了实际应用。
发明内容
本发明的发明目的是提供一种共振隧穿二极管及其制作方法，改善器件稳定性及峰谷电流比。
为实现上述目的，本发明的第一方面提供一种共振隧穿二极管，包括：
第一势垒层，第二势垒层以及位于所述第一势垒层与所述第二势垒层 之间的势阱层，所述第一势垒层的材料为Al xIn yN 1-x-y，1>x>0，1>y>0，和/或所述第二势垒层的材料为Al mIn nN 1-m-n，1>m>0，1>n>0；所述势阱层的材料包含Ga元素。
可选地，所述势阱层的材料为InGaN、GaN、AlInGaN中的至少一种。
可选地，所述第一势垒层的材料为Al xIn yN 1-x-y，y≤45％，和/或所述第二势垒层的材料为Al mIn nN 1-m-n，n≤45％。
可选地，当所述第一势垒层的材料为Al xIn yN 1-x-y时，y≤30％；当所述第二势垒层的材料为Al mIn nN 1-m-n时，n≤30％。
可选地，所述第一势垒层与所述势阱层之间设置有第一隔离层，和/或所述第二势垒层与所述势阱层之间设置有第二隔离层。
可选地，所述第一隔离层和/或所述第二隔离层的材料为AlN。
可选地，所述第一隔离层的厚度范围为0.1nm～2nm；和/或所述第二隔离层的厚度范围为0.1nm～2nm。
可选地，所述共振隧穿二极管还包括集电极与发射极，所述集电极靠近所述第一势垒层，所述发射极靠近所述第二势垒层；所述集电极与所述第一势垒层之间设置有第三隔离层，和/或所述发射极与所述第二势垒层之间设置有第四隔离层。
可选地，所述集电极与所述发射极的材料为GaN基材料。
可选地，所述第三隔离层和/或所述第四隔离层的材料为AlN。
本发明的第二方面提供共振隧穿二极管的制作方法，包括：
外延生长第一势垒层、势阱层以及第二势垒层，所述第一势垒层的材料为Al xIn yN 1-x-y，1>x>0，1>y>0，和/或所述第二势垒层的材料为Al mIn nN 1-m-n，1>m>0，1>n>0；所述势阱层的材料包含Ga元素。
可选地，所述势阱层的材料为InGaN、GaN、AlInGaN中的至少一种。
可选地，所述第一势垒层的材料为Al xIn yN 1-x-y，y≤30％，和/或所述第二势垒层的材料为Al mIn nN 1-m-n，n≤30％。
可选地，当所述第一势垒层的材料为Al xIn yN 1-x-y时，所述第一势垒层的外延生长温度范围为600℃～900℃；当所述第二势垒层的材料为Al mIn nN 1-m-n时，所述第二势垒层的外延生长温度范围为600℃～900℃。
可选地，所述共振隧穿二极管的制作方法还包括：外延生长所述势阱层前，在所述第一势垒层上外延生长第一隔离层；和/或外延生长所述第二势垒层前，在所述势阱层上外延生长第二隔离层。
可选地，在所述第一势垒层远离所述势阱层的一侧外延生长集电极，或在外延生长所述第一势垒层前，先外延生长集电极；在所述第二势垒层远离所述势阱层的一侧外延生长发射极。
可选地，所述共振隧穿二极管的制作方法还包括：在所述第一势垒层远离所述势阱层的一侧外延生长集电极前，在所述第一势垒层远离所述势阱层的一侧外延生长第三隔离层；或外延生长集电极后，所述第一势垒层前，外延生长第三隔离层；
和/或在所述第二势垒层远离所述势阱层的一侧外延生长发射极前，在所述第二势垒层远离所述势阱层的一侧外延生长第四隔离层。
可选地，所述集电极与所述发射极的材料为GaN基材料。
可选地，所述第一隔离层和/或所述第二隔离层的材料为AlN。
可选地，所述第一隔离层的厚度范围为0.1nm～2nm；和/或所述第二隔离层的厚度范围为0.1nm～2nm。
与现有技术相比，本发明的有益效果在于：
采用含In的AlN材料作为第一势垒层和/或第二势垒层，对应降低第一势垒层、第二势垒层的生长温度，从而避免高温制程。避免高温制程可避免 高温引起势阱层中的Ga原子向第一势垒层与第二势垒层扩散，保证第一势垒层与第二势垒层的组分均一、防止有效厚度变薄，从而改善器件稳定性及峰谷电流比。
同时利用第一隔离层与第二隔离层，阻挡势阱层中的Ga原子向第一势垒层与第二势垒层扩散，保证第一势垒层与第二势垒层的组分均一、防止有效厚度变薄，从而改善器件稳定性及峰谷电流比。
附图说明
图1是本发明第一实施例的共振隧穿二极管的制作方法的流程图；
图2是图1中的流程对应的中间结构示意图；
图3是本发明第一实施例的共振隧穿二极管的截面结构示意图；
图4是本发明第二实施例的共振隧穿二极管的制作方法的流程图；
图5是本发明第三实施例的共振隧穿二极管的截面结构示意图；
图6是本发明第四实施例的共振隧穿二极管的截面结构示意图；
图7是本发明第五实施例的共振隧穿二极管的截面结构示意图；
图8是本发明第六实施例的共振隧穿二极管的截面结构示意图；
图9是本发明第七实施例的共振隧穿二极管的截面结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
共振隧穿二极管1、2、3、4、5、6     衬底10
第一势垒层11                       第二势垒层12
势阱层13                           第一隔离层14
第二隔离层15                       第三隔离层16
第四隔离层17                        集电极20
发射极30
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的共振隧穿二极管的制作方法的流程图；图2是图1中的流程对应的中间结构示意图。图3是本发明第一实施例的共振隧穿二极管的截面结构示意图。
首先，参照图1中的步骤S1与图2所示，依次外延生长第一势垒层11、势阱层13以及第二势垒层12，势阱层13的材料包含Ga元素，第二势垒层12的材料为Al mIn nN 1-m-n，1>m>0，1>n>0。
本实施例中，第一势垒层11可以在衬底10上外延生长。
衬底10的材料可以包括：蓝宝石、碳化硅、硅及SOI衬底中的至少一种，或蓝宝石、碳化硅、硅及SOI衬底中的至少一种及其上的Ⅲ族氮化物材料，或集成器件中的Ⅲ族氮化物外延层，本实施例对此不加以限制。
第一势垒层11、势阱层13以及第二势垒层12的外延生长工艺可以包括：原子层沉积法(ALD，Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法(MOCVD，Metal-organic Chemical Vapor Deposition)、或其组合方式。
一个可选方案中，第一势垒层11的材料为AlGaN，采用MOCVD外延 生长时，第一势垒层11的外延生长温度范围为900℃～1300℃。
需要说明的是，本实施例中，以化学元素代表某种材料，但不限定该材料中各化学元素的摩尔占比。例如AlGaN材料中，包含Al、Ga、N三种元素，但不限定各自的质量百分占比大小。
势阱层13的禁带宽度小于第一势垒层11的禁带宽度。
势阱层13的材料为GaN，禁带宽度为3.4eV。采用MOCVD外延生长时，势阱层13的外延生长温度范围为800℃～1200℃。
第二势垒层12的材料可以为Al mIn nN 1-m-n，m为Al元素的质量占Al元素、In元素以及N元素的质量之和的百分比，n为In元素的质量占Al元素、In元素以及N元素的质量之和的百分比。第二势垒层12的外延生长温度越高，n越小；外延生长温度越低，n越大。第二势垒层12的外延生长温度越低，越能避免势阱层13中的Ga原子分别向第一势垒层11与第二势垒层12扩散。
第二势垒层12的禁带宽度大于势阱层13的禁带宽度。
AlN的禁带宽度为6.2eV，AlInN材料中的In的含量越高，AlInN材料的禁带宽度越小。n≤45％，第二势垒层12可与材料为GaN的势阱层13形成隧穿效率较高的量子阱。采用MOCVD外延生长时，n≤45％时，第二势垒层12的外延生长温度范围为600℃～900℃；30％<n<45％时，第二势垒层12的外延生长温度范围为600℃～800℃；n≤30％时，第二势垒层12的外延生长温度范围为700℃～900℃。
然而，第二势垒层12的外延生长温度越低，晶格缺陷越多。因而，优选地，n≤30％。
另一个可选方案中，势阱层13的材料为InGaN或AlInGaN，InGaN的禁带宽度介于0.7eV～3.4eV。AlInGaN的禁带宽度介于0.7eV～6.2eV。第二势垒层12的材料为Al mIn nN 1-m-n，n≤45％，也可与材料为InGaN的势阱层13形成隧穿效率较高的量子阱。优选地，n≤30％。
采用含In的AlN材料作为第二势垒层12，可降低第二势垒层12的生长温度，从而避免高温制程，进而避免高温引起势阱层13中的Ga原子分别向第一势垒层11与第二势垒层12扩散，保证第一势垒层11与第二势垒层12的组分均一、防止有效厚度变薄，从而改善器件稳定性及峰谷电流比。
接着，参照图3所示，去除衬底10。
衬底10可以采用激光剥离法或化学腐蚀法去除。
一些实施例中，也可以不去除衬底10。换言之，衬底10保留在共振隧穿二极管1中。
参照图3所示，本发明第一实施例的共振隧穿二极管1包括：
第一势垒层11，第二势垒层12以及位于第一势垒层11与第二势垒层12之间的势阱层13，第一势垒层11的材料为AlGaN，势阱层13的材料包含Ga元素，第二势垒层12的材料为Al mIn nN 1-m-n，1>m>0，1>n>0。
第一势垒层11、势阱层13以及第二势垒层12形成了双势垒量子阱结构。势阱层13的禁带宽度小于第一势垒层11与第二势垒层12的禁带宽度。一个可选方案中，势阱层13的材料可以为GaN。第二势垒层12的材料为Al mIn nN 1-m-n，n≤45％，可与材料为GaN的势阱层13形成隧穿效率较高的量子阱。优选地，n≤30％。
另一个可选方案中，势阱层13的材料为InGaN或AlInGaN。第二势垒层12的材料为Al mIn nN 1-m-n，n≤45％，可与材料为InGaN的势阱层13形成隧穿效率较高的量子阱。优选地，n≤30％。
图4是本发明第二实施例的共振隧穿二极管的制作方法的流程图。参照图4所示，本实施例二的共振隧穿二极管及其制作方法与实施例一的共振隧穿二极管1及其制作方法大致相同，区别仅在于：步骤S1'，依次在衬底10上外延生长第二势垒层12、势阱层13与第一势垒层11，势阱层13的材料包含Ga元素，第一势垒层11的材料为Al xIn yN 1-x-y，1>x>0，1>y>0。
第二势垒层12的材料可以为AlGaN。势阱层13的材料可以为InGaN、GaN、AlInGaN中的至少一种。
第一势垒层11的材料为Al xIn yN 1-x-y，x为Al元素的质量占Al元素、In元素以及N元素的质量之和的百分比，y为In元素的质量占Al元素、In元素以及N元素的质量之和的百分比。第一势垒层11的外延生长温度越高，y越小；外延生长温度越低，y越大。第一势垒层11的外延生长温度越低，越能避免势阱层13中的Ga原子分别向第一势垒层11与第二势垒层12扩散。
y≤45％，第一势垒层11可与材料为GaN的势阱层13形成隧穿效率较高的量子阱。采用MOCVD外延生长时，y≤45％时，第一势垒层11的外延生长温度范围为600℃～900℃；30％<y<45％时，第一势垒层11的外延生长温度范围为600℃～800℃；y≤30％时，第一势垒层11的外延生长温度范围为700℃～900℃。然而，第一势垒层11的外延生长温度越低，晶格缺陷越多。因而，优选地，y≤30％。
采用含In的AlN材料作为第一势垒层11，可降低第一势垒层11的生长温度，从而避免高温制程，进而避免高温引起势阱层13中的Ga原子分别向第一势垒层11与第二势垒层12扩散，保证第一势垒层11与第二势垒层12的组分均一、防止有效厚度变薄，从而改善器件稳定性及峰谷电流比。
本发明第二实施例的共振隧穿二极管中，第一势垒层11的材料为Al xIn yN 1-x-y，1>x>0，1>y>0。
一个可选方案中，势阱层13的材料可以为GaN。第一势垒层11的材料为Al xIn yN 1-x-y，y≤45％，可与材料为GaN的势阱层13形成隧穿效率较高的量子阱。优选地，y≤30％。
另一个可选方案中，势阱层13的材料为InGaN或AlInGaN。第一势垒层11的材料为Al xIn yN 1-x-y，y≤45％，可与材料为InGaN的势阱层13形成隧穿效率较高的量子阱。优选地，y≤30％。
一些实施例中，在衬底10上外延生长的第二势垒层12的材料可以为Al mIn nN 1-m-n，1>m>0，1>n>0；或在衬底10上外延生长的第一势垒层11的材料为Al xIn yN 1-x-y，1>x>0，1>y>0。
图5是本发明第三实施例的共振隧穿二极管的截面结构示意图。
参照图5所示，本实施例三的共振隧穿二极管2与实施例一、二的共振隧穿二极管1大致相同，区别仅在于：第一势垒层11与势阱层13之间设置有第一隔离层14，第二势垒层12与势阱层13之间设置有第二隔离层15。
第一隔离层14的设置，可以进一步阻挡势阱层13中的Ga原子向第一势垒层11扩散，保证第一势垒层11的组分均一、防止有效厚度变薄，从而改善共振隧穿二极管1的器件稳定性及峰谷电流比。第一隔离层14的材料可以为AlN。
第一隔离层14的厚度范围可以为0.1nm～2nm。
第二隔离层15的设置，可以进一步阻挡势阱层13中的Ga原子向第二势垒层12扩散，保证第二势垒层12的组分均一、防止有效厚度变薄，从而改善共振隧穿二极管1的器件稳定性及峰谷电流比。第二隔离层15的材料可以为AlN。
第二隔离层15的厚度范围可以为0.1nm～2nm。
对应地，本实施例三的共振隧穿二极管2的制作方法与实施例一、二的共振隧穿二极管1的制作方法大致相同，区别仅在于：外延生长势阱层13前，在第一势垒层11上外延生长第一隔离层14；外延生长第二势垒层12前，在势阱层13上外延生长第二隔离层15。
第一隔离层14与第二隔离层15的外延生长工艺可以参照第一势垒层11、势阱层13以及第二势垒层12的外延生长工艺。
图6是本发明第四实施例的共振隧穿二极管的截面结构示意图。
参照图6所示，本实施例四的共振隧穿二极管3及其制作方法与实施例三的共振隧穿二极管2及其制作方法大致相同，区别仅在于：省略第二隔离层15以及制作第二隔离层15的步骤。
图7是本发明第五实施例的共振隧穿二极管的截面结构示意图。
参照图7所示，本实施例五的共振隧穿二极管4及其制作方法与实施例三的共振隧穿二极管2及其制作方法大致相同，区别仅在于：省略第一隔离层14以及制作第一隔离层14的步骤。
图8是本发明第六实施例的共振隧穿二极管的截面结构示意图。
参照图8所示，本实施例六的共振隧穿二极管5与实施例一至五的共振隧穿二极管1、2、3、4大致相同，区别仅在于：还包括集电极20与发射极30，集电极20靠近第一势垒层11，发射极30靠近第二势垒层12。
集电极20与发射极30的材料为Ⅲ族氮化物，例如可以为GaN基材料，更具体地，可以为GaN。
对应地，本实施例的制作方法与前述实施例的制作方法大致相同，区别仅在于：步骤S1之后还进行步骤S2：在第一势垒层11远离势阱层13的一侧外延生长集电极20，在第二势垒层12远离势阱层13的一侧外延生长发射极30。
集电极20与发射极30的材料为Ⅲ族氮化物。
或本实施例的制作方法与前述实施例的制作方法的区别仅在于：步骤S1中：在外延生长第一势垒层11前，在衬底10上外延生长集电极20；和/或去除衬底10之前进行：在第二势垒层12上外延生长发射极30。
集电极20与发射极30的外延生长工艺可以参照第一势垒层11、势阱层13以及第二势垒层12的外延生长工艺。
图9是本发明第七实施例的共振隧穿二极管的截面结构示意图。
参照图9所示，本实施例七的共振隧穿二极管6与实施例六的共振隧穿二极管5大致相同，区别仅在于：集电极20与第一势垒层11之间设置有第三隔离层16，发射极30与第二势垒层12之间设置有第四隔离层17。
第三隔离层16可以防止集电极20中的Ga原子向第一势垒层11内扩散。第四隔离层17可以防止发射极30中的Ga原子向第二势垒层12内扩散。
第三隔离层16与第四隔离层17的材料可以为AlN。
第三隔离层16的厚度范围可以为0.1nm～2nm。第四隔离层17的厚度范围可以为0.1nm～2nm。
一些实施例中，第三隔离层16与第四隔离层17可以择一设置。
对应地，本实施例的制作方法与前述实施例的制作方法大致相同，区别仅在于：步骤S1中：在第一势垒层11远离势阱层13的一侧外延生长集电极20前，在第一势垒层11远离势阱层13的一侧外延生长第三隔离层16；或在衬底10上外延生长集电极20后，第一势垒层11前，外延生长第三隔离层16；
和/或步骤S1中：在第二势垒层12远离势阱层13的一侧外延生长发射极30前，在第二势垒层12远离势阱层13的一侧外延生长第四隔离层17。
第三隔离层16与第四隔离层17的外延生长工艺可以参照第一隔离层14与第二隔离层15的外延生长工艺。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (17)

  1. 一种共振隧穿二极管，其特征在于，包括：
    第一势垒层(11)，第二势垒层(12)以及位于所述第一势垒层(11)与所述第二势垒层(12)之间的势阱层(13)，所述第一势垒层(11)的材料为Al xIn yN 1-x-y，1>x>0，1>y>0，和/或所述第二势垒层(12)的材料为Al mIn nN 1-m-n，1>m>0，1>n>0；所述势阱层的材料(13)包含Ga元素。
  2. 根据权利要求1所述的共振隧穿二极管，其特征在于，所述势阱层(13)的材料为InGaN、GaN、AlInGaN中的至少一种。
  3. 根据权利要求2所述的共振隧穿二极管，其特征在于，所述第一势垒层(11)的材料为Al xIn yN 1-x-y，y≤45％，和/或所述第二势垒层(12)的材料为Al mIn nN 1-m-n，n≤45％。
  4. 根据权利要求2所述的共振隧穿二极管，其特征在于，当所述第一势垒层(11)的材料为Al xIn yN 1-x-y时，y≤30％；当所述第二势垒层(12)的材料为Al mIn nN 1-m-n时，n≤30％。
  5. 根据权利要求1所述的共振隧穿二极管，其特征在于，所述第一势垒层(11)与所述势阱层(13)之间设置有第一隔离层(14)，和/或所述第二势垒层(12)与所述势阱层(13)之间设置有第二隔离层(15)。
  6. 根据权利要求5所述的共振隧穿二极管，其特征在于，所述第一隔离层(14)和/或所述第二隔离层(15)的材料为AlN。
  7. 根据权利要求5所述的共振隧穿二极管，其特征在于，所述第一隔离层(14)的厚度范围为0.1nm～2nm；和/或所述第二隔离层(15)的厚度范围为0.1nm～2nm。
  8. 根据权利要求1至4任一项所述的共振隧穿二极管，其特征在于，还包括集电极(20)与发射极(30)，所述集电极(20)靠近所述第一势垒层(11)，所述发射极(30)靠近所述第二势垒层(12)；所述集电极(20)与所述第一 势垒层(11)之间设置有第三隔离层(16)，和/或所述发射极(30)与所述第二势垒层(12)之间设置有第四隔离层(17)。
  9. 根据权利要求8所述的共振隧穿二极管，其特征在于，所述集电极(20)与所述发射极(30)的材料为GaN基材料。
  10. 根据权利要求8所述的共振隧穿二极管，其特征在于，所述第三隔离层(16)和/或所述第四隔离层(17)的材料为AlN。
  11. 一种共振隧穿二极管的制作方法，其特征在于，包括：
    外延生长第一势垒层(11)、势阱层(13)以及第二势垒层(12)，所述第一势垒层(11)的材料为Al xIn yN 1-x-y，1>x>0，1>y>0，和/或所述第二势垒层(12)的材料为Al mIn nN 1-m-n，1>m>0，1>n>0；所述势阱层的材料(13)包含Ga元素。
  12. 根据权利要求11所述的共振隧穿二极管的制作方法，其特征在于，所述势阱层(13)的材料为InGaN、GaN、AlInGaN中的至少一种。
  13. 根据权利要求12所述的共振隧穿二极管的制作方法，其特征在于，所述第一势垒层(11)的材料为Al xIn yN 1-x-y，y≤30％，和/或所述第二势垒层(12)的材料为Al mIn nN 1-m-n，n≤30％。
  14. 根据权利要求11所述的共振隧穿二极管的制作方法，其特征在于，当所述第一势垒层(11)的材料为Al xIn yN 1-x-y时，所述第一势垒层(11)的外延生长温度范围为600℃～900℃；当所述第二势垒层(12)的材料为Al mIn nN 1-m-n时，所述第二势垒层(12)的外延生长温度范围为600℃～900℃。
  15. 根据权利要求11至14任一项所述的共振隧穿二极管的制作方法，其特征在于，还包括：外延生长所述势阱层(13)前，在所述第一势垒层(11)上外延生长第一隔离层(14)；和/或外延生长所述第二势垒层(12)前，在所述势阱层(13)上外延生长第二隔离层(15)。
  16. 根据权利要求11至14任一项所述的共振隧穿二极管的制作方法，其特征在于，在所述第一势垒层(11)远离所述势阱层(13)的一侧外延生 长集电极(20)，或在外延生长所述第一势垒层(11)前，先外延生长集电极(20)；在所述第二势垒层(12)远离所述势阱层(13)的一侧外延生长发射极(30)。
  17. 根据权利要求16所述的共振隧穿二极管的制作方法，其特征在于，还包括：在所述第一势垒层(11)远离所述势阱层(13)的一侧外延生长集电极(20)前，在所述第一势垒层(11)远离所述势阱层(13)的一侧外延生长第三隔离层(16)；或外延生长集电极(20)后，所述第一势垒层(11)前，外延生长第三隔离层(16)；
    和/或在所述第二势垒层(12)远离所述势阱层(13)的一侧外延生长发射极(30)前，在所述第二势垒层(12)远离所述势阱层(13)的一侧外延生长第四隔离层(17)。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7002175B1 (en) * 2004-10-08 2006-02-21 Agency For Science, Technology And Research Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration
CN105845716A (zh) * 2016-05-12 2016-08-10 西安电子科技大学 渐变In组分InGaN子量子阱的RTD二极管及工艺

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7002175B1 (en) * 2004-10-08 2006-02-21 Agency For Science, Technology And Research Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration
CN105845716A (zh) * 2016-05-12 2016-08-10 西安电子科技大学 渐变In组分InGaN子量子阱的RTD二极管及工艺

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