WO2022180659A1 - Method for manufacturing group-iii nitride semiconductor epitaxial wafer - Google Patents

Method for manufacturing group-iii nitride semiconductor epitaxial wafer Download PDF

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WO2022180659A1
WO2022180659A1 PCT/JP2021/006744 JP2021006744W WO2022180659A1 WO 2022180659 A1 WO2022180659 A1 WO 2022180659A1 JP 2021006744 W JP2021006744 W JP 2021006744W WO 2022180659 A1 WO2022180659 A1 WO 2022180659A1
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channel layer
layer
nitride semiconductor
iii nitride
epitaxial wafer
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Japanese (ja)
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亮平 野々田
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三菱電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2015—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline semiconductor material, e.g. lattice adaptation, heteroepitaxy

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  • the present disclosure relates to a method for manufacturing a Group III nitride semiconductor epitaxial wafer.
  • Group III nitride semiconductors are known as electronic device materials capable of high output, high efficiency, and wideband operation, and in particular, high electron mobility transistors (HEMTs) using two-dimensional electron gas are popular. has been developed. In a HEMT using a III-nitride semiconductor, electrons accumulate due to the polarization effect at the heterointerface between the channel layer and the electron supply layer, forming a high-concentration two-dimensional electron gas.
  • HEMTs high electron mobility transistors
  • a high-resistance buffer layer intentionally doped with impurities is provided below the channel layer for the purpose of maintaining the breakdown voltage of the transistor and suppressing leakage current between the source and drain.
  • the total thickness of the high-resistance buffer layer and channel layer is usually about 1 to 2 ⁇ m.
  • the impurities doped into the high-resistance buffer layer act as traps, causing current collapse during transistor operation, deterioration of distorted transmission characteristics, and the like.
  • Patent Document 1 discloses a Group III nitride semiconductor in which the film thickness from the nucleation layer to the channel layer is 1 ⁇ m or less. Reducing the thickness of the channel layer is expected to maintain the breakdown voltage of the transistor and suppress leakage current. Also, if a high-resistance buffer layer doped with impurities is not provided, there is no trap due to impurities, and current collapse and deterioration of distorted transmission characteristics can be suppressed.
  • thinning the channel layer makes it more susceptible to donor impurities such as oxygen and silicon.
  • a nitride semiconductor layer is formed on a heterogeneous substrate such as sapphire, SiC, or Si
  • a nucleation layer is formed on the substrate and a nitride semiconductor layer is formed on the nucleation layer in order to alleviate lattice mismatch. form a layer.
  • three-dimensional growth with severe surface unevenness is dominant.
  • two-dimensional growth begins and surface flatness is restored.
  • a growth plane inclined with respect to the widely used growth plane (0001) appears.
  • Donor impurities such as oxygen and silicon are more likely to be incorporated in the slanted growth plane compared to (0001). While the donor impurity concentration is at the background level during (0001) growth, it increases up to the order of 10 17 cm ⁇ 3 in the three-dimensional growth region.
  • the channel layer When the channel layer is not thinned, the distance between the three-dimensional growth region and the two-dimensional electron gas layer formed at the interface between the channel layer and the electron supply layer is sufficiently large, so that the nucleation layer and the channel layer are not separated. Impurities near the interface do not affect the characteristics. On the other hand, when the channel layer is thinned, the high-concentration oxygen and silicon impurities incorporated in the three-dimensional growth region at the interface between the nucleation layer and the channel layer act as leak paths, resulting in a significant leak current. occur.
  • the present disclosure has been made in view of the above problems, and aims to obtain a method for manufacturing a Group III nitride semiconductor epitaxial wafer that suppresses current collapse, deterioration of strain transmission characteristics, and leakage current.
  • a method for manufacturing a Group III nitride semiconductor epitaxial wafer according to the present disclosure includes forming a nucleation layer on a substrate, forming a channel layer on the nucleation layer, and providing electrons on the channel layer.
  • the channel layer has a film thickness of 200 nm or more and 500 nm or less, and a chlorine source gas is supplied in the channel layer forming step.
  • a chlorine raw material gas is supplied in the step of forming a thin-film channel layer without providing a high-resistance buffer layer, so current collapse, deterioration of strain transmission characteristics, and leakage current are suppressed.
  • a nitride semiconductor epitaxial wafer is obtained.
  • FIG. 1 is a cross-sectional view of a group III nitride semiconductor epitaxial wafer according to Embodiment 1;
  • FIG. 2 is a diagram showing a concentration profile of a Group III nitride semiconductor epitaxial wafer according to Embodiment 1;
  • FIG. 4 is a diagram for explaining formation of a nucleation layer in the method for manufacturing a Group III nitride semiconductor epitaxial wafer according to Embodiment 1; 4 is a diagram for explaining formation of a channel layer in the method for manufacturing a group III nitride semiconductor epitaxial wafer according to the first embodiment;
  • FIG. 1 is a cross-sectional view of a group III nitride semiconductor epitaxial wafer according to Embodiment 1;
  • FIG. 2 is a diagram showing a concentration profile of a Group III nitride semiconductor epitaxial wafer according to Embodiment 1;
  • FIG. 4 is a diagram for explaining formation of a nucleation layer in
  • FIG. 4 is a diagram for explaining formation of an electron supply layer in the method for manufacturing a group III nitride semiconductor epitaxial wafer according to Embodiment 1;
  • FIG. FIG. 5 is a diagram showing a concentration profile of a group III nitride semiconductor epitaxial wafer of a comparative example;
  • FIG. 1 is a cross-sectional view schematically showing a wafer 10 according to Embodiment 1.
  • FIG. Wafer 10 comprises substrate 11 , nucleation layer 12 , channel layer 13 and electron supply layer 14 .
  • the substrate 11 is made of silicon carbide (SiC). However, the material is not limited to SiC, and silicon (Si), sapphire, or the like suitable for epitaxial growth of gallium nitride (GaN) may also be used.
  • the conductivity type of the substrate 11 is preferably high resistance and semi-insulating, but is not limited to this.
  • the substrate 11 does not have to have an off-angle, but preferably has an off-angle in the range of 0.2° or more and 4.0° or less.
  • the off-angle is 0.2° or more, the length of the terrace on the growth surface becomes short, and source atoms tend to reach the edge of the step, ie, step-flow growth.
  • the channel layer 13 tends to grow two-dimensionally even in the initial stage of growth, and the formation of a three-dimensional growth region is suppressed. That is, the incorporation of oxygen and silicon near the interface between the nucleation layer 12 and the channel layer 13 is suppressed.
  • the off-angle exceeds 4.0°, the promotion of step-flow growth becomes excessive, step bunching becomes conspicuous, and surface flatness deteriorates.
  • the direction of the off-angle is not particularly limited, but when it is inclined toward ⁇ 10-10>, the step ends are aligned in a straight line, making it easier to obtain high surface flatness.
  • the nucleation layer 12 is formed on the substrate 11 and is made of aluminum nitride (AlN) with a thickness of 50 nm, for example.
  • AlN aluminum nitride
  • the film thickness of the nucleation layer 12 is not limited to this.
  • the material is not limited to AlN, and may be Al x Ga 1-x N or its laminated structure.
  • a channel layer 13 is formed on the nucleation layer 12 and is made of GaN. No high resistance buffer layer is provided between the nucleation layer 12 and the channel layer 13 .
  • the high-resistance buffer layer is made of Al x Ga 1-x N or its laminated structure, and has a carbon concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and an iron concentration of 5 ⁇ 10 16 cm ⁇ 3 or more. It is a layer that is Since no high-resistance buffer layer is provided, trapping due to impurities is suppressed, and current collapse and deterioration of strain transmission characteristics are suppressed.
  • the film thickness of the channel layer 13 is preferably 200 nm or more and 500 nm or less, for example, 350 nm.
  • the film thickness is less than 200 nm, the effect of reducing the density of dislocations caused by lattice mismatch between the substrate and the semiconductor epitaxial layer by pair annihilation as the film thickness increases becomes insufficient. In this case, the dislocation density of the channel layer 13 becomes extremely high, resulting in degradation of device characteristics. If the film thickness exceeds 500 nm, leakage current between the source and the drain becomes significant, degrading device characteristics.
  • FIG. 2 shows the profile of the total concentration of oxygen and silicon and the concentration of carbon in the channel layer 13 .
  • the total concentration of oxygen and silicon is equal to or lower than the concentration of carbon.
  • the concentration is constant in the channel layer 13 in FIG. 2, this is for the sake of explanation, and may vary depending on the location.
  • the carbon concentration of channel layer 13 is preferably in the range of 0.5 ⁇ 10 16 to 10 ⁇ 10 16 cm ⁇ 3 . More preferably, it is 1 ⁇ 10 16 to 5 ⁇ 10 16 cm ⁇ 3 . If the carbon concentration is higher than 10 ⁇ 10 16 cm ⁇ 3 , the carbon itself causes actualization of current collapse and deterioration of strain transmission characteristics. Also, if the carbon concentration is lower than 0.5 ⁇ 10 16 cm ⁇ 3 , electrons generated by nitrogen vacancies in the GaN semiconductor layer cannot be sufficiently compensated.
  • the electron supply layer 14 is formed on the channel layer 13 and made of Al x Ga 1-x N.
  • the film thickness and composition x may be selected so as to obtain a desired two-dimensional electron gas concentration.
  • x is 0.2 and the film thickness is 30 nm.
  • Electron supply layer 14 may be doped with either oxygen or silicon, or both.
  • a cap layer made of a nitride semiconductor such as GaN may be provided on the electron supply layer 14 .
  • Nucleation layer 12, channel layer 13 and electron supply layer 14 are formed by metal organic chemical vapor deposition (MOCVD). Hydrogen, nitrogen, or a mixed gas thereof is used as the carrier gas.
  • MOCVD metal organic chemical vapor deposition
  • Hydrogen, nitrogen, or a mixed gas thereof is used as the carrier gas.
  • MBE molecular beam epitaxy
  • the nucleation layer 12 is formed on the substrate 11 (Fig. 3).
  • TMAl trimethylaluminum
  • ammonia are used as raw materials for growing the nucleation layer 12 .
  • a channel layer 13 is formed on the nucleation layer 12 (Fig. 4).
  • TMGa trimethylgallium
  • ammonia are used as materials for growing the channel layer 13 .
  • the growth conditions are, for example, a temperature of 900-1100° C., a pressure of 50-400 Torr, and a V/III ratio of 100-10000.
  • chlorine raw material gas is supplied together with these raw material gases.
  • Supply of the chlorine source gas is started when the formation of the channel layer 13 is started.
  • Chlorine (Cl) of the chlorine source gas does not contribute to the growth of the nitride semiconductor, but has the effect of etching the semiconductor layer.
  • etching and film formation can proceed simultaneously.
  • the three-dimensional growth portion with severe unevenness is preferentially etched.
  • film formation can proceed while suppressing three-dimensional growth.
  • incorporation of oxygen and silicon resulting from the three-dimensional growth region is suppressed. Therefore, leakage current is suppressed.
  • TBCl Hydrogen chloride
  • TBCl tertiary butyl chloride
  • an electron supply layer 14 is formed on the channel layer 13 (FIG. 5).
  • trimethylaluminum (TMAl), trimethylgallium (TMGa), and ammonia are used as materials for growing the electron supply layer 14 .
  • FIG. 6 shows the profile of the total concentration of oxygen and silicon and the concentration of carbon in the channel layer of the group III nitride semiconductor epitaxial wafer formed by the conventional manufacturing method.
  • the chlorine raw material gas is not supplied when the channel layer 13 is formed.
  • the oxygen and silicon concentrations are high in the three-dimensional growth region near the interface between the nucleation layer 12 and the channel layer 13 .
  • the film thickness is 500 nm or less, this three-dimensional growth region becomes a leak path.
  • the high-resistance buffer layer is not provided, and the chlorine raw material gas is supplied in the step of forming the thin-film channel layer 13. Therefore, the current collapse, the deterioration of the strain transmission characteristics, and the leak current are reduced. A suppressed III-nitride semiconductor epitaxial wafer is obtained. In addition, since the channel layer 13 is thin, there are effects of maintaining the breakdown voltage of the transistor and suppressing leakage current.
  • the supply of the chlorine raw material gas may not be started from the beginning of the growth of the channel layer 13, and the supply may be started in the middle of the growth. Also in this case, three-dimensional growth is suppressed.
  • the supply of the chlorine raw material gas may be stopped during the growth of the channel layer 13 . If the three-dimensional growth is sufficiently suppressed, the supply of the chlorine raw material gas may be stopped. In this case, a decrease in throughput due to a decrease in the growth rate of the semiconductor layer due to etching can be prevented.
  • Embodiment 2 A group III nitride semiconductor epitaxial wafer according to the second embodiment is the same as that of the first embodiment, and its cross-sectional view is shown in FIG.
  • the difference from the first embodiment lies in the step of forming channel layer 13 .
  • a surfactant raw material gas is supplied in addition to the chlorine raw material gas. This has the effect of promoting two-dimensional growth. The supply of the surfactant raw material gas is started when the formation of the channel layer 13 is started.
  • surfactant source gases examples include magnesium (Mg) source gases such as biscyclopentadienylmagnesium, and indium (In) source gases such as trimethylindium (TMIn).
  • Mg or In in this raw material gas becomes a surfactant raw material.
  • Mg or In in the process of forming the channel layer 13 three-dimensional growth can be suppressed and two-dimensional growth can be promoted. In this case, incorporation of high-concentration oxygen and silicon in the vicinity of the interface between the nucleation layer 12 and the channel layer 13 is further suppressed, resulting in a structure in which leakage current is further suppressed.
  • In is preferable as a surfactant raw material. This is because In is desorbed from the growth surface without being incorporated into the semiconductor in the growth temperature range of GaN, and functions only as a surfactant.
  • the supply of the surfactant raw material gas may not be started from the beginning of the growth of the channel layer 13, but may be started in the middle of the growth. Further, the supply of the surfactant raw material gas may be stopped during the growth of the channel layer 13 . In both cases, the effect of promoting two-dimensional growth is observed.

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Abstract

This method includes: a step for forming a nucleation layer (12) on a substrate (11); a step for forming a channel layer (13) on the nucleation layer (12); and a step for forming an electron supply layer (14) on the channel layer (13). The film thickness of the channel layer (13) is 200-500 nm, and chlorine raw material gas is supplied in the step for forming the channel layer (13).

Description

ＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法Group III nitride semiconductor epitaxial wafer manufacturing method
　本開示は、ＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法に関するものである。 The present disclosure relates to a method for manufacturing a Group III nitride semiconductor epitaxial wafer.
　ＩＩＩ族窒化物半導体は、高出力、高効率、広帯域で動作可能な電子デバイス材料として知られており、特に２次元電子ガスを利用した高電子移動度トランジスタ（ＨＥＭＴ：Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ）が盛んに開発されている。ＩＩＩ族窒化物半導体を用いたＨＥＭＴでは、チャネル層と電子供給層のヘテロ界面において、分極効果により電子が蓄積し、高濃度の２次元電子ガスが形成される。 Group III nitride semiconductors are known as electronic device materials capable of high output, high efficiency, and wideband operation, and in particular, high electron mobility transistors (HEMTs) using two-dimensional electron gas are popular. has been developed. In a HEMT using a III-nitride semiconductor, electrons accumulate due to the polarization effect at the heterointerface between the channel layer and the electron supply layer, forming a high-concentration two-dimensional electron gas.
　通常、チャネル層の下層には、トランジスタの耐圧維持とソース・ドレイン間のリーク電流抑制等を目的とし、意図的に不純物をドープした高抵抗バッファ層が設けられる。高抵抗バッファ層およびチャネル層の膜厚は通常、合計で１～２μｍ程度である。しかし、高抵抗バッファ層にドープした不純物は、トラップとして働き、トランジスタ動作時に電流コラプスの発生、歪伝送特性の劣化などが生じてしまう。 Normally, a high-resistance buffer layer intentionally doped with impurities is provided below the channel layer for the purpose of maintaining the breakdown voltage of the transistor and suppressing leakage current between the source and drain. The total thickness of the high-resistance buffer layer and channel layer is usually about 1 to 2 μm. However, the impurities doped into the high-resistance buffer layer act as traps, causing current collapse during transistor operation, deterioration of distorted transmission characteristics, and the like.
　トランジスタの耐圧維持およびリーク電流防止を達成しつつ、電流コラプスの発生および歪伝送特性の劣化を抑える構造として、高抵抗バッファ層を設けずチャネル層を薄膜化することが考えられる。特許文献１には核形成層からチャネル層までの膜厚を１μｍ以下としたＩＩＩ族窒化物半導体が開示されている。チャネル層を薄膜化すれば、トランジスタの耐圧維持とリーク電流抑制が期待される。また不純物をドープした高抵抗バッファ層を設けなければ、不純物によるトラップがなく、電流コラプスの発生、歪伝送特性の劣化が抑えられる。 As a structure that suppresses the occurrence of current collapse and deterioration of strain transmission characteristics while maintaining the withstand voltage of the transistor and preventing leakage current, it is conceivable to thin the channel layer without providing a high resistance buffer layer. Patent Document 1 discloses a Group III nitride semiconductor in which the film thickness from the nucleation layer to the channel layer is 1 μm or less. Reducing the thickness of the channel layer is expected to maintain the breakdown voltage of the transistor and suppress leakage current. Also, if a high-resistance buffer layer doped with impurities is not provided, there is no trap due to impurities, and current collapse and deterioration of distorted transmission characteristics can be suppressed.
特開２０１１－０２３６７７号公報JP 2011-023677 A
　しかし、チャネル層を薄膜化すると、酸素およびケイ素等のドナー不純物の影響を受けやすくなる。窒化物半導体層をサファイア、ＳｉＣ、Ｓｉ等の異種基板上に形成する場合、格子不整合を緩和させるために、基板の上に核形成層を形成し、この核形成層の上に窒化物半導体層を形成する。窒化物半導体層の成長初期においては表面凹凸の激しい３次元成長が支配的となる。成長が続くと、２次元成長が開始され、表面平坦性が回復する。この半導体層初期の３次元成長領域においては、広く用いられている成長面である（０００１）に対して傾斜した成長面が出現する。傾斜した成長面においては、（０００１）と比較して酸素およびケイ素等のドナー不純物が取り込まれやすい。（０００１）成長時にはドナー性不純物濃度がバックグラウンドレベルである一方、上記３次元成長領域においては１０１７ｃｍ－３台まで増加する。 However, thinning the channel layer makes it more susceptible to donor impurities such as oxygen and silicon. When a nitride semiconductor layer is formed on a heterogeneous substrate such as sapphire, SiC, or Si, a nucleation layer is formed on the substrate and a nitride semiconductor layer is formed on the nucleation layer in order to alleviate lattice mismatch. form a layer. At the initial stage of growth of the nitride semiconductor layer, three-dimensional growth with severe surface unevenness is dominant. As the growth continues, two-dimensional growth begins and surface flatness is restored. In the three-dimensional growth region of the initial stage of the semiconductor layer, a growth plane inclined with respect to the widely used growth plane (0001) appears. Donor impurities such as oxygen and silicon are more likely to be incorporated in the slanted growth plane compared to (0001). While the donor impurity concentration is at the background level during (0001) growth, it increases up to the order of 10 17 cm −3 in the three-dimensional growth region.
　チャネル層を薄膜化しない場合、３次元成長領域と、チャネル層と電子供給層との界面に形成される２次元電子ガス層の距離が十分に離れているため、核形成層とチャネル層との界面付近の不純物が特性に影響を与えることはない。一方、チャネル層を薄膜化した場合は、核形成層とチャネル層との界面の３次元成長領域に取り込まれている高濃度の酸素およびケイ素不純物がリークパスとなり、リーク電流が顕著になるといった問題が生じる。 When the channel layer is not thinned, the distance between the three-dimensional growth region and the two-dimensional electron gas layer formed at the interface between the channel layer and the electron supply layer is sufficiently large, so that the nucleation layer and the channel layer are not separated. Impurities near the interface do not affect the characteristics. On the other hand, when the channel layer is thinned, the high-concentration oxygen and silicon impurities incorporated in the three-dimensional growth region at the interface between the nucleation layer and the channel layer act as leak paths, resulting in a significant leak current. occur.
　本開示は、上記課題を鑑みたものであり、電流コラプス、歪伝送特性の劣化、リーク電流を抑制したＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法を得ることを目的とする。 The present disclosure has been made in view of the above problems, and aims to obtain a method for manufacturing a Group III nitride semiconductor epitaxial wafer that suppresses current collapse, deterioration of strain transmission characteristics, and leakage current.
　本開示に係るＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法は、基板の上に核形成層を形成する工程と、核形成層の上にチャネル層を形成する工程と、チャネル層の上に電子供給層を形成する工程とを備え、チャネル層の膜厚は２００ｎｍ以上５００ｎｍ以下であり、チャネル層を形成する工程において、塩素原料ガスを供給するものである。 A method for manufacturing a Group III nitride semiconductor epitaxial wafer according to the present disclosure includes forming a nucleation layer on a substrate, forming a channel layer on the nucleation layer, and providing electrons on the channel layer. The channel layer has a film thickness of 200 nm or more and 500 nm or less, and a chlorine source gas is supplied in the channel layer forming step.
　本開示の製造方法によれば、高抵抗バッファ層を設けず、薄膜のチャネル層を形成する工程において塩素原料ガスを供給するため、電流コラプス、歪伝送特性の劣化、リーク電流を抑制したＩＩＩ族窒化物半導体エピタキシャルウエハを得られる。 According to the manufacturing method of the present disclosure, a chlorine raw material gas is supplied in the step of forming a thin-film channel layer without providing a high-resistance buffer layer, so current collapse, deterioration of strain transmission characteristics, and leakage current are suppressed. A nitride semiconductor epitaxial wafer is obtained.
実施の形態１に係るＩＩＩ族窒化物半導体エピタキシャルウエハの断面図である。1 is a cross-sectional view of a group III nitride semiconductor epitaxial wafer according to Embodiment 1; FIG. 実施の形態１に係るＩＩＩ族窒化物半導体エピタキシャルウエハの濃度プロファイルを示す図である。2 is a diagram showing a concentration profile of a Group III nitride semiconductor epitaxial wafer according to Embodiment 1; FIG. 実施の形態１に係るＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法において、核形成層の形成を説明するための図である。FIG. 4 is a diagram for explaining formation of a nucleation layer in the method for manufacturing a Group III nitride semiconductor epitaxial wafer according to Embodiment 1; 実施の形態１に係るＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法において、チャネル層の形成を説明するための図である。4 is a diagram for explaining formation of a channel layer in the method for manufacturing a group III nitride semiconductor epitaxial wafer according to the first embodiment; FIG. 実施の形態１に係るＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法において、電子供給層の形成を説明するための図である。4 is a diagram for explaining formation of an electron supply layer in the method for manufacturing a group III nitride semiconductor epitaxial wafer according to Embodiment 1; FIG. 比較例のＩＩＩ族窒化物半導体エピタキシャルウエハの濃度プロファイルを示す図である。FIG. 5 is a diagram showing a concentration profile of a group III nitride semiconductor epitaxial wafer of a comparative example;
実施の形態１．
　実施の形態１に係るＩＩＩ族窒化物半導体エピタキシャルウエハを説明する。図１は、実施の形態１に係るウエハ１０を模式的に示す断面図である。ウエハ１０は基板１１、核形成層１２、チャネル層１３、電子供給層１４を備える。 Embodiment 1.
A Group III nitride semiconductor epitaxial wafer according to Embodiment 1 will be described. FIG. 1 is a cross-sectional view schematically showing a wafer 10 according to Embodiment 1. FIG. Wafer 10 comprises substrate 11 , nucleation layer 12 , channel layer 13 and electron supply layer 14 .
　基板１１は炭化ケイ素（ＳｉＣ）からなる。ただしＳｉＣに限らず、窒化ガリウム（ＧａＮ）のエピタキシャル成長に適しているケイ素（Ｓｉ）、サファイアなどでもよい。基板１１の導電型は高抵抗で半絶縁性を示すものがよいが、これに限定されるものではない。 The substrate 11 is made of silicon carbide (SiC). However, the material is not limited to SiC, and silicon (Si), sapphire, or the like suitable for epitaxial growth of gallium nitride (GaN) may also be used. The conductivity type of the substrate 11 is preferably high resistance and semi-insulating, but is not limited to this.
　基板１１はオフ角度を有していなくてもよいが、０．２°以上４．０°以下の範囲でオフ角度を有することが望ましい。オフ角度が０．２°以上の場合、成長面におけるテラス長が短くなり、原料原子がステップ端に到達、すなわちステップフロー成長しやすくなる。この場合、チャネル層１３の成長初期においても２次元成長しやすくなり、３次元成長領域の形成が抑制される。すなわち、核形成層１２とチャネル層１３の界面近傍での酸素およびケイ素の取り込みを抑制する。オフ角度が４．０°を超える場合、ステップフロー成長の促進が過度となり、ステップ・バンチングが顕在化し表面平坦性が低下する。オフ角度の方向については特に限定されないが、＜１０－１０＞に向かって傾斜している場合、ステップ端が直線状に揃い高い表面平坦性を得やすくなる。 The substrate 11 does not have to have an off-angle, but preferably has an off-angle in the range of 0.2° or more and 4.0° or less. When the off-angle is 0.2° or more, the length of the terrace on the growth surface becomes short, and source atoms tend to reach the edge of the step, ie, step-flow growth. In this case, the channel layer 13 tends to grow two-dimensionally even in the initial stage of growth, and the formation of a three-dimensional growth region is suppressed. That is, the incorporation of oxygen and silicon near the interface between the nucleation layer 12 and the channel layer 13 is suppressed. If the off-angle exceeds 4.0°, the promotion of step-flow growth becomes excessive, step bunching becomes conspicuous, and surface flatness deteriorates. The direction of the off-angle is not particularly limited, but when it is inclined toward <10-10>, the step ends are aligned in a straight line, making it easier to obtain high surface flatness.
　核形成層１２は基板１１の上に形成されており、例えば膜厚５０ｎｍの窒化アルミ（ＡｌＮ）からなる。ただし核形成層１２の膜厚はこれに限定されるものではない。また、ＡｌＮに限定せず、ＡｌｘＧａ１－ｘＮまたはその積層構造であってもよい。 The nucleation layer 12 is formed on the substrate 11 and is made of aluminum nitride (AlN) with a thickness of 50 nm, for example. However, the film thickness of the nucleation layer 12 is not limited to this. Further, the material is not limited to AlN, and may be Al x Ga 1-x N or its laminated structure.
　チャネル層１３は核形成層１２の上に形成されており、ＧａＮからなる。核形成層１２とチャネル層１３の間には高抵抗バッファ層を設けていない。ここで高抵抗バッファ層とは、ＡｌｘＧａ１－ｘＮまたはその積層構造からなり、炭素の濃度が１×１０１８ｃｍ－３以上、かつ、鉄の濃度が５×１０１６ｃｍ－３以上である層のことである。高抵抗バッファ層を設けていないため不純物によるトラップが抑制され、電流コラプスと歪伝送特性の劣化が抑制される。チャネル層１３の膜厚は、２００ｎｍ以上５００ｎｍ以下が好ましく、例えば３５０ｎｍである。膜厚が２００ｎｍより薄いと、基板と半導体エピタキシャル層との格子不整合に起因して発生する転位の密度が、膜厚の増大に伴い対消滅して減少していく効果が十分でなくなる。この場合、チャネル層１３の転位密度が極めて高くなり、デバイス特性の低下が生じる。膜厚が５００ｎｍを超える場合、ソース・ドレイン間のリーク電流が顕著になり、デバイス特性が劣化してしまう。 A channel layer 13 is formed on the nucleation layer 12 and is made of GaN. No high resistance buffer layer is provided between the nucleation layer 12 and the channel layer 13 . Here, the high-resistance buffer layer is made of Al x Ga 1-x N or its laminated structure, and has a carbon concentration of 1×10 18 cm −3 or more and an iron concentration of 5×10 16 cm −3 or more. It is a layer that is Since no high-resistance buffer layer is provided, trapping due to impurities is suppressed, and current collapse and deterioration of strain transmission characteristics are suppressed. The film thickness of the channel layer 13 is preferably 200 nm or more and 500 nm or less, for example, 350 nm. If the film thickness is less than 200 nm, the effect of reducing the density of dislocations caused by lattice mismatch between the substrate and the semiconductor epitaxial layer by pair annihilation as the film thickness increases becomes insufficient. In this case, the dislocation density of the channel layer 13 becomes extremely high, resulting in degradation of device characteristics. If the film thickness exceeds 500 nm, leakage current between the source and the drain becomes significant, degrading device characteristics.
　図２に、チャネル層１３における酸素とケイ素の合計の濃度および炭素の濃度のプロファイルを示す。チャネル層１３においては全ての領域において、酸素とケイ素の合計の濃度が炭素の濃度以下である。特に核形成層１２とチャネル層１３との界面付近においても、酸素とケイ素の合計の濃度が炭素の濃度以下である。なお図２では濃度がチャネル層１３内で一定だが、これは説明のためであり、場所によって変化してもかまわない。 FIG. 2 shows the profile of the total concentration of oxygen and silicon and the concentration of carbon in the channel layer 13 . In all regions of the channel layer 13, the total concentration of oxygen and silicon is equal to or lower than the concentration of carbon. Especially near the interface between the nucleation layer 12 and the channel layer 13, the total concentration of oxygen and silicon is equal to or lower than the concentration of carbon. Although the concentration is constant in the channel layer 13 in FIG. 2, this is for the sake of explanation, and may vary depending on the location.
　酸素とケイ素の合計の濃度が炭素の濃度以下の場合、ドナーが十分に補償され、チャネル層１３の膜厚が５００ｎｍ以下の場合であっても、リーク電流の発生を抑制することができる。 When the total concentration of oxygen and silicon is equal to or less than the concentration of carbon, donors are sufficiently compensated, and even when the thickness of the channel layer 13 is 500 nm or less, the occurrence of leakage current can be suppressed.
　チャネル層１３の炭素濃度は０．５×１０１６～１０×１０１６ｃｍ－３の範囲であることが好ましい。さらに好ましくは、１×１０１６～５×１０１６ｃｍ－３である。炭素濃度が１０×１０１６ｃｍ－３よりも高いと、炭素自身の影響により電流コラプスの顕在化、歪伝送特性の劣化が生じる。また、炭素濃度が０．５×１０１６ｃｍ－３より低いと、ＧａＮ半導体層中に窒素空孔により生じる電子を十分に補償することができなくなる。 The carbon concentration of channel layer 13 is preferably in the range of 0.5×10 16 to 10×10 16 cm −3 . More preferably, it is 1×10 16 to 5×10 16 cm −3 . If the carbon concentration is higher than 10×10 16 cm −3 , the carbon itself causes actualization of current collapse and deterioration of strain transmission characteristics. Also, if the carbon concentration is lower than 0.5×10 16 cm −3 , electrons generated by nitrogen vacancies in the GaN semiconductor layer cannot be sufficiently compensated.
　電子供給層１４はチャネル層１３の上に形成されており、ＡｌｘＧａ１－ｘＮからなる。膜厚および組成ｘは所望の２次元電子ガス濃度が得られるように選択してよいが、例えばｘが０．２、膜厚が３０ｎｍである。電子供給層１４には、酸素またはケイ素のどちらか一方、あるいは両方のドーピングがなされてもよい。また、電子供給層１４上には、ＧａＮ等の窒化物半導体によるキャップ層が設けられてもよい。 The electron supply layer 14 is formed on the channel layer 13 and made of Al x Ga 1-x N. The film thickness and composition x may be selected so as to obtain a desired two-dimensional electron gas concentration. For example, x is 0.2 and the film thickness is 30 nm. Electron supply layer 14 may be doped with either oxygen or silicon, or both. A cap layer made of a nitride semiconductor such as GaN may be provided on the electron supply layer 14 .
　実施の形態１に係るＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法を説明する。核形成層１２、チャネル層１３および電子供給層１４の形成は有機金属気相成長（ＭＯＣＶＤ：Ｍｅｔａｌ　Oｒｇａｎｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法によってなされる。キャリアガスは水素または窒素、あるいはそれらの混合ガスが用いられる。ただし、ＭＯＣＶＤ法に限定したものではなく、同様の半導体層が得られる場合には、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法など別の成長法を用いてもかまわない。 A method for manufacturing a Group III nitride semiconductor epitaxial wafer according to Embodiment 1 will be described. Nucleation layer 12, channel layer 13 and electron supply layer 14 are formed by metal organic chemical vapor deposition (MOCVD). Hydrogen, nitrogen, or a mixed gas thereof is used as the carrier gas. However, the method is not limited to the MOCVD method, and other growth methods such as a molecular beam epitaxy (MBE) method may be used if a similar semiconductor layer can be obtained.
　まず基板１１の上に核形成層１２を形成する（図３）。核形成層１２成長時の原料として例えばトリメチルアルミニウム（ＴＭＡｌ）およびアンモニアを用いる。 First, the nucleation layer 12 is formed on the substrate 11 (Fig. 3). For example, trimethylaluminum (TMAl) and ammonia are used as raw materials for growing the nucleation layer 12 .
　次に核形成層１２の上にチャネル層１３を形成する（図４）。チャネル層１３成長時の原料として例えばトリメチルガリウム（ＴＭＧａ）およびアンモニアを用いる。成長条件は例えば、温度が９００～１１００℃、圧力が５０～４００Ｔｏｒｒ、Ｖ／ＩＩＩ比が１００～１００００であり、ここでは温度は１０５０℃、圧力は２００Ｔｏｒｒ、Ｖ／ＩＩＩ比は２０００である。 Next, a channel layer 13 is formed on the nucleation layer 12 (Fig. 4). For example, trimethylgallium (TMGa) and ammonia are used as materials for growing the channel layer 13 . The growth conditions are, for example, a temperature of 900-1100° C., a pressure of 50-400 Torr, and a V/III ratio of 100-10000.
　またこれらの原料ガスと共に、塩素原料ガスを供給する。塩素原料ガスはチャネル層１３の形成開始時に供給を開始する。塩素原料ガスの塩素（Ｃｌ）は、窒化物半導体の成長には寄与せず、半導体層をエッチングする効果を有する。塩素原料ガスを供給することで、エッチングと成膜を同時に進行させることができる。このとき凹凸の激しい３次元成長部が優先的にエッチングされる。すなわち、３次元成長を抑制しつつ成膜を進行させることができる。結果として、３次元成長領域に起因した酸素、ケイ素の取り込みが抑制される。よってリーク電流が抑制される。塩素原料ガスとして、塩化水素（ＨＣｌ）またはターシャリブチルクロライド（ＴＢＣｌ）などを用いる。好ましくは、ＴＢＣｌである。これは、ＴＢＣｌが液体原料であり、キャリアガス流量及び蒸気圧制御による供給量制御が容易であり、窒化物半導体の成長条件に対して適切なエッチング量となる供給量条件を取得しやすいためである。 In addition, chlorine raw material gas is supplied together with these raw material gases. Supply of the chlorine source gas is started when the formation of the channel layer 13 is started. Chlorine (Cl) of the chlorine source gas does not contribute to the growth of the nitride semiconductor, but has the effect of etching the semiconductor layer. By supplying the chlorine raw material gas, etching and film formation can proceed simultaneously. At this time, the three-dimensional growth portion with severe unevenness is preferentially etched. In other words, film formation can proceed while suppressing three-dimensional growth. As a result, incorporation of oxygen and silicon resulting from the three-dimensional growth region is suppressed. Therefore, leakage current is suppressed. Hydrogen chloride (HCl), tertiary butyl chloride (TBCl), or the like is used as the chlorine source gas. TBCl is preferred. This is because TBCl is a liquid raw material, it is easy to control the supply amount by controlling the carrier gas flow rate and the vapor pressure, and it is easy to obtain supply amount conditions that provide an appropriate etching amount for the nitride semiconductor growth conditions. be.
　次にチャネル層１３の上に電子供給層１４を形成する（図５）。電子供給層１４成長時の原料として例えばトリメチルアルミニウム（ＴＭＡｌ）、トリメチルガリウム（ＴＭＧａ）およびアンモニアを用いる。 Next, an electron supply layer 14 is formed on the channel layer 13 (FIG. 5). For example, trimethylaluminum (TMAl), trimethylgallium (TMGa), and ammonia are used as materials for growing the electron supply layer 14 .
　ここで比較として、図６に、従来の製造方法で形成したＩＩＩ族窒化物半導体エピタキシャルウエハのチャネル層における酸素とケイ素の合計の濃度および炭素の濃度のプロファイルを示す。従来の製造方法では、チャネル層１３の形成時に塩素原料ガスを供給しない。そうすると、酸素およびケイ素の濃度は、核形成層１２とチャネル層１３との界面近傍の３次元成長領域において高くなる。膜厚が５００ｎｍ以下の場合、この３次元成長領域がリークパスとなる。 For comparison, FIG. 6 shows the profile of the total concentration of oxygen and silicon and the concentration of carbon in the channel layer of the group III nitride semiconductor epitaxial wafer formed by the conventional manufacturing method. In the conventional manufacturing method, the chlorine raw material gas is not supplied when the channel layer 13 is formed. Then, the oxygen and silicon concentrations are high in the three-dimensional growth region near the interface between the nucleation layer 12 and the channel layer 13 . When the film thickness is 500 nm or less, this three-dimensional growth region becomes a leak path.
　以上のとおり、この実施の形態によれば、高抵抗バッファ層を設けず、薄膜のチャネル層１３を形成する工程において塩素原料ガスを供給するため、電流コラプス、歪伝送特性の劣化、リーク電流を抑制したＩＩＩ族窒化物半導体エピタキシャルウエハを得られる。またチャネル層１３が薄いため、トランジスタの耐圧維持とリーク電流抑制の効果がある。 As described above, according to this embodiment, the high-resistance buffer layer is not provided, and the chlorine raw material gas is supplied in the step of forming the thin-film channel layer 13. Therefore, the current collapse, the deterioration of the strain transmission characteristics, and the leak current are reduced. A suppressed III-nitride semiconductor epitaxial wafer is obtained. In addition, since the channel layer 13 is thin, there are effects of maintaining the breakdown voltage of the transistor and suppressing leakage current.
　なお、チャネル層１３の成長の始めから塩素原料ガスを供給せず、成長の途中から供給を開始してもよい。この場合も、３次元成長が抑制される。 It should be noted that the supply of the chlorine raw material gas may not be started from the beginning of the growth of the channel layer 13, and the supply may be started in the middle of the growth. Also in this case, three-dimensional growth is suppressed.
　また、塩素原料ガスの供給をチャネル層１３の成長の途中で停止してもよい。３次元成長を十分抑えれば、塩素原料ガスの供給を停止してもかまわない。この場合、エッチングによる半導体層の成長レートの低減に起因したスループット低下を防げる。 Also, the supply of the chlorine raw material gas may be stopped during the growth of the channel layer 13 . If the three-dimensional growth is sufficiently suppressed, the supply of the chlorine raw material gas may be stopped. In this case, a decrease in throughput due to a decrease in the growth rate of the semiconductor layer due to etching can be prevented.
実施の形態２．
　実施の形態２に係るＩＩＩ族窒化物半導体エピタキシャルウエハは実施の形態１と同様であり、断面図は図１で示される。実施の形態１との違いは、チャネル層１３を形成する工程にある。実施の形態２ではチャネル層１３を形成する工程において、塩素原料ガスに加えてサーファクタント原料ガスを供給する。これにより、２次元成長が促進される効果を奏する。サーファクタント原料ガスはチャネル層１３の形成開始時に供給を開始する。 Embodiment 2.
A group III nitride semiconductor epitaxial wafer according to the second embodiment is the same as that of the first embodiment, and its cross-sectional view is shown in FIG. The difference from the first embodiment lies in the step of forming channel layer 13 . In the second embodiment, in the step of forming the channel layer 13, a surfactant raw material gas is supplied in addition to the chlorine raw material gas. This has the effect of promoting two-dimensional growth. The supply of the surfactant raw material gas is started when the formation of the channel layer 13 is started.
　サーファクタント原料ガスとしてビスシクロペンタジエニルマグネシウム等のマグネシウム（Ｍｇ）原料ガス、または、トリメチルインジウム（ＴＭＩｎ）等のインジウム（Ｉｎ）原料ガスが挙げられる。 Examples of surfactant source gases include magnesium (Mg) source gases such as biscyclopentadienylmagnesium, and indium (In) source gases such as trimethylindium (TMIn).
　この原料ガス中のＭｇまたはＩｎがサーファクタント原料となる。チャネル層１３の形成工程においてＭｇまたはＩｎを供給することで、３次元成長を抑制し２次元成長を促すことができる。この場合、核形成層１２とチャネル層１３との界面近傍での高濃度の酸素およびケイ素の取り込みがさらに抑制され、リーク電流をより抑制した構造が得られる。 　Mg or In in this raw material gas becomes a surfactant raw material. By supplying Mg or In in the process of forming the channel layer 13, three-dimensional growth can be suppressed and two-dimensional growth can be promoted. In this case, incorporation of high-concentration oxygen and silicon in the vicinity of the interface between the nucleation layer 12 and the channel layer 13 is further suppressed, resulting in a structure in which leakage current is further suppressed.
　サーファクタント原料としては、Ｉｎが好ましい。これは、Ｉｎが、ＧａＮの成長温度域においては半導体中に取り込まれることがなく成長表面より脱離し、サーファクタントとしての機能のみを果たすためである。 In is preferable as a surfactant raw material. This is because In is desorbed from the growth surface without being incorporated into the semiconductor in the growth temperature range of GaN, and functions only as a surfactant.
　実施の形態１におけるサーファクタント原料ガスと同様、チャネル層１３の成長の始めからサーファクタント原料ガスを供給せず、成長の途中から供給を開始してもよい。また、サーファクタント原料ガスの供給をチャネル層１３の成長の途中で停止してもよい。どちらの場合でも２次元成長促進の効果が見られる。 As with the surfactant raw material gas in Embodiment 1, the supply of the surfactant raw material gas may not be started from the beginning of the growth of the channel layer 13, but may be started in the middle of the growth. Further, the supply of the surfactant raw material gas may be stopped during the growth of the channel layer 13 . In both cases, the effect of promoting two-dimensional growth is observed.
１０　ウエハ、１１　基板、１２　核形成層、１３　チャネル層、１４　電子供給層 10 wafer, 11 substrate, 12 nucleation layer, 13 channel layer, 14 electron supply layer

Claims (10)

  1. 　基板の上に核形成層を形成する工程と、
    　前記核形成層の上にチャネル層を形成する工程と、
    　前記チャネル層の上に電子供給層を形成する工程とを備え、
    　前記チャネル層の膜厚は２００ｎｍ以上５００ｎｍ以下であり、
    　前記チャネル層を形成する工程において、塩素原料ガスを供給する
    　ＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     forming a nucleation layer on a substrate;
    forming a channel layer on the nucleation layer;
    forming an electron supply layer on the channel layer;
    The film thickness of the channel layer is 200 nm or more and 500 nm or less,
    A method for manufacturing a Group III nitride semiconductor epitaxial wafer, wherein a chlorine source gas is supplied in the step of forming the channel layer.
  2. 　前記チャネル層は、いずれの領域においても酸素とケイ素の合計の濃度が炭素の濃度以下である
    　請求項１に記載のＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     2. The method for manufacturing a group III nitride semiconductor epitaxial wafer according to claim 1, wherein the channel layer has a total concentration of oxygen and silicon equal to or lower than the concentration of carbon in any region.
  3. 　前記基板のオフ角度は０．２°以上４．０°以下である
    　請求項１また２に記載のＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     3. The method for manufacturing a group III nitride semiconductor epitaxial wafer according to claim 1, wherein the off-angle of the substrate is 0.2[deg.] or more and 4.0[deg.] or less.
  4. 　前記チャネル層を形成する工程において、前記チャネル層の形成開始時に前記塩素原料ガスの供給を開始する
    　請求項１～３のいずれか１項に記載のＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     4. The method for manufacturing a Group III nitride semiconductor epitaxial wafer according to claim 1, wherein in the step of forming the channel layer, the supply of the chlorine source gas is started when the formation of the channel layer is started.
  5. 　前記チャネル層を形成する工程において、前記チャネル層を形成する工程の途中で前記塩素原料ガスの供給を停止する
    　請求項１～４のいずれか１項に記載のＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     5. The manufacturing of the Group III nitride semiconductor epitaxial wafer according to claim 1, wherein in the step of forming the channel layer, the supply of the chlorine source gas is stopped in the middle of the step of forming the channel layer. Method.
  6. 　前記塩素原料ガスはＨＣｌまたはＴＢＣｌである
    　請求項１～５のいずれか１項に記載のＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     The method for manufacturing a Group III nitride semiconductor epitaxial wafer according to any one of claims 1 to 5, wherein the chlorine source gas is HCl or TBCl.
  7. 　前記チャネル層を形成する工程において、さらにサーファクタント原料ガスを供給する
    　請求項１～６のいずれか１項に記載のＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     7. The method for manufacturing a Group III nitride semiconductor epitaxial wafer according to claim 1, further comprising supplying a surfactant raw material gas in the step of forming the channel layer.
  8. 　前記チャネル層を形成する工程において、前記チャネル層の形成開始時に前記サーファクタント原料ガスの供給を開始する
    　請求項７に記載のＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     8. The method for manufacturing a group III nitride semiconductor epitaxial wafer according to claim 7, wherein in the step of forming the channel layer, supply of the surfactant raw material gas is started when formation of the channel layer is started.
  9. 　前記チャネル層を形成する工程において、前記チャネル層を形成する工程の途中で前記サーファクタント原料ガスの供給を停止する
    　請求項７または８に記載のＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     9. The method of manufacturing a Group III nitride semiconductor epitaxial wafer according to claim 7, wherein in the step of forming the channel layer, supply of the surfactant raw material gas is stopped in the middle of the step of forming the channel layer.
  10. 　前記サーファクタント原料ガスはビスシクロペンタジエニルマグネシウムまたはＴＭＩｎである
    　請求項７～９のいずれか１項に記載のＩＩＩ族窒化物半導体エピタキシャルウエハの製造方法。     10. The method for manufacturing a Group III nitride semiconductor epitaxial wafer according to claim 7, wherein the surfactant source gas is biscyclopentadienylmagnesium or TMIn.
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JP2005183902A (en) * 2003-12-20 2005-07-07 Samsung Electro Mech Co Ltd Method of manufacturing nitride semiconductor and structure of nitride semiconductor manufactured by the same
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