WO2022179521A1 - 一种电信号采样装置 - Google Patents

一种电信号采样装置 Download PDF

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Publication number
WO2022179521A1
WO2022179521A1 PCT/CN2022/077435 CN2022077435W WO2022179521A1 WO 2022179521 A1 WO2022179521 A1 WO 2022179521A1 CN 2022077435 W CN2022077435 W CN 2022077435W WO 2022179521 A1 WO2022179521 A1 WO 2022179521A1
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sampling
signal
delay
module
electrical signal
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PCT/CN2022/077435
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English (en)
French (fr)
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史慧
王悦
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普源精电科技股份有限公司
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Priority to EP22758885.2A priority Critical patent/EP4266063A1/en
Priority to JP2023542992A priority patent/JP2024501347A/ja
Publication of WO2022179521A1 publication Critical patent/WO2022179521A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0218—Circuits therefor
    • G01R13/0272—Circuits therefor for sampling
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0218—Circuits therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0218—Circuits therefor
    • G01R13/0254—Circuits therefor for triggering, synchronisation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks
    • G01R31/11—Locating faults in cables, transmission lines, or networks using pulse reflection methods

Definitions

  • the embodiments of the present application relate to the technical field of electronic circuits, for example, to an electrical signal sampling device.
  • TDR Time Domain Reflectometry
  • TDT Time Domain Transmission characteristic test
  • the sampling oscilloscope can achieve a high sampling bandwidth through a very low sampling rate, but the sampling oscilloscope is generally expensive and can only be set to test repetitive signals.
  • the real-time oscilloscope can test the signal under test in real time, and integrating the TDR or TDT function in the real-time oscilloscope can effectively reduce the cost of TDR or TDT.
  • Time resolution is an important indicator of TDR
  • frequency resolution is an important indicator of TDT.
  • the factors that affect these two indicators include oscilloscope bandwidth (Bandwidth, BW) and rise time Tr of the pulse signal source.
  • BW oscilloscope bandwidth
  • the smaller the rise time Tr, the higher the time resolution of the TDR, and the TDT is the frequency domain transform of the TDR, the higher the time resolution of the TDR, and the higher the frequency resolution of the TDT.
  • the conventional methods to improve the TDR time resolution/TDT frequency resolution include increasing the bandwidth and reducing the signal rise time of the pulse signal source.
  • the signal is transmitted from the transmission to the device under test and then reflected back to
  • the time of the launch point is 2T, then 2T ⁇ T R , T ⁇ 17.5ps, that is, when the analog bandwidth of the real-time oscilloscope is increased to 10GHz, the time resolution of the TDR can reach 17.5ps;
  • the current fastest edge rise time is 35ps, then according to formula (1) - real-time oscilloscope test fast edge rise time T test , pulse source signal rise time T S and fast edge rise time T that the oscilloscope can respond to
  • the relationship between the scopes shows that only when the rise time
  • the method for improving the time or frequency resolution of a real-time oscilloscope integrated with a TDR or TDT function in the related art has high implementation costs and is complicated and difficult to implement.
  • the embodiment of the present application provides an electrical signal sampling device, so as to realize the effect of an equivalent sampling oscilloscope, increase the sampling bandwidth, and improve the time resolution.
  • An embodiment of the present application provides an electrical signal sampling device, and the electrical signal sampling device includes:
  • Pulse signal source set to generate pulse signal
  • the first sampling module is connected to the pulse signal source through a coupler; wherein, the coupler is configured to generate a test input signal and a sampled incident signal after fanning out the pulse signal in two, The test input signal is input from the coupler to the device under test and then coupled to form a test output signal; the first sampling module is configured to collect the sampled incident signal and the test output signal from the coupler;
  • a signal delay module the signal delay module generates N excitation signals through a preset delay, and the N excitation signals are used to control the pulse signal source to generate N groups of pulse signals within one cycle of the pulse signal; or , the N excitation signals are used to control the first sampling module to generate N groups of sampled incident signals within one cycle of the sampled incident signal; wherein, N is an integer greater than 1.
  • FIG. 1 is a schematic structural diagram of an electrical signal sampling device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another electrical signal sampling device provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another electrical signal sampling device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a delay circuit adopting a carry chain delay provided by an embodiment of the present application
  • 5 to 8 are schematic diagrams of waveforms of delayed sampling of an electrical signal sampling device provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another electrical signal sampling device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another electrical signal sampling device provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of an electrical signal sampling apparatus according to Embodiment 1 of the present application. This embodiment can be applied to the case of improving the time resolution or frequency resolution of a real-time oscilloscope integrating TDR or TDT functions.
  • the structure of the electrical signal sampling device 100 includes the following:
  • a pulse signal source 110 configured to generate a pulse signal
  • a first sampling module 130 the first sampling module 130 is connected to the pulse signal source 110 through a coupler 120; wherein, the coupler 120 is set to generate a test input signal after fanning out the pulse signal in half and the sampled incident signal, the test input signal is input from the coupler 120 to the device under test 150 and then coupled to form a test output signal; the first sampling module 130 is configured to collect the sampled incident signal from the coupler 120 and test output signal;
  • the signal delay module 140 generates N excitation signals through a preset delay, and the N excitation signals are used to control the pulse signal source 110 to generate N groups of pulse signals within one cycle of the pulse signal; Or, the N excitation signals are used to control the first sampling module to generate N groups of sampled incident signals within one cycle of the sampled incident signal; wherein, N is an integer greater than 1.
  • the pulse signal source 110 is used as an incident signal source of the electrical signal sampling device 100, and is configured to generate a pulse signal.
  • the pulse signal has a relatively fast rising edge, that is, the signal edge rise time is very short.
  • the rising edge of the pulse signal The time is about 35 picoseconds.
  • the pulse signal source 110 may be a high-speed pulse source implemented by a comparator or a shaping circuit.
  • the coupler 120 can be externally placed in the electrical signal sampling device 100. After the coupler 120 fan-out the pulse signal in two, one channel is used as the test input signal of the device under test 150, and the other channel is used as the sampled incident signal. Connected to the first sampling module 130 .
  • the coupler 120 is placed outside the electrical signal sampling device 100 , and the signal transmission is completed through the interaction between the electrical signal sampling device 100 and the external coupler 120 .
  • FIG. 2 is a schematic structural diagram of an electrical signal sampling device provided by an embodiment of the present application.
  • the coupler 120 is placed inside the electrical signal sampling device 100, and the signal is transmitted during the electrical signal sampling.
  • the device 100 is done internally.
  • the coupler 120 when the coupler 120 is placed inside the electrical signal sampling device 100, the sampling channel of the electrical signal sampling device 100 needs to be switched more, or the electrical signal sampling device 100 is fixed as a time domain reflectometry ( TDR instrument), the TDR/TDT function of the electrical signal sampling device provided in the embodiment of the present application cannot be realized, and the operation is more troublesome, and the coupler 120 is more flexible when placed outside the electrical signal sampling device 100 .
  • TDR instrument time domain reflectometry
  • the coupler 120 may be one of a power splitter, a directional coupler, a standing wave ratio bridge or an operational amplifier.
  • the first sampling module 130 is an analog signal sampling channel of the electrical signal sampling device 100 .
  • the first sampling module 130 is configured to collect the sampled incident signal of the pulse signal source 110 and the test output signal of the device under test 150 .
  • the first sampling module 130 is configured to display the signal waveform obtained by superimposing the collected sampled incident signal and the test output signal on the time domain display, so that those skilled in the art can simultaneously analyze the collected waveform signal. analysis.
  • the sampling of the first sampling module 130 is controlled by the electrical signal sampling device 100 , and at the same time, the sampling is performed according to the phase relationship of the sampling clock of the signal delay module 140 .
  • the signal delay module 140 generates N excitation signals through a preset delay, and the N excitation signals are used to control the pulse signal source 110, that is, the pulse signal source 110 is controlled to generate N groups of pulse signals within one cycle of the pulse signal, Alternatively, the N excitation signals are used for sampling control of the first sampling module 130, that is, the first sampling module 130 is controlled to generate N groups of sampling incident signals within one cycle of the sampling incident signal, and the signal delay module 140 passes the pre- Set the delay to generate N excitation signals to achieve the effect of an equivalent sampling oscilloscope, thereby improving the time resolution of TDR measurement or the frequency resolution of TDT measurement.
  • the electrical signal sampling apparatus 100 may be a real-time oscilloscope.
  • the device under test 150 may be a component that needs to be tested for impedance, such as a circuit board, which is not limited in this embodiment.
  • the electrical signal sampling device 100 includes: a pulse signal source 110 configured to generate a pulse signal; a first sampling module 130, the first sampling module 130 communicates with the pulse signal through the coupler 120
  • the signal source 110 is connected; wherein, the coupler 120 is set to generate a test input signal and a sampled incident signal after fanning out the pulse signal in two, and the test input signal is input from the coupler 120 to the device under test 150 After coupling to form a test output signal, the test output signal is transmitted from the device under test 150 to the coupler 120 , and the first sampling module 130 is configured to collect the sampled incident signal and the test output signal from the coupler 120
  • the signal delay module 140, the signal delay module 140 generates N excitation signals through a preset delay, and the N excitation signals are used to control the pulse signal source 110 to generate N groups of pulse signals in one cycle of the pulse signal ; or, the N excitation signals are used to control the first sampling module 130 to generate N groups of sampled incident signals within one cycle
  • FIG. 3 is a schematic structural diagram of an electrical signal sampling device provided by an embodiment of the present application.
  • the signal delay module 140 includes a sampling clock unit 142 and a delay circuit 141 ;
  • the sampling clock unit 142 is configured to generate a sampling clock signal
  • the delay circuit 141 is configured to generate N excitation signals by passing the sampling clock signal through a preset delay.
  • the pulse signal source 110 is connected to the delay circuit 141 , the delay circuit 141 is connected to the sampling clock unit 142 , and the sampling clock unit 142 is connected to the delay circuit 141 .
  • the first sampling module 130 is connected.
  • the sampling clock unit 142 is configured to provide a clock source for the pulse signal source 110 and the first sampling module 130 of the electrical signal sampling device 100, that is, to generate a sampling clock signal, and to ensure that the pulse signal source 110 and the first sampling module 130 have The fixed phase relationship or connection relationship makes the frequency and phase of the pulse signal generated by the pulse signal source 110 synchronized with the sampling clock signal.
  • sampling clock unit 142 generates two clock signals with the same delay, phase, and amplitude, that is, two sampling clock signals with the same delay, phase, and amplitude, which are respectively output to the delay. time circuit 141 and the first sampling module 130 .
  • the sampling clock unit 142 may use a phase-locked loop circuit, or a module capable of synchronously outputting two channels and synchronizing clock sources in other related solutions. This embodiment does not impose any limitations on the implementation of the sampling clock unit 120 .
  • the delay circuit 141 is configured to delay the sampling clock signal by ⁇ t, that is, the preset delay generates a plurality of excitation signals sequentially delayed by ⁇ t, so that the excitation signal and the sampling clock signal become high-speed pulse signals with a certain phase relationship.
  • the delay circuit 141 may be a carry chain, a delay chip, a delay unit or a phase shifter of a Field Programmable Gate Array (FPGA) one of the.
  • FPGA Field Programmable Gate Array
  • the delay circuit 141 can perform delay through an RC circuit, that is, different delays can be realized by adjusting the resistor R or the capacitor C, and then a delay of 100 femtoseconds (femtosecond, fs) can be realized; the delay circuit 141 can also be realized by a delay chip.
  • the delay chip of related technology can realize a delay of at least 2ps; the delay circuit 141 can also be realized by a delay unit of FPGA, and the minimum delay step of the delay unit is 30ps. ;
  • the delay circuit 141 can also use the carry chain to realize the delay, and the minimum delay that can be realized is 10ps.
  • the delay circuit 141 can also be implemented with a phase shifter.
  • the carry chain is a unit in the FPGA to realize fast operation, and its delay amount is very small, generally about 10ps, that is, the input step signal. After the 1-level carry chain, it can be delayed by about 10ps. Therefore, carry chains can be cascaded to achieve larger delays.
  • FIG. 4 is a schematic structural diagram of a delay circuit using carry chain delay provided by an embodiment of the present application.
  • an FPGA device includes carry chain 1, carry chain 2 . . .
  • the output of each stage of the carry chain can be connected to the output terminal of the FPGA device through the tap.
  • the delay corresponding to the tap of each stage is different. All taps can be selected using switches. If a different delay output is selected, input a stage
  • the jump signal after the delay output of the carry chain shown in the figure, the output of each stage of the carry chain is sequentially delayed by ⁇ t, where the size of ⁇ t is determined by the FPGA device, and different taps are selected by the switch to realize the input step signal. fine delay adjustment.
  • FIGS. 5 to 8 are schematic diagrams of delayed sampling of the electrical signal sampling device provided by the embodiments of the present application. It should be noted that in the figure, Tp represents the duration of one sampling, that is, the time for sampling many sampling points at one time, CLK is the sampling clock signal, and Tclk is the period of the sampling clock signal. Referring to FIG. 5 to FIG.
  • the electrical signal sampling device 100 samples the pulse signal input to the first sampling module 130 for the first time according to the rising edge of the sampling clock signal, then the sampling clock signal The rising edge of the pulse signal is sampled to the solid black sampling point of the pulse signal as shown in FIG. 5 ; after that, after the delay circuit delays the sampling clock signal by ⁇ t, the electrical signal sampling device 100 continues to analyze the sampling clock signal according to the rising edge of the sampling clock signal.
  • the pulse signal input to the first sampling module 130 is sampled for the second time, and the black hollow sampling point of the pulse signal as shown in FIG. 6 is sampled at the rising edge of the sampling clock signal; After the time delay of 2* ⁇ t is performed, the electrical signal sampling device 100 samples the pulse signal input to the first sampling module 130 for the third time according to the rising edge of the sampling clock signal, and then samples the pulse signal at the rising edge of the sampling clock signal.
  • the black diamond sampling points of the pulse signal are shown in Figure 7.
  • the algorithm can be used to arrange the three sampling points in sequence according to the phase relationship, and the following can be obtained:
  • the time resolution reaches ⁇ t. Therefore, when the minimum delay step of the delay circuit 141 is smaller, the time resolution of the electrical signal sampling device 100 is higher, and when a conventional FPGA carry chain is used, the time resolution can be increased to 10ps .
  • FIG. 9 is a schematic structural diagram of an electrical signal sampling device provided by an embodiment of the present application.
  • the pulse signal source 110 is connected to the sampling clock unit 142 , and the delay time
  • the circuit 141 is connected to the sampling clock unit 142 , and the delay circuit 141 is connected to the first sampling module 130 .
  • the electrical signal sampling device 100 controls the first sampling module 130 to generate N groups of sampled incident signals within one cycle of the sampled incident signal, thereby improving the time resolution of TDR&TDT, which is different from using control pulses
  • the principle that the signal source generates N groups of pulse signals in one period of the pulse signal is the same, and will not be described one by one here.
  • the sampled incident signal is sampled once on the rising edge of the clock for the first time, after the clock signal is delayed by ⁇ t for the second time, the sampled incident signal is sampled again using the sampling clock signal, and the clock signal is delayed for the third time. After 2* ⁇ t, the sampled incident signal is sampled again using the sampling clock signal. Because the three delays have a fixed and determinate phase relationship, an algorithm can be used to interleave and splicing the data sampled three times to obtain a waveform signal with a high sampling rate, so as to achieve the purpose of improving the equivalent sampling rate and time resolution. .
  • the delay circuit 141 may be one of a carry chain, an analog-to-digital conversion chip, a phase-locked loop or a delay chip.
  • the delay circuit 141 adopts the delay adjustment function of the digital-to-analog conversion chip, and its minimum delay time is about fs level, and the time resolution can be better improved by the digital-to-analog conversion chip.
  • the delay circuit 141 can also be implemented by one of a phase shifter, a phase locked loop or a delay chip.
  • FIG. 10 is a schematic structural diagram of an electrical signal sampling apparatus provided by an embodiment of the present application.
  • the electrical signal sampling apparatus 100 further includes a second sampling module 160;
  • the second sampling module 160 is connected to the signal output end of the device under test 150, and is configured to collect the second test output signal of the device under test 150 and output the second sampling signal.
  • the second sampling module 160 is an analog signal sampling channel of the electrical signal sampling device 100 , and the second sampling module 160 is configured to collect the second test output signal of the device under test 150 , and the second test output signal is received by the device under test 150 . After reaching the test input signal, the device under test 150 directly outputs the second test output signal.
  • the second sampling signal is a signal obtained after the second sampling module 160 samples the second test output signal.
  • the electrical signal sampling apparatus 100 provided in FIG. 1 is a case where the coupler 120 is placed outside the electrical signal sampling apparatus 100 , and the electrical signal sampling apparatus 100 disclosed in the embodiment of the present application further includes a second sampling In the case of the module 160 , the same applies to the case where the coupler 120 shown in FIG. 2 is placed inside the electrical signal sampling device 100 , which will not be repeatedly described in this embodiment of the present application.
  • the electrical signal sampling device integrates the TDT function, that is, includes the second sampling module 160, the second sampling module shown in 160 is connected to the device under test 150 and the signal delay module 140, respectively.
  • the signal delay module 140 includes a sampling clock unit and a delay circuit; on the basis of the above embodiment, the pulse signal source is connected to the delay circuit, and the delay circuit is connected to the sampling clock unit connected, the sampling clock unit is connected to the second sampling module.
  • the sampling clock unit is set as the pulse signal source of the electrical signal sampling device 100 110 and the second sampling module 160 provide a clock source, that is, generate a sampling clock signal, and ensure that the pulse signal source 110 and the second sampling module 160 have a fixed phase relationship or connection relationship, so that the pulse signal source 110 generates the frequency and phase of the pulse signal Synchronized with the generation of the sampling clock signal.
  • the working principle of the delay circuit is the same as that described in the above embodiments, and will not be repeated here.
  • the pulse signal source is connected to the sampling clock unit, the delay circuit is connected to the sampling clock unit, and the delay circuit is connected to the second sampling module.
  • the second sampling module is used to control the second sampling module to generate N groups of second sampling signals within one cycle of the second test output signal.
  • the first sampling module 130 is controlled to generate N groups of sampled incident signals within one cycle of the sampled incident signal, and the principle of improving the time resolution of TDR & TDT is the same, which is not repeated here.
  • the electrical signal sampling device integrating the TDR/TDT function provided by the embodiment of the present application adopts an ingenious circuit structure. Through the control of the pulse signal source delay or the control of the sampling clock, the effect of an equivalent sampling oscilloscope is realized, and the It solves the problems of huge oscilloscope analog bandwidth and ultra-high-speed edge signals, increases the equivalent sampling rate, realizes a larger system bandwidth, and easily achieves the purpose of improving the time resolution of TDR and TDT.

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Abstract

一种电信号采样装置(100)。包括：脉冲信号源(110)、第一采样模块(130)、信号延迟模块(140)；脉冲信号源(110)设置为产生脉冲信号；第一采样模块(130)通过耦合器(120)与脉冲信号源(110)连接；耦合器(120)设置为将脉冲信号一分二扇出后产生测试输入信号和采样入射信号，测试输入信号从耦合器(120)输入被测设备(150)后耦合形成测试输出信号；第一采样模块(130)设置为从耦合器(120)采集采样入射信号和测试输出信号；信号延迟模块(140)通过预设延时产生N个激励信号，N个激励信号用于控制脉冲信号源(110)在脉冲信号的一个周期内产生N组脉冲信号；或，N个激励信号用于在采样入射信号的一个周期内控制第一采样模块(130)产生N组采样入射信号。

Description

一种电信号采样装置
本申请要求在2021年2月24日提交中国专利局、申请号为202110210035.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及电子电路技术领域，例如涉及一种电信号采样装置。
背景技术
特性阻抗测试(Time Domain Reflectometry，TDR)和时域传输特性测试(Time Domain Transmission，TDT)广泛应用于信号完整性分析、电缆、印制电路板(Printed Circuit Board，PCB)测试等场景中，最常用的TDR测试设备是采样示波器，采样示波器可以通过很低的采样率实现很高的采样带宽，但采样示波器一般成本较高，而且仅能设置为重复信号的测试。
实时示波器可以实时测试被测信号，在实时示波器中集成TDR或TDT功能可以有效降低TDR或TDT的成本。时间分辨率是TDR的一个重要指标，频率分辨率是TDT的一个重要指标，而影响这两个指标的因素有示波器带宽(Bandwidth，BW)、脉冲信号源的上升时间Tr，带宽BW越大，上升时间Tr越小，TDR时间分辨率越高，且TDT为TDR的频域变换，则TDR时间分辨率越高，TDT频率分辨率也越高。
提高TDR时间分辨率/TDT频率分辨率常规的方法有提高带宽和减小脉冲信号源的信号上升时间。对于提高带宽的方法，当实时示波器的模拟带宽达到10GHz时，实时示波器能响应的快沿的上升时间T R＝35皮秒(picosecond，ps)，信号从发射到被测设备再经反射回到发射点的时间为2T，那么2T<T R，T<17.5ps，即，实时示波器的模拟带宽提高到10GHz时，TDR的时间分辨率能达到17.5ps；对于减小脉冲源信号的上升时间的方法，目前最快的沿的上升时间为35ps，则根据式(1)——实时示波器测试快沿的上升时间T 测、脉冲源信号上升时间T S和示 波器能响应的快沿的上升时间T scope之间的关系可知，只有当脉冲源信号上升时间T S远小于实时示波器能响应的快沿的上升时间T scope时，提升脉冲源信号的边沿速度才能有效的提升TDR时间分辨率&TDT频率分辨率，但设计远小于35ps的脉宽信号更加困难。
Figure PCTCN2022077435-appb-000001
综上所述，相关技术中的提高集成TDR或TDT功能的实时示波器时间或频率分辨率的方法实现成本高且实现复杂困难。
发明内容
本申请实施例提供一种电信号采样装置，以实现等效采样示波器的效果，增大采样带宽，提升时间分辨率。
本申请实施例提供了一种电信号采样装置，该电信号采样装置包括：
脉冲信号源，设置为产生脉冲信号；
第一采样模块，所述第一采样模块通过耦合器与所述脉冲信号源连接；其中，所述耦合器设置为将所述脉冲信号一分二扇出后产生测试输入信号和采样入射信号，所述测试输入信号从所述耦合器输入被测设备后耦合形成测试输出信号；所述第一采样模块设置为从所述耦合器采集所述采样入射信号和测试输出信号；
信号延迟模块，所述信号延迟模块通过预设延时产生N个激励信号，所述N个激励信号用于控制所述脉冲信号源在所述脉冲信号的一个周期内产生N组脉冲信号；或，所述N个激励信号用于在所述采样入射信号的一个周期内控制所述第一采样模块产生N组采样入射信号；其中，N为大于1的整数。
附图说明
图1是本申请实施例提供的一种电信号采样装置的结构示意图；
图2是本申请实施例提供的另一种电信号采样装置的结构示意图；
图3是本申请实施例提供的又一种电信号采样装置的结构示意图；
图4是本申请实施例提供的一种采用进位链方式延时的延时电路的结构示意图；
图5到图8是本申请实施例提供的电信号采样装置延时采样的波形示意图；
图9是本申请实施例提供的又一种电信号采样装置的结构示意图；
图10是本申请实施例提供的又一种电信号采样装置的结构示意图。
具体实施方式
下面结合附图对本申请具体实施例作详细描述。
另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部内容。在更加详细地讨论示例性实施例之前应当提到的是，一些示例性实施例被描述成作为流程图描绘的处理或方法。虽然流程图将各项操作(或步骤)描述成顺序的处理，但是其中的许多操作可以被并行地、并发地或者同时实施。此外，各项操作的顺序可以被重新安排。当其操作完成时所述处理可以被终止，但是还可以具有未包括在附图中的附加步骤。所述处理可以对应于方法、函数、规程、子例程、子程序等等。
图1为本申请实施例一提供的一种电信号采样装置的结构示意图，本实施例可适用于提高集成TDR或TDT功能的实时示波器的时间分辨率或频率分辨率的情况。
该电信号采样装置100的结构包括如下：
脉冲信号源110，设置为产生脉冲信号；
第一采样模块130，所述第一采样模块130通过耦合器120与所述脉冲信号源110连接；其中，所述耦合器120设置为将所述脉冲信号一分二扇出后产生测试输入信号和采样入射信号，所述测试输入信号从所述耦合器120输入被测设备150后耦合形成测试输出信号；所述第一采样模块130设置为从所述耦合器120采集所述采样入射信号和测试输出信号；
信号延迟模块140，所述信号延迟模块140通过预设延时产生N个激励信号，所述N个激励信号用于控制脉冲信号源110在所述脉冲信号的一个周期内产生N组脉冲信号；或，所述N个激励信号用于在所述采样入射信号的一个周期内控制所述第一采样模块产生N组采样入射信号；其中，N为大于1的整数。
其中，脉冲信号源110作为电信号采样装置100的入射信号源，设置为产生脉冲信号，该脉冲信号具有较快的上升沿，即信号边沿上升时间非常短，示例性的，脉冲信号的边沿上升时间大约为35皮秒。
可选的，脉冲信号源110可以为采用比较器或整形电路实现的高速脉冲源。
继续参见图1，耦合器120可外置于电信号采样装置100，耦合器120是将脉冲信号一分二扇出后，一路作为被测设备150的测试输入信号，另一路作为采样入射信号，连接到第一采样模块130上。
可以理解的是，在上述实施例中，耦合器120置于电信号采样装置100外部，则信号的传输均通过电信号采样装置100与外部的耦合器120交互完成。
，图2是本申请实施例提供的一种电信号采样装置的结构示意图，参见图2，所述耦合器120置于所述电信号采样装置100的内部，则信号的传输均在电信号采样装置100内部完成。
可以理解的是，当耦合器120置于电信号采样装置100内部时，则将导致电信号采样装置100的采样通道需要增加切换，或是将电信号采样装置100固定成时域反射测量仪(TDR仪)，无法实现本申请实施例所提供的电信号采样装置进行TDR/TDT功能使用，同时，操作比较麻烦，而耦合器120置于电信号采样装置100外部更灵活。
在上述实施例的基础上，所述耦合器120可以为功分器、定向耦合器、驻波比电桥或运算放大器中的一种。
第一采样模块130为电信号采样装置100的模拟信号采样通道，第一采样模块130设置为采集脉冲信号源110的采样入射信号以及被测设备150的测试输出信号。
可以理解的是，第一采样模块130设置为将采集到的采样入射信号和测试输出信号叠加后得到的信号波形在时域显示器上进行显示，以便于本领域技术人员同时对采集到的波形信号进行分析。第一采样模块130的采样受电信号采样装置100的控制，同时根据信号延迟模块140的采样时钟相位关系进行采样。
信号延迟模块140通过预设延时产生N个激励信号，N个激励信号用于对脉冲信号源110的控制，即控制脉冲信号源110在所述脉冲信号的一个周期内产生N组脉冲信号，或者，N个激励信号用于对第一采样模块130的采样控制，即在所述采样入射信号的一个周期内控制所述第一采样模块130产生N组采样入射信号，信号延迟模块140通过预设延时产生N个激励信号实现等效采样示波器的效果，进而提高TDR测量的时间分辨率或TDT测量的频率分辨率。
需要说明的是，在上述实施例的基础上，所述电信号采样装置100可以为实时示波器。被测设备150可以为线路板等需要进行阻抗测试的元器件，本实施例对此不作任何限制。
本申请实施例的技术方案，该电信号采样装置100包括：脉冲信号源110，设置为产生脉冲信号；第一采样模块130，所述第一采样模块130通过所述耦合器120与所述脉冲信号源110连接；其中，所述耦合器120设置为将所述脉冲信号一分二扇出后产生测试输入信号和采样入射信号，所述测试输入信号从所述耦合器120输入被测设备150后耦合形成测试输出信号，然后，测试输出信号从被测设备150传输至所述耦合器120，所述第一采样模块130设置为从所述耦合器120采集所述采样入射信号和测试输出信号；信号延迟模块140，所述信号延迟模块140通过预设延时产生N个激励信号，所述N个激励信号用于控制脉冲信号源110在所述脉冲信号的一个周期内产生N组脉冲信号；或，所述N个激励信号用于在所述采样入射信号的一个周期内控制所述第一采样模块130产生N组采样入射信号；其中，N为大于1的整数。解决了相关技术中提高TDR时间分辨率依赖于技术改进的问题，以实现等效采样示波器的效果，增大采样带宽，提升时间分辨率。
图3是本申请实施例提供的一种电信号采样装置的结构示意图，参见图3，在上述实施例的基础上，所述信号延迟模块140包括采样时钟单元142和延时电路141；
所述采样时钟单元142，设置为产生采样时钟信号；
所述延时电路141，设置为将所述采样时钟信号通过预设延时产生N个所述激励信号。
继续参见图3，在上述实施例的基础上，所述脉冲信号源110与所述延时电路141相连，所述延时电路141与所述采样时钟单元142相连，所述采样时钟单元142与所述第一采样模块130相连。
其中，所述采样时钟单元142设置为为电信号采样装置100的脉冲信号源110和第一采样模块130提供时钟源，即产生采样时钟信号，且保证脉冲信号源110和第一采样模块130具有固定的相位关系或连接关系，使得脉冲信号源110产生脉冲信号的频率和相位与采样时钟信号同步。
可以理解的是，采样时钟单元142产生的是两个延时、相位、幅值完全相同的两路时钟信号，即两路延时、相位、幅值完全相同的采样时钟信号，分别输出至延时电路141和第一采样模块130。
示例性的，采样时钟单元142可以采用锁相环电路，也可以采用其他相关方案中可以同步输出两路、同步时钟源的模块，本实施例对采样时钟单元120的实现方式不作任何限制。
延时电路141设置为将采样时钟信号进行确定Δt的延迟，即预设延时产生多个依次延时Δt的激励信号，以使激励信号与采样时钟信号成为具有一定相位关系的高速脉冲信号。
可以理解的是，延时电路141的不同实现方式决定了其提高的时间分辨率的大小也不同。
继续参见图3，在上述实施例的基础上，所述延时电路141可以为进位链、延时芯片、现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)的 延时单元或移相器中的一种。
示例性的，延时电路141可以通过RC电路进行延时，即通过电阻器R或电容器C的调节实现不同延时，进而可以实现100飞秒(femtosecond，fs)级的延时；延时电路141也可以通过延时芯片实现，相关技术的延时芯片可以实现步进最小2ps的延时；延时电路141还可以采用FPGA的延时单元实现，其延时单元最小延时步进是30ps；延时电路141还可以采用进位链实现延时，其可以实现的最小延时是10ps。延时电路141还可以采用移相器进行实现。在上述实施例的基础上，延时电路141不同的实现方式其对应的延时的时间不同，则所能提高的等效采样率也不同，提高的TDR时间分辨率&TDT的频率分辨率也就不同，本实施例对延时电路141的实现方式不作任何限制。
示例性的，以延时电路141采用进位链实现为例，进位链(Carry chain)是FPGA内为实现快速运算的单元，其延时量非常小，一般可以到10ps左右，即输入阶跃信号经过1级进位链，可以被延时10ps左右。因此，进位链可进行级联，以实现更大的延时。
图4是本申请实施例提供的一种采用进位链方式延时的延时电路的结构示意图，参见图4，一个FPGA器件内包括进位链1、进位链2……进位链N共N级进位链，每一级进位链的输出可以通过抽头连接FPGA器件的输出端，每一级的抽头对应的延时不一样，所有抽头可以使用开关进行选择，选择不同的延时输出，则输入一个阶跃信号，经过图示进位链的延时输出，每一级进位链输出被依次延时Δt，其中，Δt的大小由FPGA器件决定，通过开关对应选择不同的抽头，进而实现对输入阶跃信号的精细延时调节。
示例性的，图5到图8是本申请实施例提供的电信号采样装置延时采样的示意图，需要说明的是，图中Tp代表一次采样的持续时间，即一次采样很多采样点的时间，CLK为采样时钟信号，Tclk为采样时钟信号的周期。参见图5到图8，在本实施例中，假设脉冲信号的一个周期是t，延时电路能够延时的最小步进是Δt 0，延时电路实际的延时时间为Δt，且Δt>Δt 0，当采样时钟信号和脉 冲信号同步的情况下，电信号采样装置100根据采样时钟信号的上升沿对输入到第一采样模块130上的脉冲信号进行第一次采样，则在采样时钟信号的上升沿采样到如图5所示的脉冲信号的黑色实心采样点；之后，延时电路对采样时钟信号进行Δt的时间延时后，电信号采样装置100继续根据采样时钟信号的上升沿对输入到第一采样模块130上的脉冲信号进行第二次采样，则在采样时钟信号的上升沿采样到如图6所示的脉冲信号的黑色空心采样点；然后，延时电路对采样时钟信号进行2*Δt的时间延时后，电信号采样装置100根据采样时钟信号的上升沿对输入到第一采样模块130上的脉冲信号进行第三次采样，则在采样时钟信号的上升沿采样到如图7所示的脉冲信号的黑色菱形采样点。
综上所示，由于被采样的波形与采样时钟信号是有固定的相位关系的，则通过这个固定的相位关系，利用算法可以将这三次的采样点，按照相位关系依次排列，即可得到如图8所示的高采样率下采集到的波形。由此可见，脉冲信号原来的一个采样周期是t，采样率是1/t。那么，经过上述对脉冲信号延迟的方法则将采样周期由原来的t变成了Δt(即3*Δt＝t)，相应的采样率变成了3/t，采样率提高了3倍，此时的时间分辨率就达到了Δt。因此，当延时电路141的最小延时步进越小，则电信号采样装置100的时间分辨率就越高，则当采用常规的FPGA的进位链时，即可以将时间分辨率提高到10ps。
图9是本申请实施例提供的一种电信号采样装置的结构示意图，参见图9，在上述实施例的基础上，所述脉冲信号源110与所述采样时钟单元142相连，所述延时电路141与所述采样时钟单元142相连，所述延时电路141与所述第一采样模块130相连。
在本实施例中，电信号采样装置100通过在所述采样入射信号的一个周期内控制所述第一采样模块130产生N组采样入射信号，实现的提高TDR&TDT时间分辨率，其与采用控制脉冲信号源在所述脉冲信号的一个周期内产生N组脉冲信号的原理相同，在此不再一一累述。
示例性的，第一次在时钟上升沿对采样入射信号进行一次采样，第二次将 时钟信号延时Δt后，使用采样时钟信号再一次对采样入射信号进行采样，第三次将时钟信号延时2*Δt后，使用采样时钟信号再一次对采样入射信号进行采样。因为这三次延时具有固定确定的相位关系，即可采用算法将这三次采样到的数据进行交织拼接后得到高采样率的波形信号，以达到提高等效采样率的以及提高时间分辨率的目的。
在上述实施例的基础上，所述延时电路141可以为进位链、模数转换芯片、锁相环或延时芯片中的一种。
其中，延时电路141采用数模转换芯片自带的延时调节功能，其最小延时时间大约在fs级别，则通过数模转换芯片也能更好的提升时间分辨率。
在上述实施例的基础上，延时电路141也可以通过移相器、锁相环或延时芯片中的一种实现。
图10是本申请实施例提供的一种电信号采样装置的结构示意图，参见图10，在上述实施例的基础上，所述电信号采样装置100还包括第二采样模块160；
所述第二采样模块160与所述被测设备150的信号输出端相连，设置为采集所述被测设备150的第二测试输出信号，输出第二采样信号。
其中，第二采样模块160为电信号采样装置100的模拟信号采样通道，第二采样模块160设置为采集被测设备150的第二测试输出信号，第二测试输出信号是在被测设备150接收到测试输入信号后，由被测设备150直接输出第二测试输出信号。
第二采样信号即为第二采样模块160对第二测试输出信号进行采样后得到的信号。
可以理解的是，图1所提供的电信号采样装置100为所述耦合器120置于所述电信号采样装置100外部的情况，本申请实施例公开的电信号采样装置100还包括第二采样模块160的情况中，同样适用于如图2所示的耦合器120置于所述电信号采样装置100内部的情况，本申请实施例对此不再累述说明。
在上述实施例的基础上，继续参见图3和10所示的电信号采样装置的结构 示意图，当电信号采样装置集成有TDT功能，即包含第二采样模块160，则所示第二采样模块160分别与被测设备150和信号延迟模块140相连。
相应的，所述信号延迟模块140包括采样时钟单元和延时电路；在上述实施例的基础上，所述脉冲信号源与所述延时电路相连，所述延时电路与所述采样时钟单元相连，所述采样时钟单元与所述第二采样模块相连。此时，对应于N个激励信号用于控制所述脉冲信号源在所述脉冲信号的一个周期内产生N组脉冲信号，则所述采样时钟单元设置为为电信号采样装置100的脉冲信号源110和第二采样模块160提供时钟源，即产生采样时钟信号，且保证脉冲信号源110和第二采样模块160具有固定的相位关系或连接关系，使得脉冲信号源110产生脉冲信号的频率和相位与采样时钟信号的产生同步。延时电路的工作原理同上述实施例所述，在此不再累述。
在上述实施例的基础上，所述脉冲信号源与所述采样时钟单元相连，所述延时电路与所述采样时钟单元相连，所述延时电路与所述第二采样模块相连。此时，对应于所述N个激励信号用于在所述第二测试输出信号的一个周期内控制所述第二采样模块产生N组第二采样信号，则与电信号采样装置100通过在所述采样入射信号的一个周期内控制所述第一采样模块130产生N组采样入射信号，实现的提高TDR&TDT时间分辨率的原理相同，在此不再累述。
本申请实施例提供的在集成TDR/TDT功能的电信号采样装置采用了巧妙的电路结构，通过对脉冲信号源延时的控制，或者对采样时钟的控制，实现等效采样示波器的效果，克服了巨大的示波器模拟带宽和超高速边沿信号的难题，将等效采样率提高，实现更大的系统带宽，轻松简单的实现了提高TDR和TDT时间分辨率的目的。

Claims (10)

  1. 一种电信号采样装置，包括：
    脉冲信号源，设置为产生脉冲信号；
    第一采样模块，所述第一采样模块通过耦合器与所述脉冲信号源连接；其中，所述耦合器设置为将所述脉冲信号一分二扇出后产生测试输入信号和采样入射信号，所述测试输入信号从所述耦合器输入被测设备后耦合形成测试输出信号，所述测试输出信号从所述被测设备传输至所述耦合器；所述第一采样模块设置为从所述耦合器采集所述采样入射信号和测试输出信号；
    信号延迟模块，所述信号延迟模块通过预设延时产生N个激励信号，所述N个激励信号用于控制所述脉冲信号源在所述脉冲信号的一个周期内产生N组脉冲信号；或，所述N个激励信号用于在所述采样入射信号的一个周期内控制所述第一采样模块产生N组采样入射信号；其中，N为大于1的整数。
  2. 根据权利要求1所述的电信号采样装置，其中，所述信号延迟模块包括采样时钟单元和延时电路；
    所述采样时钟单元，设置为产生采样时钟信号；
    所述延时电路，设置为将所述采样时钟信号通过预设延时产生N个所述激励信号。
  3. 根据权利要求2所述的电信号采样装置，其中，所述脉冲信号源与所述延时电路相连，所述延时电路与所述采样时钟单元相连，所述采样时钟单元与所述第一采样模块相连。
  4. 根据权利要求3所述的电信号采样装置，其中，所述延时电路为进位链、延时芯片、现场可编程逻辑门阵列FPGA的延时单元或移相器中的一种。
  5. 根据权利要求2所述的电信号采样装置，其中，所述脉冲信号源与所述采样时钟单元相连，所述延时电路与所述采样时钟单元相连，所述延时电路与所述第一采样模块相连。
  6. 根据权利要求5所述的电信号采样装置，其中，所述延时电路为进位链、模数转换芯片、锁相环或延时芯片中的一种。
  7. 根据权利要求2所述的电信号采样装置，其中，所述电信号采样装置还包括第二采样模块；
    所述第二采样模块与所述被测设备的信号输出端相连，所述第二采样模块设置为采集所述被测设备的第二测试输出信号，输出第二采样信号。
  8. 根据权利要求7所述的电信号采样装置，其中，所述脉冲信号源与所述延时电路相连，所述延时电路与所述采样时钟单元相连，所述采样时钟单元与所述第二采样模块相连。
  9. 根据权利要求7所述的电信号采样装置，其中，所述脉冲信号源与所述采样时钟单元相连，所述延时电路与所述采样时钟单元相连，所述延时电路与所述第二采样模块相连。
  10. 根据权利要求1所述的电信号采样装置，其中，所述电信号采样装置为实时示波器。
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