WO2022176807A1 - Convertisseur analogue-numérique et dispositif électronique - Google Patents

Convertisseur analogue-numérique et dispositif électronique Download PDF

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WO2022176807A1
WO2022176807A1 PCT/JP2022/005708 JP2022005708W WO2022176807A1 WO 2022176807 A1 WO2022176807 A1 WO 2022176807A1 JP 2022005708 W JP2022005708 W JP 2022005708W WO 2022176807 A1 WO2022176807 A1 WO 2022176807A1
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period
signal
analog
capacitors
differential
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PCT/JP2022/005708
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English (en)
Japanese (ja)
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一徳 長谷部
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ソニーセミコンダクタソリューションズ株式会社
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Priority to JP2023500825A priority Critical patent/JPWO2022176807A1/ja
Publication of WO2022176807A1 publication Critical patent/WO2022176807A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Definitions

  • the present disclosure relates to analog-digital converters and electronic devices.
  • SAR ADC Successive Approximation Resister Analog Digital Converter
  • the charge in the capacitor holding the residual voltage may be fully charge transferred to another capacitor to generate the noise shaping signal.
  • the sampling period of the input signal is shortened, there is a risk that all charges will not be transferred in time. Failure to transfer all charges in time will also result in poor SNDR.
  • Patent document 1 samples the residual signal by a method different from the method described above, and does not present a solution to the problems of the above method.
  • the present disclosure provides an analog-to-digital converter and an electronic device that are capable of correctly sampling a residual signal after AD conversion of an input signal, and that are excellent in AD conversion accuracy and SNDR.
  • an analog-to-digital converter that converts an analog signal into a digital signal within a sampling period including consecutive first, second, and third periods, ,
  • the analog signal is sampled within the first period, and the sampled signal is sequentially converted bit by bit into the digital signal with redundancy within the second period, and an unconverted residual is obtained.
  • a digital-to-analog converter that outputs a signal; sampling the residual signal within the third period, and at least within the second period, part of the residual signal sampled during the third period within the immediately preceding sampling period and the sampling period two sampling periods before a filter unit that performs charge transfer or charge redistribution to generate a noise shaping signal based on a portion of the residual signal sampled during the third period in a DAC controller for controlling the digital-to-analog converter within the second time period based on the residual signal and the noise shaping signal.
  • the filter unit in the first period and the second period, selects a part of the residual signal sampled in the third period in the immediately preceding sampling period and the third period in the sampling period two sampling periods before.
  • the noise shaping signal may be generated by charge transferring a portion of the residual signal sampled at .
  • the filter unit in the first period and the second period, selects a part of the residual signal sampled in the third period in the immediately preceding sampling period and the third period in the sampling period two sampling periods before.
  • the noise shaping signal may be generated by charge redistribution with a portion of the residual signal sampled at .
  • the filter section is a plurality of first capacitors; a plurality of first switches that switch between whether or not to store electric charge in each of the plurality of first capacitors; Some of the first capacitors among the plurality of first capacitors accumulate electric charges according to the residual signal within the third period, During the first period and the second period, from the part of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period, charge is transferred to another first capacitor; The noise shaping signal may be generated by charge transferred to the further first capacitor.
  • the filter section is a first differential amplifier having a first differential input terminal to which the residual signal is input and a first differential output terminal to output a differential signal corresponding to the residual signal; a second differential amplifier having a second differential input terminal and a second differential output terminal, and outputting the differential noise shaping signal from the second differential output terminal;
  • the another first capacitor may be connected between the second differential input terminal and the second differential output terminal of the second differential amplifier.
  • a first chopper for periodically interchanging differential input signals input to at least one of the first differential input terminal of the first differential amplifier and the second differential input terminal of the second differential amplifier; , The differential output signal output from at least one of the first differential output terminal of the first differential amplifier and the second differential output terminal of the second differential amplifier is changed by switching the first chopper.
  • a second chopper that synchronizes and periodically replaces may also be provided.
  • the filter section is a plurality of first capacitors; a plurality of first switches that switch between whether or not to store electric charge in each of the plurality of first capacitors; Some of the first capacitors among the plurality of first capacitors accumulate electric charges according to the residual signal within the third period, During the first period and the second period, the accumulated charge of the part of the first capacitors that accumulated the residual signal in the third period of the immediately preceding sampling period is transferred to the part of the first capacitors.
  • the noise shaping signal may be generated by charge redistribution with another first capacitor.
  • Some of the first capacitors of the plurality of first capacitors store and transfer electric charges in each sampling period, and the remaining first capacitors perform one sampling period out of two successive sampling periods. may store and transfer charges.
  • the analog signal is a differential analog signal
  • two said digital-to-analog converters are provided for converting said differential analog signals to said differential digital signals
  • differential residual signals are output from the two digital-analog converters
  • the filter unit generates the differential noise shaping signal within the first period and the second period
  • the DAC controller may control the two digital-to-analog converters based on the differential residual signal and the differential noise shaping signal within the second period.
  • the DAC control unit controls the two digital-analog converters so that the sum of the signal difference of the differential residual signal and the signal difference of the differential noise shaping signal approaches zero. good too.
  • the DAC control unit a comparator that outputs a signal corresponding to the sum of the signal difference between the differential residual signals and the signal difference between the differential noise shaping signals; and a logic circuit for controlling the digital-analog converter based on the output signal of the comparator.
  • the digital-to-analog converter is a plurality of second capacitors to which the analog signal is supplied to one end of each or to which the residual signal is output from one end of each; a plurality of second switches for setting the other end side of the plurality of second capacitors to one of a plurality of voltages;
  • the DAC control section may switch-control the plurality of second switches based on the residual signal and the noise shaping signal.
  • the digital-to-analog converter is a plurality of second capacitors to which the analog signal is supplied to one end of each or to which the residual signal is output from one end of each; a plurality of second switches for setting the other end side of the plurality of second capacitors to one of a plurality of voltages;
  • the filter unit in the second period, divides a part of the residual signal sampled in the third period in the immediately preceding sampling period and the residual signal sampled in the third period in the sampling period two sampling periods before A portion of the signal may be charge redistributed with the plurality of second capacitors in the digital-to-analog converter to generate the noise shaping signal.
  • the filter section is a plurality of first capacitors; a plurality of first switches that switch between whether or not to store electric charge in each of the plurality of first capacitors; Some of the first capacitors among the plurality of first capacitors accumulate electric charges according to the residual signal within the third period, During the second period, the accumulated charges of the partial first capacitors that accumulated the residual signal in the third period of the immediately preceding sampling period are transferred to the filter section including the partial first capacitors. Charge redistribution between a first capacitor and the plurality of second capacitors may generate the noise shaping signal.
  • the analog signal is a differential analog signal
  • two said digital-to-analog converters are provided for converting said differential analog signals to said differential digital signals
  • differential residual signals are output from the two digital-analog converters
  • the filter unit generates the differential noise shaping signal within the second period
  • the DAC controller may control the two digital-to-analog converters based on the differential residual signal and the differential noise shaping signal within the second period.
  • At least some of the second capacitors among the plurality of second capacitors have a capacitance value obtained by multiplying a reference capacitance by a value less than a multiple of 2, and the remaining second capacitors are different from the reference capacitance. It may have a capacitance value that is a multiple of two or a power of two.
  • the plurality of second capacitors have a capacitance value that is a multiple of 2 with respect to the reference capacitance; Some two or more second capacitors among the plurality of second capacitors may have the same capacitance value.
  • the filter section may update the noise shaping signal in units of two consecutive sampling periods.
  • the first period may be shorter than the combined period of the second period and the third period.
  • an analog-to-digital converter that converts an analog signal to a digital signal within sampling periods that include consecutive first, second, and third time periods;
  • An electronic device comprising an information processing unit that performs information processing based on the digital signal,
  • the analog-to-digital converter is The analog signal is sampled within the first period, and the sampled signal is sequentially converted bit by bit into the digital signal with redundancy within the second period, and an unconverted residual is obtained.
  • a digital-to-analog converter that outputs a signal; sampling the residual signal within the third period, and at least within the second period, part of the residual signal sampled during the third period within the immediately preceding sampling period and the sampling period two sampling periods before a filter unit that performs charge transfer or charge redistribution to generate a noise shaping signal based on a portion of the residual signal sampled during the third period in a DAC controller that controls the digital-to-analog converter within the second period based on the residual signal and the noise shaping signal.
  • FIG. 1 is a block diagram showing a schematic configuration of an analog-digital converter according to a first embodiment; FIG. The figure which shows an example of CDAC which does not have a redundancy function.
  • FIG. 2 is a timing diagram of the ADC of FIG. 1;
  • FIG. 4 is a timing chart of ADC according to the first comparative example;
  • FIG. 4 is a timing chart of ADC according to a second comparative example;
  • FIG. 2 is a circuit diagram showing an example of the internal configuration of a filter section; Timing chart of the filter section. 2 is a flowchart showing processing operations of the ADC in FIG. 1;
  • FIG. 2 is a circuit diagram showing an example of the internal configuration of the logic circuit in FIG.
  • FIG. 1 4 is a state transition diagram of switches in the filter unit according to the first embodiment;
  • FIG. 4 is a state transition diagram of switches in the filter unit according to the first embodiment;
  • FIG. 4 is a state transition diagram of switches in the filter unit according to the first embodiment;
  • FIG. 4 is a state transition diagram of switches in the filter unit according to the first embodiment;
  • FIG. 2 is a circuit diagram showing a first example of a CDAC having a redundancy function; 11A and 11B are diagrams for explaining the AD conversion operation of the CDAC in FIG. 10;
  • FIG. 4 is a circuit diagram showing a second example of a CDAC having a redundancy function
  • FIG. 15 is a diagram for explaining the AD conversion operation of the CDAC in FIG. 14
  • FIG. 15 is a diagram for explaining the AD conversion operation of the CDAC in FIG. 14
  • FIG. 4 is a block diagram showing an example in which a chopper is connected to an integrating amplifier;
  • the circuit diagram which shows an example of an internal structure of a chopper.
  • FIG. 17 is an operation timing chart of the chopper of FIG. 16
  • FIG. 4 is a circuit diagram showing the internal configuration of a filter section within the ADC according to the second embodiment;
  • analog-digital converters and electronic devices will be described with reference to the drawings.
  • the analog-to-digital converter and the electronic device may have components and functions that are not illustrated or described. The following description does not exclude components or features not shown or described.
  • FIG. 1A is a block diagram showing a schematic configuration of an analog-to-digital converter (hereinafter referred to as ADC) 1 according to the first embodiment.
  • ADC analog-to-digital converter
  • FIG. 1A shows the fully differential circuit as single-ended for simplicity.
  • the ADC 1 of FIG. 1A repeats the process of converting an analog signal into a digital signal within sampling periods including consecutive first, second, and third periods over a plurality of sampling periods. Note that the first period is the sampling period of the input analog signal, the second period is the AD conversion period of the sampled analog signal, and the third period is the residual signal after the AD conversion is performed on a bit-by-bit basis. This is the sampling period.
  • the ADC 1 in FIG. 1A includes a sample switch 2, a capacitive DA converter (hereinafter sometimes referred to as CDAC) 3, a comparator 4, a logic circuit 5, a decoder 6, and a filter section (hereinafter L(z) ) 7 and a filter switch 8 .
  • CDAC capacitive DA converter
  • L(z) filter section
  • the sample switch 2 is turned on or off by the sample clock signal SAMPLE_CLK. For example, when the sample clock signal SAMPLE_CLK goes high, the sample switch 2 turns on and an external analog signal is input to the CDAC 3 .
  • the CDAC 3 samples the analog signal in the first period, converts the sampled signal into a digital signal sequentially bit by bit with redundancy in the second period, and converts the unconverted residual signal into a digital signal. Output.
  • the first period is a period during which the sample switch 2 is turned on and an analog signal is input to the CDAC 3 from the outside.
  • the sample switch 2 is turned on during the first period and turned off during the second and third periods.
  • FIG. 1B is a diagram showing an example of a CDAC 3 without redundant functions.
  • FIG. 1B shows an example of a fully differential ADC1.
  • a fully differential ADC 1 converts differentially input analog signals (hereinafter, also referred to as differential input signals) to AD 1-bit from the upper side by the corresponding CDAC 3 for each signal that constitutes the differential input signal.
  • unconverted residual signals from each CDAC are input to the comparator 4 , and based on the comparison determination signal of the comparator 4 , the logic circuit 5 controls AD conversion of the next bit of each CDAC 3 . AD conversion is thereby performed so that the output signal of the comparator 4 approaches zero.
  • the CDAC 3 of FIG. 1B has five capacitors C1 to C5 whose capacitance values differ by powers of 2 or multiples of 2, and three switches SW11 to SW13 connected to the capacitors C1 to C5, respectively.
  • capacitors C1 to C5 in CDAC 3 may be collectively referred to as second capacitors. Note that the filter unit 7 is omitted in FIG. 1B.
  • each of the capacitors C1 to C5 is connected to the input terminals of the sample switch 2 and the comparator 4 .
  • the switch SW11 switches whether to set one end of the capacitors C1 to C5 to 0V.
  • a switch SW12 switches whether or not to set the other ends of the capacitors C1 to C5 to the common voltage Vcom.
  • the switch SW13 switches whether to set one end of the capacitors C1 to C5 to the reference voltage Vref.
  • the common voltage Vcom is, for example, half the voltage level of the reference voltage Vref.
  • the switches SW11 to SW13 are switched on or off based on the control signal from the logic circuit 5.
  • the logic circuit 5 turns on the switch SW12 within the sampling period (first period).
  • the logic circuit 5 turns on the switch SW11 when the output voltage of the CDAC3 is to be decreased, and turns on the switch SW13 when the output voltage of the CDAC3 is to be increased.
  • the filter unit 7 in FIG. 1 samples the residual signal within the third period, and at least within the second period, part of the residual signal sampled during the third period within the immediately preceding sampling period, and two Based on a portion of the residual signal sampled during a third period within the previous sampling period, charge transfer or charge redistribution is performed to produce a noise shaping signal.
  • charge transfer or charge redistribution is performed to produce a noise shaping signal.
  • the residual signal output from the CDAC 3 and the noise shaping signal output from the filter section 7 are input to the comparator 4 .
  • the ADC 1 according to this embodiment is composed of a fully differential circuit as shown in FIG. 1B, and the comparator 4 actually receives a differential residual signal and a differential noise shaping signal be done.
  • the comparator 4 outputs a signal corresponding to the sum of the signal difference between the differential residual signals and the signal difference between the differential noise shaping signals.
  • the logic circuit 5 feedback-controls the CDAC 3 so that the sum of the signal difference of the differential residual signal and the signal difference of the differential noise shaping signal input to the comparator 4 approaches zero.
  • the logic circuit 5 also supplies the comparator 4 with a control signal EN_COMP for controlling the timing at which the comparator 4 performs the comparison operation.
  • the comparator 4 performs a comparison operation, for example, when the control signal EN_COMP is at high level. Since the comparator 4 stops the comparison operation when the control signal EN_COMP is at low level, power consumption can be reduced.
  • the comparator 4 and the logic circuit 5 are sometimes collectively referred to as the DAC control section 9.
  • the DAC controller 9 controls the CDAC 3 within the second period based on the residual signal and the noise shaping signal.
  • FIG. 2 is a timing diagram of ADC1 in FIG. 1, showing the timing of each signal within one sampling period.
  • Time t1 to t2 in FIG. 2 is an analog signal sampling period (first period).
  • Time t2 to t3 is an AD conversion period (second period) of the sampled analog signal.
  • Time t3 to t4 is a sampling period (third period) of the residual voltage by the filter section .
  • One sampling period is from time t1 to t4, and the sampling period from time t1 to t4 is repeated.
  • the ratio of the length of the first period from time t1 to t2 to the length of the second and third periods from time t2 to t4 is set to 1:2, for example.
  • FIG. 2 shows timings of the sample clock signal SAMPLE_CLK, the control signal EN_COMP, the control signal CONV_END, and the output signal of the integration amplifier 12 in the filter section 7, which will be described later, in one sampling period.
  • the filter section 7 has a capacitor group and an integrating amplifier 12 therein, and the residual signal of the CDAC 3 is transferred to the filter section 7 during a third period from time t3 to t4. are sampled on some capacitors.
  • the capacitor group in the filter section 7 may be called a plurality of first capacitors. A portion of the first capacitors in the filter section 7 accumulate charges according to the residual signal of the CDAC 3 within the third period.
  • the filter unit 7 selects part of the residual signal sampled in the third period in the immediately preceding sampling period and A part of the residual signal sampled in the third period is transferred to the integrating amplifier 12 to generate a noise shaping signal.
  • the transfer of charges from some of the first capacitors in the filter section 7 to the integration amplifier 12 is sometimes referred to as total charge transfer.
  • the filter switch 8 in FIG. 1 is turned on or off by the control signal CONV_END.
  • the filter switch 8 is turned on when the control signal CONV_END is high, and the filter switch 8 is turned off when the control signal CONV_END is low.
  • the filter switch 8 is turned on, the residual signal is input to the filter section 7 . Since the control signal CONV_END is turned on during the third period, the filter section 7 samples the residual signal during the third period.
  • a second period from time t2 to t3 is an AD conversion period for the sampled analog signal, and AD conversion is performed bit by bit from the upper bit, and the residual signal changes with time. Further, during the second period, all charges are transferred inside the filter section 7, so the noise shaping signal output from the integration amplifier 12 in the filter section 7 also changes with time.
  • a solid-line waveform shows how the output signal of the integration amplifier 12 in the filter section changes over time during the period from time t2 to t3. As a result, the comparison determination result of the comparator 4 also fluctuates, and the CDAC 3 may erroneously select the switch.
  • the CDAC 3 is provided with redundancy. , the error can be correctly corrected.
  • the redundancy of CDAC3 will be described later.
  • FIG. 3 is a timing chart of ADC1 according to the first comparative example.
  • the length of the first period from time t1 to t2 and the length of the second and third periods from time t2 to t4 are approximately 1:1.
  • the first period from time t1 to t2 can be made longer than in FIG.
  • the comparison decision of the comparator 4 is not affected by the all charge transfer in the filter section 7, and the CDAC 3 are less likely to make the wrong switch choice.
  • the sampling of the residual signal by the filter unit 7 that is performed may be imperfect. If the sampling of the residual signal is imperfect, AD conversion accuracy and SNDR may deteriorate.
  • FIG. 4 is a timing chart of ADC1 according to the second comparative example.
  • the ratio of the length of the period from time t1 to t2 to the length of the period from time t2 to t4 is, for example, 1:2, as in FIG. Therefore, even if the AD conversion process from time t2 to t3 takes a long time, sampling of the residual signal by the filter unit 7 during the third period from time t3 to t4 can be correctly performed.
  • FIG. 4 it is necessary to transfer all charges to the integration amplifier 12 in the filter section 7 during the sampling period from time t1 to t2. Therefore, there is a possibility that all charge transfer will not be completed by time t2 and will be insufficient, making it impossible to perform noise shaping normally.
  • all charges are transferred to the integrating amplifier 12 during the time t1 to t3 (first period+second period).
  • the noise shaping signal can be output after ensuring sufficient charge transfer and correct transfer of all charges.
  • FIG. 5 is a circuit diagram showing an example of the internal configuration of the filter section 7.
  • FIG. 5 includes a buffer 11, a plurality of first capacitors CA, CB1, CB2, a plurality of switches (first switching units) SW1 to SW6, and an integrating amplifier 12.
  • FIG. The filter section 7 in FIG. 5 is an active filter section 7 since it has the integration amplifier 12 .
  • the buffer 11 has a differential input terminal and a differential output terminal, and the differential residual signal output from the CDAC 3 is input to the differential input terminal. output the dynamic residual signal.
  • the filter section 7 has a capacitor group 7g consisting of three capacitors CA, CB1, and CB2 and six switches SW1 to SW6 for each signal that constitutes the differential signal. Since the capacitance values of the three capacitors CA, CB1, CB2 and the switching timings of the switches SW1 to SW6 are symmetrical, the symmetrical capacitors CA, CB1, CB2, CC and the switches SW1 to SW6 in FIG. attached. The switches SW1 to SW6 are switch-controlled by switch control signals ⁇ 1 to ⁇ 6.
  • the integration amplifier 12 has a differential input/differential output differential amplifier 12a and two capacitors CC connected between the differential input terminal and the differential output terminal of the differential amplifier 12a.
  • a switch SW1 switches whether to sample one of the signals constituting the differential signal to the capacitor CA.
  • the switch SW2 switches whether or not to sample one of the signals constituting the differential signal to the capacitor CB1.
  • the switch SW3 switches whether to sample one signal constituting the differential signal to the capacitor CB2.
  • a switch SW4 switches whether to transfer the charge stored in the capacitor CA to the capacitor CC.
  • a switch SW5 switches whether to transfer the charge accumulated in the capacitor CB1 to the capacitor CC.
  • a switch SW6 switches whether to transfer the charge accumulated in the capacitor CB2 to the capacitor CC.
  • FIG. 6 is a timing chart of the filter section 7.
  • FIG. A switching period of the switches SW1 to SW6 in the filter section 7 corresponds to two sampling periods of the ADC1. Therefore, FIG. 6 shows two sampling periods of ADC1.
  • Time t1 to t2 and time t4 to t5 are the first period (analog signal sampling period), time t2 to t3 and time t5 to t6 are the second period (AD conversion period), time t3 to t4 and time t6 to t7 This is the third period (residual signal sampling period).
  • times t1 to t4 are called a first sampling period
  • times t4 to t7 are called a second sampling period.
  • FIG. 6 shows timings for two sampling cycles of the sample clock signal SAMPLE_CLK, the control signal EN_COMP, the control signal CONV_END, and the switch control signals ⁇ 1 to ⁇ 6. 6 also shows the switching states of the switches SW1 to SW6 in the filter section 7. As shown in FIG. In FIG. 6, for the sake of simplification, three capacitors CA, CB1, and CB2 connected to one signal forming the differential signal in the filter section 7, switches SW1 to SW6, and one of the integration amplifier 12 Only capacitor CC is shown.
  • FIG. 1 The stored charge on capacitor CA is part of the residual signal sampled in the sampling period immediately preceding the first sampling period, and the stored charge on capacitor CB1 is sampled in the second sampling period before the first sampling period. is part of the residual signal.
  • FIG. 1 The accumulated charge on capacitor CA is part of the residual signal sampled in the first sampling period immediately preceding the second sampling period, and the accumulated charge on capacitor CB2 is the portion of the residual signal sampled in the first sampling period immediately preceding the second sampling period. A portion of the sampled residual signal.
  • both the first period and the second period are used, so that all the charges are transferred.
  • the capacitor CA in the filter section 7 accumulates and transfers electric charges in each sampling period, while the capacitors CB1 and CB2 alternately accumulate and transfer electric charges in each sampling period.
  • the noise shaping signal can be generated by the filter unit 7, and the generated noise shaping signal can be used to control the CDAC 3, thereby improving AD conversion accuracy and SNDR. .
  • the ratio of the length of time t1-t2 (first period) and the length of time t2-t4 (second and third periods) is, for example, 1:2, and the residual signal of time t3-t4 is sampled. Since the period for sampling is also sufficiently long, a sufficient sampling period for the residual signal can be ensured.
  • FIG. 7 is a flowchart showing the processing operation of ADC1 in FIG. 1, and shows the processing operation in two sampling cycles, like the timing chart in FIG.
  • a variable n is initialized to zero, and an externally input analog signal is sampled (step S1).
  • Step S1 shows the operation from time t1 to t2 (first period) in FIG.
  • a variable n is a variable that counts the number of times the comparator 4 performs comparison determination.
  • Step S2 an AD conversion operation is performed based on the comparison determination of the comparator 4 (step S2).
  • Steps S2 to S4 show the operation during times t2 to t3 (second period) in FIG.
  • the variable n is incremented by 1 (step S3).
  • step S5 shows the operation from time t3 to t4 (third period) in FIG.
  • steps S1 to S5 are performed during the first sampling period from time t1 to t4 in FIG. Subsequently, when entering the second sampling period, the variable n is initialized to zero and the externally input analog signal is sampled (step S6), as in step S1. Step S6 shows the operation from time t4 to t5 (first period) in FIG.
  • Step S7 an AD conversion operation is performed based on the comparison determination of the comparator 4 (step S7).
  • Steps S7 to S9 show the operation from time t5 to t6 (second period) in FIG.
  • the variable n is incremented by 1 (step S8).
  • step S10 shows the operation from time t6 to t7 (third period) in FIG.
  • FIG. 8 is a circuit diagram showing an example of the internal configuration of the logic circuit 5 of FIG.
  • the logic circuit 5 of FIG. 8 has a NOR gate 21, a shift register 22, inverters 23 and 24, AND gates 25 and 26, and pulse generation circuits 27 and 28.
  • the NOR gate 21 performs a NOR operation on the differential output signals of the comparator 4.
  • the shift register 22 is configured, for example, by cascade-connecting a plurality of flip-flops (hereinafter referred to as F/Fs), and the output signal of the NOR gate 21 is supplied to the clock terminal of each F/F. .
  • F/Fs flip-flops
  • each F/F in the shift register 22 sequentially propagates a high level signal each time the output signal of the NOR gate 21 changes from low level to high level.
  • the number of F/F stages in the shift register 22 is the number of bits of the physical resolution of the ADC1.
  • the control signal CONV_END is the output signal of the F/F at the final stage.
  • the control signal CONV_END goes high during the third period of sampling the residual signal, as shown in FIG.
  • a control signal CONV_END is used to turn the filter switch 8 on or off.
  • the filter switch 8 is turned on when the control signal CONV_END is at high level.
  • the filter unit 7 takes the differential residual signal output from the CDAC 3 into the buffer 11 and samples it with the capacitor CA and the capacitor CB1 or CB2.
  • the AND gate 25 outputs the AND signal of the signal obtained by inverting the control signal CONV_END by the inverter 23 and the output signal of the NOR gate 21 .
  • the output signal of the AND gate 25 temporarily becomes high level each time the output signal of the comparator 4 becomes low level during the second period.
  • the output signal of AND gate 25 is input to the control terminal of comparator 4 .
  • the comparator 4 performs the comparison determination operation only while the output signal of the AND gate 25 is at high level. With such control, the comparator 4 performs comparison determination only when the CDAC 3 performs AD conversion for each bit.
  • the pulse generation circuit 27 generates switch control signals ⁇ 1 to ⁇ 3 based on the sample clock signal SAMPLE_CLK and the output signal of the AND gate 26.
  • AND gate 26 outputs a logical product signal of a signal obtained by inverting sample clock signal SAMPLE_CLK by inverter 24 and control signal CONV_END.
  • the pulse generation circuit 28 generates switch control signals ⁇ 4 to ⁇ 6 based on the sample clock signal SAMPLE_CLK and the control signal CONV_END.
  • FIG. 9A, 9B, 9C and 9D are state transition diagrams of the switches SW1 to SW6 in the filter section 7.
  • FIG. 9A, 9B, 9C and 9D are state transition diagrams of the switches SW1 to SW6 in the filter section 7.
  • the switch control signal ⁇ 1 transitions from low level to high level when the sample clock signal SAMPLE_CLK is at low level and the control signal CONV_END is at high level, and the switch SW1 transitions from off to on. do.
  • the switch control signal ⁇ 1 transitions from high level to low level, and the switch SW1 transitions from on to off.
  • the switch control signal ⁇ 5 transitions from low level to high level, and the switch control signal ⁇ 6 remains low level. Therefore, the switch SW5 transitions from off to on, and the switch SW6 remains off.
  • the switch control signal ⁇ 5 transitions from high level to low level, and the switch control signal ⁇ 6 remains at low level. Therefore, the switch SW5 transitions from high level to low level, and the switch SW6 remains off.
  • the ADC 1 uses not only the analog signal sampling period (first period) but also the AD conversion period (second period) to to the integration amplifier 12. Therefore, the noise shaping signal output from the filter section 7 and input to the comparator 4 changes during AD conversion, and an error may occur in the AD conversion. Therefore, the CDAC 3 according to this embodiment has a redundancy function so that even if an error occurs in AD conversion, the error can be corrected. Since the CDAC 3 has a redundancy function, it can perform AD conversion with redundancy, and even if an error occurs during AD conversion, it can automatically correct the error.
  • FIG. 10 is a circuit diagram showing a first example of CDAC 3 having a redundant function.
  • the CDAC 3 of FIG. 10 has a capacitor group 10a made up of a plurality of capacitors each having a different capacitance value (which may be referred to as second capacitors in this specification), and a plurality of switches 10b.
  • the plurality of second capacitors have different capacitance values, but at least some of the second capacitors have capacitance values that are multiples of 2 or powers of 2 with respect to the reference capacitance value, while the remaining second capacitors It has a capacitance value obtained by multiplying the reference capacitance value by a value less than a multiple of two.
  • FIG. 10 is a circuit diagram showing a first example of CDAC 3 having a redundant function.
  • the CDAC 3 of FIG. 10 has a capacitor group 10a made up of a plurality of capacitors each having a different capacitance value (which may be referred to as second capacitors in this specification), and a plurality of switches 10
  • three of the six capacitors have capacitance values of 1C, 2C, and 4C with a reference capacitance value of C, while the remaining three capacitors have capacitance values of 7C, 12C, and 23C. It has a capacitance value.
  • the ratio between the number of second capacitors having a capacitance value that is a multiple of 2 or a power of 2 and the number of second capacitors having a capacitance value that is less than a multiple of 2 is arbitrary.
  • FIG. 11 is a diagram explaining the AD conversion operation of the CDAC 3 in FIG. If the most significant bit of CDAC3 is zero for the analog input signal, the output signal level LV1 of CDAC3 will be lower than the analog input signal level. Therefore, 1 is selected in the second bit from the uppermost bit, and the output signal level LV2 of CDAC 3 becomes higher than the analog input signal level. Therefore, 0 is selected in the third bit from the highest order, and the output signal level LV3 of CDA becomes lower than the analog input signal level. For this reason, it is supposed that 1 is selected in the fourth bit from the uppermost bit, but 0 is selected by mistake. In this case, the output signal level LV4 of CDAC3 becomes a voltage level lower than the output signal level LV3.
  • the capacitance value of the capacitor corresponding to the upper bit of the CDAC 3 is the capacitance value obtained by multiplying the reference capacitance value by a value smaller than a multiple of 2, even if the AD conversion is erroneous on the way, the correct AD conversion will be performed later.
  • the error can be reduced little by little, and finally a correct digital value is obtained as shown in FIG. 11, and the residual signal is also reduced.
  • FIG. 12 is a circuit diagram showing the internal configuration of the CDAC 3 according to a comparative example.
  • a plurality of capacitors in the CDAC 3 of FIG. 12 have capacitance values that are powers of 2 times the reference capacitance value.
  • FIG. 13 is a diagram explaining the AD conversion operation of the CDAC3 in FIG. FIG. 13, like FIG. 11, shows an example in which the AD conversion operation is erroneous at the 4th bit from the high order. In this case, even if correct AD conversion is performed after the 5th bit, the finally obtained digital signal will be a value that is 0.5 LSB or more away from the AD conversion value of the original analog input signal, and the residual signal will also be growing.
  • FIG. 14 is a circuit diagram showing a second example of CDAC3 having a redundant function.
  • the CDAC 3 of FIG. 14 has a plurality of capacitors C0 to C11, and each capacitor C0 to C11 has a capacitance value that is a power of 2 times the reference capacitance value C0.
  • the plurality of capacitors C0 to C11 include a plurality of capacitors C1, C1R and capacitors C6, C6R having the same capacitance value.
  • two capacitors C1 and C1R each having a capacitance value of 2C0 and two capacitors C6 and C6R each having a capacitance value of 64C0 are provided.
  • switches connected to a plurality of capacitors are omitted in FIG. 14, switches similar to those in FIG. 10 are actually connected to each capacitor.
  • FIG. 15A and 15B are diagrams for explaining the AD conversion operation of the CDAC3 in FIG.
  • FIG. 15A shows the AD conversion operation by the capacitors C4 to C8 within the dashed frame in FIG.
  • the intermediate voltage level of the output signal VR1 of the CDAC 3 before AD conversion of the bit corresponding to the capacitor C8 in FIG. 14 is lower than the analog input signal level. Therefore, the bit corresponding to capacitor C8 will be 1 and the intermediate voltage level of output signal VR2 of CDAC 3 will be higher than the analog input signal level. Therefore, the bit corresponding to the capacitor C7 should be 0, but it is erroneously set to 1. In this case, the intermediate voltage level of output signal VR3 of CDAC3 is higher than the analog input signal level. Therefore, the bit corresponding to capacitor C6 is 0.
  • the intermediate voltage level of the output signal VR4 of CDAC3 becomes higher than the analog input signal level. Therefore, the bit corresponding to capacitor C6R becomes 0.
  • the intermediate voltage level of output signal VR5 of CDAC3 becomes lower than the analog input signal level. Therefore, the bit corresponding to capacitor C5 will be 1.
  • the intermediate voltage level of output signal VR6 of CDAC3 becomes higher than the analog input signal level. Therefore, the bit corresponding to capacitor C4 is 0.
  • the error can be relieved by providing a plurality of capacitors having the same capacitance value, and the accuracy of the finally obtained digital value can be maintained.
  • FIG. 15B is a diagram explaining the AD conversion operation when the analog input signal level is lower than that in FIG. 15A.
  • the intermediate voltage level of the output signal VR1 of the CDAC 3 before AD conversion of the bit corresponding to the capacitor C8 in FIG. 15 is higher than the analog input signal level. Therefore, the bit corresponding to capacitor C8 becomes 0, and the intermediate voltage level of output signal VR2 of CDAC3 becomes lower than the analog input signal level. Therefore, suppose that the bit corresponding to the capacitor C7 should be 1, but is erroneously set to 0. In this case, the intermediate voltage level of output signal VR3 of CDAC3 is lower than the analog input signal level. Therefore, the bit corresponding to capacitor C6 is 1.
  • the bit corresponding to capacitor C6R becomes 1.
  • the intermediate voltage level of the output signal VR5 of CDAC3 becomes higher than the analog input signal level. Therefore, the bit corresponding to capacitor C5 will be 0.
  • the intermediate voltage level of output signal VR6 of CDAC3 becomes lower than the analog input signal level. Therefore, the bit corresponding to capacitor C4 is 1.
  • FIGS. 15A and 15B even if AD conversion is erroneous in some bits in the CDAC 3 regardless of the analog input signal level, the error can be corrected by providing a plurality of capacitors having the same capacitance value. can be rescued.
  • the ADC 1 is a fully differential SAR ADC 1 that AD-converts differential analog signals and outputs differential digital signals.
  • a chopper is a through mode in which a switch group is connected to the differential input terminal and the differential output terminal of a differential input and differential output amplifier to pass through the differential input signal and the differential output signal.
  • a cross mode for crossing each of the dynamic input signal and the differential output signal is periodically interlocked and switched. In the second mode, since the differential input side and the differential output side are synchronous and the differential signals are crossed, no problem occurs in signal transmission.
  • FIG. 16 is a block diagram showing an example in which choppers 31 and 32 are connected to differential input terminals and differential output terminals of at least one of the buffer 11 and integrating amplifier 12 in the filter section 7, respectively.
  • the left side of FIG. 16 schematically shows a through mode signal transmission path, and the right side schematically shows a cross mode signal transmission path.
  • FIG. 17 is a circuit diagram showing an example of the internal configuration of choppers 31 and 32.
  • FIG. Choppers 31 and 32 of FIG. 17 have four switches SW16 to SW19 arranged between differential input terminals TL1 and TL2 and differential output terminals TL3 and TL4.
  • a switch SW16 switches whether to short-circuit the terminals TL1 and TL3.
  • a switch SW17 switches whether to short-circuit the terminals TL3 and TL4.
  • a switch SW18 switches whether to short-circuit the terminals TL1 and TL4.
  • a switch SW19 switches whether to short-circuit the terminals TL2 and TL3.
  • FIG. 18 is an operation timing chart of choppers 31 and 32 in FIG. As shown, the chopper alternates between through mode and cross mode. During the through mode, the switches SW16 and SW17 in FIG. 17 are turned on and the switches SW18 and SW19 are turned off. Further, during the cross code, the switches SW16 and SW17 in FIG. 17 are turned off and the switches SW18 and SW19 are turned on. It is desirable to make the periods of through mode and cross mode equal.
  • the choppers 31 and 32 By providing the choppers 31 and 32, the low-frequency noise of the SAR ADC 1 can be shifted to the high-frequency side, and as a result, the flicker noise can be reduced.
  • the period for sampling the analog signal and the period for AD converting the sampled analog signal are used to transfer from the capacitor group 7g in the filter section 7 to the integrating amplifier 12.
  • a full charge transfer is performed to generate the noise shaping signal. This ensures sufficient time for all charge transfers. If all charges are transferred to the integration amplifier 12 in the filter section 7 during the AD conversion period, the output signal of the integration amplifier 12 in the filter section 7 fluctuates during AD conversion, causing an error in the AD conversion by the CDAC 3. There is a risk.
  • the CDAC 3 according to the present embodiment has a redundancy function, even if an error occurs in the AD conversion operation, the error can be corrected by performing AD conversion with redundancy in the CDAC 3, and finally can maintain the accuracy of the digital signal obtained in
  • the ADC 1 according to the first embodiment includes an active filter section 7 having an integral amplifier 12, but it is also possible to configure the ADC 1 using a passive filter section 7a that does not have an integral amplifier 12. .
  • the ADC 1a according to the second embodiment has the same configuration as the ADC 1 in FIG. 1, but the internal configuration of the filter section 7a is different from the filter section 7 in the ADC 1 in FIG.
  • FIG. 19 is a circuit diagram showing the internal configuration of the filter section 7a within the ADC 1a according to the second embodiment.
  • the filter unit 7a of FIG. 19 has capacitors CA, CB1, CB2, and CC and switches SW21 to SW24 for each signal constituting the differential signal on the rear stage side of the differential input and differential output buffer 11. .
  • Switches SW21 and SW22 are connected in series between the output node of the buffer 11 and the output node of the filter section .
  • a capacitor CA is connected between the common connection node of the switches SW21 and SW24 and the ground node.
  • a switch SW23 and a capacitor CB1 are connected in series between a common connection node of the switches SW21 and SW22 and a ground node.
  • a switch SW24 and a capacitor CB2 are connected in series between a common connection node of the switches SW21 and SW22 and a ground node.
  • a capacitor CC is connected between the output node of the filter section 7 and the ground node.
  • FIG. 20 is a timing chart of ADC1a according to the second embodiment.
  • the switching period of the switches SW1 to SW6 in the filter section 7a in FIG. 19 corresponds to two sampling periods (first sampling period and second sampling period) of the ADC 1a, as in FIG.
  • the switches SW22 and SW23 in the filter section 7a are turned on, and the other switches are turned off.
  • the charge stored in capacitors CA and CB1 is charge redistributed in capacitors CA, CB1, and CC.
  • the noise shaping signal output from the filter section 7a may fluctuate and the capacitor in the CDAC 3 may be selected erroneously.
  • the CDAC 3 by providing the CDAC 3 with a redundant function, it is possible to prevent the deterioration of AD conversion accuracy.
  • the capacitor CA in the filter section 7a is used for sampling the residual signal every sampling period, while the capacitors CB1 and CB2 are alternately used for sampling every sampling period.
  • Capacitor CC is also used for charge redistribution every sampling period.
  • FIG. 21 is a flow chart showing the processing operation of the ADC 1a according to the second embodiment, and shows the processing operation in two sampling periods, like the timing chart of FIG.
  • a variable n is initialized to zero, and an externally input analog signal is sampled (step S11).
  • Step S11 shows the operation from time t1 to t2 (first period) in FIG.
  • a variable n is a variable that counts the number of times the comparator 4 performs comparison determination.
  • Step S12 an AD conversion operation is performed based on the comparison determination of the comparator 4 (step S12).
  • Steps S12 to S14 show the operation during times t2 to t3 (second period) in FIG.
  • the variable n is incremented by 1 (step S13).
  • step S15 shows the operation from time t3 to t4 (third period) in FIG.
  • Step S11 to S15 are performed during the first sampling period from time t1 to t4 in FIG. Subsequently, when entering the second sampling period, the variable n is initialized to zero as in step S11, and the externally input analog signal is sampled (step S16). Step S16 shows the operation from time t4 to t5 (first period) in FIG.
  • Step S17 an AD conversion operation is performed based on the comparison determination of the comparator 4 (step S17).
  • Steps S17 to S9 show the operation during times t5 to t6 (second period) in FIG.
  • the variable n is incremented by 1 (step S18).
  • step S19 When it is determined in step S19 that the variable n has reached N, the residual signal output from the CDAC 3 is sampled in the capacitors CA and CB2 in the filter section 7a (step S20).
  • Step S20 shows the operation from time t6 to t7 (third period) in FIG.
  • the logic circuit 5 has the same internal configuration as that of FIG. It outputs control signals ⁇ 1 to ⁇ 6.
  • 22A, 22B and 22C are state transition diagrams of the switches SW1 to SW6 in the filter section 7a.
  • the switch control signal ⁇ 1 transitions from low level to high level when the sample clock signal SAMPLE_CLK is at low level and the control signal CONV_END is at high level, and the switch SW1 transitions from off to on. do.
  • the switch control signal ⁇ 1 transitions from high level to low level, and the switch SW1 transitions from on to off.
  • the switch control signal ⁇ 2 transitions from low level to high level when the sample clock signal SAMPLE_CLK is at high level or the control signal CONV_END is at low level, and the switch SW2 transitions from off to on. do. Thereafter, when the sample clock signal SAMPLE_CLK is at low level and the control signal CONV_END is at high level, the switch control signal ⁇ 2 transitions from high level to low level, and the switch SW2 transitions from on to off.
  • the switch control signal ⁇ 3 transitions from high level to low level, and the switch control signal ⁇ 4 transitions from low level to high level. Therefore, the switch SW23 transitions from ON to OFF, and the switch SW24 transitions from OFF to ON.
  • the switch control signal ⁇ 3 transitions from low level to high level, and the switch control signal ⁇ 4 transitions from high level to low level. Therefore, the switch SW23 transitions from off to on, and the switch SW24 transitions from on to off.
  • the ADC 1a according to the second embodiment can be configured in the same manner as the ADC 1 according to the first embodiment, except that it includes a passive filter section 7a.
  • CDAC3 has a redundancy function as shown in FIGS. 10-15B.
  • a chopper shown in FIG. 16 may be provided.
  • the ADC 1a includes the passive filter unit 7a. Since charge redistribution is performed within the portion 7a, sufficient time for charge redistribution can be secured. By performing charge redistribution during the AD conversion period, there is a risk of erroneous selection of capacitors in the CDAC 3, but by providing the CDAC 3 with a redundant function, there is no risk of deterioration in AD conversion accuracy.
  • the differential residual signal output from the CDAC 3 and the differential noise shaping signal output from the filter section 7 are input to the comparator 4.
  • a comparator 4 for comparing and judging motion signals is required.
  • the SAR ADC 1b synthesizes the differential noise shaping signal output from the filter section 7b with the output signal of the CDAC 3 and inputs it to the comparator 4.
  • the comparator 4 that performs comparison and determination of one system of differential signals can be used.
  • FIG. 23 is a block diagram showing a schematic configuration of ADC 1b according to the third embodiment.
  • the same reference numerals are assigned to the same components as in FIG. 1, and the following description will focus on the differences.
  • the ADC 1b in FIG. 23 includes a sample switch 2, a CDAC 3, a comparator 4, a logic circuit 5, a decoder 6, a filter section (L(z)) 7b, and a filter switch 8, similarly to the ADIC in FIG. 1A. It has In addition, the ADC 1b in FIG. 23 has an adder 10. FIG.
  • the adder 10 updates the residual signal of the CDAC 3 by performing charge redistribution between the capacitors in the filter section 7 and the capacitors in the CDAC 3 .
  • the ADC 1b in FIG. 23 feeds back the noise shaping signal output from the filter section 7b to the residual signal of the CDAC 3, so it can be called an error feedback SAR ADC 1b.
  • the differential signal of the residual signal of the CDAC 3, which is subjected to error feedback, is input to the comparator 4 of FIG. In this manner, the comparator 4 in FIG. 23 receives a single differential input signal instead of two, so that the internal configuration of the comparator 4 can be simplified.
  • the filter section 7b in FIG. 23 has an internal configuration different from that of the filter section 7 in FIG. 1, and the filter section 7b in FIG. The internal configuration of the filter section 7b in FIG. 23 will be described later.
  • ADC 1b in FIG. 23 shows an example in which a single-ended analog signal is input through sample switch 2, but in reality, like ADC 1 according to the first and second embodiments, a fully differential type is the ADC1 of
  • FIG. 24 is a timing chart of ADC1b in FIG. 23, showing the timing of each signal within one sampling period.
  • ADC1b of FIG. 23 the residual signal sampled in a part of capacitor group 7g in filter section 7b is transferred to capacitors in CDAC3 during the period (second period) from time t2 to t3 in FIG. Allocate.
  • the slight change in the voltage VCOPM from the holding voltage level in the first half of time t2 to t3 is due to the charge redistribution described above.
  • the residual signal input to the comparator 4 fluctuates during the AD conversion, and there is a risk of erroneous selection of the capacitor in the CDAC 3 .
  • the CDAC 3 by providing the CDAC 3 with a redundancy function, errors can be corrected, so AD conversion accuracy can be maintained.
  • FIG. 25 is a timing chart according to a comparative example.
  • FIG. 25 shows that the charge accumulated in the capacitor in the filter section 7b is transferred to the capacitor in the filter section 7b during the period (first period) during which the analog signal is sampled and the period (second period) during which the AD conversion is performed. and the capacitor in the CDAC 3, a period (hereinafter referred to as a fourth period) is provided.
  • the length of the first period to the third period is equal to the length of the fourth period. must be shortened, and there is a possibility that the AD conversion precision will be lowered or the SNDR will be deteriorated.
  • FIG. 26 is a circuit diagram showing an example of the internal configuration of the filter section 7b of FIG.
  • the filter unit 7b shown in FIG. 26 includes a buffer 11 for differential input and differential output, and switches SW31, SW32a, SW32b, SW33a, SW33b, SW34a, SW34b, SW35a, It has SW35b, SW36a and SW36b and capacitors CA, CB1 and CB2.
  • the switches SW31 and SW34 are connected in series between the output node of the buffer 11 and the output node of the filter section 7b, and the capacitor CA is connected between the common connection node of these switches SW31 and SW34 and the ground node. .
  • the switches SW32a and SW35a are connected in series between the output node of the buffer 11 and the ground node.
  • the switches SW35b and SW32b are connected in series between the output node of the filter section 7b and the ground node.
  • a capacitor CB1 is connected between a common connection node of the switches SW32a and SW35a and a common connection node of the switches SW32b and SW35b.
  • the switches SW33a and SW36a are connected in series between the output node of the buffer 11 and the ground node.
  • the switches SW36b and SW33b are connected in series between the output node of the filter section 7b and the ground node.
  • a capacitor CB2 is connected between a common connection node of the switches SW33a and SW36a and a common connection node of the switches SW33b and SW36b.
  • the switch SW31 receives the switch control signal ⁇ 1, the switches SW32a and SW32b use the switch control signal ⁇ 2, the switches SW33a and SW33b use the switch control signal ⁇ 3, the switch SW34 uses the switch control signal ⁇ 4, and the switches SW35a and SW35b use the switch control signal ⁇ 5. , and the switches SW36a and SW36b are switch-controlled by a switch control signal ⁇ 6.
  • FIG. 27 is a timing chart of the filter section 7b in FIG.
  • the switching period of the switches SW1 to SW6 in the filter section 7b in FIG. 23 corresponds to two sampling periods (first sampling period and second sampling period) of the ADC 1b, as in FIG.
  • All the switches in the filter section 7b are in the OFF state during times t4 to t5 (first period) within the second sampling period. As a result, the charges stored in the capacitors CA, CB1 and CB2 in the filter section 7b are held as they are.
  • FIG. 28 is a flow chart showing the processing operation of the ADC 1b in FIG. 23, and shows the processing operation in two sampling periods, like the timing chart in FIG.
  • a variable n is initialized to zero, and an externally input analog signal is sampled (step S21).
  • Step S21 shows the operation from time t1 to t2 (first period) in FIG.
  • a variable n is a variable that counts the number of times the comparator 4 performs comparison determination.
  • Step S22 an AD conversion operation is performed based on the comparison determination of the comparator 4 (step S22).
  • Steps S22 to S24 show the operation during times t2 to t3 (second period) in FIG.
  • the variable n is incremented by 1 (step S23).
  • step S24 When it is determined in step S24 that the variable n has reached N, the residual signal output from the CDAC 3 is sampled in the capacitors CA and CB1 in the filter section 7b (step S25).
  • Step S25 shows the operation from time t3 to t4 (third period) in FIG.
  • Step S21 to S25 are performed during the first sampling period from time t1 to t4 in FIG. Subsequently, in the second sampling period, similarly to step S21, the variable n is initialized to zero, and the externally input analog signal is sampled (step S26). Step S26 shows the operation from time t4 to t5 (first period) in FIG.
  • Step S27 an AD conversion operation is performed based on the comparison determination of the comparator 4 (step S27).
  • Steps S27 to S29 show the operation during time t5 to t6 (second period) in FIG.
  • the variable n is incremented by 1 (step S28).
  • step S29 it is determined whether or not the variable n has reached the number of bits N of the physical resolution of the ADC 1b (step S29). If the variable n has not reached N, the process returns to step S22. While the processing of steps S26 to S29 is being executed, the charges in the capacitors CA and CB2 in the filter section 7b are redistributed to each capacitor in the CDAC3.
  • step S30 shows the operation from time t6 to t7 (third period) in FIG.
  • FIG. 29 is a circuit diagram showing an example of the internal configuration of the logic circuit 5 of FIG.
  • the logic circuit 5 of FIG. 29 has basically the same circuit configuration as the logic circuit 5 of FIG.
  • the pulse generation circuits 27 and 28 in the logic circuit 5 of FIG. 29 output switch control signals ⁇ 1 to ⁇ 6 at timings different from those of the pulse generation circuits 27 and 28 in the logic circuit 5 of FIG.
  • FIGS. 30A, 30B, 30C and 30D are state transition diagrams of the switches SW1 to SW6 in the filter section 7b.
  • the state transition diagrams of FIGS. 30A, 30B, 30C, and 30D are basically the same as those of FIGS. 9A, 9B, 9C, and 9D, and detailed description thereof will be omitted.
  • the ADC 1b according to the third embodiment differs from the ADC 1b according to the first and second embodiments described above in that it is of the error feedback type. It has a redundancy function as shown in 15B. Also, a chopper shown in FIG. 16 may be provided.
  • the charge accumulated in the capacitor in the filter section 7b is transferred to the capacitor in the filter section 7b and the CDAC 3 during the AD conversion period. Since the charge redistribution is performed by the capacitors of , there is no need to provide a separate period for charge redistribution. Therefore, charge redistribution for error feedback is performed without shortening the analog signal sampling period (first period), the AD conversion period (second period), and the residual signal sampling period (third period). be able to. By performing charge redistribution during the AD conversion period, there is a risk of erroneous selection of the capacitance in the CDAC 3. However, as described with reference to FIGS. There is no possibility that the AD conversion precision will be lowered.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be applied to any type of movement such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, robots, construction machinery, agricultural machinery (tractors), etc. It may also be implemented as a body-mounted device.
  • FIG. 31 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • Vehicle control system 7000 comprises a plurality of electronic control units connected via communication network 7010 .
  • the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside information detection unit 7400, an inside information detection unit 7500, and an integrated control unit 7600.
  • the communication network 7010 that connects these multiple control units conforms to any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay (registered trademark). It may be an in-vehicle communication network.
  • Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a storage unit that stores programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various devices to be controlled. Prepare.
  • Each control unit has a network I/F for communicating with other control units via a communication network 7010, and communicates with devices or sensors inside and outside the vehicle by wired communication or wireless communication. A communication I/F for communication is provided. In FIG.
  • the functional configuration of the integrated control unit 7600 includes a microcomputer 7610, a general-purpose communication I/F 7620, a dedicated communication I/F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle equipment I/F 7660, an audio image output unit 7670, An in-vehicle network I/F 7680 and a storage unit 7690 are shown.
  • Other control units are similarly provided with microcomputers, communication I/Fs, storage units, and the like.
  • the drive system control unit 7100 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 7100 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the drive system control unit 7100 may have a function as a control device such as ABS (Antilock Brake System) or ESC (Electronic Stability Control).
  • a vehicle state detection section 7110 is connected to the drive system control unit 7100 .
  • the vehicle state detection unit 7110 includes, for example, a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, an accelerator pedal operation amount, a brake pedal operation amount, and a steering wheel steering. At least one of sensors for detecting angle, engine speed or wheel rotation speed is included.
  • Drive system control unit 7100 performs arithmetic processing using signals input from vehicle state detection unit 7110, and controls the internal combustion engine, drive motor, electric power steering device, brake device, and the like.
  • the body system control unit 7200 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 7200 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • body system control unit 7200 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • Body system control unit 7200 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the driving motor, according to various programs. For example, the battery control unit 7300 receives information such as battery temperature, battery output voltage, or remaining battery capacity from a battery device including a secondary battery 7310 . The battery control unit 7300 performs arithmetic processing using these signals, and performs temperature adjustment control of the secondary battery 7310 or control of a cooling device provided in the battery device.
  • the vehicle exterior information detection unit 7400 detects information outside the vehicle in which the vehicle control system 7000 is installed.
  • the imaging section 7410 and the vehicle exterior information detection section 7420 is connected to the vehicle exterior information detection unit 7400 .
  • the imaging unit 7410 includes at least one of a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras.
  • the vehicle exterior information detection unit 7420 includes, for example, an environment sensor for detecting the current weather or weather, or a sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000. ambient information detection sensor.
  • the environmental sensor may be, for example, at least one of a raindrop sensor that detects rainy weather, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall.
  • the ambient information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device.
  • LIDAR Light Detection and Ranging, Laser Imaging Detection and Ranging
  • These imaging unit 7410 and vehicle exterior information detection unit 7420 may be provided as independent sensors or devices, or may be provided as a device in which a plurality of sensors or devices are integrated.
  • FIG. 32 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420.
  • the imaging units 7910 , 7912 , 7914 , 7916 , and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 7900 .
  • An image pickup unit 7910 provided in the front nose and an image pickup unit 7918 provided above the windshield in the vehicle interior mainly acquire an image in front of the vehicle 7900 .
  • Imaging units 7912 and 7914 provided in the side mirrors mainly acquire side images of the vehicle 7900 .
  • An imaging unit 7916 provided in the rear bumper or back door mainly acquires an image behind the vehicle 7900 .
  • An imaging unit 7918 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 32 shows an example of the imaging range of each of the imaging units 7910, 7912, 7914, and 7916.
  • the imaging range a indicates the imaging range of the imaging unit 7910 provided in the front nose
  • the imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided in the side mirrors, respectively
  • the imaging range d is The imaging range of an imaging unit 7916 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.
  • the vehicle exterior information detectors 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and above the windshield of the vehicle interior of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices.
  • the exterior information detectors 7920, 7926, and 7930 provided above the front nose, rear bumper, back door, and windshield of the vehicle 7900 may be LIDAR devices, for example.
  • These vehicle exterior information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, and the like.
  • the vehicle exterior information detection unit 7400 causes the imaging section 7410 to capture an image of the exterior of the vehicle, and receives the captured image data.
  • the vehicle exterior information detection unit 7400 also receives detection information from the vehicle exterior information detection unit 7420 connected thereto.
  • the vehicle exterior information detection unit 7420 is an ultrasonic sensor, radar device, or LIDAR device
  • the vehicle exterior information detection unit 7400 emits ultrasonic waves, electromagnetic waves, or the like, and receives reflected wave information.
  • the vehicle exterior information detection unit 7400 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received information.
  • the vehicle exterior information detection unit 7400 may perform environment recognition processing for recognizing rainfall, fog, road surface conditions, etc., based on the received information.
  • the vehicle exterior information detection unit 7400 may calculate the distance to the vehicle exterior object based on the received information.
  • the vehicle exterior information detection unit 7400 may perform image recognition processing or distance detection processing for recognizing people, vehicles, obstacles, signs, characters on the road surface, etc., based on the received image data.
  • the vehicle exterior information detection unit 7400 performs processing such as distortion correction or alignment on the received image data, and synthesizes image data captured by different imaging units 7410 to generate a bird's-eye view image or a panoramic image. good too.
  • the vehicle exterior information detection unit 7400 may perform viewpoint conversion processing using image data captured by different imaging units 7410 .
  • the in-vehicle information detection unit 7500 detects in-vehicle information.
  • the in-vehicle information detection unit 7500 is connected to, for example, a driver state detection section 7510 that detects the state of the driver.
  • the driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the biometric information of the driver, a microphone that collects sounds in the vehicle interior, or the like.
  • a biosensor is provided, for example, on a seat surface, a steering wheel, or the like, and detects biometric information of a passenger sitting on a seat or a driver holding a steering wheel.
  • the in-vehicle information detection unit 7500 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 7510, and determine whether the driver is dozing off. You may The in-vehicle information detection unit 7500 may perform processing such as noise canceling processing on the collected sound signal.
  • the integrated control unit 7600 controls overall operations within the vehicle control system 7000 according to various programs.
  • An input section 7800 is connected to the integrated control unit 7600 .
  • the input unit 7800 is realized by a device that can be input-operated by the passenger, such as a touch panel, button, microphone, switch or lever.
  • the integrated control unit 7600 may be input with data obtained by recognizing voice input by a microphone.
  • the input unit 7800 may be, for example, a remote control device using infrared rays or other radio waves, or may be an externally connected device such as a mobile phone or PDA (Personal Digital Assistant) corresponding to the operation of the vehicle control system 7000.
  • PDA Personal Digital Assistant
  • the input unit 7800 may be, for example, a camera, in which case the passenger can input information through gestures.
  • the input section 7800 may include an input control circuit that generates an input signal based on information input by the passenger or the like using the input section 7800 and outputs the signal to the integrated control unit 7600, for example.
  • a passenger or the like operates the input unit 7800 to input various data to the vehicle control system 7000 and instruct processing operations.
  • the storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, and the like. Also, the storage unit 7690 may be realized by a magnetic storage device such as a HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.
  • ROM Read Only Memory
  • RAM Random Access Memory
  • the storage unit 7690 may be realized by a magnetic storage device such as a HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.
  • the general-purpose communication I/F 7620 is a general-purpose communication I/F that mediates communication between various devices existing in the external environment 7750.
  • General-purpose communication I/F 7620 is a cellular communication protocol such as GSM (registered trademark) (Global System of Mobile communications), WiMAX (registered trademark), LTE (registered trademark) (Long Term Evolution) or LTE-A (LTE-Advanced) , or other wireless communication protocols such as wireless LAN (also referred to as Wi-Fi®), Bluetooth®, and the like.
  • General-purpose communication I / F 7620 for example, via a base station or access point, external network (e.g., Internet, cloud network or operator-specific network) equipment (e.g., application server or control server) connected to You may
  • external network e.g., Internet, cloud network or operator-specific network
  • equipment e.g., application server or control server
  • the general-purpose communication I/F 7620 uses, for example, P2P (Peer To Peer) technology to connect terminals (for example, terminals of drivers, pedestrians, stores, or MTC (Machine Type Communication) terminals) near the vehicle. may be connected with P2P (Peer To Peer) technology to connect terminals (for example, terminals of drivers, pedestrians, stores, or MTC (Machine Type Communication) terminals) near the vehicle.
  • P2P Peer To Peer
  • MTC Machine Type Communication
  • the dedicated communication I/F 7630 is a communication I/F that supports a communication protocol designed for use in vehicles.
  • the dedicated communication I/F 7630 uses standard protocols such as WAVE (Wireless Access in Vehicle Environment), DSRC (Dedicated Short Range Communications), which is a combination of lower layer IEEE 802.11p and higher layer IEEE 1609, or cellular communication protocol. May be implemented.
  • the dedicated communication I/F 7630 is typically used for vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication. ) perform V2X communication, which is a concept involving one or more of the communications.
  • the positioning unit 7640 receives GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), performs positioning, and obtains the latitude, longitude, and altitude of the vehicle. Generate location information containing Note that the positioning unit 7640 may specify the current position by exchanging signals with a wireless access point, or may acquire position information from a terminal such as a mobile phone, PHS, or smart phone having a positioning function.
  • GNSS Global Navigation Satellite System
  • GPS Global Positioning System
  • the beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from wireless stations installed on the road, and acquires information such as the current position, traffic jams, road closures, or required time. Note that the function of the beacon reception unit 7650 may be included in the dedicated communication I/F 7630 described above.
  • the in-vehicle device I/F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle.
  • the in-vehicle device I/F 7660 may establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB).
  • a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB).
  • the in-vehicle device I/F 7660 is connected via a connection terminal (and cable if necessary) not shown, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface, or MHL (Mobile High -definition Link), etc.
  • In-vehicle equipment 7760 includes, for example, at least one of mobile equipment or wearable equipment possessed by passengers, or information equipment carried in or attached to the vehicle. In-vehicle equipment 7760 may also include a navigation device that searches for a route to an arbitrary destination. or exchange data signals.
  • the in-vehicle network I/F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. In-vehicle network I/F 7680 transmits and receives signals and the like according to a predetermined protocol supported by communication network 7010 .
  • the microcomputer 7610 of the integrated control unit 7600 uses at least one of a general-purpose communication I/F 7620, a dedicated communication I/F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I/F 7660, and an in-vehicle network I/F 7680.
  • the vehicle control system 7000 is controlled according to various programs on the basis of the information acquired by. For example, the microcomputer 7610 calculates control target values for the driving force generator, steering mechanism, or braking device based on acquired information on the inside and outside of the vehicle, and outputs a control command to the drive system control unit 7100. good too.
  • the microcomputer 7610 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control may be performed for the purpose of In addition, the microcomputer 7610 controls the driving force generator, the steering mechanism, the braking device, etc. based on the acquired information about the surroundings of the vehicle, thereby autonomously traveling without depending on the operation of the driver. Cooperative control may be performed for the purpose of driving or the like.
  • ADAS Advanced Driver Assistance System
  • Microcomputer 7610 receives information obtained through at least one of general-purpose communication I/F 7620, dedicated communication I/F 7630, positioning unit 7640, beacon receiving unit 7650, in-vehicle device I/F 7660, and in-vehicle network I/F 7680. Based on this, three-dimensional distance information between the vehicle and surrounding objects such as structures and people may be generated, and local map information including the surrounding information of the current position of the vehicle may be created. Further, based on the acquired information, the microcomputer 7610 may predict dangers such as vehicle collisions, pedestrians approaching or entering closed roads, and generate warning signals.
  • the warning signal may be, for example, a signal for generating a warning sound or lighting a warning lamp.
  • the audio/image output unit 7670 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 7710, a display section 7720, and an instrument panel 7730 are illustrated as output devices.
  • Display 7720 may include, for example, at least one of an on-board display and a head-up display.
  • the display unit 7720 may have an AR (Augmented Reality) display function.
  • the output device may be headphones, a wearable device such as an eyeglass-type display worn by a passenger, or other devices such as a projector or a lamp.
  • the display device displays the results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats such as text, images, tables, and graphs. Display visually.
  • the voice output device converts an audio signal including reproduced voice data or acoustic data into an analog signal and outputs the analog signal audibly.
  • At least two control units connected via the communication network 7010 may be integrated as one control unit.
  • an individual control unit may be composed of multiple control units.
  • vehicle control system 7000 may comprise other control units not shown.
  • some or all of the functions that any control unit has may be provided to another control unit. In other words, as long as information is transmitted and received via the communication network 7010, the predetermined arithmetic processing may be performed by any one of the control units.
  • sensors or devices connected to any control unit may be connected to other control units, and multiple control units may send and receive detection information to and from each other via communication network 7010. .
  • the ADCs 1, 1a, and 1b according to the present embodiment described with reference to FIGS. 1 to 30B can be used when converting the detection signals of various sensors used in the vehicle control system 7000 described above into digital signals.
  • this technique can take the following structures. (1) An analog-to-digital converter that converts an analog signal into a digital signal within a sampling period that includes a first period, a second period, and a third consecutive period, The analog signal is sampled within the first period, and the sampled signal is sequentially converted bit by bit into the digital signal with redundancy within the second period, and an unconverted residual is obtained.
  • a digital-to-analog converter that outputs a signal; sampling the residual signal within the third period, and at least within the second period, part of the residual signal sampled during the third period within the immediately preceding sampling period and the sampling period two sampling periods before a filter unit that performs charge transfer or charge redistribution to generate a noise shaping signal based on a portion of the residual signal sampled during the third period in a DAC controller that controls the digital-to-analog converter within the second time period based on the residual signal and the noise shaping signal.
  • the filter section selects a portion of the residual signal sampled in the third period in the immediately preceding sampling period and the The analog-to-digital converter according to (1), wherein the noise shaping signal is generated by charge transferring a portion of the residual signal sampled in the third period.
  • the filter section selects a part of the residual signal sampled in the third period in the immediately preceding sampling period and the The analog-to-digital converter according to (1), wherein the noise shaping signal is generated by charge redistribution with a portion of the residual signal sampled in the third period.
  • the filter section a plurality of first capacitors; a plurality of first switches that switch between whether or not to store electric charge in each of the plurality of first capacitors; Some of the first capacitors among the plurality of first capacitors accumulate electric charges according to the residual signal within the third period, During the first period and the second period, from the part of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period, charge is transferred to another first capacitor; The analog-to-digital converter of (2), wherein the noise shaping signal is generated by charge transferred to the further first capacitor.
  • the filter section a first differential amplifier having a first differential input terminal to which the residual signal is input and a first differential output terminal to output a differential signal corresponding to the residual signal; a second differential amplifier having a second differential input terminal and a second differential output terminal, and outputting the differential noise shaping signal from the second differential output terminal;
  • the filter section a plurality of first capacitors; a plurality of first switches that switch between whether or not to store electric charge in each of the plurality of first capacitors; Some of the first capacitors among the plurality of first capacitors accumulate electric charges according to the residual signal within the third period, During the first period and the second period, the accumulated charge of the part of the first capacitors that accumulated the residual signal in the third period of the immediately preceding sampling period is transferred to the part of the first capacitors.
  • the analog-to-digital converter of (3) wherein charge redistribution with another first capacitor produces the noise shaping signal.
  • Some of the plurality of first capacitors store and transfer electric charges in each sampling period, and the remaining first capacitors store and transfer electric charge in one of the two consecutive sampling periods.
  • the analog-to-digital converter according to any one of (4) to (7), which stores and transfers charge in the sampling period.
  • the analog signal is a differential analog signal; two said digital-to-analog converters are provided for converting said differential analog signals to said differential digital signals; differential residual signals are output from the two digital-analog converters;
  • the filter unit generates the differential noise shaping signal within the first period and the second period,
  • the DAC control unit controls the two digital-analog converters based on the differential residual signal and the differential noise shaping signal within the second period, (1) to (8) ).
  • the DAC controller controls the two digital-to-analog converters so that the sum of the signal difference between the differential residual signals and the signal difference between the differential noise shaping signals approaches zero.
  • the DAC control unit a comparator that outputs a signal corresponding to the sum of the signal difference between the differential residual signals and the signal difference between the differential noise shaping signals; and a logic circuit that controls the digital-to-analog converter based on the output signal of the comparator.
  • the digital-to-analog converter is a plurality of second capacitors to which the analog signal is supplied to one end of each or to which the residual signal is output from one end of each; a plurality of second switches for setting the other end side of the plurality of second capacitors to one of a plurality of voltages;
  • the analog-digital according to any one of (1) to (11), wherein the DAC control unit switches and controls the plurality of second switches based on the residual signal and the noise shaping signal. converter.
  • the digital-to-analog converter is a plurality of second capacitors to which the analog signal is supplied to one end of each or to which the residual signal is output from one end of each; a plurality of second switches for setting the other end side of the plurality of second capacitors to one of a plurality of voltages;
  • the filter unit in the second period, divides a part of the residual signal sampled in the third period in the immediately preceding sampling period and the residual signal sampled in the third period in the sampling period two sampling periods before
  • the analog-to-digital converter of claim 1 wherein a portion of the signal is charge redistributed with the plurality of second capacitors in the digital-to-analog converter to generate the noise shaping signal.
  • the filter section a plurality of first capacitors; a plurality of first switches that switch between whether or not to store electric charge in each of the plurality of first capacitors; Some of the first capacitors among the plurality of first capacitors accumulate electric charges according to the residual signal within the third period, During the second period, the accumulated charges of the partial first capacitors that accumulated the residual signal in the third period of the immediately preceding sampling period are transferred to the filter section including the partial first capacitors. 13.
  • the analog signal is a differential analog signal; two said digital-to-analog converters are provided for converting said differential analog signals to said differential digital signals; differential residual signals are output from the two digital-analog converters;
  • the filter unit generates the differential noise shaping signal within the second period, (14), wherein the DAC control unit controls the two digital-to-analog converters based on the differential residual signal and the differential noise shaping signal within the second period.
  • Analog-to-digital converter At least some of the plurality of second capacitors have a capacitance value obtained by multiplying a reference capacitance by a value less than a multiple of 2, and the remaining second capacitors have the reference capacitance.
  • the plurality of second capacitors have a capacitance value that is a multiple of 2 with respect to the reference capacitance;
  • an analog-to-digital converter that converts an analog signal to a digital signal within a sampling period that includes a first period, a second period, and a third consecutive period;
  • An electronic device comprising an information processing unit that performs information processing based on the digital signal,
  • the analog-to-digital converter is The analog signal is sampled within the first period, and the sampled signal is sequentially converted bit by bit into the digital signal with redundancy within the second period, and an unconverted residual is obtained.
  • a digital-to-analog converter that outputs a signal; sampling the residual signal within the third period, and at least within the second period, part of the residual signal sampled during the third period within the immediately preceding sampling period and the sampling period two sampling periods before a filter unit that performs charge transfer or charge redistribution to generate a noise shaping signal based on a portion of the residual signal sampled during the third period in and a DAC controller that controls the digital-to-analog converter within the second period based on the residual signal and the noise shaping signal.
  • ADC analog-digital converter
  • 2 sample switch 3 CDAC, 4 comparator, 5 logic circuit, 6 decoder, 7, 7a, 7b filter section, 7g capacitor group, 8 filter switch, 9 DAC control Section 10a Capacitor Group 10b Switch 11 Buffer 12 Integrating Amplifier 12a Differential Amplifier 21 NOR Gate 22 Shift Register 23, 24 Inverter 25, 26 AND Gate 27, 28 Pulse Generation Circuit 31, 32 Chopper 7000 vehicle control system 7010 communication network 7100 drive system control unit 7110 vehicle state detection unit 7200 body system control unit 7300 battery control unit 7310 secondary battery 7400 vehicle exterior information detection unit 7410 imaging unit 7420 vehicle exterior information detection unit 7500 vehicle interior information detection unit 7510 driver state detection unit 7600 integrated control unit 7610 microcomputer 7640 positioning unit 7650 beacon reception unit 7670 audio image output unit 7690 storage unit 7710 audio speaker 7720 Display unit, 7730 instrument panel, 7750 external environment, 7760 in-vehicle equipment, 7800 input unit, 7900 vehicle,

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Le problème décrit par la présente invention est de fournir un convertisseur analogique-numérique ayant une excellente précision de conversion A/N et un excellent SNDR. En guise de solution, l'invention porte sur un convertisseur analogique-numérique pour convertir un signal analogique en un signal numérique dans une période d'échantillonnage comprenant, successivement, un premier intervalle, un deuxième intervalle, et un troisième intervalle, le convertisseur analogique-numérique comprenant : un convertisseur numérique-analogique pour échantillonner un signal analogique dans le premier intervalle, convertir le signal échantillonné en un signal numérique avec une redondance fournie dans le deuxième intervalle et un bit après un autre, et délivrer en sortie des signaux résiduels qui n'ont pas été convertis ; une unité de filtre pour échantillonner les signaux résiduels dans le troisième intervalle, et, dans au moins le deuxième intervalle, mettre en œuvre, sur la base de certains des signaux résiduels échantillonnés dans le troisième intervalle dans la dernière période d'échantillonnage et certains des signaux résiduels échantillonnés dans le troisième intervalle dans l'avant dernière période d'échantillonnage, un transfert de charge ou une redistribution de charge pour générer un signal de mise en forme de bruit ; et une unité de commande de CNA pour commander, sur la base des signaux résiduels et du signal de mise en forme de bruit, le convertisseur numérique-analogique dans le deuxième intervalle.
PCT/JP2022/005708 2021-02-22 2022-02-14 Convertisseur analogue-numérique et dispositif électronique WO2022176807A1 (fr)

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US10483995B1 (en) * 2019-02-22 2019-11-19 Caelus Technologies Limited Calibration of radix errors using Least-Significant-Bit (LSB) averaging in a Successive-Approximation Register Analog-Digital Converter (SAR-ADC) during a fully self-calibrating routine

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US20170085349A1 (en) * 2015-09-22 2017-03-23 Mediatek Inc. Analog-to-digital converter with bandpass noise transfer function
US20170317683A1 (en) * 2016-04-29 2017-11-02 Analog Devices, Inc. Techniques for power efficient oversampling successive approximation register
US20180069564A1 (en) * 2016-09-08 2018-03-08 Mediatek Inc. Analog-to-digital converter with noise shaping
JP2018050282A (ja) * 2016-09-20 2018-03-29 株式会社東芝 逐次比較型ａｄ変換器
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