WO2022210380A1 - Dispositif d'imagerie et dispositif électronique - Google Patents

Dispositif d'imagerie et dispositif électronique Download PDF

Info

Publication number
WO2022210380A1
WO2022210380A1 PCT/JP2022/014505 JP2022014505W WO2022210380A1 WO 2022210380 A1 WO2022210380 A1 WO 2022210380A1 JP 2022014505 W JP2022014505 W JP 2022014505W WO 2022210380 A1 WO2022210380 A1 WO 2022210380A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel signals
capacitors
signal
output
column amplifier
Prior art date
Application number
PCT/JP2022/014505
Other languages
English (en)
Japanese (ja)
Inventor
尚人 長城
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニーセミコンダクタソリューションズ株式会社 filed Critical ソニーセミコンダクタソリューションズ株式会社
Publication of WO2022210380A1 publication Critical patent/WO2022210380A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present disclosure relates to imaging devices and electronic devices.
  • An imaging device is equipped with an analog-digital converter that converts an analog signal (pixel signal) output from a pixel through a signal line into a digital signal (see, for example, Patent Document 1). If an analog-digital converter is provided for each signal line, the circuit scale becomes large. Therefore, pixel signals on each signal line are sampled and held in capacitors, and the pixel signals held in the capacitors are sequentially converted from analog to digital. A configuration in which the signal is converted into a digital signal by a device is conceivable.
  • an object of the present disclosure is to provide an imaging device and an electronic device capable of high-speed analog-to-digital conversion without increasing the circuit scale.
  • a pixel array unit that outputs a plurality of photoelectrically converted pixel signals to a plurality of signal lines; two or more column amplifier groups that output a plurality of correlated pixel signals, which are differences between reset levels and signal levels of the two or more corresponding pixel signals, for each signal line group including two or more signal lines; a plurality of capacitive multiplexers each having a plurality of capacities for holding the plurality of correlated pixel signals; an analog-to-digital converter that sequentially converts the plurality of correlated pixel signals held in the plurality of capacitors into digital signals;
  • An imaging device is provided in which the number of the plurality of capacitors is greater than the number of the column amplifier groups.
  • each of the two or more column amplifier groups has a plurality of column amplifiers that output a plurality of correlated pixel signals that are differences between reset levels and signal levels of the corresponding two or more pixel signals;
  • Each of the plurality of capacitance multiplexers may include the plurality of capacitances for holding the correlated pixel signals output from the corresponding column amplifier among the plurality of column amplifiers.
  • Each of the plurality of column amplifiers a differential amplifier in which the potential of the signal line is input to the non-inverting input node; a first switch having one end connected to the output node of the differential amplifier and the other end connected to the inverting input node of the differential amplifier; a second switch one end of which is connected to the output node of the differential amplifier; a first capacitive element having one end connected to the other end of the second switch and having the other end connected to the other end of the first switch and the inverting input node of the differential amplifier; a second capacitive element connected between the other end of the first capacitive element and a reference potential node; and a third switch, one end of which is connected to the other end of the second switch and one end of the first capacitive element, and the other end of which is applied with a reference voltage.
  • each of the plurality of capacitance multiplexers has a plurality of switched capacitors including the plurality of capacitances;
  • Each of the plurality of capacitive multiplexers may hold the correlated pixel signal by sampling with the plurality of switched capacitors.
  • some of the plurality of capacitors hold correlated pixel signals output from a predetermined column amplifier group out of the two or more column amplifier groups; Two or more capacitors other than the one portion of the plurality of capacitors are sequentially selected and output from a column amplifier group other than the predetermined column amplifier group out of the two or more column amplifier groups. may hold the correlated pixel signal.
  • the plurality of capacitors are connected to the plurality of correlated pixels output from the two or more column amplifier groups within a period in which the signal levels of the plurality of pixel signals are output from the pixel array section to the two or more signal lines. may hold the signal.
  • the plurality of capacitors are arranged in a period during which the reset levels of the plurality of pixel signals are output from the pixel array section to the two or more signal lines and when the signal levels of the plurality of pixel signals are output to the two or more signal lines.
  • the held plurality of correlated pixel signals may be sequentially transferred to the analog-digital converter within the output period.
  • some of the plurality of capacitors hold the correlated pixel signals during a period in which the signal levels of the plurality of pixel signals are output from the pixel array unit to the two or more signal lines; Two or more capacitors other than the part of the capacitors among the plurality of capacitors are rotated in turn during a period in which the signal levels of the plurality of pixel signals are output from the pixel array section to the two or more signal lines.
  • the holding operation of the correlated pixel signal may be suspended.
  • the two or more column amplifier groups have a first column amplifier group and a second column amplifier group, each of the plurality of capacitance multiplexers has a first capacitance, a second capacitance, and a third capacitance;
  • the plurality of first capacitors in the plurality of capacitor multiplexers are configured to operate within a first period in which the signal levels of the plurality of pixel signals are output from the pixel array section to the two or more signal lines. holding the plurality of correlated pixel signals output from the column amplifier group of The plurality of second capacitors and the plurality of third capacitors in the plurality of capacitor multiplexers are alternately selected every first period and output from the second column amplifier group. A plurality of correlated pixel signals may be held.
  • the plurality of correlated pixel signals held in the plurality of first capacitors and the plurality of second capacitors or the plurality of third capacitors are transferred from the pixel array section to the
  • the pixel signals may be sequentially transferred to the analog-digital converter during a second period in which the signal levels of the plurality of pixel signals are output to two or more signal lines.
  • the plurality of second capacitors and the plurality of third capacitors in the plurality of capacitor multiplexers hold the plurality of correlated pixel signals or convert the plurality of correlated pixel signals for each of the first period. You may switch alternately whether holding
  • the two or more column amplifier groups have a first column amplifier group, a second column amplifier group, and a third column amplifier group, each of the plurality of capacitance multiplexers has a first capacitance, a second capacitance, a third capacitance, and a fourth capacitance;
  • the plurality of first capacitors in the plurality of capacitor multiplexers are configured to output the signal levels of the plurality of pixel signals to the two or more signal lines during a first period in which the pixel array section outputs the signal levels of the plurality of pixel signals.
  • the plurality of second capacitors in the plurality of capacitor multiplexers hold the plurality of correlated pixel signals output from the second column amplifier group within the first period;
  • the plurality of third capacitors and the plurality of fourth capacitors in the plurality of capacitor multiplexers are alternately selected for each of the first periods, and the plurality of capacitors output from the third column amplifier group of correlated pixel signals may be held.
  • the plurality of correlated pixel signals held in the first capacitor, the second capacitor, and the third capacitor or the fourth capacitor holding the plurality of correlated pixel signals are the A first period, a second period in which the signal levels of the plurality of pixel signals are output to the two or more signal lines, and the first period immediately after the second period, in order. It may be transferred to an analog-to-digital converter.
  • a rest period may be provided.
  • the analog-digital converter may be a successive approximation analog-digital converter.
  • the capacitance multiplexer differentially outputs the correlated pixel signal held in one of the plurality of capacitances;
  • the successive approximation analog-digital converter may convert the differential correlated pixel signals output from the capacitive multiplexer into the digital signals.
  • an imaging device that converts a photoelectrically converted pixel signal into a digital signal and outputs the digital signal; and a signal processing circuit that performs signal processing based on the digital signal
  • the imaging device is a pixel array unit that outputs a plurality of photoelectrically converted pixel signals to a plurality of signal lines; two or more column amplifier groups that output a plurality of correlated pixel signals, which are differences between reset levels and signal levels of the two or more corresponding pixel signals, for each signal line group including two or more signal lines; a capacitor unit having a plurality of capacitors for holding the plurality of correlated pixel signals; an analog-to-digital converter that sequentially converts the plurality of correlated pixel signals held in the plurality of capacitors into digital signals;
  • An electronic device is provided in which the number of the plurality of capacitors is greater than the number of the column amplifier groups.
  • FIG. 1 is a block diagram showing a schematic configuration of an imaging device according to a first embodiment
  • FIG. FIG. 2 is a circuit diagram showing an example of the configuration of a pixel (pixel circuit)
  • FIG. 2 is a plan view schematically showing an outline of a parallel-type semiconductor chip structure of a CMOS image sensor
  • FIG. 2 is an exploded perspective view schematically showing an outline of a laminated chip structure of a CMOS image sensor
  • FIG. 2 is a block diagram showing the basic configuration of a column signal processing system including a column amplifier section, a capacitor section, and an AD conversion section
  • FIG. 6 is a timing chart of the column signal processing system according to the basic configuration example of FIG. 5;
  • FIG. 2 is a circuit diagram showing a schematic configuration of a column signal processing system according to a first specific example
  • FIG. 8 is an operation timing chart of the column signal processing system according to the first specific example shown in FIG. 7
  • FIG. 9 is a diagram showing the flow of pixel signals from time t2 to t3 in FIG. 8
  • FIG. 9 is a diagram showing the flow of pixel signals from time t3 to t4 in FIG. 8
  • FIG. 9 is a diagram showing the flow of pixel signals from time t4 to t5 in FIG. 8
  • FIG. 9 is a diagram showing the flow of pixel signals at times t5 to t6 in FIG. 8
  • FIG. 9 is a diagram showing the flow of pixel signals from time t6 to t7 in FIG.
  • FIG. 8 is a diagram showing the flow of pixel signals from time t7 to t8 in FIG. 8;
  • FIG. 4 is an operation timing chart of a column signal processing system according to a comparative example;
  • FIG. 2 is a schematic block diagram of an image pickup apparatus including an assist processing section;
  • FIG. 10 is a circuit diagram showing a schematic configuration of a column signal processing system according to a second specific example;
  • FIG. 18 is an operation timing chart of the column signal processing system according to the second specific example shown in FIG. 17;
  • FIG. 8 is a circuit diagram of a column signal processing system in which voltage generating circuits are added to FIG. 7; The figure which shows a level diagram.
  • FIG. 4 is an operation timing chart of a column signal processing system according to a comparative example.
  • FIG. 2 is a schematic block diagram of an image pickup apparatus including an assist processing section
  • FIG. 10 is a circuit diagram showing a schematic configuration of
  • FIG. 2 is a circuit diagram of an example of the configuration of a current reuse column amplifier; A detailed circuit diagram of a successive approximation analog-digital converter.
  • FIG. 7 is a block diagram showing an example of a system configuration of an indirect TOF range image sensor according to a second embodiment of the present disclosure
  • FIG. 4 is a circuit diagram showing an example of the circuit configuration of pixels in an indirect TOF range image sensor according to the second embodiment
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system
  • FIG. FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;
  • an imaging device and an electronic device will be described below with reference to the drawings.
  • the main components of the imaging device and the electronic device will be mainly described below, the imaging device and the electronic device may have components and functions that are not illustrated or described. The following description does not exclude components or features not shown or described.
  • FIG. 1 is a block diagram showing a schematic configuration of an imaging device according to the first embodiment.
  • the imaging device 10 in FIG. 1 is a CMOS (Complementary Metal-Oxide Semiconductor) image sensor.
  • the imaging device 10 of FIG. 1 includes a pixel array section 11, a row selection section 12, a constant current source section 13, a column amplifier section, an analog-digital conversion section (hereinafter referred to as an AD conversion section) 15, a horizontal A transfer scanning unit 16 , a signal processing unit 17 and a timing control unit 18 are provided.
  • CMOS Complementary Metal-Oxide Semiconductor
  • a plurality of pixel control lines 31 (31 1 to 31 m ) and a plurality of signal lines 32 (32 1 to 32 n ) are arranged vertically and horizontally.
  • a plurality of pixels 20 are arranged near the intersections of the lines 32 .
  • the direction in which the pixel control lines extend is called the row direction
  • the direction in which the signal lines extend is called the column direction.
  • the row selection unit 12 is composed of a shift register, an address decoder, and the like, and controls pixel row scanning and pixel row addressing when selecting each pixel 20 of the pixel array unit 11 .
  • the specific configuration of the row selection unit 12 is omitted from the drawing, it generally has two scanning systems, a readout scanning system and a discharge scanning system.
  • the readout scanning system In order to read out pixel signals from the pixels 20, the readout scanning system sequentially selectively scans the pixels 20 of the pixel array section 11 row by row. A pixel signal read out from the pixel 20 is an analog signal.
  • the sweep-scanning system performs sweep-scanning ahead of the read-out scanning by the shutter speed for the read-out rows to be read-scanned by the read-out scanning system.
  • a so-called electronic shutter operation is performed by sweeping out (resetting) unnecessary charges by this sweeping scanning system.
  • the electronic shutter operation refers to an operation of discarding the photocharges of the photoelectric conversion element and newly starting exposure (starting accumulation of photocharges).
  • the constant current source unit 13 includes a plurality of load current sources I (see FIG. 2) made up of, for example, MOS transistors connected to each of the signal lines 32 1 to 32 n for each pixel column. A bias current is supplied through each of the signal lines 32 1 to 32 n to each pixel 20 in the pixel row selected and scanned by .
  • the column amplifier section 14 is composed of a set of column amplifiers provided corresponding to each of the signal lines 32 1 to 32 n for each pixel column. Each column amplifier of the column amplifier section 14 amplifies the pixel signal read from each pixel 20 of the pixel array section 11 and supplied through the signal lines 32 1 to 32 n and supplies the amplified pixel signal to the AD conversion section 15 .
  • the column amplifier unit 14 performs processing (CDS processing) for obtaining a difference between a signal component (so-called D phase) input from each pixel 20 of the pixel array unit 11 through the signal line 32 and a reset component (so-called P phase). and outputs the difference as a pixel signal.
  • a capacitance section 19 is provided in the subsequent stage of the column amplifier section 14 .
  • the capacitive section 19 holds the pixel signal input from the column amplifier section 14, for example, by sampling with a switched capacitor.
  • An AD conversion section is provided in the subsequent stage of the capacity section 19 .
  • the AD conversion unit 15 converts a set of a plurality of analog-digital converters (hereinafter referred to as AD converters) provided corresponding to the pixel columns of the pixel array unit 11 (for example, provided for each pixel column). This is a column-parallel type AD converter.
  • the AD converter 15 converts the analog pixel signals output through the signal lines 32 1 to 32 n for each pixel column and amplified by the column amplifier 14 into digital pixel signals.
  • the AD conversion method adopted by the AD conversion unit 15 does not matter.
  • the AD converter may be a single-slope AD converter or a successive approximation AD converter.
  • a single-slope type AD converter in order to perform digital CDS processing for removing fixed pattern noise of pixels, additional time is required to perform AD conversion processing twice for the P-phase signal and the D-phase signal and auto-zero processing. become necessary. Also, when the pixel signal and the reference signal of the ramp wave cross each other, through current and kickback occur. Furthermore, the crossing time depends on the pixel signal level and may interfere with the AD conversion processing of other pixel columns. In addition, since the amplification transistor in the pixel is used to hold the voltage at the time of AD conversion, the time required for conversion to a digital signal limits the readout speed of the pixel signal.
  • a successive approximation AD converter can perform AD conversion processing faster and with lower power consumption than a single slope AD converter.
  • the successive approximation AD converter performs a binary search, it can perform AD conversion processing more efficiently than a single slope AD converter that performs comparison with a ramp wave whose voltage level sweeps.
  • the horizontal transfer scanning unit 16 is composed of a shift register, an address decoder, and the like, and controls the scanning of pixel rows and the addressing of pixel rows when reading out signals from the pixels 20 of the pixel array unit 11 . Under the control of the horizontal transfer scanning unit 16, pixel signals converted into digital signals by the AD conversion unit 15 are read out to the horizontal transfer lines L in units of pixel columns.
  • the signal processing unit 17 performs predetermined signal processing on digital pixel signals supplied through the horizontal transfer line L to generate two-dimensional image data. For example, the signal processing unit 17 performs digital signal processing such as correction of vertical line defects and point defects, parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing unit 17 outputs the generated image data to a subsequent device as an output signal of the CMOS image sensor 10 .
  • the timing control unit 18 generates various timing signals, clock signals, control signals, etc. Based on these generated signals, the row selection unit 12, the constant current source unit 13, the column amplifier unit 14, the AD conversion unit 15, the horizontal transfer scanning unit 16, the signal processing unit 17 and the like are driven and controlled.
  • FIG. 2 is a circuit diagram showing an example of the configuration of the pixel (pixel circuit) 20.
  • the pixel 20 has, for example, a photodiode 21 as a photoelectric conversion element.
  • the pixel 20 includes a transfer transistor 22 , a reset transistor 23 , an amplification transistor 24 and a selection transistor 25 in addition to the photodiode 21 .
  • the four transistors of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, for example, N-channel MOS field effect transistors (FETs) are used.
  • FETs N-channel MOS field effect transistors
  • the combination of the conductivity types of the four transistors 22 to 25 illustrated here is merely an example, and the combination is not limited to these combinations.
  • a plurality of pixel control lines are commonly wired to each pixel 20 in the same pixel row as the pixel control line 31 described above.
  • the plurality of pixel control lines are connected to the output terminals corresponding to the respective pixel rows of the row selection section 12 in units of pixel rows.
  • the row selection unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to a plurality of pixel control lines.
  • the photodiode 21 has an anode electrode connected to a low-potential power source (for example, ground), photoelectrically converts the received light into photocharges (here, photoelectrons) corresponding to the amount of light, and converts the light into photoelectrons. Accumulate electric charge.
  • a cathode electrode of the photodiode 21 is electrically connected to the gate of the amplification transistor 24 via the transfer transistor 22 .
  • the region to which the gate of the amplification transistor 24 is electrically connected is a floating diffusion (floating diffusion region/impurity diffusion region) FD.
  • the floating diffusion FD is a charge-voltage converter that converts charge into voltage.
  • the gate of the transfer transistor 22 is supplied from the row selection section 12 with a transfer signal TRG whose high level (for example, VDD level) is active.
  • TRG transfer signal
  • the transfer transistor 22 becomes conductive in response to the transfer signal TRG, the photocharges photoelectrically converted by the photodiode 21 and accumulated in the photodiode 21 are transferred to the floating diffusion FD.
  • the reset transistor 23 is connected between the node of the high potential side power supply voltage VDD and the floating diffusion FD.
  • a gate of the reset transistor 23 is supplied with a reset signal RST from the row selection unit 12 whose high level is active.
  • the reset transistor 23 becomes conductive in response to the reset signal RST, and resets the floating diffusion FD by dumping the charge of the floating diffusion FD to the voltage VDD node.
  • the amplification transistor 24 has a gate connected to the floating diffusion FD and a drain connected to the node of the high potential side power supply voltage VDD.
  • the amplification transistor 24 serves as an input part of a source follower that reads out a signal obtained by photoelectric conversion in the photodiode 21 . That is, the amplification transistor 24 has its source connected to the signal line 32 via the selection transistor 25 .
  • the amplifier transistor 24 and the load current source I connected to one end of the signal line 32 constitute a source follower that converts the voltage of the floating diffusion FD to the potential of the signal line 32 .
  • the selection transistor 25 has a drain connected to the source of the amplification transistor 24 and a source connected to the signal line 32 .
  • the gate of the selection transistor 25 is supplied with a selection signal SEL from the row selection section 12 whose high level is active.
  • the selection transistor 25 becomes conductive in response to the selection signal SEL, thereby transmitting the signal output from the amplification transistor 24 to the signal line 32 with the pixel 20 in the selected state.
  • the circuit configuration of the pixel 20 is exemplified by a 4Tr configuration composed of four transistors (Tr), including the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25.
  • Tr transistors
  • a 3Tr configuration in which the selection transistor 25 is omitted and the amplification transistor 24 has the function of the selection transistor 25 can be used, or a circuit configuration of 5Tr or more with an increased number of transistors can be used as necessary. can.
  • CMOS image sensor 10 As the semiconductor chip structure of the CMOS image sensor 10 having the above configuration, a parallel-type semiconductor chip structure and a stacked-type semiconductor chip structure can be exemplified.
  • the pixel 20 when the substrate surface on which the wiring layer is arranged is defined as the front surface (front surface), A back-illuminated pixel structure that captures light emitted from the back side or a front-illuminated pixel structure that captures light emitted from the front side can be used.
  • a parallel-type semiconductor chip structure and a stacked-type semiconductor chip structure will be described below.
  • FIG. 3 is a plan view schematically showing the outline of the parallel-type semiconductor chip structure of the CMOS image sensor 10. As shown in FIG. As shown in FIG. 3, in the parallel-type semiconductor chip structure, a circuit portion around the pixel array portion 11 is formed on the same semiconductor chip (semiconductor substrate) 41 as the pixel array portion 11 in which the pixels 20 are arranged in a matrix.
  • FIG. 4 is an exploded perspective view schematically showing the outline of the stacked chip structure of the CMOS image sensor 10.
  • the laminated semiconductor chip structure has a structure in which at least two semiconductor chips (semiconductor substrates), a first-layer semiconductor chip 42 and a second-layer semiconductor chip 43, are stacked.
  • the pixel array section 11 is formed on the semiconductor chip 42 of the first layer.
  • a row selection unit 12 a constant current source unit 13, a column amplifier unit 14, a capacitance unit 19, an analog-digital conversion unit (AD conversion unit) 15, a horizontal transfer scanning unit 16, a signal processing unit 17, and a timing control unit Circuit portions such as 18 are formed on the semiconductor chip 43 of the second layer.
  • the semiconductor chip 42 in the first layer and the semiconductor chip 43 in the second layer are electrically connected through connecting portions (VIAs) 44A and 44B such as Cu--Cu connections.
  • the size (area) of the semiconductor chip 42 of the first layer is enough to form the pixel array section 11. Therefore, the size (area) of the semiconductor chip 42 of the first layer can be ), and thus the overall size of the chip can be reduced. Furthermore, a process suitable for manufacturing the pixels 20 can be applied to the semiconductor chip 42 of the first layer, and a process suitable for manufacturing the circuit portion can be applied to the semiconductor chip 43 of the second layer. There is also the advantage that the process can be optimized in manufacturing. In particular, it becomes possible to apply advanced processes in the fabrication of the circuit portion.
  • the laminated structure is not limited to the two-layer structure. , three or more layers.
  • a row selection section 12 a constant current source section 13, a column amplifier section 14, an AD conversion section 15, a horizontal transfer scanning section 16, a signal processing section 17, a timing control section 18, etc.
  • the circuit portion of can be dispersedly formed in the semiconductor chips of the second and subsequent layers.
  • FIG. 5 is a block diagram showing the basic configuration of a column signal processing system including a column amplifier section, a capacitor section, and an AD conversion section.
  • the column signal processing system in FIG. 5 has a column amplifier section and a capacitor section for each of the plurality of signal lines.
  • the column signal processing system has a plurality of column amplifier sections and a plurality of capacity sections, and the plurality of capacity sections share one AD conversion section.
  • the column amplifier section has the same number of column amplifiers as the number of pixel columns.
  • the capacitive section has the same number of capacitive multiplexers as the number of pixel columns.
  • FIG. 5 shows that for one successive approximation AD converter 150, each potential VSL0 to VSL7 of a plurality of signal lines 32, for example, eight signal lines 32, is divided into eight columns corresponding to the eight signal lines 32.
  • An example of a configuration for multiplexing and processing through an amplifier 140 and a capacitance multiplexer 190 is shown.
  • the column amplifier 140 has an amplifier 141 , a first switch 142 , a second switch 143 , a third switch 144 , a first capacitive element 145 and a second capacitive element 146 .
  • a first capacitive element 145 (hereinafter simply referred to as “capacitor 145”) has a capacitance value CF
  • a second capacitive element 146 (hereinafter simply referred to as “capacitor 146”) is , has a capacitance Cs.
  • the amplifier 141 inputs the potential VSL (VSL0 to VSL7) of the signal line 32 to the non-inverting (+) input terminal.
  • the first switch 142 (hereinafter simply referred to as “switch 142”) has one end connected to the output terminal of the amplifier 141 and the other end connected to the inverting (-) input terminal of the amplifier 141, and is used for switch control. ON (close)/OFF (open) operation is performed according to the polarity (high level/low level) of the signal Sp .
  • switch 143 One end of the second switch 143 (hereinafter simply referred to as “switch 143 ”) is connected to the output terminal of the amplifier 141 .
  • the capacitive element 145 has one end connected to the other end of the switch 143 and the other end connected to the other end of the switch 142 and the inverting input terminal of the amplifier 141 .
  • the capacitive element 146 is connected between the other end of the capacitive element 145, the output terminal of the amplifier 141, and a reference potential (for example, ground) node.
  • the switch 143 performs on/off operation according to the polarity of the switch control signal S D .
  • the switch 143, the capacitive element 145, and the capacitive element 146 are connected in series between the output terminal of the amplifier 141 and the reference potential (for example, ground) node in that order.
  • a common connection node N1 between the capacitive elements 145 and 146 and the other end of the switch 142 are electrically connected.
  • switch 144 One end of the third switch 144 (hereinafter simply referred to as "switch 144") is connected to a common connection node N2 between the switch 143 and the capacitive element 145, and depending on the polarity of the switch control signal SVR , Performs on/off operation.
  • the other end of the switch 144 is applied with a local reference voltage VR that defines the zero voltage of the output of the column amplifier 140 . That is, switch 144 selectively applies local reference voltage VR to common connection node N2 between switch 143 and capacitive element 145 .
  • a capacitive multiplexer 190 constituting the capacitive section 19 has four switches 191 to 194 and one capacitive element 195, and is configured to perform sampling using a switched capacitor.
  • Capacitive element 195 has a capacitance value CIN.
  • the switch 191 has one end connected to the output terminal of the column amplifier 140, that is, the output terminal of the amplifier 141, and performs ON/OFF operation according to the polarity of the switch control signal SIN .
  • the switch 192 has one end connected to the other end of the switch 191 and performs ON/OFF operation according to the polarity of the switch control signal SVMI0 .
  • a specific reference voltage VX is applied to the other end of the switch 192 .
  • a local reference voltage VR may be used as the specific reference voltage VX.
  • the switch 193 has one end connected to the other end of the capacitive element 195, and performs on/off operation according to the polarity of the switch control signal SVM .
  • the other end of the switch 193 is applied with an intermediate voltage VM used when resetting the capacitor array section (CDAC) 155 of the successive approximation AD converter 150 .
  • the switch 194 has one end connected to the other end of the capacitive element 195 and one end of the switch 193, and performs ON/OFF operation according to the polarity of the switch control signal SSUM0 .
  • the other end of the switch 194 is commonly connected among the eight capacitance multiplexers 190 corresponding to the potentials VSL0 to VSL7 of the signal line 32 and serves as the output end of the capacitance multiplexer 190.
  • the successive approximation AD converter 150 has a preamplifier 151 , a comparator 152 , a SAR logic section 153 , a digital-analog converter (DAC) 154 and a capacitor array section (CDAC) 155 .
  • the preamplifier 151 consists of an amplifier 1511 and a switch 1512 .
  • the amplifier 1511 receives the analog voltage supplied from the capacitive multiplexer 190 at its inverting (-) input terminal and the output common mode reference voltage VCM at its non-inverting (+) input terminal.
  • the switch 1512 is an auto-zero (offset cancellation due to input/output short-circuit) switch, and is connected between the inverting (-) input terminal and the output terminal of the preamplifier 151. Depending on the polarity of the switch control signal SAZ , Performs on/off operation.
  • the comparator 152 compares the analog voltage supplied through the preamplifier 151 with the comparison reference voltage in synchronization with the comparator clock CKI, and supplies the comparison result to the SAR logic unit 153 .
  • the SAR logic unit 153 is composed of, for example, an N-bit successive approximation register, stores the comparison result of the comparator 152 for each bit in synchronization with the clock CK, and outputs it as an N-bit digital value DOUT after AD conversion. .
  • the digital-analog converter 154 and the capacitor array section 155 constitute an N-bit capacitive digital-analog converter. Then, in this capacitive digital-analog converter, the N-bit digital value DOUT output from the SAR logic section 153 is converted into an analog voltage, which is applied to the inverting (-) input terminal of the amplifier 1511 as its input.
  • the timing chart of FIG. 6 shows the potential VSL of the signal line 32, switch control signals S P and S VR , switch control signals S D , S IN and S VM , switch control signals S VMI0 , S SUM0 to S VMI7 and S SUM7 . , clock CK, switch control signal S AZ , and comparator clock CKI.
  • the potentials VSL0 to VSL7 of the eight signal lines 32 are input to the corresponding dedicated column amplifiers 140, respectively.
  • the switch control signal S P and the switch control signal S VR become high level, so that the switches 142 and 144 are turned on. (closed) state.
  • the capacitive element 145 and the capacitive element 146 are charged with the reset component (P-phase voltage).
  • the reset component (P-phase voltage) of the voltage at the common connection node N2 between the switch 143 and the capacitive element 145 varies greatly (with low precision) depending on the pixel 20, but the local reference voltage VR is on the column amplifier 140 side. small variation (high precision).
  • the switch control signal S P and the switch control signal S VR go low, turning the switches 142 and 144 off (open), and at the same time, the switch control signal S D goes high, The switch 143 is turned on (closed). At this time, the capacitive elements 145 and 146 and the amplifier 141 form a non-inverting amplifier circuit, and the output voltage Vout of the column amplifier 140 becomes substantially the same voltage as the local reference voltage VR.
  • the capacitive element 145 and the capacitive element 146 Feedback is applied so that the voltage of the common connection node N1 becomes the same voltage as the signal component (D-phase voltage).
  • CDS processing is performed to take the difference between the reset component (P-phase voltage) and the signal component (D-phase voltage). )/CF times the amplified voltage.
  • the column amplifier 140 outputs the correlated pixel signal 1, which is the difference between the reset level and the signal level of the pixel signal.
  • a signal component amplified by the column amplifier 140 is input to a capacitive multiplexer 190 composed of the same number of capacitive elements 195 as the column amplifier 140 .
  • the switch control signal S IN and the switch control signal S VM become high level during the D phase, and the switches 191 and 193 are turned on in response to this, so that the intermediate voltage VM is applied to the capacitive element 195 . is applied.
  • the switch control signal S IN and the switch control signal S VM become low level, and the switches 191 and 193 are turned off in response to this, so that the capacitive element 195 having the capacitance value C IN holds electric charge.
  • Charge transfer is performed by dividing the P-phase time by eight. Since the D phase is used for sampling, charge transfer can only occur during the P phase.
  • the comparator clock CKI is input to the comparator 152 to start comparison.
  • the comparison result of the comparator 152 is fed back to the digital-analog converter 154 via the SAR logic section 153, and binary search is performed so that the input of the preamplifier 151 becomes 0V.
  • CDAC capacitive array section
  • the switch control signal SAZ is set to a high level to turn on (close) the switch 1512 of the preamplifier 151, thereby resetting the charge of the capacitive array section (CDAC) 155.
  • CDAC capacitive array section
  • the successive approximation AD converter 150 in FIG. 5 operates only during the P phase, and intermittently waits without doing anything during the D phase.
  • the circuit current is stopped during standby so as not to consume power, but the parts that cannot respond at high speed cannot be stopped, resulting in waste.
  • the power supply current changes greatly between the P phase and the D phase, it takes time to stabilize the power supply voltage immediately after the return.
  • FIG. 7 is a circuit diagram showing a schematic configuration of a column signal processing system according to the first specific example.
  • the column signal processing system in FIG. 7 includes two or more column amplifier groups 147 , a capacitor section 19 and an AD converter 150 .
  • the two or more column amplifier groups 147 output a plurality of correlated pixel signals that are the difference between the reset level and the signal level of the corresponding two or more pixel signals for each signal line group including two or more signal lines.
  • Two or more column amplifier groups 147 constitute the column amplifier section in FIG.
  • FIG. 7 shows an example having two column amplifier groups 147A and 147B, the number of column amplifier groups 147 may be three or more as described later.
  • a signal line group consisting of four signal lines VSL0 to VSL3 is input to one column amplifier group 147A
  • a signal consisting of four signal lines VSL4 to VSL7 is input to the other column amplifier group 147B.
  • a group of lines is entered.
  • Each column amplifier group 147A, 147B has four column amplifiers 140, respectively.
  • Each column amplifier 140 receives one of four signal lines VSL0 to VSL3 and VSL4 to VSL7.
  • Each column amplifier 140 has the same circuit configuration as the column amplifier 140 in FIG.
  • the number of signal lines input to each column amplifier group 147 does not necessarily have to be four.
  • Each column amplifier group 147 is provided with the same number of column amplifiers 140 as the number of signal lines input to each column amplifier group 147 .
  • the capacity unit 19 has a plurality of capacity multiplexers 190 .
  • Each capacitive multiplexer 190 has a plurality of capacities that hold a plurality of correlated pixel signals. More specifically, each capacitive multiplexer 190 has multiple switched capacitors 196A, 196B, 196C that hold multiple correlated pixel signals. Each capacitive multiplexer 190 holds the correlated pixel signal by sampling with a plurality of switched capacitors 196A, 196B, 196C.
  • the capacity section 19 corresponds to the capacity section 19 in FIG.
  • a plurality of capacitive multiplexers 190 are provided in the same number as the number of column amplifiers 140 in each column amplifier group 147 .
  • Some switched capacitors 196A among the plurality of switched capacitors 196A, 196B, 196C hold correlated pixel signals output from predetermined column amplifier groups 147A among the two or more column amplifier groups 147A, 147B.
  • two or more switched capacitors 196B, 196C other than a part of the switched capacitors 196A are selected in turn, and selected from the two or more column amplifier groups 147A, 147B in advance.
  • the correlated pixel signals output from the column amplifier group 147B other than the column amplifier group 147A are held.
  • the plurality of switched capacitors 196A, 196B, and 196C correspond to the plurality of capacitors output from the two or more column amplifier groups 147 within the period in which the signal levels of the plurality of pixel signals are output from the pixel array section 11 to the two or more signal lines. Holds the correlated pixel signal.
  • the plurality of switched capacitors 196A, 196B, and 196C are connected to the signal levels of the plurality of pixel signals on the two or more signal lines during the period in which the reset levels of the plurality of pixel signals are output from the pixel array section 11 to the two or more signal lines. is output, the held plurality of correlated pixel signals are transferred to the analog-digital converter in turn.
  • Some of the switched capacitors 196A, 196B, and 196C hold the correlated pixel signals for each period in which the signal levels of the plurality of pixel signals are output from the pixel array section 11 to two or more signal lines. do.
  • the switched capacitors 196B and 196C other than a part of the switched capacitors 196A sequentially output the signal levels of the plurality of pixel signals from the pixel array section 11 to two or more signal lines. During the period, the holding operation of the correlated pixel signal is suspended.
  • the capacitance multiplexer 190 in FIG. 7 differs in internal configuration from the capacitance multiplexer 190 in FIG.
  • the capacitive multiplexer 190 of FIG. 7 has three switched capacitors 196A, 196B, 196C.
  • the switched capacitor 196A has switches 191A1, 191A3, 192A, 193A1, 193A2, 194A1, 194A2 and capacitors 195A1, 195A2. These switches are controlled by switch control signals S IN0A , S IN1A , S INA , S VM1A[n] , S VMA , S VMA and S SUMA[n] , respectively.
  • the switched capacitor 19B has switches 191B1, 191B3, 192B, 193B1, 193B2, 194B1, 194B2 and capacitors 195B1, 195B2. These switches are switch-controlled by switch control signals S IN0B , S IN1B , S INB , S VM1B[n] , S VMB , S VMB and S SUMB[n] , respectively.
  • the switched capacitor 196C has switches 191C1, 191C3, 192C, 193C1, 193C2, 194C1, 194C2 and capacitors 195C1, 195C2. These switches are controlled by switch control signals S IN0C , S IN1C , S INC , S VM1C[n] , S VMC , S VMC and S SUMC[n] , respectively.
  • each column amplifier 140 in one column amplifier group 147A is connected to one end of each of switches 191A1, 191B1, and 191C1 in the corresponding capacitive multiplexer 190.
  • the output node of each column amplifier in the other column amplifier group 147B is connected to one end of each of switches 191B1 and 191C1 in the corresponding capacitive multiplexer 190.
  • the other end of the switch 191A1 is connected to one end of the capacitor 195A1 and one end of the switch 192A.
  • a reference voltage VR is applied to one end of the switch 191A3, and the other end of the switch 191A3 is connected to the other end of the switch 192A and one end of the capacitor 195A2.
  • One end of the switch 193A1 and one end of the switch 194A1 are connected to the other end of the capacitor 195A1.
  • a common mode reference voltage VCM is applied to the other end of the switch 193A1 and one end of the switch 193A2.
  • the other end of switch 193A2 is connected to the other end of capacitor 195A2 and one end of switch 194A2.
  • the other ends of the switches 194A1, 194B1, and 194C1 in the three switched capacitors 196A, 196B, and 196C in the capacitance multiplexer 190 are connected to the inverting input node of the successive approximation AD converter 150.
  • the other ends of the switches 194 A 2 , 194 B 2 and 194 C 2 in the three switched capacitors 196 A, 196 B and 196 C in the capacitive multiplexer 190 are connected to the non-inverting input node of the successive approximation AD converter 150 .
  • each capacitive multiplexer 190 in the capacitive section 19 outputs a differential signal.
  • there are four capacitive multiplexers 190 and four differential signals output from the four capacitive multiplexers 190 are input to the inverting input node and the non-inverting input node of the successive approximation AD converter 150 .
  • the successive approximation AD converter 150 in FIG. 7 differentially performs AD conversion processing based on differential input signals.
  • a successive approximation AD converter 150 in FIG. have.
  • the preamplifier 151 has a differential input/differential output amplifier 1511 and two switches 1512 .
  • One switch 1512 is connected between one of the differential output nodes of amplifier 1511 and the non-inverting input node.
  • the other switch 1512 is connected between the other differential output node of amplifier 1511 and the inverting input node.
  • FIG. 8 is an operation timing chart of the column signal processing system according to the first specific example shown in FIG. FIG. 8 shows a reset signal RST input to the gate of the reset transistor in FIG. 2, a TRG signal input to the gate of the transfer transistor, and switch control signals S IN0A , S IN1A , S IN0B , S IN1B , S IN0C .
  • the D-phase sampling period and the P-phase sampling period are alternately repeated.
  • Time t1 to t2 in FIG. 8 is the D-phase sampling period.
  • switch control signals S VMA and S VMB become high, and switches 193A1, 193A2, 193B1, and 193B2 are turned on.
  • capacitor 195A1, capacitor 195A2, capacitor 195B1, and capacitor 195B2 a common mode reference voltage VCM is applied to each other end.
  • the switched capacitor 196A holds the correlated pixel signal, which is the difference between the reset level of the pixel signal and the signal level, which is output from one of the two column amplifier groups 147A and 147B.
  • the switched capacitor 196B holds (samples) the correlated pixel signal output from the other column amplifier group 147B of the two column amplifier groups 147A and 147B.
  • capacitors 195A1 and 195A2 are collectively referred to as capacitor 195A
  • capacitors 195B1 and 195B2 are collectively referred to as capacitor 195B
  • capacitors 195C1 and 195C2 are collectively referred to as capacitor 195C.
  • the time t2 to t3 is the P-phase sampling period, and the capacitance section 19 does not sample the correlated pixel signal during this period. Instead, a process of sequentially transferring the correlated pixel signals held in the capacitor 19 to the successive approximation AD converter 150 is performed.
  • the four capacitors 195A in the four switched capacitors 196A holding the correlated pixel signals from one column amplifier group 147A sequentially transfer the held correlated pixel signals to the successive approximation AD converter 150. do.
  • the correlated pixel signals held by the four capacitors 195B in the four switched capacitors 196B are not yet transferred to the successive approximation AD converter 150 during the period from t2 to t3.
  • Time t3-t4 is a D-phase sampling period, during which the four capacitors 195A in the four switched capacitors 196A are output from one column amplifier group 147A out of the two column amplifier groups 147A and 147B. hold the correlated pixel signal.
  • the four switched capacitors 196C hold (sample) correlated pixel signals output from the other column amplifier group 147B of the two column amplifier groups 147A and 147B.
  • the correlated pixel signals in the four capacitors 195B held during the D-phase sampling period from time t1 to t2 are sequentially transferred to the successive approximation AD converter 150. be done.
  • Time t4 to t5 is a P-phase sampling period. During this period, four capacitors 195A in four switched capacitors 196A holding correlated pixel signals from one column amplifier group 147A are connected to the held correlation pixel signals. The pixel signals are sequentially transferred to the successive approximation AD converter 150 .
  • the correlated pixel signal output from one column amplifier group 147A is always held in the switched capacitor 196A, and the correlated pixel signal output from the other column amplifier group 147B is held in the switched capacitors 196B and 196CC. held alternately.
  • One of the two switched capacitors 196B and 196C in the capacitor section 19 alternately suspends the sampling operation of the correlated pixel signal during the D-phase sampling period.
  • sampling of the correlated pixel signal to the capacitor section 19 is performed only during the D-phase sampling period.
  • the transfer of the correlated pixel signal from the capacitor unit 19 to the successive approximation AD converter 150 is performed during the P-phase sampling period and the D-phase sampling period.
  • FIGS. 9 to 14 are diagrams schematically showing the flow of pixel signals (correlated pixel signals) at times t2 to t8 in FIG. Pixel signals at times t2-t3 in FIG. 9, times t3-t4 in FIG. 10, times t4-t5 in FIG. 11, times t5-t6 in FIG. 12, times t6-t7 in FIG. 13, and times t7-t8 in FIG.
  • the flow of (correlated pixel signals) is indicated by arrow lines.
  • pixel signals (P-phase signals) on the signal lines VSL0 to VSL3 are input to one column amplifier group 147A, and are applied to the signal lines VSL4 to VSL7.
  • the upper pixel signal (P-phase signal) is input to the other column amplifier group 147B.
  • the pixel signal is a reset-level P-phase signal, and the capacitors 145 and 146 in each column amplifier 140 in each of the column amplifier groups 147A and 147B hold charges according to the P-phase signal.
  • the pixel signals (D-phase signals) on the signal lines VSL0 to VSL3 are input to one column amplifier group 147A, and the signal line Pixel signals (D-phase signals) on VSL4 to VSL7 are input to the other column amplifier group 147B.
  • correlated pixel signals which are the difference between the P-phase signal and the D-phase signal, are generated and output from each column amplifier 140 .
  • a correlated pixel signal output from one column amplifier group 147A is held in a capacitor 195A within a switched capacitor 196A.
  • the correlated pixel signal output from the other column amplifier group 147B is held in the capacitor 195B within the switched capacitor 196B.
  • the pixel signals (P-phase signals) on the signal lines VSL0 to VSL3 are input to one column amplifier group 147A, and the signal line Pixel signals (P-phase signals) on VSL4 to VSL7 are input to the other column amplifier group 147B.
  • Charges according to these P-phase signals are held in capacitors 145 and 146 in each column amplifier 140 in each column amplifier group 147A, 147B.
  • the correlated pixel signals held in the four capacitors 195A in the switched capacitor 196A are transferred to the successive approximation AD converter 150 in order.
  • the pixel signals (D-phase signals) on the signal lines VSL0 to VSL3 are input to one column amplifier group 147A, and the signal line Pixel signals (D-phase signals) on VSL4 to VSL7 are input to the other column amplifier group 147B. Generate and output a signal.
  • Correlated pixel signals output from one column amplifier group 147A are held in four capacitors 195A in the switched capacitor 196A.
  • Correlated pixel signals output from the other column amplifier group 147B are held in four capacitors 195C in the switched capacitor 196C. Also, during this period, the correlated pixel signals held in the switched capacitor 196B are transferred to the successive approximation AD converter 150 in order.
  • the pixel signals (P-phase signals) on the signal lines VSL0 to VSL3 are input to one column amplifier group 147A, and the signal line Pixel signals (P-phase signals) on VSL4 to VSL7 are input to the other column amplifier group 147B.
  • Charges according to these P-phase signals are held in capacitors 145 and 146 in each column amplifier 140 in each column amplifier group 147A, 147B.
  • the correlated pixel signals held in the four capacitors 195A in the switched capacitor 196A are transferred to the successive approximation AD converter 150 in order.
  • the pixel signals (D-phase signals) on the signal lines VSL0 to VSL3 are input to one column amplifier group 147A, and the signal line Pixel signals (D-phase signals) on VSL4 to VSL7 are input to the other column amplifier group 147B. Generate and output a signal.
  • Correlated pixel signals output from one column amplifier group 147A are held in four capacitors 195A in the switched capacitor 196A.
  • Correlated pixel signals output from the other column amplifier group 147B are held in four capacitors 195B in the switched capacitor 196B.
  • the correlated pixel signals held in the four capacitors 195C in the switched capacitor 196C are transferred to the successive approximation AD converter 150 in order.
  • the switched capacitor 196A is dedicated to sampling the correlated pixel signal output from one column amplifier group 147A.
  • the switched capacitors 196B and 196C are alternately used to sample the correlation image signal output from the other column amplifier group 147B. In this way, random noise can be reduced by using the three switched capacitors 196A, 196B, and 196C intentionally non-uniformly to sample the correlation image signal instead of using them evenly.
  • FIG. 15A is a block diagram of a column processing system according to a comparative example.
  • the column signal processing system of FIG. 15A equally uses the three switched capacitors 196A, 196B, and 196C in the capacitor section 19.
  • the column signal processing system of FIG. 15A has a configuration in which switches 191A2, 191B2 and 191C2 are added to the internal configuration of each capacitive multiplexer 190 of FIG.
  • One end of each of the switches 191A2, 191B2, 191C2 is connected to the output node of the other column amplifier group 147B.
  • FIG. 15B is an operation timing chart of a column signal processing system according to a comparative example.
  • the correlated pixel signals output from one column amplifier group 147A are held in four capacitors 195A in the switched capacitors 196A in the capacitive section 19.
  • FIG. Correlated pixel signals output from the other column amplifier group 147B are held in four capacitors 195B in the switched capacitor 196B.
  • the correlated pixel signals held in the four capacitors 195A in the switched capacitor 196A are transferred to the successive approximation AD converter 150 in order.
  • the correlated pixel signals output from one column amplifier group 147A are held in four capacitors 195C in the switched capacitors 196C in the capacitive section 19.
  • Correlated pixel signals output from the other column amplifier group 147B are held in four capacitors 195A in the switched capacitor 196A.
  • the correlated pixel signals held in the four capacitors 195B in the switched capacitor 196B are transferred to the successive approximation AD converter 150 in order.
  • the correlated pixel signals held in the four capacitors 195C in the switched capacitor 196C are transferred to the successive approximation AD converter 150 in order.
  • the correlated pixel signals output from one column amplifier group 147A are held in four capacitors 195B in the switched capacitors 196B in the capacitive section 19.
  • Correlated pixel signals output from the other column amplifier group 147B are held in four capacitors 195C in the switched capacitor 196A.
  • the correlated pixel signals held in the four capacitors 195A in the switched capacitor 196A are transferred to the successive approximation AD converter 150 in order.
  • the correlated pixel signals held in the four capacitors 195B in the switched capacitor 196B are transferred to the successive approximation AD converter 150 in order.
  • the three switched capacitors 196A, 196B, and 196C in the capacitor section 19 are evenly used. More specifically, the correlated pixel signals output from one column amplifier group 147A are held in the order of the switched capacitors 196A ⁇ 196C ⁇ 196B ⁇ 196A ⁇ . Also, the correlated pixel signals output from the other column amplifier group 147B are held in the order of the switched capacitors 196B ⁇ 196A ⁇ 196C ⁇ 196B ⁇ .
  • the symmetry is slightly worse than that of the comparative example, random noise is less visible
  • calibration can be performed in a short time, and the calibration result can be obtained.
  • the memory capacity to be stored can be reduced.
  • the number of combinations of switched capacitors 196A, 196B, and 196C can be reduced, the number of wirings of column amplifier group 147 and capacitor section 19 can be reduced, and the circuit scale of the column signal processing system can be reduced.
  • a digital signal after AD conversion processing by the AD converter 150 may have poor linearity, may contain an offset error, or may contain a gain error. Therefore, in an imaging apparatus, various correction processes may be performed on digital pixel signals generated by AD-converting pixel signals.
  • FIG. 16 is a schematic block diagram of an imaging device 100a including an assist processing section 61.
  • the imaging device 100a has an AD conversion section 15 and an assist processing section 61.
  • the assist processing unit 61 includes a linearity correction/decoding processing unit 62 , an offset/gain error correction unit 63 , and a storage unit 64 .
  • the linearity correction/decoding processing unit 62 has a decoding processing/error correction unit 65 and an error detection unit 66 .
  • the decoding processing/error correction unit 65 corrects errors in the digital signal output from the AD converter 150 based on the linearity correction data output from the error detection unit 66, and outputs a decoded signal.
  • the error detector 66 detects a linearity error based on the decoded signal and generates linearity correction data.
  • the offset/gain error correction section 63 has an offset detection section 67 , an offset correction section 68 , a gain error detection section 69 and a gain error correction section 70 .
  • the offset detection unit 67 detects an offset based on the decoded signal and generates offset correction data.
  • the offset correction unit 68 corrects the offset of the decoded signal based on the offset correction data, and generates an offset-corrected decoded signal.
  • a gain error detection section 69 detects a gain error based on the output signal of the offset detection section 67 and generates gain error correction data.
  • the gain error correcting section 70 corrects the gain error of the offset-corrected decoded signal based on the gain error correction data, and generates a gain error-corrected decoded signal.
  • the storage unit 64 stores linearity correction data, offset correction data, and gain error correction data.
  • the storage unit 64 associates and stores identification information indicating a combination of the switched capacitors 196A, 196B, and 196C, linearity correction data, offset correction data, and gain error correction data. Therefore, the greater the number of combinations of the switched capacitors 196A, 196B, and 196C, the greater the processing load on the assist processing section 61 and the greater the memory capacity of the storage section.
  • FIG. 17 is a circuit diagram showing a schematic configuration of a column signal processing system according to the second specific example.
  • the column signal processing system of FIG. It has three switched capacitors 196A, 196B, 196C and 196D.
  • FIG. 18 is an operation timing chart of the column signal processing system according to the second specific example shown in FIG.
  • the pixel signals on the signal lines VSL0 to VSL3 are held in the capacitors 145 and 146 in the four column amplifiers 140 in the first column amplifier group 147A.
  • the pixel signals on the signal lines VSL4 to VSL7 are held in the capacitors 145 and 146 in the four column amplifiers 140 in the second column amplifier group 147B
  • the pixel signals on the signal lines nVSL8 to VSL11 are held in the third column. It is held in the capacitors 145 and 146 in the four column amplifiers 140 in the amplifier group 147C.
  • the correlated pixel signals corresponding to the pixel signals on the signal lines VSL0 to VSL3 are held in the four capacitors 195A in the switched capacitors 196A in the capacitive section 19.
  • Correlated pixel signals corresponding to the pixel signals on the signal lines VSL4 to VSL7 are held in four capacitors 195B in the switched capacitor 196B.
  • the correlated pixel signals corresponding to the pixel signals on the signal lines VSL8 to VSL11 are held in four capacitors 195C in the switched capacitor 196C.
  • the correlated pixel signals held in the four capacitors 195A in the switched capacitor 196A are transferred to the successive approximation AD converter 150 in order. Pixel signals from the signal lines VSL0 to VSL11 are not input to any column amplifier group 147 during this period.
  • the correlated pixel signals held in the four capacitors 195B in the switched capacitor 196B are transferred to the successive approximation AD converter 150 in order.
  • the pixel signals on the signal lines VSL0 to VSL3 are held in the capacitors 145 and 146 in the four column amplifiers 140 in the first column amplifier group 147A, and the pixel signals on the signal lines VSL4 to VSL7 are held in the first column amplifier group 147A.
  • the pixel signals on the signal lines VSL8 to VSL11 are held by the capacitors 145 and 146 in the four column amplifiers 140 in the 2-column amplifier group 147B, and the pixel signals on the signal lines VSL8 to VSL11 are transferred to the capacitors 145 and 145 in the four column amplifiers 140 in the fourth column amplifier group. It is held in capacitor 146 .
  • the correlated pixel signals corresponding to the pixel signals on the signal lines VSL0 to VSL3 are held in the four capacitors 195A in the switched capacitors 196A in the capacitor section 19.
  • Correlated pixel signals corresponding to the pixel signals on the signal lines VSL4 to VSL7 are held in four capacitors 195B in the switched capacitor 196B.
  • Correlated pixel signals corresponding to the pixel signals on the signal lines VSL8 to VSL11 are held in four capacitors 195D in the switched capacitor D.
  • the switched capacitors 196A and 196B are connected to the first column amplifier group 147A and the second column amplifier group 147A.
  • Each of the correlated pixel signals output from the amplifier group 147B is held.
  • the switched capacitor 196C and the switched capacitor 196D alternately hold the correlated pixel signals output from the third column amplifier group 147C.
  • the four switched capacitors 196A, 196B, 196C, and 196D in the capacitor section 19 are selected unevenly, so random noise is less visible. Also, since there are only four combinations of switched capacitors 196A, 196B, 196C, and 196D, the calibration time can be shortened, and the memory capacity for storing calibration results can be reduced. Further, since the number of wirings of the column amplifier group 147 and the capacitor section 19 can be reduced, the circuit scale of the column signal processing system can be reduced.
  • the image pickup apparatus uses the switched capacitors 196 ( The number of capacitors 195) is increased.
  • the specific number of column amplifier groups 147 and the number of capacitors 195 do not matter.
  • AD conversion processing as shown in FIG. 8 becomes possible, random noise becomes less visible, calibration can be performed in a short time, and memory capacity for storing calibration results can be reduced.
  • the number of wires in the capacitive multiplexer 190 can be reduced.
  • FIG. 19 is a circuit diagram of a column signal processing system in which circuits for generating voltages VR, VCM, VH, VM, and VL are added to FIG.
  • FIG. 19 shows the column amplifier 140, the capacitance multiplexer 190, and the reference voltage generator 160 that generates the reference voltage used in the successive approximation analog-digital converter 150.
  • the reference voltage generating section 160 is composed of a first amplifier section 161 , a second amplifier section 162 and a third amplifier section 163 .
  • the first amplifier section 161 generates a local reference voltage VR that defines the zero voltage of the output of the column amplifier 140 .
  • Local reference voltage VR is supplied to column amplifier 140 through voltage line L1.
  • the second amplifier section 162 supplies the output common mode reference voltage VCM of the preamplifier 151 to the capacitance multiplexer 190 through the voltage line L2.
  • the output common mode reference voltage VCM is also supplied to successive approximation analog-to-digital converter 150 through voltage line L3.
  • a third amplifier unit 163 generates a high voltage VH, a medium voltage VM, and a low voltage VL used in the capacitor array unit (CDAC) 155 .
  • a high voltage VH, a middle voltage VM, and a low voltage VL are supplied to a capacitor array section (CDAC) 155 through voltage lines L4, L5, and L6.
  • the capacitor 145 of the column amplifier 140 is charged with the local reference voltage VR, and during the D phase, the local reference voltage VR is used as the negative side signal input of the capacitance multiplexer 190 (CMUX) 190 .
  • the capacitive multiplexer 190 is configured differentially. Switches 192_A, 192_B, and 192_C on the input side short the differentials during comparison by the comparator 152 and are not connected to the common node. By doing so, the input side of the capacitive multiplexer 190 is completely isolated when the comparator 152 compares, so that the settling of the capacitive array section (CDAC) 155 in the successive approximation analog-digital converter 150 can be accelerated.
  • CDAC capacitive array section
  • the switches 193_AP, 193_AM, switches 193_BP, 193_BM, and switches 193_CP, 193_CM on the output side of the capacitive multiplexer 190 are connected to the voltage line L2 that transmits the output common mode reference voltage VCM, and are turned on during sampling.
  • the output common mode reference voltage VCM is the same voltage as the input operating potential of preamplifier 151 .
  • the high voltage VH, medium voltage VM, and low voltage VL generated by the third amplifier section 163 are reference voltages for the capacitor array section (CDAC) 155 . Since the capacitor array unit (CDAC) 155 operates at high speed during comparison by the comparator 152, it is required that the high voltage VH and the low voltage VL can respond quickly and have low impedance.
  • the high voltage VH/low voltage VL are set to 0.8 V (VDD_L) and the same voltage as the ground, respectively, in order to apply a sufficient gate voltage to the switches forming the capacitor array section (CDAC) 155 . Since the voltage of the output of the column amplifier 140 is high, the switches constituting the capacitance multiplexer 190 are all constructed of high-voltage transistors.
  • FIG. 20 shows a level diagram.
  • the voltage range of the potential VSL of the signal line 32 varies depending on the sensor specifications, here, the voltage drops according to the lightness with 2V as the reference, and the maximum voltage drop is 450 mV.
  • the potential VSL of the signal line 32 is amplified by the column amplifier 140.
  • the higher the gain the more the noise of the subsequent successive approximation analog-digital converter 150 is suppressed, and the noise of the column amplifier 140 itself is also reduced. It is desirable to obtain as large a gain as possible.
  • the power supply voltage is 2.8 V, it is necessary to suppress the output of the column amplifier 140 within a range obtained by adding the operating range and margin of the circuit.
  • the input of the successive approximation analog-digital converter 150 is a differential voltage, and the negative side input is fixed to the reference voltage.
  • a differential 0 V is input to the successive approximation analog-to-digital converter 150, and as it gets brighter (ie, the potential VSL on the signal line 32 decreases), a negative differential voltage is applied.
  • the relationship with the output code of the successive approximation analog-digital converter 150 is such that the differential 1.8 V corresponds to 3/4 full scale, and 7/8 full scale is output when 0 V is input. ing.
  • input conversion noise can be reduced by increasing the gain. As shown in FIG. 20, if the gain is increased eight times ( ⁇ 8), the input range is halved. Furthermore, the gain can be increased, but since the contribution of the column amplifier 140 is dominant in the input-converted noise, there is little merit in increasing the gain to 8 times or more.
  • FIG. 21 shows a circuit diagram of an example of the configuration of a current reuse column amplifier.
  • the current reuse column amplifier 1400 has a current amplifying transistor 1401, current source transistors 1402 and 1403, cascode transistors 1404 and 1405, switches 1406, 1407 and 1408, a reference side capacitive element 1409, and a feedback capacitive element 1410. there is
  • the current amplification transistor 1401 the current source transistor 1403, and the cascode transistor 1404, for example, P-channel MOS field effect transistors are used.
  • the current amplifying transistor 1401 and the current source transistor 1402 are connected in series between the signal line 32 and a reference potential (for example, ground) node in that order. That is, the current amplification transistor 1401 has the source electrode connected to the signal line 32 .
  • a predetermined bias voltage nbias is applied to the gate electrode of the current source transistor 1402 .
  • the current source transistor 1402 causes a constant bias current corresponding to the predetermined bias voltage nbias to flow through the signal line 32 .
  • the current source transistor 1403, the cascode transistor 1404, and the cascode transistor 1405 are connected in series between the node of the power supply voltage VDD and the drain electrode of the current source transistor 1402 in that order.
  • a predetermined bias voltage pbias is applied to the gate electrode of the current source transistor 1403, a predetermined bias voltage pcas is applied to the gate electrode of the cascode transistor 1404, and a predetermined bias voltage is applied to the gate electrode of the cascode transistor 1405. ncas is applied.
  • the switch 1406 is connected between the gate electrode of the current amplification transistor 1401 and the drain electrode of the cascode transistor 1404 (drain electrode of the cascode transistor 1405), and is turned on (closed) according to the polarity of the switch control signal S P . )/off (open) operation.
  • the reference-side capacitive element 1409 is connected between the gate electrode of the current amplification transistor 1401 and a reference potential (for example, ground) node.
  • One end of the feedback capacitive element 1410 is connected to the gate electrode of the current amplification transistor 1401 .
  • the switch 1047 is connected between the other end of the feedback capacitance element 1410 and the drain electrode of the cascode transistor 1404 (the drain electrode of the cascode transistor 1405), and turns on/off depending on the polarity of the switch control signal SD . take action.
  • switch 1408 One end of the switch 1408 is connected to a common connection node N11 between the feedback capacitive element 1410 and the switch 1047, and performs ON/OFF operation according to the polarity of the switch control signal SVR .
  • the other end of switch 1408 is applied to local reference voltage VR. This causes switch 1408 to selectively provide local reference voltage VR to common connection node N11 under the control of switch control signal SVR.
  • the source electrode of the current amplification transistor 1401 becomes the (+) input terminal
  • the gate electrode becomes the (-) input terminal
  • the common connection node N12 of the cascode transistors 1404 and 1405 becomes the output terminal.
  • a column amplifier 1400 is configured. Since the current amplification transistor 1401 uses the bias current of the signal line 32, it can efficiently amplify the voltage.
  • the switch 1406 corresponds to the switch 142 in FIG. corresponds to switch 144 in FIG.
  • the reference-side capacitive element 1409 corresponds to the capacitive element 146 having the capacitance value CS
  • the feedback capacitive element 1410 corresponds to the capacitive element 145 having the capacitance value CF.
  • Successive approximation analog-to-digital converter 150 is highly power efficient. A detailed circuit diagram of the successive approximation analog-digital converter 150 is shown in FIG.
  • the circuit of the successive approximation type analog-digital converter 150 is configured completely differentially.
  • a typical successive approximation analog-digital converter often integrates an input capacitor that samples the input voltage and a DAC capacitor (CDAC), but here they are separated for multiplexing. .
  • CDAC DAC capacitor
  • FIG. 22 also illustrates the input capacitance unit 19 (hereinafter referred to as "capacity multiplexer 190" for convenience) that also serves as the capacitance multiplexer 190.
  • Capacity multiplexer 190 for convenience
  • FIG. Here, for the sake of simplicity, only one of the plurality of input capacitors 19 (190) is shown.
  • the switches 191_P and 191_M and the switches 193_P and 193_M are turned on (closed) to charge the capacitive elements 195_P and 195_M.
  • the switch 192 and the switches 194_P and 194_M are turned on (closed) to connect the capacitance multiplexer 190 to the successive approximation analog-to-digital converter 150 .
  • the switch 192 only shorts between the differentials without being connected to a specific reference potential. This is to prevent the common-mode potential of the preamplifier 151 from fluctuating due to the input common-mode potential. If the output common mode potential of the preamplifier 151 and the output common mode reference voltage VCM are matched, the input common mode potential of the preamplifier 151 will always be the same as the output common mode reference voltage VCM.
  • the output of the column amplifier 140 is single-ended, the input common-mode potential fluctuates depending on the signal, but the input common-mode potential of the preamplifier 151 does not change, so linearity is improved.
  • the input side is the output of the column amplifier 140 (2.4V to 0.6V) and the local reference voltage VR (2.4V), but the output common mode reference voltage VCM is fixed at about 0.5V, so it is low.
  • a voltage (VDD_L) preamplifier 151 can be used.
  • the input differential voltage is as high as 1.8V
  • the input voltage of the preamplifier 151 is sufficiently attenuated because it is connected in series with the DAC capacitor (CDAC) during charge transfer.
  • CDAC DAC capacitor
  • the preamplifier 151, comparator 152, SAR logic unit 153, and DAC capacitor (CDAC) switch in the comparison loop of the successive approximation analog-digital converter 150 all use transistors with the same power supply voltage and the same film thickness. This enables high-speed operation.
  • the SAR logic unit 153 is completely isolated from the column amplifier 140 and reference nodes other than the high voltage VH/low voltage VL during operation. Since these nodes are not very fast and low impedance, it is necessary not to affect the settling of the DAC capacitance (CDAC).
  • CDAC DAC capacitance
  • the capacitor array of DAC capacitors consists of 14 capacitors grouped in 6-4-4.
  • the first 6-bit group is MSB
  • the middle 4-bit group is LSB1
  • the last 4-bit group is LSB0.
  • Each group is separated by a bridge capacitive element and the weight per capacitive element is changed. If the weight of MSB is 1, LSB1 is 1/8 and LSB0 is 1/32.
  • the weights of the most significant bit in LSB1 and the least significant bit of MSB are the same value, providing redundancy.
  • LSB0 similarly duplicates the most significant bit. Since the redundancy is 2 bits in total, the bit precision of the successive approximation analog-digital converter 150 is finally 12 BIT. Redundancy is for compensating for insufficient settling of upper bits and for correcting nonlinearity due to variations in bridge capacitive elements.
  • redundant bits In order to expand the range of redundancy, redundant bits should be inserted as high as possible, but there is a trade-off in that the number of capacitive elements increases, and noise also increases. Also, redundant bits need to be inserted in each group to compensate for variations in the bridge capacitive elements.
  • the capacitance value CB of the bridge capacitance element can be expressed by the following equation, where ⁇ ( ⁇ 1) is the weight ratio to the lower group, and CTL is the total capacitance value of the lower group (including the actual capacitance value of the lower group). can.
  • CB CTL/ ⁇ (1/ ⁇ ) ⁇ 1 ⁇
  • the bridge capacitive element determines the weight of the entire low-order bit, nonlinearity occurs when the ratio with the unit capacitive element deviates. Therefore, it is necessary to mount them so as not to shift as much as possible. However, it is difficult to match the ratio of the bridge capacitive element and the unit capacitive element because it is not an integer multiple and there is no continuity in the layout. Therefore, it seems necessary to perform digital correction by multiplying each group by a non-integer correction factor.
  • the second embodiment of the present disclosure is an example in which the technology according to the present disclosure is applied to an indirect TOF (Indirect-Time of Flight) range image sensor.
  • Indirect TOF range image sensors reflect light emitted from a light source on an object to be measured (subject), and measure the light flight time based on the detection of the arrival phase difference of the reflected light. It is a sensor that measures the distance between
  • FIG. 23 is a block diagram showing an example of a system configuration of an indirect TOF range image sensor according to the second embodiment of the present disclosure
  • the indirect TOF range image sensor 50 has a laminated structure including a sensor chip 51 and a circuit chip 52 laminated on the sensor chip 51 .
  • the sensor chip 51 and the circuit chip 52 are electrically connected through connecting portions (not shown) such as vias (VIAs) and Cu--Cu connections.
  • FIG. 23 illustrates a state in which the wiring of the sensor chip 51 and the wiring of the circuit chip 52 are electrically connected via the connection portion described above.
  • a pixel array section 53 is formed on the sensor chip 51 .
  • the pixel array section 53 includes a plurality of pixels 54 arranged in a matrix (array) in a two-dimensional grid pattern on the sensor chip 51 .
  • each of the plurality of pixels 54 receives incident light (for example, near-infrared light), performs photoelectric conversion, and outputs an analog pixel signal.
  • Two signal lines VSL1 and VSL2 are wired in the pixel array section 53 for each pixel column. Assuming that the number of pixel columns in the pixel array section 53 is M (M is an integer), a total of (2 ⁇ M) signal lines VSL are wired in the pixel array section 53 .
  • Each of the plurality of pixels 54 has first and second taps A and B (details of which will be described later).
  • the signal line VSL1 outputs an analog pixel signal AINP1 based on the charges of the first taps A of the pixels 54 in the corresponding pixel column.
  • an analog pixel signal AINP2 based on the charges of the second taps B of the pixels 54 in the corresponding pixel column is output to the signal line VSL2.
  • the analog pixel signals AINP1 and AINP2 will be described later.
  • a row selection unit 55 , a column signal processing unit 56 , an output circuit unit 57 , and a timing control unit 58 are arranged on the circuit chip 52 .
  • the row selection unit 55 drives the pixels 54 of the pixel array unit 53 in units of pixel rows to output pixel signals AINP1 and AINP2.
  • the analog pixel signals AINP1 and AINP2 output from the pixels 54 in the selected row are supplied to the column signal processor 56 through the two signal lines VSL1 and VSL2 under the driving of the row selector 55 .
  • the column signal processing section 56 has a plurality of analog-digital converters (ADC) 59 provided corresponding to the pixel columns of the pixel array section 53 (for example, for each pixel column).
  • the analog-digital converter 59 performs analog-digital conversion processing on the analog pixel signals AINP1 and AINP2 supplied through the signal lines VSL1 and VSL2, and outputs them to the output circuit section 57.
  • FIG. The output circuit section 57 performs predetermined signal processing on the digitized pixel signals AINP1 and AINP2 output from the column signal processing section 56, and outputs them to the outside of the circuit chip 52.
  • the timing control unit 58 generates various timing signals, clock signals, control signals, etc., and drives the row selection unit 55, the column signal processing unit 56, the output circuit unit 57, etc. based on these signals. control.
  • FIG. 24 is a circuit diagram showing an example of the circuit configuration of the pixels 54 in the indirect TOF range image sensor 50 according to the second embodiment.
  • the pixel 54 has, for example, a photodiode 541 as a photoelectric conversion element.
  • the pixel 54 includes an overflow transistor 542, two transfer transistors 543 and 544, two reset transistors 545 and 546, two floating diffusion layers 547 and 548, two amplification transistors 549, 550 and 2 It is configured to have two selection transistors 551 and 552 .
  • the two floating diffusion layers 547 and 548 correspond to the first and second taps A and B (hereinafter sometimes simply referred to as "taps A and B") shown in FIG.
  • the photodiode 541 photoelectrically converts the received light to generate electric charge.
  • the photodiode 541 can have, for example, a back-illuminated pixel structure.
  • the structure is not limited to the backside irradiation type structure, and a front side irradiation type structure that takes in the light irradiated from the substrate surface side can also be used.
  • the overflow transistor 542 is connected between the cathode electrode of the photodiode 541 and the power supply line of the power supply voltage VDD, and has the function of resetting the photodiode 541 . Specifically, the overflow transistor 542 becomes conductive in response to the overflow gate signal TRG supplied from the row selection unit 55, thereby transferring the charge generated by the photodiode 541 to the floating diffusion layers 547 and 548. Each is transferred sequentially.
  • the floating diffusion layers 547 and 548 corresponding to the first and second taps A and B accumulate the charge transferred from the photodiode 541, convert it into a voltage signal having a voltage value corresponding to the charge amount, and convert it into a pixel signal. Generate AINP1 and AINP2.
  • the two reset transistors 545 and 546 are connected between the two floating diffusion layers 547 and 548 respectively and the power supply line of the power supply voltage VDD.
  • the reset transistors 545 and 546 become conductive in response to the reset signal RST supplied from the row selection unit 55, thereby extracting charges from the floating diffusion layers 347 and 348, respectively, and initializing the charge amounts. do.
  • the two amplification transistors 549 and 550 are connected between the power supply line of the power supply voltage VDD and the two selection transistors 551 and 552, respectively, and charge is converted into voltage in the floating diffusion layers 547 and 548, respectively. Each voltage signal is amplified.
  • the two selection transistors 551, 552 are connected between the two amplification transistors 549, 550, respectively, and the signal lines VSL1, VSL2, respectively.
  • the selection transistors 551 and 552 become conductive in response to the selection signal SEL supplied from the row selection section 55, thereby converting the voltage signals amplified by the amplification transistors 549 and 550 into analog pixel signals. They are output to two signal lines VSL1 and VSL2 as AINP1 and AINP2.
  • the two signal lines VSL1 and VSL2 are connected to the input terminal of one analog-digital converter 59 in the column signal processing section 56 for each pixel column, and the analog signals output from the pixels 54 for each pixel column are connected. of pixel signals AINP1 and AINP2 are transmitted to the analog-digital converter 59.
  • circuit configuration of the pixel 54 is not limited to the circuit configuration illustrated in FIG. 24 as long as it is a circuit configuration that can generate analog pixel signals AINP1 and AINP2 by photoelectric conversion.
  • the technology according to the present disclosure can be applied to the column signal processing unit 56 including the analog-digital converter 59 in the indirect TOF range image sensor 50 configured as described above. More specifically, as the column signal processing unit 56 including the analog-digital converter 59, as in the first embodiment, the column amplifier unit 14, the capacitor unit 19, and the successive approximation analog-digital conversion unit A column signal processing system according to Example 1, Example 2, Example 3, or Example 4, including 15A, can be used.
  • CMOS image sensor and the indirect TOF range image sensor described in the above embodiments are examples, and can be changed as appropriate.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be applied to any type of movement such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, robots, construction machinery, agricultural machinery (tractors), etc. It may also be implemented as a body-mounted device.
  • FIG. 25 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • Vehicle control system 7000 comprises a plurality of electronic control units connected via communication network 7010 .
  • the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside information detection unit 7400, an inside information detection unit 7500, and an integrated control unit 7600.
  • the communication network 7010 that connects these multiple control units conforms to any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay (registered trademark). It may be an in-vehicle communication network.
  • Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a storage unit that stores programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various devices to be controlled. Prepare.
  • Each control unit has a network I/F for communicating with other control units via a communication network 7010, and communicates with devices or sensors inside and outside the vehicle by wired communication or wireless communication. A communication I/F for communication is provided. In FIG.
  • the functional configuration of the integrated control unit 7600 includes a microcomputer 7610, a general-purpose communication I/F 7620, a dedicated communication I/F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle equipment I/F 7660, an audio image output unit 7670, An in-vehicle network I/F 7680 and a storage unit 7690 are shown.
  • Other control units are similarly provided with microcomputers, communication I/Fs, storage units, and the like.
  • the drive system control unit 7100 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 7100 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the drive system control unit 7100 may have a function as a control device such as ABS (Antilock Brake System) or ESC (Electronic Stability Control).
  • a vehicle state detection section 7110 is connected to the drive system control unit 7100 .
  • the vehicle state detection unit 7110 includes, for example, a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, an accelerator pedal operation amount, a brake pedal operation amount, and a steering wheel steering. At least one of sensors for detecting angle, engine speed or wheel rotation speed is included.
  • Drive system control unit 7100 performs arithmetic processing using signals input from vehicle state detection unit 7110, and controls the internal combustion engine, drive motor, electric power steering device, brake device, and the like.
  • the body system control unit 7200 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 7200 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • body system control unit 7200 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • Body system control unit 7200 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the driving motor, according to various programs. For example, the battery control unit 7300 receives information such as battery temperature, battery output voltage, or remaining battery capacity from a battery device including a secondary battery 7310 . The battery control unit 7300 performs arithmetic processing using these signals, and performs temperature adjustment control of the secondary battery 7310 or control of a cooling device provided in the battery device.
  • the vehicle exterior information detection unit 7400 detects information outside the vehicle in which the vehicle control system 7000 is installed.
  • the imaging section 7410 and the vehicle exterior information detection section 7420 is connected to the vehicle exterior information detection unit 7400 .
  • the imaging unit 7410 includes at least one of a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras.
  • the vehicle exterior information detection unit 7420 includes, for example, an environment sensor for detecting the current weather or weather, or a sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000. ambient information detection sensor.
  • the environmental sensor may be, for example, at least one of a raindrop sensor that detects rainy weather, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall.
  • the ambient information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device.
  • LIDAR Light Detection and Ranging, Laser Imaging Detection and Ranging
  • These imaging unit 7410 and vehicle exterior information detection unit 7420 may be provided as independent sensors or devices, or may be provided as a device in which a plurality of sensors or devices are integrated.
  • FIG. 26 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420.
  • the imaging units 7910 , 7912 , 7914 , 7916 , and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 7900 .
  • An image pickup unit 7910 provided in the front nose and an image pickup unit 7918 provided above the windshield in the vehicle interior mainly acquire an image in front of the vehicle 7900 .
  • Imaging units 7912 and 7914 provided in the side mirrors mainly acquire side images of the vehicle 7900 .
  • An imaging unit 7916 provided in the rear bumper or back door mainly acquires an image behind the vehicle 7900 .
  • An imaging unit 7918 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 26 shows an example of the imaging range of each of the imaging units 7910, 7912, 7914, and 7916.
  • the imaging range a indicates the imaging range of the imaging unit 7910 provided in the front nose
  • the imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided in the side mirrors, respectively
  • the imaging range d is The imaging range of an imaging unit 7916 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.
  • the vehicle exterior information detectors 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and above the windshield of the vehicle interior of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices.
  • the exterior information detectors 7920, 7926, and 7930 provided above the front nose, rear bumper, back door, and windshield of the vehicle 7900 may be LIDAR devices, for example.
  • These vehicle exterior information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, and the like.
  • the vehicle exterior information detection unit 7400 causes the imaging section 7410 to capture an image of the exterior of the vehicle, and receives the captured image data.
  • the vehicle exterior information detection unit 7400 also receives detection information from the vehicle exterior information detection unit 7420 connected thereto.
  • the vehicle exterior information detection unit 7420 is an ultrasonic sensor, radar device, or LIDAR device
  • the vehicle exterior information detection unit 7400 emits ultrasonic waves, electromagnetic waves, or the like, and receives reflected wave information.
  • the vehicle exterior information detection unit 7400 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received information.
  • the vehicle exterior information detection unit 7400 may perform environment recognition processing for recognizing rainfall, fog, road surface conditions, etc., based on the received information.
  • the vehicle exterior information detection unit 7400 may calculate the distance to the vehicle exterior object based on the received information.
  • the vehicle exterior information detection unit 7400 may perform image recognition processing or distance detection processing for recognizing people, vehicles, obstacles, signs, characters on the road surface, etc., based on the received image data.
  • the vehicle exterior information detection unit 7400 performs processing such as distortion correction or alignment on the received image data, and synthesizes image data captured by different imaging units 7410 to generate a bird's-eye view image or a panoramic image. good too.
  • the vehicle exterior information detection unit 7400 may perform viewpoint conversion processing using image data captured by different imaging units 7410 .
  • the in-vehicle information detection unit 7500 detects in-vehicle information.
  • the in-vehicle information detection unit 7500 is connected to, for example, a driver state detection section 7510 that detects the state of the driver.
  • the driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the biometric information of the driver, a microphone that collects sounds in the vehicle interior, or the like.
  • a biosensor is provided, for example, on a seat surface, a steering wheel, or the like, and detects biometric information of a passenger sitting on a seat or a driver holding a steering wheel.
  • the in-vehicle information detection unit 7500 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 7510, and determine whether the driver is dozing off. You may The in-vehicle information detection unit 7500 may perform processing such as noise canceling processing on the collected sound signal.
  • the integrated control unit 7600 controls overall operations within the vehicle control system 7000 according to various programs.
  • An input section 7800 is connected to the integrated control unit 7600 .
  • the input unit 7800 is realized by a device that can be input-operated by the passenger, such as a touch panel, button, microphone, switch or lever.
  • the integrated control unit 7600 may be input with data obtained by recognizing voice input by a microphone.
  • the input unit 7800 may be, for example, a remote control device using infrared rays or other radio waves, or may be an externally connected device such as a mobile phone or PDA (Personal Digital Assistant) corresponding to the operation of the vehicle control system 7000.
  • PDA Personal Digital Assistant
  • the input unit 7800 may be, for example, a camera, in which case the passenger can input information through gestures.
  • the input section 7800 may include an input control circuit that generates an input signal based on information input by the passenger or the like using the input section 7800 and outputs the signal to the integrated control unit 7600, for example.
  • a passenger or the like operates the input unit 7800 to input various data to the vehicle control system 7000 and instruct processing operations.
  • the storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, and the like. Also, the storage unit 7690 may be realized by a magnetic storage device such as a HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.
  • ROM Read Only Memory
  • RAM Random Access Memory
  • the storage unit 7690 may be realized by a magnetic storage device such as a HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.
  • the general-purpose communication I/F 7620 is a general-purpose communication I/F that mediates communication between various devices existing in the external environment 7750.
  • General-purpose communication I/F 7620 is a cellular communication protocol such as GSM (registered trademark) (Global System of Mobile communications), WiMAX (registered trademark), LTE (registered trademark) (Long Term Evolution) or LTE-A (LTE-Advanced) , or other wireless communication protocols such as wireless LAN (also referred to as Wi-Fi®), Bluetooth®, and the like.
  • General-purpose communication I / F 7620 for example, via a base station or access point, external network (e.g., Internet, cloud network or operator-specific network) equipment (e.g., application server or control server) connected to You may
  • external network e.g., Internet, cloud network or operator-specific network
  • equipment e.g., application server or control server
  • the general-purpose communication I/F 7620 uses, for example, P2P (Peer To Peer) technology to connect terminals (for example, terminals of drivers, pedestrians, stores, or MTC (Machine Type Communication) terminals) near the vehicle. may be connected with P2P (Peer To Peer) technology to connect terminals (for example, terminals of drivers, pedestrians, stores, or MTC (Machine Type Communication) terminals) near the vehicle.
  • P2P Peer To Peer
  • MTC Machine Type Communication
  • the dedicated communication I/F 7630 is a communication I/F that supports a communication protocol designed for use in vehicles.
  • the dedicated communication I/F 7630 uses standard protocols such as WAVE (Wireless Access in Vehicle Environment), DSRC (Dedicated Short Range Communications), which is a combination of lower layer IEEE 802.11p and higher layer IEEE 1609, or cellular communication protocol. May be implemented.
  • the dedicated communication I/F 7630 is typically used for vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication. ) perform V2X communication, which is a concept involving one or more of the communications.
  • the positioning unit 7640 receives GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), performs positioning, and obtains the latitude, longitude, and altitude of the vehicle. Generate location information containing Note that the positioning unit 7640 may specify the current position by exchanging signals with a wireless access point, or may acquire position information from a terminal such as a mobile phone, PHS, or smart phone having a positioning function.
  • GNSS Global Navigation Satellite System
  • GPS Global Positioning System
  • the beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from wireless stations installed on the road, and acquires information such as the current position, traffic jams, road closures, or required time. Note that the function of the beacon reception unit 7650 may be included in the dedicated communication I/F 7630 described above.
  • the in-vehicle device I/F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle.
  • the in-vehicle device I/F 7660 may establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB).
  • a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB).
  • the in-vehicle device I/F 7660 is connected via a connection terminal (and cable if necessary) not shown, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface, or MHL (Mobile High -definition Link), etc.
  • In-vehicle equipment 7760 includes, for example, at least one of mobile equipment or wearable equipment possessed by passengers, or information equipment carried in or attached to the vehicle. In-vehicle equipment 7760 may also include a navigation device that searches for a route to an arbitrary destination. or exchange data signals.
  • the in-vehicle network I/F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. In-vehicle network I/F 7680 transmits and receives signals and the like according to a predetermined protocol supported by communication network 7010 .
  • the microcomputer 7610 of the integrated control unit 7600 uses at least one of a general-purpose communication I/F 7620, a dedicated communication I/F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I/F 7660, and an in-vehicle network I/F 7680.
  • the vehicle control system 7000 is controlled according to various programs on the basis of the information acquired by. For example, the microcomputer 7610 calculates control target values for the driving force generator, steering mechanism, or braking device based on acquired information on the inside and outside of the vehicle, and outputs a control command to the drive system control unit 7100. good too.
  • the microcomputer 7610 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control may be performed for the purpose of In addition, the microcomputer 7610 controls the driving force generator, the steering mechanism, the braking device, etc. based on the acquired information about the surroundings of the vehicle, thereby autonomously traveling without depending on the operation of the driver. Cooperative control may be performed for the purpose of driving or the like.
  • ADAS Advanced Driver Assistance System
  • Microcomputer 7610 receives information obtained through at least one of general-purpose communication I/F 7620, dedicated communication I/F 7630, positioning unit 7640, beacon receiving unit 7650, in-vehicle device I/F 7660, and in-vehicle network I/F 7680. Based on this, three-dimensional distance information between the vehicle and surrounding objects such as structures and people may be generated, and local map information including the surrounding information of the current position of the vehicle may be created. Further, based on the acquired information, the microcomputer 7610 may predict dangers such as vehicle collisions, pedestrians approaching or entering closed roads, and generate warning signals.
  • the warning signal may be, for example, a signal for generating a warning sound or lighting a warning lamp.
  • the audio/image output unit 7670 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 7710, a display section 7720 and an instrument panel 7730 are illustrated as output devices.
  • Display 7720 may include, for example, at least one of an on-board display and a head-up display.
  • the display unit 7720 may have an AR (Augmented Reality) display function.
  • the output device may be headphones, a wearable device such as an eyeglass-type display worn by a passenger, or other devices such as a projector or a lamp.
  • the display device displays the results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats such as text, images, tables, and graphs. Display visually.
  • the voice output device converts an audio signal including reproduced voice data or acoustic data into an analog signal and outputs the analog signal audibly.
  • At least two control units connected via the communication network 7010 may be integrated as one control unit.
  • an individual control unit may be composed of multiple control units.
  • vehicle control system 7000 may comprise other control units not shown.
  • some or all of the functions that any control unit has may be provided to another control unit. In other words, as long as information is transmitted and received via the communication network 7010, the predetermined arithmetic processing may be performed by any one of the control units.
  • sensors or devices connected to any control unit may be connected to other control units, and multiple control units may send and receive detection information to and from each other via communication network 7010. .
  • this technique can take the following structures.
  • a pixel array unit that outputs a plurality of photoelectrically converted pixel signals to a plurality of signal lines; two or more column amplifier groups that output a plurality of correlated pixel signals, which are differences between reset levels and signal levels of the two or more corresponding pixel signals, for each signal line group including two or more signal lines; a plurality of capacitive multiplexers each having a plurality of capacities for holding the plurality of correlated pixel signals; an analog-to-digital converter that sequentially converts the plurality of correlated pixel signals held in the plurality of capacitors into digital signals;
  • the imaging device wherein the number of the plurality of capacitors is larger than the number of the column amplifier groups.
  • each of the two or more column amplifier groups has a plurality of column amplifiers that output a plurality of correlated pixel signals that are differences between reset levels and signal levels of the corresponding two or more pixel signals;
  • each of the plurality of capacitor multiplexers includes the plurality of capacitors that hold the correlated pixel signals output from the corresponding column amplifier among the plurality of column amplifiers.
  • each of the plurality of column amplifiers a differential amplifier in which the potential of the signal line is input to the non-inverting input node; a first switch having one end connected to the output node of the differential amplifier and the other end connected to the inverting input node of the differential amplifier; a second switch one end of which is connected to the output node of the differential amplifier; a first capacitive element having one end connected to the other end of the second switch and having the other end connected to the other end of the first switch and the inverting input node of the differential amplifier; a second capacitive element connected between the other end of the first capacitive element and a reference potential node; and a third switch having one end connected to the other end of the second switch and one end of the first capacitive element, and having the other end to which a reference voltage is applied.
  • each of the plurality of capacitance multiplexers has a plurality of switched capacitors including the plurality of capacitances;
  • some of the plurality of capacitors hold correlated pixel signals output from a predetermined column amplifier group among the two or more column amplifier groups; Two or more capacitors other than the one portion of the plurality of capacitors are sequentially selected and output from a column amplifier group other than the predetermined column amplifier group out of the two or more column amplifier groups.
  • the imaging device according to any one of (1) to (4), which holds the correlated pixel signals.
  • the plurality of capacitors are the plurality of capacitors output from the two or more column amplifier groups within a period in which the signal levels of the plurality of pixel signals are output from the pixel array section to the two or more signal lines.
  • the imaging device according to any one of (1) to (5), which holds the correlated pixel signals of .
  • the plurality of capacitors are arranged within a period in which the reset levels of the plurality of pixel signals are output from the pixel array section to the two or more signal lines, and during a period in which the reset levels of the plurality of pixel signals are output to the two or more signal lines.
  • the imaging apparatus according to any one of (1) to (6), wherein the held plurality of correlated pixel signals are sequentially transferred to the analog-digital converter within a period in which the signal level is output. .
  • Some of the plurality of capacitors hold the correlated pixel signals during a period in which the signal levels of the plurality of pixel signals are output from the pixel array section to the two or more signal lines. , during a period in which the signal levels of the plurality of pixel signals are output from the pixel array section to the two or more signal lines in turn, the two or more capacitors other than the one portion of the plurality of capacitors,
  • the imaging device according to (6) or (7), wherein the holding operation of the correlated pixel signal is suspended.
  • the two or more column amplifier groups include a first column amplifier group and a second column amplifier group; each of the plurality of capacitance multiplexers has a first capacitance, a second capacitance, and a third capacitance;
  • the plurality of first capacitors in the plurality of capacitor multiplexers are configured to operate within a first period in which the signal levels of the plurality of pixel signals are output from the pixel array section to the two or more signal lines. holding the plurality of correlated pixel signals output from the column amplifier group of The plurality of second capacitors and the plurality of third capacitors in the plurality of capacitor multiplexers are alternately selected every first period and output from the second column amplifier group.
  • the imaging device according to any one of (1) to (8), which holds a plurality of correlated pixel signals or the plurality of correlated pixel signals output from the third column amplifier group. (10) The plurality of correlated pixel signals held in the plurality of first capacitors and the plurality of second capacitors or the plurality of third capacitors are stored in the pixel array during the first period.
  • the imaging apparatus according to (9), wherein the signal levels of the plurality of pixel signals are sequentially transferred to the analog-digital converter during a second period in which the signal levels of the plurality of pixel signals are output from the unit to the two or more signal lines.
  • the plurality of second capacitors and the plurality of third capacitors in the plurality of capacitor multiplexers hold the plurality of correlated pixel signals or the plurality of correlated pixel signals for each of the first period.
  • the two or more column amplifier groups include a first column amplifier group, a second column amplifier group, and a third column amplifier group; each of the plurality of capacitance multiplexers has a first capacitance, a second capacitance, a third capacitance, and a fourth capacitance;
  • the plurality of first capacitors in the plurality of capacitor multiplexers are configured to output the signal levels of the plurality of pixel signals to the two or more signal lines during a first period in which the pixel array section outputs the signal levels of the plurality of pixel signals.
  • the plurality of second capacitors in the plurality of capacitor multiplexers hold the plurality of correlated pixel signals output from the second column amplifier group within the first period;
  • the plurality of third capacitors and the plurality of fourth capacitors in the plurality of capacitor multiplexers are alternately selected for each of the first periods, and the plurality of capacitors output from the third column amplifier group or the plurality of correlated pixel signals output from the fourth column amplifier group.
  • the plurality of correlated pixel signals held in the first capacitor, the second capacitor, and the third capacitor or the fourth capacitor holding the plurality of correlated pixel signals; is the first period, the second period in which the signal levels of the plurality of pixel signals are output to the two or more signal lines, and the first period immediately after the second period,
  • the imaging device according to (12) which is transferred in turn to the analog-to-digital converter.
  • (14) either inputting the plurality of pixel signals to the column amplifier group or holding the plurality of correlated pixel signals in the plurality of capacitors after the consecutive first period and the second period;
  • the imaging apparatus according to any one of (1) to (14), wherein the analog-digital converter is a successive approximation analog-digital converter.
  • the capacitance multiplexer differentially outputs the correlated pixel signal held in one of the plurality of capacitances;
  • the imaging apparatus according to (15), wherein the successive approximation analog-digital converter converts the differential correlated pixel signals output from the capacitive multiplexer into the digital signals.
  • an imaging device that converts a photoelectrically converted pixel signal into a digital signal and outputs the digital signal; and a signal processing circuit that performs signal processing based on the digital signal
  • the imaging device is a pixel array unit that outputs a plurality of photoelectrically converted pixel signals to a plurality of signal lines; two or more column amplifier groups that output a plurality of correlated pixel signals, which are differences between reset levels and signal levels of the two or more corresponding pixel signals, for each signal line group including two or more signal lines; a capacitor unit having a plurality of capacitors for holding the plurality of correlated pixel signals; an analog-to-digital converter that sequentially converts the plurality of correlated pixel signals held in the plurality of capacitors into digital signals;
  • the electronic device wherein the number of the plurality of capacitors is larger than the number of the column amplifier groups.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

La présente invention vise à effectuer une conversion analogique-numérique à grande vitesse sans augmenter l'échelle du circuit. La solution selon l'invention porte sur un dispositif d'imagerie qui comprend : une unité de réseau de pixels qui délivre de multiples signaux de pixel qui ont subi une conversion photoélectrique en de multiples lignes de signal ; deux groupes d'amplificateurs de colonne ou plus qui, pour chaque groupe de lignes de signal contenant deux lignes de signal ou plus, délivrent de multiples signaux de pixel corrélés, qui sont la différence entre le niveau de réinitialisation et le niveau de signal de deux signaux de pixel correspondants ou plus ; de multiples multiplexeurs de capacité, dont chacun a de multiples capacités pour contenir les multiples signaux de pixel corrélés ; et un convertisseur analogique-numérique qui convertit progressivement les multiples signaux de pixel corrélés contenus dans les multiples capacités en signaux numériques, le nombre de capacités étant supérieur au nombre de groupes d'amplificateurs de colonne.
PCT/JP2022/014505 2021-03-31 2022-03-25 Dispositif d'imagerie et dispositif électronique WO2022210380A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-060807 2021-03-31
JP2021060807A JP2024079862A (ja) 2021-03-31 2021-03-31 撮像装置及び電子機器

Publications (1)

Publication Number Publication Date
WO2022210380A1 true WO2022210380A1 (fr) 2022-10-06

Family

ID=83459130

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/014505 WO2022210380A1 (fr) 2021-03-31 2022-03-25 Dispositif d'imagerie et dispositif électronique

Country Status (2)

Country Link
JP (1) JP2024079862A (fr)
WO (1) WO2022210380A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019057873A (ja) * 2017-09-22 2019-04-11 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子及び電子機器
JP2019092143A (ja) * 2017-11-10 2019-06-13 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、撮像装置、および、固体撮像素子の制御方法
WO2020045373A1 (fr) * 2018-08-30 2020-03-05 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie à semi-conducteur

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019057873A (ja) * 2017-09-22 2019-04-11 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子及び電子機器
JP2019092143A (ja) * 2017-11-10 2019-06-13 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、撮像装置、および、固体撮像素子の制御方法
WO2020045373A1 (fr) * 2018-08-30 2020-03-05 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie à semi-conducteur

Also Published As

Publication number Publication date
JP2024079862A (ja) 2024-06-12

Similar Documents

Publication Publication Date Title
CN111164965B (zh) 固态摄像器件和电子设备
JP7225127B2 (ja) 撮像素子及び電子機器
US11659300B2 (en) Solid-state image sensor, method of driving solid-state image sensor, and electronic apparatus
JP7350718B2 (ja) 撮像素子及び電子機器
WO2020153055A1 (fr) Dispositif de conversion numérique-analogique, dispositif d'imagerie et équipement électronique
WO2022210380A1 (fr) Dispositif d'imagerie et dispositif électronique
WO2021261375A1 (fr) Dispositif d'imagerie et appareil électronique
US20230247323A1 (en) Imaging device and imaging method
WO2023243497A1 (fr) Élément d'imagerie transistorisé et dispositif d'imagerie
WO2023067924A1 (fr) Dispositif de photographie et appareil électronique
US20230247328A1 (en) Imaging device and electronic device
WO2023243527A1 (fr) Dispositif de capture d'image à semi-conducteur, et appareil de capture d'image
WO2022176807A1 (fr) Convertisseur analogue-numérique et dispositif électronique
WO2023181663A1 (fr) Comparateur, amplificateur et dispositif d'imagerie à semi-conducteurs
WO2023136093A1 (fr) Élément d'imagerie et appareil électronique
WO2024043150A1 (fr) Système de caméra et son procédé de commande
JP2023110120A (ja) 撮像装置及び電子機器
TW202402036A (zh) 固態影像擷取裝置以及影像擷取設備

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22780593

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22780593

Country of ref document: EP

Kind code of ref document: A1