WO2022176523A1 - Dispositif capteur - Google Patents

Dispositif capteur Download PDF

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Publication number
WO2022176523A1
WO2022176523A1 PCT/JP2022/002527 JP2022002527W WO2022176523A1 WO 2022176523 A1 WO2022176523 A1 WO 2022176523A1 JP 2022002527 W JP2022002527 W JP 2022002527W WO 2022176523 A1 WO2022176523 A1 WO 2022176523A1
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WO
WIPO (PCT)
Prior art keywords
circuit
detection signal
sensor
bias
output
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PCT/JP2022/002527
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English (en)
Japanese (ja)
Inventor
恭英 高▲瀬▼
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株式会社村田製作所
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Publication of WO2022176523A1 publication Critical patent/WO2022176523A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means

Definitions

  • the present invention relates to a sensor device composed of a bridge circuit having sensor elements whose characteristics change according to the detected physical quantity.
  • this type of sensor device includes, for example, a sensor circuit disclosed in Patent Document 1.
  • the sensor in this sensor device is composed of a bridge circuit in which four resistors are bridge-connected, the polarities are sequentially switched by the first switching circuit, and a bias voltage having a constant voltage difference is applied to the bridge circuit.
  • the output of the bridge circuit is amplified by a preamplifier, AD-converted by an AD conversion circuit composed of a delta-sigma modulation circuit and a digital filter, and output to a microcomputer.
  • the digital filter adds the signals output from the delta-sigma modulation circuit when the voltage application state to the bridge circuit is the first state, and adds the signals output from the delta-sigma modulation circuit when the voltage application state to the bridge circuit is the second state. Subtract the output signal.
  • the digital processing of this addition and subtraction by the digital filter cancels the offset voltages of the preamplifier and the delta-sigma modulation circuit.
  • the microcomputer does not need to cancel the offset voltages of the preamplifier and the delta-sigma modulation circuit, nor does it need to use a chopper amplifier or the like to reduce the offset voltage of the preamplifier.
  • the settling time from the timing when the physical quantity change of the sensor element is detected until the bridge circuit output falls within the allowable error range. becomes longer, and a delay occurs in the response time until a change in the physical quantity detected by the sensor appears in the output of the sensor device.
  • the sensor detection signal reception circuit which is composed of a preamplifier, an AD conversion circuit, etc.
  • the sensor and this IC must be physically separated on the circuit board. Due to the parasitic capacitance of the wiring between the sensor and the IC, the IC package, and the like, there occurs a non-negligible delay in the response time.
  • the present invention was made to solve such problems, a bridge circuit comprising at least one sensor element whose characteristics change according to a detected physical quantity; a bias circuit for applying a bias voltage required for operation of the bridge circuit to a bias terminal of the bridge circuit; a detection signal receiving circuit that receives the sensor detection signal output from the detection signal output terminal of the bridge circuit; and a negative capacitance circuit that is connected to the detection signal output end and generates a negative capacitance component that cancels out the parasitic capacitance component parasitic on the detection signal output end.
  • the parasitic capacitance appearing at the detection signal output end of the bridge circuit is canceled by the negative capacitance component generated by the negative capacitance circuit connected to the detection signal output end of the bridge circuit. be. Therefore, the settling time from when the sensor element detects a change in physical quantity until the bridge circuit output falls within the allowable error range is shortened. Therefore, a physical quantity change detected by the sensor element, which appears at the detection signal output terminal of the bridge circuit in accordance with the characteristic change of the sensor element, quickly appears in the detection output of the sensor device.
  • FIG. 1A is a circuit diagram showing a schematic configuration of a sensor device according to a first embodiment of the present invention
  • FIG. 1B is a circuit configuration diagram of a negative capacitance circuit shown in FIG.
  • (a) is a graph showing changes in the physical quantity input to the sensor element of the sensor device shown in FIG. 1
  • (b) is a detection signal of the sensor device shown in FIG. 1 in response to the change in the physical quantity shown in (a).
  • Fig. 4 is a graph representing the sensor detection signal appearing at the output
  • FIG. 5 is a circuit diagram showing a schematic configuration of a sensor device according to a second embodiment of the invention
  • 4 is a graph showing a sensor detection signal appearing at a detection signal output terminal of the sensor device shown in FIG.
  • FIG. 5 is a circuit diagram showing a schematic configuration of a sensor device according to a third embodiment of the invention
  • FIG. 4 is a circuit diagram showing a schematic configuration of a sensor device according to a fourth embodiment of the invention
  • (a) is a circuit configuration diagram of a first modification of the negative capacitance circuit in the sensor device of each embodiment
  • (b) is a circuit configuration of a second modification of the negative capacitance circuit in the sensor device of each embodiment
  • It is a diagram.
  • FIG. 1(a) is a circuit diagram showing a schematic configuration of a sensor device 1A according to the first embodiment of the present invention.
  • the sensor device 1A is composed of a bridge circuit 2 excited by a bias circuit, a negative capacitance circuit 3 and a detection signal receiving circuit 4.
  • the bridge circuit 2 constitutes a sensor, and in this embodiment, one sensor element Z and three resistors R1, R2, and R3 are bridge-connected.
  • the bridge circuit 2 may be configured with at least one sensor element Z.
  • four sensor elements Z may be configured in a bridge connection.
  • the sensor element Z is composed of, for example, a magnetoresistive element whose characteristics change according to the detected physical quantity. This sensor element Z is represented by a symbol with an arrow attached to a resistance in the same figure, indicating that the resistance value of the sensor element Z changes according to the detected physical quantity.
  • a connection point between the sensor element Z and the resistor R1 and a connection point between the resistor R2 and the resistor R3 constitute bias terminals 2a and 2b, respectively, and a bias voltage Vbias is applied between the bias terminals 2a and 2b. be done. At this time, the bias end 2b may be grounded.
  • the source of the bias voltage Vbias constitutes a bias circuit that applies the bias voltage required for the operation of the bridge circuit 2 to the bias terminals 2a and 2b of the bridge circuit 2.
  • a connection point between the sensor element Z and the resistor R2 and a connection point between the resistor R1 and the resistor R3 constitute detection signal output terminals 2c and 2d, respectively. A change in the detected physical quantity appears as a sensor detection signal s.
  • the resistance values of the sensor element Z and the three resistors R1, R2, and R3 are such that when the sensor element Z does not detect a change in physical quantity, the bias voltage Vbias is applied to each of the detection signal output terminals 2c and 2d. is set to a value at which 1/2 of the voltage appears, but it is not limited to this.
  • the detection signal receiving circuit 4 receives the sensor detection signal s output from the detection signal output terminals 2c and 2d of the bridge circuit 2 according to the characteristic change of the sensor element Z.
  • the detection signal receiving circuit 4 is composed of an amplifier circuit that receives and amplifies the sensor detection signal s output from the detection signal output terminals 2c and 2d. A signal S is output.
  • Each negative capacitance circuit 3 is connected to the detection signal output terminals 2c and 2d and acts as a negative capacitance that cancels out the capacitive component of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d.
  • each negative capacitance circuit 3 includes a capacitor Co whose one end is connected to the detection signal output terminals 2c and 2d, and a non-inverting capacitor Co connected in parallel to the capacitor Co. and an amplifier circuit 5.
  • the capacitor Co has a capacitance value less than half the capacitance value of the parasitic capacitance Cs.
  • the non-inverting amplifier circuit 5 amplifies the potential at one end of the capacitor Co and applies it to the other end of the capacitor Co.
  • the non-inverting amplifier circuit 5 of the negative capacitance circuit 3 applies a voltage Va directed from the other end to one end of the capacitor Co, and one end of the capacitor Co is connected.
  • a current io flows from the capacitor Co into the detection signal output terminals 2c and 2d.
  • the capacitive component of the parasitic capacitance Cs is canceled by the negative capacitive component generated by the negative capacitive circuit 2 . Therefore, in the sensor device 1A, even if a parasitic capacitance Cs is generated at the detection signal output terminals 2c and 2d, the sensor detection signal s appearing at the detection signal output terminals 2c and 2d is detected without being affected by the parasitic capacitance Cs.
  • the signals are input to the detection signal receiving circuit 4 from the signal output terminals 2c and 2d.
  • the sensor detection signal s shown in the graph of FIG. 2(b) appears at the detection signal output terminals 2c and 2d.
  • the vertical axis of the graph shown in FIG. 1A represents the magnitude of the physical quantity p input to the sensor element Z, for example, the magnitude of the magnetic field when the sensor element Z is a magnetoresistive element, and the horizontal axis represents time. represents t.
  • the vertical axis of the graph shown in FIG. 8(b) represents the magnitude of the sensor detection signal s, and the horizontal axis represents time t.
  • the characteristics of the sensor detection signal s whose response characteristics are delayed by the time constant determined by the product of the resistance component, and the characteristic line 23 indicated by the thick solid line are the response characteristics compensated for by the negative capacitance circuit 3 reducing the time constant.
  • 4 shows characteristics of a sensor detection signal s in the embodiment. At the timing t1 when a change in the physical quantity p is detected in the sensor element Z, in the characteristic line 23, the rise of the sensor detection signal s is faster than the rise of the characteristic line 22 affected by the parasitic capacitance Cs. We are approaching the start of the 21st.
  • the sensor detection signal s falls faster than the characteristic line 22 affected by the parasitic capacitance Cs. is approaching the falling edge of the characteristic line 21 .
  • the parasitic capacitance Cs appearing at the detection signal output terminals 2c and 2d of the bridge circuit 2 is generated by the negative capacitance circuit 3 connected to the detection signal output terminals 2c and 2d.
  • the parasitic capacitive component is canceled by the negative capacitive component. Therefore, the settling time from when the sensor element Z detects a change in physical quantity until the output of the bridge circuit 2 falls within the allowable error range is shortened. Therefore, physical quantity changes detected by the sensor element Z, which appear at the detection signal output terminals 2c and 2d in accordance with changes in the characteristics of the sensor element Z, quickly appear in the detection output of the sensor device 1A.
  • the detection signal receiving circuit 4 is configured as an IC (highly integrated circuit) and the sensor configured by the bridge circuit 2 and this IC must be physically separated on the circuit board, the sensor device 1A There is no delay in the detection output of the sensor, and stable sensor operation can be provided.
  • the non-inverting amplifier circuit 5 converts the capacitor A sufficient voltage Va is not applied to the other end of Co. Therefore, the current io that cancels the capacitance component does not flow from the capacitor Co to the parasitic capacitance Cs, and the capacitor Co that constitutes the negative capacitance circuit 3 behaves conversely as a parasitic capacitance that is parasitic on the detection signal output terminals 2c and 2d. It will happen.
  • the capacitance value of the capacitor Co is set to be less than half the capacitance value of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d.
  • the capacitive component of the parasitic capacitance that the capacitor Co constituting the negative capacitance circuit 3 inversely parasitics on the detection signal output terminals 2c and 2d can be reduced to less than half the originally parasitic capacitance Cs. can.
  • FIG. 3 is a circuit diagram showing a schematic configuration of the sensor device 1B according to the second embodiment of the invention.
  • the same reference numerals are given to the same or corresponding parts as those in FIG. 1, and the description thereof will be omitted.
  • the sensor device 1B includes a bias circuit 6 that outputs a bias voltage Vbias having a constant voltage difference, and a bias voltage inverting circuit 7 provided between the bias circuit 6 and the bridge circuit 2, in addition to the configuration of the sensor device 1A. Further, the difference from the sensor device 1A according to the first embodiment is that the detection signal receiving circuit 4 has a signal inverting circuit 8 therein.
  • a bias circuit is configured by applying a fixed bias voltage Vbias to the ground voltage.
  • the bias circuit 6 is composed of a regulator having two bias voltage outputs, and outputs a bias voltage Vbias having a constant voltage difference.
  • the bias circuit 6 outputs a positive bias voltage, eg, a bias voltage of 5 [V] in this embodiment, from one voltage output terminal, and outputs a negative bias voltage from the other voltage output terminal.
  • the negative bias voltage may be the ground voltage, and in this embodiment, the ground voltage (0 [V]) is output as the negative bias voltage.
  • the bias voltage inverting circuit 7 is configured, for example, as a crossbar switch including four switches SW1, SW2, SW3, and SW4. The polarities of the bias voltages Vbias applied to the terminals 2a and 2b are sequentially reversed.
  • the signal inverting circuit 8 is composed of a crossbar switch built in the detection signal receiving circuit 4 and sequentially inverts the polarity of the detection output signal S output from the detection signal receiving circuit 4 .
  • FIG. 4 shows the detection signal when the bias voltage Vbias sequentially inverted by the bias voltage inverting circuit 7 and the change in physical quantity shown in the graph of FIG.
  • the sensor detection signal s appearing at the outputs 2c, 2d is shown.
  • the same reference numerals are given to the same or corresponding parts as those in FIG. 2, and the description thereof will be omitted.
  • the bias circuit 6 outputs two bias voltages, a positive bias voltage of 5[V] and a ground voltage of 0[V].
  • the analog detection output signal S output from the detection signal receiving circuit 4 is sequentially inverted by the signal inverting circuit 8, and the offset voltage of the detection signal receiving circuit 4 is set to a frequency different from the frequency band of the sensor detection signal s. , the offset voltage of the detection signal receiving circuit 4 included in the detection output signal S output from the detection signal receiving circuit 4 is separated.
  • the same effects as those of the sensor device 1A of the first embodiment are exhibited, and as shown in FIG.
  • the rise of the sensor detection signal s is faster than the rise of the characteristic line 22 which does not include the negative capacitance circuit 3 and is affected by the parasitic capacitance Cs.
  • the rise of the ideal characteristic line 21 is approaching.
  • the sensor detection signal s falls faster than the characteristic line 22 affected by the parasitic capacitance Cs. is approaching the falling edge of the characteristic line 21 .
  • the offset voltage of the detection signal reception circuit 4 has the same polarity in the sensor detection signal s of each polarity. superimpose. Further, the sensor detection signals s whose polarities are sequentially inverted are returned to their original polarities and output from the sensor device 1B by further inverting the detection output signals S of the detection signal receiving circuit 4 by the signal inverting circuit 8. be done. On the other hand, since the offset voltage of the detection signal receiving circuit 4 is modulated to the frequency that has been sequentially inverted by the signal inverting circuit 8, it is output in a frequency band different from that of the sensor detection signal s. It is separated from the signal S. Therefore, according to the sensor device 1B of the second embodiment, changes in the physical quantity detected by the sensor element Z are transmitted from the sensor device 1B at high speed without delay, and at the same time as the offset voltage of the detection signal receiving circuit 4. is output correctly without including
  • FIG. 5 is a circuit diagram showing a schematic configuration of a sensor device 1C according to the third embodiment of the invention.
  • the same reference numerals are given to the same or corresponding parts as those in FIG. 3, and the description thereof will be omitted.
  • the sensor device 1C differs from the sensor device 1B according to the second embodiment in that the detection signal receiving circuit 4 includes an AD conversion circuit 9 and a digital filter 10, but does not include the signal inverting circuit 8.
  • the AD conversion circuit 9 converts each sensor detection signal s output from the detection signal output terminals 2c and 2d with the polarities sequentially reversed by sequentially inverting the polarity of the bias voltage Vbias applied to the bias terminals 2a and 2b. , to convert analog signals to digital signals.
  • the bias voltage inversion circuit 7 and the AD conversion circuit 9 are supplied with the same clock signal clk, and the AD conversion in the AD conversion circuit 9 is performed in synchronization with the polarity inversion of the bias voltage Vbias in the bias voltage inversion circuit 7. .
  • the digital filter 10 suppresses noise superimposed on each sensor detection signal s converted into a digital signal, adds the sensor detection signal s of one polarity output from the AD conversion circuit 9, and adds the sensor detection signal s of the other polarity. By subtracting the detection signal s, the offset voltage of the AD conversion circuit 9 included in the sensor detection signal s is suppressed.
  • the same effects as those of the sensor devices 1A and 1B of the first and second embodiments are obtained.
  • the appearing parasitic capacitance Cs is canceled by the negative capacitance component generated by the negative capacitance circuit 3 connected to the detection signal output terminals 2c and 2d. Therefore, no delay occurs in the response time until the change in the physical quantity detected by the sensor element Z appears in the detection output of the sensor device 1C.
  • the sensor detection signal s that is input from the bridge circuit 2 to the detection signal receiving circuit 4 after being sequentially inverted in polarity is converted from an analog signal to a digital signal by the AD conversion circuit 9. is converted to At this time, the offset voltage of the AD conversion circuit 9 with the same polarity is superimposed on the sensor detection signal s of each polarity converted into a digital signal. Therefore, in the digital filter 10, the sensor detection signal s output from the AD conversion circuit 9 is added when the sensor detection signal s has one polarity, and the sensor detection signal s from the AD conversion circuit 9 when the sensor detection signal s has the other polarity.
  • the offset voltage of the AD conversion circuit 9 can be canceled from the sensor detection signal s by digital processing. Therefore, from the sensor device 1C, changes in the physical quantity detected by the sensor element Z can be accurately detected as a digital detection output signal S at high speed without delay and without including the offset voltage of the AD conversion circuit 9. Output with low noise.
  • FIG. 6 is a circuit diagram showing a schematic configuration of a sensor device 1D according to the fourth embodiment of the invention.
  • the same reference numerals are given to the same or corresponding parts as those in FIG. 5, and the description thereof will be omitted.
  • the sensor device 1D differs from the sensor device 1C according to the third embodiment in that the detection signal receiving circuit 4 includes a pre-amplifier circuit 11 between the bridge circuit 2 and the AD conversion circuit 9 .
  • a preamplifier circuit 11 amplifies the sensor detection signal s output from the bridge circuit 2 .
  • each polarity sensor detection signal s input to the digital filter 10 is superimposed with each offset voltage of the preamplifier circuit 11 and the AD conversion circuit 9 with the same polarity. Therefore, in the digital filter 10, the sensor detection signal s output from the AD conversion circuit 9 is added when the sensor detection signal s has one polarity, and the sensor detection signal s from the AD conversion circuit 9 when the sensor detection signal s has the other polarity. By subtracting the output sensor detection signal s, each offset voltage of the preamplifier circuit 11 and the AD conversion circuit 9 can be canceled from the sensor detection signal s by digital processing. Therefore, from the sensor device 1D, changes in the physical quantity detected by the sensor element Z are digitalized at high speed without delay and without including the offset voltages of the preamplifier circuit 11 and the AD converter circuit 9. It is accurately output as the detection output signal S with low noise.
  • the non-inverting amplifier circuit 5 constituting the negative capacitance circuit 3 is configured by a non-inverting amplifier circuit 5A whose amplification gain is adjustable, as shown in FIG. 7(a).
  • the voltage Va applied by the non-inverting amplifier circuit 5A to the other end of the capacitor Co is freely adjusted according to the capacitive component of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d. Therefore, the capacitance component of the parasitic capacitance Cs is accurately canceled by the negative capacitance circuit 3 .
  • the capacitor Co forming the negative capacitance circuit 3 may be configured by a variable capacitor CoA whose capacitance value is adjustable, as shown in FIG. 7(b). good. According to this configuration, the current io flowing from the capacitor CoA to the parasitic capacitance Cs can be adjusted freely according to the capacitive component of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d by adjusting the capacitance value of the capacitor CoA. adjusted. Therefore, the capacitance component of the parasitic capacitance Cs is accurately canceled by the negative capacitance circuit 3 .

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Abstract

L'invention concerne un dispositif capteur dans lequel il n'y a pas de retard dans le temps de réponse jusqu'à ce qu'une variation d'une quantité physique détectée par un élément capteur apparaisse dans la sortie du dispositif capteur. Le dispositif capteur 1A comprend un circuit en pont 2 qui est excité par un circuit de polarisation, des circuits de capacité négative 3, et un circuit de réception de signal de détection 4. Le circuit en pont 2 est configuré par la connexion en pont d'un élément capteur Z et de résistances R1, R2, R3. Une tension de polarisation Vbias est appliquée aux extrémités de polarisation 2a, 2b, et la variation d'une quantité physique détectée par l'élément capteur Z apparaît en tant que signal de détection de capteur s au niveau d'extrémités de sortie de signal de détection 2c, 2d. Le circuit de réception de signal de détection 4 reçoit le signal de détection de capteur s, qui est délivré par les extrémités de sortie de signal de détection 2c, 2d du circuit en pont 2 conformément à une variation de caractéristique d'élément capteur Z. Les circuits de capacité négative 3 sont respectivement connectés aux extrémités de sortie de signal de détection 2c, 2d et agissent en tant que capacités négatives qui éliminent la composante de capacité de la capacité parasite Cs agissant sur les extrémités de sortie de signal de détection 2c, 2d.
PCT/JP2022/002527 2021-02-16 2022-01-25 Dispositif capteur WO2022176523A1 (fr)

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JP2021022366 2021-02-16
JP2021-022366 2021-02-16

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002521696A (ja) * 1998-07-29 2002-07-16 ルスト・アントリープステヒニク・ゲゼルシヤフト・ミト・ベシユレンクテル・ハフツング 磁気抵抗センサの信号を評価する方法及びこの方法を実施する装置
JP4814209B2 (ja) * 2007-12-21 2011-11-16 オンセミコンダクター・トレーディング・リミテッド Ａｄコンバータ
JP2012500407A (ja) * 2008-08-15 2012-01-05 ケンブリッジ ディスプレイ テクノロジー リミテッド アクティブマトリクス表示装置
US20120025819A1 (en) * 2010-07-30 2012-02-02 Nxp B.V. Magnetoresistive sensor
JP2019105583A (ja) * 2017-12-14 2019-06-27 アルプスアルパイン株式会社 電流センサ、電流センサの製造方法および半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002521696A (ja) * 1998-07-29 2002-07-16 ルスト・アントリープステヒニク・ゲゼルシヤフト・ミト・ベシユレンクテル・ハフツング 磁気抵抗センサの信号を評価する方法及びこの方法を実施する装置
JP4814209B2 (ja) * 2007-12-21 2011-11-16 オンセミコンダクター・トレーディング・リミテッド Ａｄコンバータ
JP2012500407A (ja) * 2008-08-15 2012-01-05 ケンブリッジ ディスプレイ テクノロジー リミテッド アクティブマトリクス表示装置
US20120025819A1 (en) * 2010-07-30 2012-02-02 Nxp B.V. Magnetoresistive sensor
JP2019105583A (ja) * 2017-12-14 2019-06-27 アルプスアルパイン株式会社 電流センサ、電流センサの製造方法および半導体装置

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