WO2022176523A1 - Sensor device - Google Patents

Sensor device Download PDF

Info

Publication number
WO2022176523A1
WO2022176523A1 PCT/JP2022/002527 JP2022002527W WO2022176523A1 WO 2022176523 A1 WO2022176523 A1 WO 2022176523A1 JP 2022002527 W JP2022002527 W JP 2022002527W WO 2022176523 A1 WO2022176523 A1 WO 2022176523A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
detection signal
sensor
bias
output
Prior art date
Application number
PCT/JP2022/002527
Other languages
French (fr)
Japanese (ja)
Inventor
恭英 高▲瀬▼
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2022176523A1 publication Critical patent/WO2022176523A1/en

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01DMEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means

Definitions

  • the present invention relates to a sensor device composed of a bridge circuit having sensor elements whose characteristics change according to the detected physical quantity.
  • this type of sensor device includes, for example, a sensor circuit disclosed in Patent Document 1.
  • the sensor in this sensor device is composed of a bridge circuit in which four resistors are bridge-connected, the polarities are sequentially switched by the first switching circuit, and a bias voltage having a constant voltage difference is applied to the bridge circuit.
  • the output of the bridge circuit is amplified by a preamplifier, AD-converted by an AD conversion circuit composed of a delta-sigma modulation circuit and a digital filter, and output to a microcomputer.
  • the digital filter adds the signals output from the delta-sigma modulation circuit when the voltage application state to the bridge circuit is the first state, and adds the signals output from the delta-sigma modulation circuit when the voltage application state to the bridge circuit is the second state. Subtract the output signal.
  • the digital processing of this addition and subtraction by the digital filter cancels the offset voltages of the preamplifier and the delta-sigma modulation circuit.
  • the microcomputer does not need to cancel the offset voltages of the preamplifier and the delta-sigma modulation circuit, nor does it need to use a chopper amplifier or the like to reduce the offset voltage of the preamplifier.
  • the settling time from the timing when the physical quantity change of the sensor element is detected until the bridge circuit output falls within the allowable error range. becomes longer, and a delay occurs in the response time until a change in the physical quantity detected by the sensor appears in the output of the sensor device.
  • the sensor detection signal reception circuit which is composed of a preamplifier, an AD conversion circuit, etc.
  • the sensor and this IC must be physically separated on the circuit board. Due to the parasitic capacitance of the wiring between the sensor and the IC, the IC package, and the like, there occurs a non-negligible delay in the response time.
  • the present invention was made to solve such problems, a bridge circuit comprising at least one sensor element whose characteristics change according to a detected physical quantity; a bias circuit for applying a bias voltage required for operation of the bridge circuit to a bias terminal of the bridge circuit; a detection signal receiving circuit that receives the sensor detection signal output from the detection signal output terminal of the bridge circuit; and a negative capacitance circuit that is connected to the detection signal output end and generates a negative capacitance component that cancels out the parasitic capacitance component parasitic on the detection signal output end.
  • the parasitic capacitance appearing at the detection signal output end of the bridge circuit is canceled by the negative capacitance component generated by the negative capacitance circuit connected to the detection signal output end of the bridge circuit. be. Therefore, the settling time from when the sensor element detects a change in physical quantity until the bridge circuit output falls within the allowable error range is shortened. Therefore, a physical quantity change detected by the sensor element, which appears at the detection signal output terminal of the bridge circuit in accordance with the characteristic change of the sensor element, quickly appears in the detection output of the sensor device.
  • FIG. 1A is a circuit diagram showing a schematic configuration of a sensor device according to a first embodiment of the present invention
  • FIG. 1B is a circuit configuration diagram of a negative capacitance circuit shown in FIG.
  • (a) is a graph showing changes in the physical quantity input to the sensor element of the sensor device shown in FIG. 1
  • (b) is a detection signal of the sensor device shown in FIG. 1 in response to the change in the physical quantity shown in (a).
  • Fig. 4 is a graph representing the sensor detection signal appearing at the output
  • FIG. 5 is a circuit diagram showing a schematic configuration of a sensor device according to a second embodiment of the invention
  • 4 is a graph showing a sensor detection signal appearing at a detection signal output terminal of the sensor device shown in FIG.
  • FIG. 5 is a circuit diagram showing a schematic configuration of a sensor device according to a third embodiment of the invention
  • FIG. 4 is a circuit diagram showing a schematic configuration of a sensor device according to a fourth embodiment of the invention
  • (a) is a circuit configuration diagram of a first modification of the negative capacitance circuit in the sensor device of each embodiment
  • (b) is a circuit configuration of a second modification of the negative capacitance circuit in the sensor device of each embodiment
  • It is a diagram.
  • FIG. 1(a) is a circuit diagram showing a schematic configuration of a sensor device 1A according to the first embodiment of the present invention.
  • the sensor device 1A is composed of a bridge circuit 2 excited by a bias circuit, a negative capacitance circuit 3 and a detection signal receiving circuit 4.
  • the bridge circuit 2 constitutes a sensor, and in this embodiment, one sensor element Z and three resistors R1, R2, and R3 are bridge-connected.
  • the bridge circuit 2 may be configured with at least one sensor element Z.
  • four sensor elements Z may be configured in a bridge connection.
  • the sensor element Z is composed of, for example, a magnetoresistive element whose characteristics change according to the detected physical quantity. This sensor element Z is represented by a symbol with an arrow attached to a resistance in the same figure, indicating that the resistance value of the sensor element Z changes according to the detected physical quantity.
  • a connection point between the sensor element Z and the resistor R1 and a connection point between the resistor R2 and the resistor R3 constitute bias terminals 2a and 2b, respectively, and a bias voltage Vbias is applied between the bias terminals 2a and 2b. be done. At this time, the bias end 2b may be grounded.
  • the source of the bias voltage Vbias constitutes a bias circuit that applies the bias voltage required for the operation of the bridge circuit 2 to the bias terminals 2a and 2b of the bridge circuit 2.
  • a connection point between the sensor element Z and the resistor R2 and a connection point between the resistor R1 and the resistor R3 constitute detection signal output terminals 2c and 2d, respectively. A change in the detected physical quantity appears as a sensor detection signal s.
  • the resistance values of the sensor element Z and the three resistors R1, R2, and R3 are such that when the sensor element Z does not detect a change in physical quantity, the bias voltage Vbias is applied to each of the detection signal output terminals 2c and 2d. is set to a value at which 1/2 of the voltage appears, but it is not limited to this.
  • the detection signal receiving circuit 4 receives the sensor detection signal s output from the detection signal output terminals 2c and 2d of the bridge circuit 2 according to the characteristic change of the sensor element Z.
  • the detection signal receiving circuit 4 is composed of an amplifier circuit that receives and amplifies the sensor detection signal s output from the detection signal output terminals 2c and 2d. A signal S is output.
  • Each negative capacitance circuit 3 is connected to the detection signal output terminals 2c and 2d and acts as a negative capacitance that cancels out the capacitive component of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d.
  • each negative capacitance circuit 3 includes a capacitor Co whose one end is connected to the detection signal output terminals 2c and 2d, and a non-inverting capacitor Co connected in parallel to the capacitor Co. and an amplifier circuit 5.
  • the capacitor Co has a capacitance value less than half the capacitance value of the parasitic capacitance Cs.
  • the non-inverting amplifier circuit 5 amplifies the potential at one end of the capacitor Co and applies it to the other end of the capacitor Co.
  • the non-inverting amplifier circuit 5 of the negative capacitance circuit 3 applies a voltage Va directed from the other end to one end of the capacitor Co, and one end of the capacitor Co is connected.
  • a current io flows from the capacitor Co into the detection signal output terminals 2c and 2d.
  • the capacitive component of the parasitic capacitance Cs is canceled by the negative capacitive component generated by the negative capacitive circuit 2 . Therefore, in the sensor device 1A, even if a parasitic capacitance Cs is generated at the detection signal output terminals 2c and 2d, the sensor detection signal s appearing at the detection signal output terminals 2c and 2d is detected without being affected by the parasitic capacitance Cs.
  • the signals are input to the detection signal receiving circuit 4 from the signal output terminals 2c and 2d.
  • the sensor detection signal s shown in the graph of FIG. 2(b) appears at the detection signal output terminals 2c and 2d.
  • the vertical axis of the graph shown in FIG. 1A represents the magnitude of the physical quantity p input to the sensor element Z, for example, the magnitude of the magnetic field when the sensor element Z is a magnetoresistive element, and the horizontal axis represents time. represents t.
  • the vertical axis of the graph shown in FIG. 8(b) represents the magnitude of the sensor detection signal s, and the horizontal axis represents time t.
  • the characteristics of the sensor detection signal s whose response characteristics are delayed by the time constant determined by the product of the resistance component, and the characteristic line 23 indicated by the thick solid line are the response characteristics compensated for by the negative capacitance circuit 3 reducing the time constant.
  • 4 shows characteristics of a sensor detection signal s in the embodiment. At the timing t1 when a change in the physical quantity p is detected in the sensor element Z, in the characteristic line 23, the rise of the sensor detection signal s is faster than the rise of the characteristic line 22 affected by the parasitic capacitance Cs. We are approaching the start of the 21st.
  • the sensor detection signal s falls faster than the characteristic line 22 affected by the parasitic capacitance Cs. is approaching the falling edge of the characteristic line 21 .
  • the parasitic capacitance Cs appearing at the detection signal output terminals 2c and 2d of the bridge circuit 2 is generated by the negative capacitance circuit 3 connected to the detection signal output terminals 2c and 2d.
  • the parasitic capacitive component is canceled by the negative capacitive component. Therefore, the settling time from when the sensor element Z detects a change in physical quantity until the output of the bridge circuit 2 falls within the allowable error range is shortened. Therefore, physical quantity changes detected by the sensor element Z, which appear at the detection signal output terminals 2c and 2d in accordance with changes in the characteristics of the sensor element Z, quickly appear in the detection output of the sensor device 1A.
  • the detection signal receiving circuit 4 is configured as an IC (highly integrated circuit) and the sensor configured by the bridge circuit 2 and this IC must be physically separated on the circuit board, the sensor device 1A There is no delay in the detection output of the sensor, and stable sensor operation can be provided.
  • the non-inverting amplifier circuit 5 converts the capacitor A sufficient voltage Va is not applied to the other end of Co. Therefore, the current io that cancels the capacitance component does not flow from the capacitor Co to the parasitic capacitance Cs, and the capacitor Co that constitutes the negative capacitance circuit 3 behaves conversely as a parasitic capacitance that is parasitic on the detection signal output terminals 2c and 2d. It will happen.
  • the capacitance value of the capacitor Co is set to be less than half the capacitance value of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d.
  • the capacitive component of the parasitic capacitance that the capacitor Co constituting the negative capacitance circuit 3 inversely parasitics on the detection signal output terminals 2c and 2d can be reduced to less than half the originally parasitic capacitance Cs. can.
  • FIG. 3 is a circuit diagram showing a schematic configuration of the sensor device 1B according to the second embodiment of the invention.
  • the same reference numerals are given to the same or corresponding parts as those in FIG. 1, and the description thereof will be omitted.
  • the sensor device 1B includes a bias circuit 6 that outputs a bias voltage Vbias having a constant voltage difference, and a bias voltage inverting circuit 7 provided between the bias circuit 6 and the bridge circuit 2, in addition to the configuration of the sensor device 1A. Further, the difference from the sensor device 1A according to the first embodiment is that the detection signal receiving circuit 4 has a signal inverting circuit 8 therein.
  • a bias circuit is configured by applying a fixed bias voltage Vbias to the ground voltage.
  • the bias circuit 6 is composed of a regulator having two bias voltage outputs, and outputs a bias voltage Vbias having a constant voltage difference.
  • the bias circuit 6 outputs a positive bias voltage, eg, a bias voltage of 5 [V] in this embodiment, from one voltage output terminal, and outputs a negative bias voltage from the other voltage output terminal.
  • the negative bias voltage may be the ground voltage, and in this embodiment, the ground voltage (0 [V]) is output as the negative bias voltage.
  • the bias voltage inverting circuit 7 is configured, for example, as a crossbar switch including four switches SW1, SW2, SW3, and SW4. The polarities of the bias voltages Vbias applied to the terminals 2a and 2b are sequentially reversed.
  • the signal inverting circuit 8 is composed of a crossbar switch built in the detection signal receiving circuit 4 and sequentially inverts the polarity of the detection output signal S output from the detection signal receiving circuit 4 .
  • FIG. 4 shows the detection signal when the bias voltage Vbias sequentially inverted by the bias voltage inverting circuit 7 and the change in physical quantity shown in the graph of FIG.
  • the sensor detection signal s appearing at the outputs 2c, 2d is shown.
  • the same reference numerals are given to the same or corresponding parts as those in FIG. 2, and the description thereof will be omitted.
  • the bias circuit 6 outputs two bias voltages, a positive bias voltage of 5[V] and a ground voltage of 0[V].
  • the analog detection output signal S output from the detection signal receiving circuit 4 is sequentially inverted by the signal inverting circuit 8, and the offset voltage of the detection signal receiving circuit 4 is set to a frequency different from the frequency band of the sensor detection signal s. , the offset voltage of the detection signal receiving circuit 4 included in the detection output signal S output from the detection signal receiving circuit 4 is separated.
  • the same effects as those of the sensor device 1A of the first embodiment are exhibited, and as shown in FIG.
  • the rise of the sensor detection signal s is faster than the rise of the characteristic line 22 which does not include the negative capacitance circuit 3 and is affected by the parasitic capacitance Cs.
  • the rise of the ideal characteristic line 21 is approaching.
  • the sensor detection signal s falls faster than the characteristic line 22 affected by the parasitic capacitance Cs. is approaching the falling edge of the characteristic line 21 .
  • the offset voltage of the detection signal reception circuit 4 has the same polarity in the sensor detection signal s of each polarity. superimpose. Further, the sensor detection signals s whose polarities are sequentially inverted are returned to their original polarities and output from the sensor device 1B by further inverting the detection output signals S of the detection signal receiving circuit 4 by the signal inverting circuit 8. be done. On the other hand, since the offset voltage of the detection signal receiving circuit 4 is modulated to the frequency that has been sequentially inverted by the signal inverting circuit 8, it is output in a frequency band different from that of the sensor detection signal s. It is separated from the signal S. Therefore, according to the sensor device 1B of the second embodiment, changes in the physical quantity detected by the sensor element Z are transmitted from the sensor device 1B at high speed without delay, and at the same time as the offset voltage of the detection signal receiving circuit 4. is output correctly without including
  • FIG. 5 is a circuit diagram showing a schematic configuration of a sensor device 1C according to the third embodiment of the invention.
  • the same reference numerals are given to the same or corresponding parts as those in FIG. 3, and the description thereof will be omitted.
  • the sensor device 1C differs from the sensor device 1B according to the second embodiment in that the detection signal receiving circuit 4 includes an AD conversion circuit 9 and a digital filter 10, but does not include the signal inverting circuit 8.
  • the AD conversion circuit 9 converts each sensor detection signal s output from the detection signal output terminals 2c and 2d with the polarities sequentially reversed by sequentially inverting the polarity of the bias voltage Vbias applied to the bias terminals 2a and 2b. , to convert analog signals to digital signals.
  • the bias voltage inversion circuit 7 and the AD conversion circuit 9 are supplied with the same clock signal clk, and the AD conversion in the AD conversion circuit 9 is performed in synchronization with the polarity inversion of the bias voltage Vbias in the bias voltage inversion circuit 7. .
  • the digital filter 10 suppresses noise superimposed on each sensor detection signal s converted into a digital signal, adds the sensor detection signal s of one polarity output from the AD conversion circuit 9, and adds the sensor detection signal s of the other polarity. By subtracting the detection signal s, the offset voltage of the AD conversion circuit 9 included in the sensor detection signal s is suppressed.
  • the same effects as those of the sensor devices 1A and 1B of the first and second embodiments are obtained.
  • the appearing parasitic capacitance Cs is canceled by the negative capacitance component generated by the negative capacitance circuit 3 connected to the detection signal output terminals 2c and 2d. Therefore, no delay occurs in the response time until the change in the physical quantity detected by the sensor element Z appears in the detection output of the sensor device 1C.
  • the sensor detection signal s that is input from the bridge circuit 2 to the detection signal receiving circuit 4 after being sequentially inverted in polarity is converted from an analog signal to a digital signal by the AD conversion circuit 9. is converted to At this time, the offset voltage of the AD conversion circuit 9 with the same polarity is superimposed on the sensor detection signal s of each polarity converted into a digital signal. Therefore, in the digital filter 10, the sensor detection signal s output from the AD conversion circuit 9 is added when the sensor detection signal s has one polarity, and the sensor detection signal s from the AD conversion circuit 9 when the sensor detection signal s has the other polarity.
  • the offset voltage of the AD conversion circuit 9 can be canceled from the sensor detection signal s by digital processing. Therefore, from the sensor device 1C, changes in the physical quantity detected by the sensor element Z can be accurately detected as a digital detection output signal S at high speed without delay and without including the offset voltage of the AD conversion circuit 9. Output with low noise.
  • FIG. 6 is a circuit diagram showing a schematic configuration of a sensor device 1D according to the fourth embodiment of the invention.
  • the same reference numerals are given to the same or corresponding parts as those in FIG. 5, and the description thereof will be omitted.
  • the sensor device 1D differs from the sensor device 1C according to the third embodiment in that the detection signal receiving circuit 4 includes a pre-amplifier circuit 11 between the bridge circuit 2 and the AD conversion circuit 9 .
  • a preamplifier circuit 11 amplifies the sensor detection signal s output from the bridge circuit 2 .
  • each polarity sensor detection signal s input to the digital filter 10 is superimposed with each offset voltage of the preamplifier circuit 11 and the AD conversion circuit 9 with the same polarity. Therefore, in the digital filter 10, the sensor detection signal s output from the AD conversion circuit 9 is added when the sensor detection signal s has one polarity, and the sensor detection signal s from the AD conversion circuit 9 when the sensor detection signal s has the other polarity. By subtracting the output sensor detection signal s, each offset voltage of the preamplifier circuit 11 and the AD conversion circuit 9 can be canceled from the sensor detection signal s by digital processing. Therefore, from the sensor device 1D, changes in the physical quantity detected by the sensor element Z are digitalized at high speed without delay and without including the offset voltages of the preamplifier circuit 11 and the AD converter circuit 9. It is accurately output as the detection output signal S with low noise.
  • the non-inverting amplifier circuit 5 constituting the negative capacitance circuit 3 is configured by a non-inverting amplifier circuit 5A whose amplification gain is adjustable, as shown in FIG. 7(a).
  • the voltage Va applied by the non-inverting amplifier circuit 5A to the other end of the capacitor Co is freely adjusted according to the capacitive component of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d. Therefore, the capacitance component of the parasitic capacitance Cs is accurately canceled by the negative capacitance circuit 3 .
  • the capacitor Co forming the negative capacitance circuit 3 may be configured by a variable capacitor CoA whose capacitance value is adjustable, as shown in FIG. 7(b). good. According to this configuration, the current io flowing from the capacitor CoA to the parasitic capacitance Cs can be adjusted freely according to the capacitive component of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d by adjusting the capacitance value of the capacitor CoA. adjusted. Therefore, the capacitance component of the parasitic capacitance Cs is accurately canceled by the negative capacitance circuit 3 .

Abstract

Provided is a sensor device in which there is no delay in the response time until a change in a physical quantity detected by a sensor element appears in the output of the sensor device. The sensor device 1A comprises a bridge circuit 2 that is excited by a bias circuit, negative capacitance circuits 3, and a detection signal reception circuit 4. The bridge circuit 2 is configured through the bridge connection of a sensor element Z and resistors R1, R2, R3. A bias voltage Vbias is applied to bias ends 2a, 2b, and change in a physical quantity detected by the sensor element Z appears as a sensor detection signal s at detection signal output ends 2c, 2d. The detection signal reception circuit 4 receives the sensor detection signal s, which is output from the detection signal output ends 2c, 2d of the bridge circuit 2 according to sensor element Z characteristic variation. The negative capacitance circuits 3 are respectively connected to the detection signal output ends 2c, 2d and act as negative capacitances that cancel out the capacitance component of parasitic capacitance Cs acting on the detection signal output ends 2c, 2d.

Description

センサ装置sensor device
 本発明は、検出される物理量に応じて特性が変化するセンサ素子を備えるブリッジ回路から構成されるセンサ装置に関するものである。 The present invention relates to a sensor device composed of a bridge circuit having sensor elements whose characteristics change according to the detected physical quantity.
 従来、この種のセンサ装置としては、例えば、特許文献1に開示されたセンサ回路を有するものがある。 Conventionally, this type of sensor device includes, for example, a sensor circuit disclosed in Patent Document 1.
 このセンサ装置におけるセンサは、4つの抵抗がブリッジ接続されたブリッジ回路から構成され、第1切替回路により極性が順次切り替えられて、一定電圧差を持つバイアス電圧がブリッジ回路に印加される。ブリッジ回路の出力は、プリアンプで増幅された後、デルタシグマ変調回路およびデジタルフィルタから構成されるAD変換回路によってAD変換されて、マイコンへ出力される。デジタルフィルタは、ブリッジ回路への電圧印加状態が第1の状態では、デルタシグマ変調回路から出力される信号を加算し、ブリッジ回路への電圧印加状態が第2の状態では、デルタシグマ変調回路から出力される信号を減算する。デジタルフィルタによるこの加算および減算のデジタル処理により、プリアンプおよびデルタシグマ変調回路の各オフセット電圧がキャンセルされる。 The sensor in this sensor device is composed of a bridge circuit in which four resistors are bridge-connected, the polarities are sequentially switched by the first switching circuit, and a bias voltage having a constant voltage difference is applied to the bridge circuit. The output of the bridge circuit is amplified by a preamplifier, AD-converted by an AD conversion circuit composed of a delta-sigma modulation circuit and a digital filter, and output to a microcomputer. The digital filter adds the signals output from the delta-sigma modulation circuit when the voltage application state to the bridge circuit is the first state, and adds the signals output from the delta-sigma modulation circuit when the voltage application state to the bridge circuit is the second state. Subtract the output signal. The digital processing of this addition and subtraction by the digital filter cancels the offset voltages of the preamplifier and the delta-sigma modulation circuit.
 このため、マイコンで、プリアンプおよびデルタシグマ変調回路の各オフセット電圧をキャンセルする処理が不要になり、また、プリアンプのオフセット電圧を低減するためにチョッパアンプ等を用いる必要がなくなる。 Therefore, the microcomputer does not need to cancel the offset voltages of the preamplifier and the delta-sigma modulation circuit, nor does it need to use a chopper amplifier or the like to reduce the offset voltage of the preamplifier.
特許第4814209号公報Japanese Patent No. 4814209
 しかしながら、上記従来の特許文献1に開示されたセンサ装置では、ブリッジ回路の検出信号出力端に生じる寄生容量により、センサ素子の物理量変化検出タイミングからブリッジ回路出力が許容誤差範囲に収まるまでのセトリング時間が長くなり、センサが検出する物理量変化がセンサ装置の出力に現れるまでの応答時間に遅延が生じる。特に、プリアンプやAD変換回路等から構成されるセンサ検出信号の受信回路がIC(高集積化回路)として構成され、センサとこのICとを回路基板上で物理的に分離しなければならないケースでは、センサとICとの間の配線やICパッケージ等に寄生する寄生容量に起因して、その応答時間に無視できない遅延が生じる。 However, in the sensor device disclosed in the conventional patent document 1, due to the parasitic capacitance generated at the detection signal output end of the bridge circuit, the settling time from the timing when the physical quantity change of the sensor element is detected until the bridge circuit output falls within the allowable error range. becomes longer, and a delay occurs in the response time until a change in the physical quantity detected by the sensor appears in the output of the sensor device. Especially in the case where the sensor detection signal reception circuit, which is composed of a preamplifier, an AD conversion circuit, etc., is configured as an IC (highly integrated circuit), and the sensor and this IC must be physically separated on the circuit board. Due to the parasitic capacitance of the wiring between the sensor and the IC, the IC package, and the like, there occurs a non-negligible delay in the response time.
 本発明はこのような課題を解決するためになされたもので、
検出される物理量に応じて特性が変化するセンサ素子を少なくとも1つ備えるブリッジ回路と、
ブリッジ回路の作動に要するバイアス電圧をブリッジ回路のバイアス端に印加するバイアス回路と、
ブリッジ回路の検出信号出力端から出力されるセンサ検出信号を受信する検出信号受信回路と、
検出信号出力端に接続されて、検出信号出力端に寄生する寄生容量成分を相殺する負性容量成分を生成する負性容量回路と
を備え、センサ装置を構成した。
The present invention was made to solve such problems,
a bridge circuit comprising at least one sensor element whose characteristics change according to a detected physical quantity;
a bias circuit for applying a bias voltage required for operation of the bridge circuit to a bias terminal of the bridge circuit;
a detection signal receiving circuit that receives the sensor detection signal output from the detection signal output terminal of the bridge circuit;
and a negative capacitance circuit that is connected to the detection signal output end and generates a negative capacitance component that cancels out the parasitic capacitance component parasitic on the detection signal output end.
 本構成によれば、ブリッジ回路の検出信号出力端に現れる寄生容量は、ブリッジ回路の検出信号出力端に接続される負性容量回路が生成する負性容量成分により、その寄生容量成分が相殺される。したがって、センサ素子の物理量変化検出タイミングからブリッジ回路出力が許容誤差範囲に収まるまでのセトリング時間は短縮される。このため、ブリッジ回路の検出信号出力端にセンサ素子の特性変化に応じて現れる、センサ素子が検出する物理量変化は、センサ装置の検出出力に速やかに現れるようになる。 According to this configuration, the parasitic capacitance appearing at the detection signal output end of the bridge circuit is canceled by the negative capacitance component generated by the negative capacitance circuit connected to the detection signal output end of the bridge circuit. be. Therefore, the settling time from when the sensor element detects a change in physical quantity until the bridge circuit output falls within the allowable error range is shortened. Therefore, a physical quantity change detected by the sensor element, which appears at the detection signal output terminal of the bridge circuit in accordance with the characteristic change of the sensor element, quickly appears in the detection output of the sensor device.
 この結果、本発明によれば、センサ素子が検出する物理量変化がセンサ装置の検出出力に現れるまでの応答時間に遅延が生じなくなるセンサ装置を提供することが出来る。 As a result, according to the present invention, it is possible to provide a sensor device in which there is no delay in the response time until changes in the physical quantity detected by the sensor element appear in the detection output of the sensor device.
(a)は、本発明の第1の実施形態によるセンサ装置の概略構成を示す回路図、(b)は(a)に示す負性容量回路の回路構成図である。1A is a circuit diagram showing a schematic configuration of a sensor device according to a first embodiment of the present invention, and FIG. 1B is a circuit configuration diagram of a negative capacitance circuit shown in FIG. (a)は、図1に示すセンサ装置のセンサ素子に入力される物理量の変化を表すグラフ、(b)は、(a)に示す物理量の変化に応じて図1に示すセンサ装置の検出信号出力端に現れるセンサ検出信号を表すグラフである。(a) is a graph showing changes in the physical quantity input to the sensor element of the sensor device shown in FIG. 1, and (b) is a detection signal of the sensor device shown in FIG. 1 in response to the change in the physical quantity shown in (a). Fig. 4 is a graph representing the sensor detection signal appearing at the output; 本発明の第2の実施形態によるセンサ装置の概略構成を示す回路図である。FIG. 5 is a circuit diagram showing a schematic configuration of a sensor device according to a second embodiment of the invention; 図3に示すセンサ装置の検出信号出力端に現れるセンサ検出信号および順次反転するバイアス電圧を表すグラフである。4 is a graph showing a sensor detection signal appearing at a detection signal output terminal of the sensor device shown in FIG. 3 and a sequentially inverted bias voltage; 本発明の第3の実施形態によるセンサ装置の概略構成を示す回路図である。FIG. 5 is a circuit diagram showing a schematic configuration of a sensor device according to a third embodiment of the invention; 本発明の第4の実施形態によるセンサ装置の概略構成を示す回路図である。FIG. 4 is a circuit diagram showing a schematic configuration of a sensor device according to a fourth embodiment of the invention; (a)は、各実施形態のセンサ装置における負性容量回路の第1変形例の回路構成図、(b)は、各実施形態のセンサ装置における負性容量回路の第2変形例の回路構成図である。(a) is a circuit configuration diagram of a first modification of the negative capacitance circuit in the sensor device of each embodiment; (b) is a circuit configuration of a second modification of the negative capacitance circuit in the sensor device of each embodiment; It is a diagram.
 次に、本発明のセンサ装置を実施するための形態について、説明する。 Next, a form for implementing the sensor device of the present invention will be described.
 図1(a)は、本発明の第1の実施形態によるセンサ装置1Aの概略構成を示す回路図である。 FIG. 1(a) is a circuit diagram showing a schematic configuration of a sensor device 1A according to the first embodiment of the present invention.
 センサ装置1Aは、バイアス回路によって励起されるブリッジ回路2、負性容量回路3および検出信号受信回路4から構成される。 The sensor device 1A is composed of a bridge circuit 2 excited by a bias circuit, a negative capacitance circuit 3 and a detection signal receiving circuit 4.
 ブリッジ回路2は、センサを構成し、本実施形態では、1つのセンサ素子Zと3つの抵抗R1,R2,R3とがブリッジ接続されて、構成されている。ブリッジ回路2は、センサ素子Zを少なくとも1つ備えて構成されればよい。したがって、例えば、4つのセンサ素子Zがブリッジ接続されて構成されてもよい。センサ素子Zは、検出される物理量に応じて特性が変化する、例えば、磁気抵抗素子などから構成され、例えば、磁気抵抗効果によって周囲の磁界変化によってその電気抵抗値が変化する。このセンサ素子Zは、同図では抵抗に矢印を付した記号で表され、センサ素子Zの抵抗値が検出物理量に応じて変化することを示している。 The bridge circuit 2 constitutes a sensor, and in this embodiment, one sensor element Z and three resistors R1, R2, and R3 are bridge-connected. The bridge circuit 2 may be configured with at least one sensor element Z. Thus, for example, four sensor elements Z may be configured in a bridge connection. The sensor element Z is composed of, for example, a magnetoresistive element whose characteristics change according to the detected physical quantity. This sensor element Z is represented by a symbol with an arrow attached to a resistance in the same figure, indicating that the resistance value of the sensor element Z changes according to the detected physical quantity.
 センサ素子Zと抵抗R1との接続点、および、抵抗R2と抵抗R3との接続点はそれぞれバイアス端2a,2bを構成し、バイアス端2aとバイアス端2bとの間にはバイアス電圧Vbiasが印加される。このとき、バイアス端2bは接地されていてもよい。バイアス電圧Vbiasの供給源は、ブリッジ回路2の作動に要するバイアス電圧をブリッジ回路2のバイアス端2a,2bに印加するバイアス回路を構成する。また、センサ素子Zと抵抗R2との接続点、および、抵抗R1と抵抗R3との接続点はそれぞれ検出信号出力端2c,2dを構成し、検出信号出力端2c,2dにはセンサ素子Zで検出される物理量の変化がセンサ検出信号sとして現れる。本実施形態では説明のため、センサ素子Zと3つの抵抗R1,R2,R3の各抵抗値は、センサ素子Zで物理量の変化が検出されないとき、各検出信号出力端2c,2dにバイアス電圧Vbiasの1/2の電圧が現れる値に設定されているが、これに限定しない。 A connection point between the sensor element Z and the resistor R1 and a connection point between the resistor R2 and the resistor R3 constitute bias terminals 2a and 2b, respectively, and a bias voltage Vbias is applied between the bias terminals 2a and 2b. be done. At this time, the bias end 2b may be grounded. The source of the bias voltage Vbias constitutes a bias circuit that applies the bias voltage required for the operation of the bridge circuit 2 to the bias terminals 2a and 2b of the bridge circuit 2. FIG. A connection point between the sensor element Z and the resistor R2 and a connection point between the resistor R1 and the resistor R3 constitute detection signal output terminals 2c and 2d, respectively. A change in the detected physical quantity appears as a sensor detection signal s. In this embodiment, for the sake of explanation, the resistance values of the sensor element Z and the three resistors R1, R2, and R3 are such that when the sensor element Z does not detect a change in physical quantity, the bias voltage Vbias is applied to each of the detection signal output terminals 2c and 2d. is set to a value at which 1/2 of the voltage appears, but it is not limited to this.
 検出信号受信回路4は、センサ素子Zの特性変化に応じてブリッジ回路2の検出信号出力端2c,2dから出力されるセンサ検出信号sを受信する。本実施形態では、検出信号受信回路4は、検出信号出力端2c,2dから出力されるセンサ検出信号sを受信して増幅する増幅回路から構成され、センサ検出信号sを増幅したアナログの検出出力信号Sを出力する。 The detection signal receiving circuit 4 receives the sensor detection signal s output from the detection signal output terminals 2c and 2d of the bridge circuit 2 according to the characteristic change of the sensor element Z. In this embodiment, the detection signal receiving circuit 4 is composed of an amplifier circuit that receives and amplifies the sensor detection signal s output from the detection signal output terminals 2c and 2d. A signal S is output.
 各負性容量回路3は、検出信号出力端2c,2dに接続されて、検出信号出力端2c,2dに寄生する寄生容量Csの容量成分を相殺する負性容量としてふるまう。本実施形態では、各負性容量回路3は、図1(b)に示すように、一端が検出信号出力端2c,2dに接続されるコンデンサCoと、コンデンサCoに並列に接続される非反転増幅回路5とから構成される。コンデンサCoは、寄生容量Csの容量値の半分以下の容量値を持つ。また、非反転増幅回路5は、コンデンサCoの一端の電位を増幅してコンデンサCoの他端に与える。 Each negative capacitance circuit 3 is connected to the detection signal output terminals 2c and 2d and acts as a negative capacitance that cancels out the capacitive component of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d. In this embodiment, as shown in FIG. 1B, each negative capacitance circuit 3 includes a capacitor Co whose one end is connected to the detection signal output terminals 2c and 2d, and a non-inverting capacitor Co connected in parallel to the capacitor Co. and an amplifier circuit 5. The capacitor Co has a capacitance value less than half the capacitance value of the parasitic capacitance Cs. Also, the non-inverting amplifier circuit 5 amplifies the potential at one end of the capacitor Co and applies it to the other end of the capacitor Co.
 このような本実施形態によるセンサ装置1Aでは、負性容量回路3の非反転増幅回路5により、コンデンサCoには、その他端から一端へ向かう電圧Vaが印加され、コンデンサCoの一端が接続される検出信号出力端2c,2dには、コンデンサCoから電流ioが流入する。負性容量回路3が無い場合、検出信号出力端2c,2dに寄生する寄生容量Csには、ブリッジ回路2から流入する電流ibによって電流isが流れるが(is=ib)、負性容量回路3を備える本実施形態では、コンデンサCoから流入する電流ioが電流isとして流れる(is=io)。したがって、寄生容量Csの容量成分は、負性容量回路2が生成する負性容量成分によって相殺される。このため、センサ装置1Aでは、検出信号出力端2c,2dに寄生容量Csが生じても、寄生容量Csの影響を受けることなく、検出信号出力端2c,2dに現れるセンサ検出信号sは、検出信号出力端2c,2dから検出信号受信回路4に入力されることとなる。 In the sensor device 1A according to this embodiment, the non-inverting amplifier circuit 5 of the negative capacitance circuit 3 applies a voltage Va directed from the other end to one end of the capacitor Co, and one end of the capacitor Co is connected. A current io flows from the capacitor Co into the detection signal output terminals 2c and 2d. In the absence of the negative capacitance circuit 3, the current is flows through the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d due to the current ib flowing from the bridge circuit 2 (is = ib). , the current io flowing from the capacitor Co flows as the current is (is=io). Therefore, the capacitive component of the parasitic capacitance Cs is canceled by the negative capacitive component generated by the negative capacitive circuit 2 . Therefore, in the sensor device 1A, even if a parasitic capacitance Cs is generated at the detection signal output terminals 2c and 2d, the sensor detection signal s appearing at the detection signal output terminals 2c and 2d is detected without being affected by the parasitic capacitance Cs. The signals are input to the detection signal receiving circuit 4 from the signal output terminals 2c and 2d.
 例えば、センサ素子Zに図2(a)のグラフに示す物理量変化が入力されると、検出信号出力端2c,2dには図2(b)のグラフに示すセンサ検出信号sが現れる。同図(a)に示すグラフの縦軸はセンサ素子Zに入力される物理量pの大きさ、例えば、センサ素子Zが磁気抵抗素子である場合には磁界の大きさを表し、横軸は時間tを表す。同図(b)に示すグラフの縦軸はセンサ検出信号sの大きさを表し、横軸は時間tを表す。 For example, when the change in physical quantity shown in the graph of FIG. 2(a) is input to the sensor element Z, the sensor detection signal s shown in the graph of FIG. 2(b) appears at the detection signal output terminals 2c and 2d. The vertical axis of the graph shown in FIG. 1A represents the magnitude of the physical quantity p input to the sensor element Z, for example, the magnitude of the magnetic field when the sensor element Z is a magnetoresistive element, and the horizontal axis represents time. represents t. The vertical axis of the graph shown in FIG. 8(b) represents the magnitude of the sensor detection signal s, and the horizontal axis represents time t.
 また、同図(b)に示すグラフで破線で示す特性線21は、理想的な応答特性を有するセンサ検出信号sの特性、一点鎖線で示す特性線22は、寄生容量Csとブリッジ回路2の抵抗分との積で決まる時定数で応答特性が遅延したセンサ検出信号sの特性、太い実線で示す特性線23は、負性容量回路3によって時定数が小さくなって応答特性が補償された本実施形態におけるセンサ検出信号sの特性を表している。センサ素子Zに物理量pの変化が検出されるタイミングt1において、特性線23では、センサ検出信号sの立ち上がりが、寄生容量Csの影響を受ける特性線22の立ち上がりよりも速く、理想的な特性線21の立ち上がりに近付いている。また、センサ素子Zに物理量pの変化が検出されなくなるタイミングt2において、特性線23では、センサ検出信号sの立ち下がりが、寄生容量Csの影響を受ける特性線22の立ち下がりよりも速く、理想的な特性線21の立ち下がりに近付いている。 A characteristic line 21 indicated by a broken line in the graph shown in FIG. The characteristics of the sensor detection signal s whose response characteristics are delayed by the time constant determined by the product of the resistance component, and the characteristic line 23 indicated by the thick solid line are the response characteristics compensated for by the negative capacitance circuit 3 reducing the time constant. 4 shows characteristics of a sensor detection signal s in the embodiment. At the timing t1 when a change in the physical quantity p is detected in the sensor element Z, in the characteristic line 23, the rise of the sensor detection signal s is faster than the rise of the characteristic line 22 affected by the parasitic capacitance Cs. We are approaching the start of the 21st. At the timing t2 when the change in the physical quantity p is no longer detected in the sensor element Z, in the characteristic line 23, the sensor detection signal s falls faster than the characteristic line 22 affected by the parasitic capacitance Cs. is approaching the falling edge of the characteristic line 21 .
 このように本実施形態によるセンサ装置1Aによれば、ブリッジ回路2の検出信号出力端2c,2dに現れる寄生容量Csは、検出信号出力端2c,2dに接続される負性容量回路3が生成する負性容量成分により、その寄生容量成分が相殺される。したがって、センサ素子Zの物理量変化検出タイミングからブリッジ回路2の出力が許容誤差範囲に収まるまでのセトリング時間は短縮される。このため、検出信号出力端2c,2dにセンサ素子Zの特性変化に応じて現れる、センサ素子Zが検出する物理量変化は、センサ装置1Aの検出出力に速やかに現れるようになる。この結果、センサ素子Zが検出する物理量変化、例えば、磁気抵抗素子が検出する磁界変化が、センサ装置1Aの検出出力に現れるまでの応答時間に遅延が生じなくなる。よって、検出信号受信回路4がIC(高集積化回路)として構成され、ブリッジ回路2で構成されるセンサとこのICとを回路基板上で物理的に分離しなければならないケースでも、センサ装置1Aの検出出力に遅延が生じることはなく、安定したセンサ動作を提供することができる。 Thus, according to the sensor device 1A of this embodiment, the parasitic capacitance Cs appearing at the detection signal output terminals 2c and 2d of the bridge circuit 2 is generated by the negative capacitance circuit 3 connected to the detection signal output terminals 2c and 2d. The parasitic capacitive component is canceled by the negative capacitive component. Therefore, the settling time from when the sensor element Z detects a change in physical quantity until the output of the bridge circuit 2 falls within the allowable error range is shortened. Therefore, physical quantity changes detected by the sensor element Z, which appear at the detection signal output terminals 2c and 2d in accordance with changes in the characteristics of the sensor element Z, quickly appear in the detection output of the sensor device 1A. As a result, there is no delay in the response time until changes in the physical quantity detected by the sensor element Z, such as changes in the magnetic field detected by the magnetoresistive element, appear in the detection output of the sensor device 1A. Therefore, even in the case where the detection signal receiving circuit 4 is configured as an IC (highly integrated circuit) and the sensor configured by the bridge circuit 2 and this IC must be physically separated on the circuit board, the sensor device 1A There is no delay in the detection output of the sensor, and stable sensor operation can be provided.
 また、検出信号出力端2c,2dに現れるセンサ検出信号sの周波数領域が、負性容量回路3を構成する非反転増幅回路5の動作が追いつかなくなる高周波数領域では、非反転増幅回路5によってコンデンサCoの他端に十分な電圧Vaが印加されなくなる。したがって、コンデンサCoから寄生容量Csにその容量成分を相殺する電流ioが流れなくなり、負性容量回路3を構成するコンデンサCoが、逆に、検出信号出力端2c,2dに寄生する寄生容量としてふるまうこととなる。しかし、本実施形態によるセンサ装置1Aによれば、このような場合においても、コンデンサCoの容量値が、検出信号出力端2c,2dに寄生する寄生容量Csの容量値の半分以下に設定されることで、負性容量回路3を構成するコンデンサCoが、検出信号出力端2c,2dに逆に寄生してしまう寄生容量の容量成分を、元々寄生する寄生容量Csの半分以下に低減することができる。 In addition, in the high frequency range where the operation of the non-inverting amplifier circuit 5 constituting the negative capacitance circuit 3 cannot keep up with the frequency range of the sensor detection signal s appearing at the detection signal output terminals 2c and 2d, the non-inverting amplifier circuit 5 converts the capacitor A sufficient voltage Va is not applied to the other end of Co. Therefore, the current io that cancels the capacitance component does not flow from the capacitor Co to the parasitic capacitance Cs, and the capacitor Co that constitutes the negative capacitance circuit 3 behaves conversely as a parasitic capacitance that is parasitic on the detection signal output terminals 2c and 2d. It will happen. However, according to the sensor device 1A of the present embodiment, even in such a case, the capacitance value of the capacitor Co is set to be less than half the capacitance value of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d. As a result, the capacitive component of the parasitic capacitance that the capacitor Co constituting the negative capacitance circuit 3 inversely parasitics on the detection signal output terminals 2c and 2d can be reduced to less than half the originally parasitic capacitance Cs. can.
 図3は、本発明の第2の実施形態によるセンサ装置1Bの概略構成を示す回路図である。なお、同図において図1と同一または相当する部分には同一符号を付してその説明は省略する。 FIG. 3 is a circuit diagram showing a schematic configuration of the sensor device 1B according to the second embodiment of the invention. In the figure, the same reference numerals are given to the same or corresponding parts as those in FIG. 1, and the description thereof will be omitted.
 センサ装置1Bは、一定電圧差を持つバイアス電圧Vbiasを出力するバイアス回路6と、バイアス回路6とブリッジ回路2との間に設けられるバイアス電圧反転回路7とを、センサ装置1Aの構成に加えてさらに備え、検出信号受信回路4が信号反転回路8を内部に有する点が、第1の実施形態によるセンサ装置1Aと相違する。 The sensor device 1B includes a bias circuit 6 that outputs a bias voltage Vbias having a constant voltage difference, and a bias voltage inverting circuit 7 provided between the bias circuit 6 and the bridge circuit 2, in addition to the configuration of the sensor device 1A. Further, the difference from the sensor device 1A according to the first embodiment is that the detection signal receiving circuit 4 has a signal inverting circuit 8 therein.
 第1の実施形態によるセンサ装置1Aでは、固定したバイアス電圧Vbiasが接地電圧に対して印加されて、バイアス回路が構成された。しかし、本実施形態では、バイアス回路6は、2つのバイアス電圧出力を備えるレギュレータから構成され、一定電圧差を持つバイアス電圧Vbiasを出力する。バイアス回路6は、一方の電圧出力端から正のバイアス電圧、例えば、本実施形態では5[V]のバイアス電圧を出力し、他方の電圧出力端から負のバイアス電圧を出力する。負のバイアス電圧は接地電圧でもよく、本実施形態では負のバイアス電圧として接地電圧(0[V])を出力する。 In the sensor device 1A according to the first embodiment, a bias circuit is configured by applying a fixed bias voltage Vbias to the ground voltage. However, in this embodiment, the bias circuit 6 is composed of a regulator having two bias voltage outputs, and outputs a bias voltage Vbias having a constant voltage difference. The bias circuit 6 outputs a positive bias voltage, eg, a bias voltage of 5 [V] in this embodiment, from one voltage output terminal, and outputs a negative bias voltage from the other voltage output terminal. The negative bias voltage may be the ground voltage, and in this embodiment, the ground voltage (0 [V]) is output as the negative bias voltage.
 バイアス電圧反転回路7は、例えば4つのスイッチSW1,SW2,SW3,SW4からなるクロスバースイッチとして構成され、各スイッチSW1~SW4の接続状態を順次切り替えることで、バイアス回路6によってブリッジ回路2のバイアス端2a,2bに印加されるバイアス電圧Vbiasの極性を順次反転する。信号反転回路8は検出信号受信回路4に内蔵されたクロスバースイッチから構成され、検出信号受信回路4から出力される検出出力信号Sの極性を順次反転する。 The bias voltage inverting circuit 7 is configured, for example, as a crossbar switch including four switches SW1, SW2, SW3, and SW4. The polarities of the bias voltages Vbias applied to the terminals 2a and 2b are sequentially reversed. The signal inverting circuit 8 is composed of a crossbar switch built in the detection signal receiving circuit 4 and sequentially inverts the polarity of the detection output signal S output from the detection signal receiving circuit 4 .
 図4は、バイアス電圧反転回路7によって順次反転されたバイアス電圧Vbias、および、図2と同様に、センサ素子Zに図2(a)のグラフに示す物理量変化が入力されたときに、検出信号出力端2c,2dに現れるセンサ検出信号sを示す。なお、同図において図2と同一または相当する部分には同一符号を付してその説明は省略する。ここで、バイアス回路6は、5[V]の正のバイアス電圧および接地電圧0[V]の2つのバイアス電圧を出力するものとする。 FIG. 4 shows the detection signal when the bias voltage Vbias sequentially inverted by the bias voltage inverting circuit 7 and the change in physical quantity shown in the graph of FIG. The sensor detection signal s appearing at the outputs 2c, 2d is shown. In the figure, the same reference numerals are given to the same or corresponding parts as those in FIG. 2, and the description thereof will be omitted. Here, it is assumed that the bias circuit 6 outputs two bias voltages, a positive bias voltage of 5[V] and a ground voltage of 0[V].
 センサ装置1Bでは、検出信号受信回路4から出力されるアナログの検出出力信号Sを信号反転回路8によって順次反転して、検出信号受信回路4のオフセット電圧をセンサ検出信号sの周波数帯域と異なる周波数に変調することで、検出信号受信回路4から出力される検出出力信号Sに含まれる検出信号受信回路4のオフセット電圧を分別する。 In the sensor device 1B, the analog detection output signal S output from the detection signal receiving circuit 4 is sequentially inverted by the signal inverting circuit 8, and the offset voltage of the detection signal receiving circuit 4 is set to a frequency different from the frequency band of the sensor detection signal s. , the offset voltage of the detection signal receiving circuit 4 included in the detection output signal S output from the detection signal receiving circuit 4 is separated.
 このような第2の実施形態のセンサ装置1Bでも、第1の実施形態のセンサ装置1Aと同様な作用効果が奏され、図4に示すように、センサ素子Zに物理量pの変化が検出されるタイミングt1において、センサ装置1Bの特性を表す特性線23では、センサ検出信号sの立ち上がりが、負性容量回路3を備えないで寄生容量Csの影響を受ける特性線22の立ち上がりよりも速く、理想的な特性線21の立ち上がりに近付いている。また、センサ素子Zに物理量pの変化が検出されなくなるタイミングt2において、特性線23では、センサ検出信号sの立ち下がりが、寄生容量Csの影響を受ける特性線22の立ち下がりよりも速く、理想的な特性線21の立ち下がりに近付いている。 In the sensor device 1B of the second embodiment as described above, the same effects as those of the sensor device 1A of the first embodiment are exhibited, and as shown in FIG. At timing t1, in the characteristic line 23 representing the characteristics of the sensor device 1B, the rise of the sensor detection signal s is faster than the rise of the characteristic line 22 which does not include the negative capacitance circuit 3 and is affected by the parasitic capacitance Cs. The rise of the ideal characteristic line 21 is approaching. At the timing t2 when the change in the physical quantity p is no longer detected in the sensor element Z, in the characteristic line 23, the sensor detection signal s falls faster than the characteristic line 22 affected by the parasitic capacitance Cs. is approaching the falling edge of the characteristic line 21 .
 また、ブリッジ回路2から検出信号受信回路4にセンサ検出信号sが極性が順次反転されて入力される際、各極性のセンサ検出信号sには、検出信号受信回路4のオフセット電圧が同じ極性で重畳する。さらに、極性が順次反転された各センサ検出信号sは、検出信号受信回路4の検出出力信号Sが信号反転回路8によってさらに反転されることで、元の極性に戻されてセンサ装置1Bから出力される。一方、検出信号受信回路4のオフセット電圧は、信号反転回路8によって順次反転していた周波数に変調されるため、センサ検出信号sとは異なる周波数帯域で出力され、検出信号受信回路4の検出出力信号Sと分別される。このため、第2の実施形態のセンサ装置1Bによれば、センサ装置1Bからは、センサ素子Zが検出する物理量変化が、遅延を生じることなく高速に、しかも、検出信号受信回路4のオフセット電圧を含むことなく、正確に出力される。 Further, when the sensor detection signal s is sequentially inverted in polarity and input from the bridge circuit 2 to the detection signal reception circuit 4, the offset voltage of the detection signal reception circuit 4 has the same polarity in the sensor detection signal s of each polarity. superimpose. Further, the sensor detection signals s whose polarities are sequentially inverted are returned to their original polarities and output from the sensor device 1B by further inverting the detection output signals S of the detection signal receiving circuit 4 by the signal inverting circuit 8. be done. On the other hand, since the offset voltage of the detection signal receiving circuit 4 is modulated to the frequency that has been sequentially inverted by the signal inverting circuit 8, it is output in a frequency band different from that of the sensor detection signal s. It is separated from the signal S. Therefore, according to the sensor device 1B of the second embodiment, changes in the physical quantity detected by the sensor element Z are transmitted from the sensor device 1B at high speed without delay, and at the same time as the offset voltage of the detection signal receiving circuit 4. is output correctly without including
 図5は、本発明の第3の実施形態によるセンサ装置1Cの概略構成を示す回路図である。なお、同図において図3と同一または相当する部分には同一符号を付してその説明は省略する。 FIG. 5 is a circuit diagram showing a schematic configuration of a sensor device 1C according to the third embodiment of the invention. In the figure, the same reference numerals are given to the same or corresponding parts as those in FIG. 3, and the description thereof will be omitted.
 センサ装置1Cは、検出信号受信回路4がAD変換回路9とデジタルフィルタ10とを備え、信号反転回路8を備えない点において、第2の実施形態によるセンサ装置1Bと相違する。 The sensor device 1C differs from the sensor device 1B according to the second embodiment in that the detection signal receiving circuit 4 includes an AD conversion circuit 9 and a digital filter 10, but does not include the signal inverting circuit 8.
 AD変換回路9は、バイアス端2a,2bに印加されるバイアス電圧Vbiasの極性が順次反転されることで検出信号出力端2c,2dから極性が順次反転して出力される各センサ検出信号sを、アナログ信号からデジタル信号に変換する。バイアス電圧反転回路7とAD変換回路9には同一のクロック信号clkが与えられており、AD変換回路9におけるAD変換は、バイアス電圧反転回路7におけるバイアス電圧Vbiasの極性反転と同期して行われる。デジタルフィルタ10は、デジタル信号に変換された各センサ検出信号sに重畳する雑音を抑制すると共に、AD変換回路9から出力される一方の極性のセンサ検出信号sを加算し、他方の極性のセンサ検出信号sを減算して、センサ検出信号sに含まれるAD変換回路9のオフセット電圧を抑制する。 The AD conversion circuit 9 converts each sensor detection signal s output from the detection signal output terminals 2c and 2d with the polarities sequentially reversed by sequentially inverting the polarity of the bias voltage Vbias applied to the bias terminals 2a and 2b. , to convert analog signals to digital signals. The bias voltage inversion circuit 7 and the AD conversion circuit 9 are supplied with the same clock signal clk, and the AD conversion in the AD conversion circuit 9 is performed in synchronization with the polarity inversion of the bias voltage Vbias in the bias voltage inversion circuit 7. . The digital filter 10 suppresses noise superimposed on each sensor detection signal s converted into a digital signal, adds the sensor detection signal s of one polarity output from the AD conversion circuit 9, and adds the sensor detection signal s of the other polarity. By subtracting the detection signal s, the offset voltage of the AD conversion circuit 9 included in the sensor detection signal s is suppressed.
 このような第3の実施形態のセンサ装置1Cでも、第1,第2の各実施形態のセンサ装置1A,1Bと同様な作用効果が奏され、ブリッジ回路2の検出信号出力端2c,2dに現れる寄生容量Csは、検出信号出力端2c,2dに接続される負性容量回路3が生成する負性容量成分により、その寄生容量成分が相殺される。このため、センサ素子Zが検出する物理量変化がセンサ装置1Cの検出出力に現れるまでの応答時間に、遅延が生じなくなる。 In the sensor device 1C of the third embodiment, the same effects as those of the sensor devices 1A and 1B of the first and second embodiments are obtained. The appearing parasitic capacitance Cs is canceled by the negative capacitance component generated by the negative capacitance circuit 3 connected to the detection signal output terminals 2c and 2d. Therefore, no delay occurs in the response time until the change in the physical quantity detected by the sensor element Z appears in the detection output of the sensor device 1C.
 また、第3の実施形態のセンサ装置1Cによれば、ブリッジ回路2から検出信号受信回路4に極性が順次反転されて入力されるセンサ検出信号sは、AD変換回路9でアナログ信号からデジタル信号に変換される。この際、デジタル信号に変換される各極性のセンサ検出信号sには、AD変換回路9のオフセット電圧が同じ極性で重畳する。したがって、デジタルフィルタ10において、センサ検出信号sが一方の極性のときにAD変換回路9から出力されるセンサ検出信号sが加算され、センサ検出信号sが他方の極性のときにAD変換回路9から出力されるセンサ検出信号sが減算されることで、AD変換回路9のオフセット電圧は、センサ検出信号sからデジタル処理によってキャンセルすることができる。このため、センサ装置1Cからは、センサ素子Zが検出する物理量変化が、遅延を生じることなく高速に、しかも、AD変換回路9のオフセット電圧を含むことなく、デジタルの検出出力信号Sとして正確に低雑音で出力される。 Further, according to the sensor device 1C of the third embodiment, the sensor detection signal s that is input from the bridge circuit 2 to the detection signal receiving circuit 4 after being sequentially inverted in polarity is converted from an analog signal to a digital signal by the AD conversion circuit 9. is converted to At this time, the offset voltage of the AD conversion circuit 9 with the same polarity is superimposed on the sensor detection signal s of each polarity converted into a digital signal. Therefore, in the digital filter 10, the sensor detection signal s output from the AD conversion circuit 9 is added when the sensor detection signal s has one polarity, and the sensor detection signal s from the AD conversion circuit 9 when the sensor detection signal s has the other polarity. By subtracting the output sensor detection signal s, the offset voltage of the AD conversion circuit 9 can be canceled from the sensor detection signal s by digital processing. Therefore, from the sensor device 1C, changes in the physical quantity detected by the sensor element Z can be accurately detected as a digital detection output signal S at high speed without delay and without including the offset voltage of the AD conversion circuit 9. Output with low noise.
 図6は、本発明の第4の実施形態によるセンサ装置1Dの概略構成を示す回路図である。なお、同図において図5と同一または相当する部分には同一符号を付してその説明は省略する。 FIG. 6 is a circuit diagram showing a schematic configuration of a sensor device 1D according to the fourth embodiment of the invention. In the figure, the same reference numerals are given to the same or corresponding parts as those in FIG. 5, and the description thereof will be omitted.
 センサ装置1Dは、検出信号受信回路4がブリッジ回路2とAD変換回路9との間に前置増幅回路11を備える点において、第3の実施形態によるセンサ装置1Cと相違する。前置増幅回路11は、ブリッジ回路2から出力されるセンサ検出信号sを増幅する。 The sensor device 1D differs from the sensor device 1C according to the third embodiment in that the detection signal receiving circuit 4 includes a pre-amplifier circuit 11 between the bridge circuit 2 and the AD conversion circuit 9 . A preamplifier circuit 11 amplifies the sensor detection signal s output from the bridge circuit 2 .
 この第4の実施形態によるセンサ装置1Dでは、デジタルフィルタ10に入力される各極性のセンサ検出信号sには、前置増幅回路11およびAD変換回路9の各オフセット電圧が同じ極性で重畳する。したがって、デジタルフィルタ10において、センサ検出信号sが一方の極性のときにAD変換回路9から出力されるセンサ検出信号sが加算され、センサ検出信号sが他方の極性のときにAD変換回路9から出力されるセンサ検出信号sが減算されることで、前置増幅回路11およびAD変換回路9の各オフセット電圧は、センサ検出信号sからデジタル処理によってキャンセルすることができる。このため、センサ装置1Dからは、センサ素子Zが検出する物理量変化が、遅延を生じることなく高速に、しかも、前置増幅回路11およびAD変換回路9の各オフセット電圧を含むことなく、デジタルの検出出力信号Sとして正確に低雑音で出力される。 In the sensor device 1D according to the fourth embodiment, each polarity sensor detection signal s input to the digital filter 10 is superimposed with each offset voltage of the preamplifier circuit 11 and the AD conversion circuit 9 with the same polarity. Therefore, in the digital filter 10, the sensor detection signal s output from the AD conversion circuit 9 is added when the sensor detection signal s has one polarity, and the sensor detection signal s from the AD conversion circuit 9 when the sensor detection signal s has the other polarity. By subtracting the output sensor detection signal s, each offset voltage of the preamplifier circuit 11 and the AD conversion circuit 9 can be canceled from the sensor detection signal s by digital processing. Therefore, from the sensor device 1D, changes in the physical quantity detected by the sensor element Z are digitalized at high speed without delay and without including the offset voltages of the preamplifier circuit 11 and the AD converter circuit 9. It is accurately output as the detection output signal S with low noise.
 なお、上記の各実施形態において、負性容量回路3を構成する非反転増幅回路5は、図7(a)に示すように、増幅利得が調整自在な非反転増幅回路5Aによって構成されるようにしてもよい。本構成によれば、コンデンサCoの他端に非反転増幅回路5Aによって印加される電圧Vaは、検出信号出力端2c,2dに寄生する寄生容量Csの容量成分に応じて自在に調整される。このため、寄生容量Csは負性容量回路3によって的確にその容量成分が相殺されるようになる。 In each of the above embodiments, the non-inverting amplifier circuit 5 constituting the negative capacitance circuit 3 is configured by a non-inverting amplifier circuit 5A whose amplification gain is adjustable, as shown in FIG. 7(a). can be According to this configuration, the voltage Va applied by the non-inverting amplifier circuit 5A to the other end of the capacitor Co is freely adjusted according to the capacitive component of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d. Therefore, the capacitance component of the parasitic capacitance Cs is accurately canceled by the negative capacitance circuit 3 .
 また、上記の各実施形態において、負性容量回路3を構成するコンデンサCoは、図7(b)に示すように、その容量値が調整自在な可変容量コンデンサCoAによって構成されるようにしてもよい。本構成によれば、コンデンサCoAから寄生容量Csに流れ込む電流ioは、コンデンサCoAの容量値を調整することで、検出信号出力端2c,2dに寄生する寄生容量Csの容量成分に応じて自在に調整される。このため、寄生容量Csは負性容量回路3によって的確にその容量成分が相殺されるようになる。 In each of the above embodiments, the capacitor Co forming the negative capacitance circuit 3 may be configured by a variable capacitor CoA whose capacitance value is adjustable, as shown in FIG. 7(b). good. According to this configuration, the current io flowing from the capacitor CoA to the parasitic capacitance Cs can be adjusted freely according to the capacitive component of the parasitic capacitance Cs parasitic on the detection signal output terminals 2c and 2d by adjusting the capacitance value of the capacitor CoA. adjusted. Therefore, the capacitance component of the parasitic capacitance Cs is accurately canceled by the negative capacitance circuit 3 .
 1A,1B,1C,1D…センサ装置
 2…ブリッジ回路
 2a,2b…バイアス端
 2c,2d…検出信号出力端
 3…負性容量回路
 4…検出信号受信回路
 5…非反転増幅回路
 6…バイアス回路
 7…バイアス電圧反転回路
 8…信号反転回路
 9…AD変換回路
 10…デジタルフィルタ
 11…前置増幅回路
 Cs…寄生容量
 Co…コンデンサ
 Z…センサ素子
1A, 1B, 1C, 1D... Sensor device 2... Bridge circuit 2a, 2b... Bias terminal 2c, 2d... Detection signal output terminal 3... Negative capacitance circuit 4... Detection signal receiving circuit 5... Non-inverting amplifier circuit 6... Bias circuit 7 Bias voltage inversion circuit 8 Signal inversion circuit 9 AD conversion circuit 10 Digital filter 11 Preamplifier circuit Cs Parasitic capacitance Co Capacitor Z Sensor element

Claims (8)

  1.  検出される物理量に応じて特性が変化するセンサ素子を少なくとも1つ備えるブリッジ回路と、
     前記ブリッジ回路の作動に要するバイアス電圧を前記ブリッジ回路のバイアス端に印加するバイアス回路と、
     前記ブリッジ回路の検出信号出力端から出力されるセンサ検出信号を受信する検出信号受信回路と、
     前記検出信号出力端に接続されて、前記検出信号出力端に寄生する寄生容量成分を相殺する負性容量成分を生成する負性容量回路と
     を備えるセンサ装置。
    a bridge circuit comprising at least one sensor element whose characteristics change according to a detected physical quantity;
    a bias circuit that applies a bias voltage required for operating the bridge circuit to a bias terminal of the bridge circuit;
    a detection signal receiving circuit for receiving a sensor detection signal output from a detection signal output terminal of the bridge circuit;
    a negative capacitance circuit that is connected to the detection signal output terminal and generates a negative capacitance component that cancels out a parasitic capacitance component parasitic on the detection signal output terminal.
  2.  前記バイアス回路は一定電圧差を持つバイアス電圧を出力し、
     前記バイアス回路と前記ブリッジ回路との間に設けられ、前記バイアス回路によって前記バイアス端に印加されるバイアス電圧の極性を順次反転するバイアス電圧反転回路と、前記検出信号受信回路から出力される検出出力信号の極性を順次反転する信号反転回路とを備え、
     前記検出信号受信回路から出力される検出出力信号を前記信号反転回路によって順次反転して、前記検出信号受信回路のオフセット電圧を前記センサ検出信号の周波数帯域と異なる周波数に変調することで、前記検出信号受信回路から出力される検出出力信号に含まれる前記検出信号受信回路のオフセット電圧を分別する
     ことを特徴とする請求項1に記載のセンサ装置。
    the bias circuit outputs a bias voltage having a constant voltage difference;
    a bias voltage inverting circuit provided between the bias circuit and the bridge circuit for sequentially inverting the polarity of the bias voltage applied to the bias terminal by the bias circuit; and a detection output output from the detection signal receiving circuit. a signal inverting circuit that sequentially inverts the polarity of the signal,
    By sequentially inverting the detection output signal output from the detection signal receiving circuit by the signal inverting circuit and modulating the offset voltage of the detection signal receiving circuit to a frequency different from the frequency band of the sensor detection signal, the detection 2. The sensor device according to claim 1, wherein an offset voltage of said detection signal receiving circuit included in a detection output signal output from said signal receiving circuit is separated.
  3.  前記バイアス回路は一定電圧差を持つバイアス電圧を出力し、
     前記バイアス回路と前記ブリッジ回路との間に設けられ、前記バイアス回路によって前記バイアス端に印加されるバイアス電圧の極性を順次反転するバイアス電圧反転回路を備え、
     前記検出信号受信回路は、前記バイアス端に印加されるバイアス電圧の極性が順次反転されることで前記検出信号出力端から極性が順次反転して出力される各前記センサ検出信号をアナログ信号からデジタル信号に変換するAD変換回路と、デジタル信号に変換された各前記センサ検出信号に重畳する雑音を抑制すると共に、前記AD変換回路から出力される一方の極性の前記センサ検出信号を加算し、他方の極性の前記センサ検出信号を減算して前記センサ検出信号に含まれる前記AD変換回路のオフセット電圧を抑制するデジタルフィルタとを備える
     ことを特徴とする請求項1に記載のセンサ装置。
    the bias circuit outputs a bias voltage having a constant voltage difference;
    a bias voltage inverting circuit provided between the bias circuit and the bridge circuit for sequentially inverting the polarity of the bias voltage applied to the bias terminal by the bias circuit;
    The detection signal receiving circuit converts each of the sensor detection signals, which are sequentially inverted in polarity and output from the detection signal output terminal by sequentially inverting the polarity of the bias voltage applied to the bias terminal, from an analog signal to a digital signal. An AD conversion circuit that converts into a signal, suppresses noise superimposed on each of the sensor detection signals converted into digital signals, adds the sensor detection signals of one polarity output from the AD conversion circuit, and adds the sensor detection signals of one polarity output from the AD conversion circuit. 2 . The sensor device according to claim 1 , further comprising a digital filter that subtracts the sensor detection signal having the polarity of + to suppress an offset voltage of the AD conversion circuit included in the sensor detection signal.
  4.  前記ブリッジ回路と前記AD変換回路との間に前記ブリッジ回路から出力される前記センサ検出信号を増幅する前置増幅回路を備え、
     前記デジタルフィルタは、デジタル信号に変換された各前記センサ検出信号に重畳する雑音を抑制すると共に、前記AD変換回路から出力される一方の極性の前記センサ検出信号を加算し、他方の極性の前記センサ検出信号を減算して前記前置増幅回路および前記AD変換回路の各オフセット電圧を抑制する
     ことを特徴とする請求項3に記載のセンサ装置。
    A pre-amplifier circuit for amplifying the sensor detection signal output from the bridge circuit is provided between the bridge circuit and the AD conversion circuit,
    The digital filter suppresses noise superimposed on each of the sensor detection signals converted into digital signals, adds the sensor detection signals of one polarity output from the AD conversion circuit, and adds the sensor detection signals of the other polarity. 4. The sensor device according to claim 3, wherein each offset voltage of said pre-amplifier circuit and said AD converter circuit is suppressed by subtracting a sensor detection signal.
  5.  前記負性容量回路は、
     前記検出信号出力端に寄生する寄生容量の容量値の半分以下の容量値を持つ、一端が前記検出信号出力端に接続されるコンデンサと、
     前記コンデンサに並列に接続され、前記コンデンサの一端の電位を増幅して前記コンデンサの他端に与える非反転増幅回路と
     から構成されることを特徴とする請求項1から請求項4のいずれか1項に記載のセンサ装置。
    The negative capacitance circuit is
    a capacitor whose one end is connected to the detection signal output end and which has a capacitance value equal to or less than half the capacitance value of the parasitic capacitance parasitic on the detection signal output end;
    5. A non-inverting amplifier circuit connected in parallel to the capacitor, amplifies the potential of one end of the capacitor and applies the amplified potential to the other end of the capacitor. 10. A sensor device according to claim 1.
  6.  前記非反転増幅回路は増幅利得が調整自在であることを特徴とする請求項5に記載のセンサ装置。 The sensor device according to claim 5, wherein the non-inverting amplifier circuit has an adjustable amplification gain.
  7.  前記コンデンサは容量値が調整自在であることを特徴とする請求項5に記載のセンサ装置。 The sensor device according to claim 5, wherein the capacitance value of the capacitor is adjustable.
  8.  前記センサ素子は磁気抵抗素子であることを特徴とする請求項1から請求項7のいずれか1項に記載のセンサ装置。 The sensor device according to any one of claims 1 to 7, wherein the sensor element is a magnetoresistive element.
PCT/JP2022/002527 2021-02-16 2022-01-25 Sensor device WO2022176523A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-022366 2021-02-16
JP2021022366 2021-02-16

Publications (1)

Publication Number Publication Date
WO2022176523A1 true WO2022176523A1 (en) 2022-08-25

Family

ID=82931550

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/002527 WO2022176523A1 (en) 2021-02-16 2022-01-25 Sensor device

Country Status (1)

Country Link
WO (1) WO2022176523A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002521696A (en) * 1998-07-29 2002-07-16 ルスト・アントリープステヒニク・ゲゼルシヤフト・ミト・ベシユレンクテル・ハフツング Method for evaluating the signal of a magnetoresistive sensor and an apparatus for implementing the method
JP4814209B2 (en) * 2007-12-21 2011-11-16 オンセミコンダクター・トレーディング・リミテッド AD converter
JP2012500407A (en) * 2008-08-15 2012-01-05 ケンブリッジ ディスプレイ テクノロジー リミテッド Active matrix display device
US20120025819A1 (en) * 2010-07-30 2012-02-02 Nxp B.V. Magnetoresistive sensor
JP2019105583A (en) * 2017-12-14 2019-06-27 アルプスアルパイン株式会社 Current sensor, manufacturing method for current sensor and semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002521696A (en) * 1998-07-29 2002-07-16 ルスト・アントリープステヒニク・ゲゼルシヤフト・ミト・ベシユレンクテル・ハフツング Method for evaluating the signal of a magnetoresistive sensor and an apparatus for implementing the method
JP4814209B2 (en) * 2007-12-21 2011-11-16 オンセミコンダクター・トレーディング・リミテッド AD converter
JP2012500407A (en) * 2008-08-15 2012-01-05 ケンブリッジ ディスプレイ テクノロジー リミテッド Active matrix display device
US20120025819A1 (en) * 2010-07-30 2012-02-02 Nxp B.V. Magnetoresistive sensor
JP2019105583A (en) * 2017-12-14 2019-06-27 アルプスアルパイン株式会社 Current sensor, manufacturing method for current sensor and semiconductor device

Similar Documents

Publication Publication Date Title
JP4352562B2 (en) Signal processing device
US5231351A (en) Magnetoresistive speed sensor processing circuit utilizing a symmetrical hysteresis signal
KR101127891B1 (en) Output amplifier circuit and sensor device using the same
US7764118B2 (en) Auto-correction feedback loop for offset and ripple suppression in a chopper-stabilized amplifier
US5909132A (en) Resistance bridge and its use in conversion systems
US8193807B2 (en) Magnetic sensor device
US20100321105A1 (en) Switched capacitor notch filter
US4246497A (en) Phase measuring circuit
RU2553086C1 (en) Amplifier and signal processing device
CN108694962B (en) Amplifier and semiconductor device using the same
US11561237B2 (en) Circuit for sensing an analog signal, corresponding electronic system and method
US20110260788A1 (en) Amplifier device and sensor module
CN114978054A (en) Self-stabilizing zero operational amplifier
WO2018042528A1 (en) Capacitive sensor
JP2972552B2 (en) Detection circuit and detection method for capacitive sensor
WO2022176523A1 (en) Sensor device
US20170241807A1 (en) Readout circuit
US8941438B2 (en) Bandwidth limiting for amplifiers
JP2019114901A (en) Semiconductor device and sensor system
JP3584803B2 (en) Pressure sensor circuit
JP5284875B2 (en) Offset voltage correction circuit
Tirupathi et al. A low offset switched capacitor based interfacing circuit for integrated capacitive sensors
US8018273B2 (en) Filter circuit
JP2023141832A (en) Amplifier circuit and sensor circuit
JP2006129107A (en) Signal amplifier

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22755847

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22755847

Country of ref document: EP

Kind code of ref document: A1