WO2022174527A1 - 一种芯片外延层结构及其制造方法 - Google Patents

一种芯片外延层结构及其制造方法 Download PDF

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WO2022174527A1
WO2022174527A1 PCT/CN2021/094642 CN2021094642W WO2022174527A1 WO 2022174527 A1 WO2022174527 A1 WO 2022174527A1 CN 2021094642 W CN2021094642 W CN 2021094642W WO 2022174527 A1 WO2022174527 A1 WO 2022174527A1
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layer
etching
epitaxial layer
buffer layer
chip
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PCT/CN2021/094642
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French (fr)
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张帆
吴永胜
林少军
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福建兆元光电有限公司
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Publication of WO2022174527A1 publication Critical patent/WO2022174527A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Definitions

  • the invention relates to the field of chip manufacturing, in particular to a chip epitaxial layer structure and a manufacturing method thereof.
  • RGB red, green, and blue
  • LEDs with both blue and green light sources are usually used in combination with other means, which can be realized on one LED chip, and there are three colors of RGB at the same time.
  • RGB red, green, and blue
  • LEDs with blue and green light sources require the growth of blue-green bi-color epitaxy.
  • blue-green bi-color epitaxy requires the growth of blue epitaxial layers and green epitaxial layers on a substrate.
  • electrode interfaces are respectively fabricated on the blue epitaxial layer and the green epitaxial layer by etching technology. Since the depth of the existing etching process cannot be precisely controlled, the epitaxial layer will inevitably be damaged.
  • the technical problem to be solved by the present invention is to provide a chip epitaxial layer structure and a manufacturing method thereof, so as to realize a chip epitaxial layer structure with a low degree of etching damage.
  • a chip epitaxial layer structure includes a substrate layer, a lower epitaxial layer, an upper epitaxial layer and an etching buffer layer;
  • the lower epitaxial layer is located at one end of the substrate layer, an end of the lower epitaxial layer away from the substrate layer is provided with the etching buffer layer, and an end of the etching buffer layer away from the substrate layer is provided with the etching buffer layer.
  • the etching rate of the etching buffer layer is lower than the etching rate of the upper epitaxial layer.
  • a method for manufacturing a chip epitaxial layer which can manufacture the above-mentioned chip epitaxial layer structure, comprising the steps of:
  • the beneficial effect of the present invention is that an etching buffer layer is added between the upper epitaxial layer and the lower epitaxial layer, and the etching rate of the etching buffer layer is lower than that of the upper epitaxial layer, that is, in the process of etching the upper epitaxial layer,
  • the wear rate of the etching buffer layer is lower than that of the upper epitaxial layer, so that it can protect the lower epitaxial layer during the etching process of the upper epitaxial layer. Even if the precision of the etching operation is low, it will only damage the etching buffer. layer without damaging the lower epitaxial layer, which ensures the color rendering effect of the LED chip.
  • the upper epitaxial layer and the lower epitaxial layer can be set with different colors to realize the manufacture of high-quality LED two-color chip epitaxial structure.
  • FIG. 1 is a schematic diagram of a chip epitaxial layer structure according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an etching buffer layer according to an embodiment of the present invention.
  • FIG. 3 is a method for manufacturing a chip epitaxial layer according to an embodiment of the present invention.
  • Substrate layer 2. The first N-type gallium nitride layer; 3. The first multilayer quantum well layer; 4. The first P-type gallium nitride layer; 5. The etching buffer layer; 6. The second N-type gallium nitride layer; 7. the second multilayer quantum well layer; 8. the second p-type gallium nitride layer.
  • a chip epitaxial layer structure includes a substrate layer, a lower epitaxial layer, an upper epitaxial layer and an etching buffer layer;
  • the lower epitaxial layer is located at one end of the substrate layer, an end of the lower epitaxial layer away from the substrate layer is provided with the etching buffer layer, and an end of the etching buffer layer away from the substrate layer is provided with the etching buffer layer.
  • the etching rate of the etching buffer layer is lower than the etching rate of the upper epitaxial layer.
  • the beneficial effect of the present invention is that an etching buffer layer is added between the upper epitaxial layer and the lower epitaxial layer, and the etching rate of the etching buffer layer is lower than that of the upper epitaxial layer, that is, the upper epitaxial layer is etched During the etching process, the wear rate of the etching buffer layer is lower than that of the upper epitaxial layer, thus protecting the lower epitaxial layer during the etching process of the upper epitaxial layer. Even if the precision of the etching operation is low, it will only The damage to the etching buffer layer will not damage the lower epitaxial layer, which ensures the color rendering effect of the LED chip.
  • the upper epitaxial layer and the lower epitaxial layer can be set to different colors to realize the manufacture of high-quality LED dual-color chip epitaxial structure.
  • the lower epitaxial layer includes a first N-type gallium nitride layer, a first multi-layer quantum well layer and a first P-type gallium nitride layer;
  • the first N-type gallium nitride layer, the first multilayer quantum well layer and the first P-type gallium nitride layer are sequentially arranged from an end close to the substrate layer to an end away from the substrate layer.
  • the lower epitaxial layer includes an N-type gallium nitride layer, a P-type gallium nitride layer and a quantum well layer, so as to realize the color rendering effect of the lower epitaxial layer.
  • the upper epitaxial layer includes a second N-type gallium nitride layer, a second multi-layer quantum well layer and a second P-type gallium nitride layer;
  • the second N-type gallium nitride layer, the second multilayer quantum well layer and the second P-type gallium nitride layer are sequentially arranged from an end close to the substrate layer to an end away from the substrate layer.
  • the upper epitaxial layer includes an N-type gallium nitride layer, a P-type gallium nitride layer and a quantum well layer, so as to realize the color rendering effect of the upper epitaxial layer.
  • the etching buffer layer is provided with an etching hole, and the depth of the etching hole is smaller than the thickness of the etching buffer layer.
  • an etching hole is arranged on the etching buffer layer, the etching hole does not penetrate the etching buffer layer, and a pit structure is formed above it, which ensures the growth quality of the upper epitaxial layer and makes the etching buffer layer.
  • the addition does not affect the growth of the upper buffer layer.
  • the thickness of the etching buffer layer is 2000-20000 angstroms.
  • the depth of the etching hole is 3800 angstroms, and the diameter of the etching hole is 1-10 microns.
  • the etching hole of this size is beneficial to the growth of the upper epitaxial layer while playing a protective role.
  • the etching buffer layer is SiO2 or Si2N4.
  • a method for manufacturing a chip epitaxial layer which can manufacture the above-mentioned chip epitaxial structure, including steps:
  • the first embodiment of the present invention is:
  • a chip epitaxial layer structure comprising a substrate layer 1, a lower epitaxial layer (composed of 2-4), an upper epitaxial layer (composed of 6-8) and an etching buffer layer 5;
  • the substrate layer 1 is sapphire
  • the lower epitaxial layer is located at one end of the substrate layer 1 , the end of the lower epitaxial layer away from the substrate layer 1 is provided with the etching buffer layer 5 , and the etching buffer layer 5 is away from the substrate layer 1 . one end is provided with the upper epitaxial layer;
  • the etching rate of the etching buffer layer 5 is lower than the etching rate of the upper epitaxial layer; the etching buffer layer 5 is provided with an etching hole, and the depth of the etching hole is smaller than that of the etching buffer thickness of layer 5;
  • the thickness x of the etching buffer layer 5 is 2000 ⁇ x ⁇ 20000 angstroms
  • the depth y of the etching hole is 2000 ⁇ y ⁇ 20000 angstroms
  • the diameter of the etching hole is 1-10 microns ;
  • the thickness of the etching buffer layer 5 is 4000 angstroms, the depth of the etching hole is 3800 angstroms, and the diameter of the etching hole is 3 microns;
  • a thickness of 4000 angstroms, a depth of 3800 angstroms and a diameter of 3 microns is a typical set of process parameters that are easily achieved at present;
  • the thickness of the etching buffer layer 5 is 2000 angstroms, the depth of the etching hole is 1900 angstroms, and the diameter of the etching hole is 1 micrometer;
  • the thickness of the etching buffer layer 5 is 20000 angstroms, the depth of the etching hole is 19900 angstroms, and the diameter of the etching hole is 10 microns;
  • the etching buffer layer 5 is SiO2 or Si2N4;
  • the lower epitaxial layer includes a first N-type gallium nitride layer 2, a first multilayer quantum well layer 3 and a first P-type gallium nitride layer 4; the first N-type gallium nitride layer 2, the first A multi-layer quantum well layer 3 and the first P-type gallium nitride layer 4 are sequentially arranged from the end close to the substrate layer 1 to the end far from the substrate layer 1;
  • the lower epitaxial layer is a green light-emitting film layer with a wavelength of 520 nanometers
  • the upper epitaxial layer includes a second N-type gallium nitride layer 6, a second multi-layer quantum well layer 7 and a second P-type gallium nitride layer 8; the second N-type gallium nitride layer 6, the second multiple The quantum well layer 7 and the second P-type gallium nitride layer 8 are sequentially arranged from the end close to the substrate layer 1 to the end far from the substrate layer 1;
  • the upper epitaxial layer is a blue light emitting film with a wavelength of 460 nm.
  • the second embodiment of the present invention is:
  • a method for manufacturing a chip epitaxial layer which can manufacture the chip epitaxial layer structure described in Embodiment 1, comprising the steps of:
  • ICP etching is used to etch the upper epitaxial layer according to a preset chip drawing
  • the wet etching includes acid etching and alkaline etching
  • the exposed etch buffer layer is removed using hydrogen fluoride.
  • the present invention provides a chip epitaxial layer structure and a manufacturing method thereof.
  • the double-layer epitaxial layer of a GaN luminescent material based on a sapphire substrate is generally a vertical stack, and the lower epitaxial layer is an epitaxial layer that emits green light.
  • the upper epitaxial layer is an epitaxial layer that emits blue light (the lower epitaxial layer and the upper epitaxial layer can exchange light-emitting colors with each other).
  • SiO2 or Si3N4 is used as a buffer layer.
  • the buffer layer is grown on the lower layer of GaN.
  • the material used in the buffer layer is a material that facilitates the continued growth of the upper layer of GaN.
  • patterned holes are made on the buffer layer, which is beneficial to obtain better crystal quality during the growth of the upper layer of GaN.
  • Epitaxial wafers using this structure can be used to process blue-green two-color integrated chips and further cooperate with phosphors or quantum dots to process full-color integrated LED chips, including full-color integrated Micro LED chips.
  • the ICP etching method is used. After the upper blue epitaxial layer is etched, the etching rate will slow down when encountering the SiO2 buffer layer. After ensuring that the upper GaN layer is etched cleanly, the SiO2 The buffer layer has not been completely consumed, ensuring the integrity of the underlying green GaN film.
  • the buffer layer can ensure a wide etching window for the integrated process, making the mass production of the process feasible.

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

本发明提供了一种芯片外延层结构及其制造方法，包括衬底层、下层外延层、上层外延层及刻蚀缓冲层；所述下层外延层位于所述衬底层一端，所述下层外延层远离所述衬底层的一端设置有所述刻蚀缓冲层，所述刻蚀缓冲层远离所述衬底层的一端设置有所述上层外延层；所述刻蚀缓冲层的刻蚀速率低于所述上层外延层的刻蚀速率；在上层外延层和下层外延层之间加入刻蚀缓冲层，且刻蚀缓冲层的刻蚀速率小于上层外延层，即在对上层外延层进行刻蚀的过程中，刻蚀缓冲层的磨损速度低于上层外延层，从而在对上层外延层的刻蚀过程中起到对下层外延层的保护作用。

Description

一种芯片外延层结构及其制造方法 技术领域
本发明涉及芯片制造领域，尤其涉及一种芯片外延层结构及其制造方法。
 背景技术
全彩色Micro LED需要RGB（红绿蓝）三种颜色的光源，在现有技术中，通常使用同时具备蓝绿光源的LED再组合以其他手段就可以实现在一颗LED芯片上，同时存在RGB三种颜色的可能性，不用分别生产多种LED芯片；而制备同时具备蓝绿光源的LED需要生长蓝绿双色外延，目前蓝绿双色外延需要在一片衬底上分别生长蓝色外延层及绿色外延层，再通过刻蚀技术在蓝色外延层层和绿色外延层上分别制作出电极接口，因现有的刻蚀工艺在深度上是不能精确控制的，因此必然会伤害到外延层。
 技术问题
本发明所要解决的技术问题是：提供一种芯片外延层结构及其制造方法，实现刻蚀损伤程度低的芯片外延层结构。
 技术解决方案
为了解决上述技术问题，本发明采用的一种技术方案为：
一种芯片外延层结构，包括衬底层、下层外延层、上层外延层及刻蚀缓冲层；
所述下层外延层位于所述衬底层一端，所述下层外延层远离所述衬底层的一端设置有所述刻蚀缓冲层，所述刻蚀缓冲层远离所述衬底层的一端设置有所述上层外延层；
所述刻蚀缓冲层的刻蚀速率低于所述上层外延层的刻蚀速率。
为了解决上述技术问题，本发明采用的另一种技术方案为：
一种芯片外延层制造方法，可制造上述的一种芯片外延层结构，包括步骤：
S1、在衬底层上生长下层外延层；
S2、在所述下层外延层上生长初始刻蚀缓冲层；
S3、在所述初始刻蚀缓冲层上刻蚀出刻蚀孔得到刻蚀缓冲层；
S4、在所述刻蚀缓冲层上生长上层外延层。
 有益效果
本发明的有益效果在于：在上层外延层和下层外延层之间加入刻蚀缓冲层，且刻蚀缓冲层的刻蚀速率小于上层外延层，即在对上层外延层进行刻蚀的过程中，刻蚀缓冲层的磨损速度低于上层外延层，从而在对上层外延层的刻蚀过程中起到对下层外延层的保护作用，即使刻蚀操作的精度低，也只会损伤到刻蚀缓冲层而不会损伤到下层外延层，保证了LED芯片的显色效果，上层外延层和下层外延层可设置不同的颜色，实现高质量的LED双色芯片外延结构的制造。
 附图说明
图1为本发明实施例的一种芯片外延层结构示意图；
图2为本发明实施例的一种刻蚀缓冲层结构示意图；
图3为本发明实施例的一种芯片外延层制造方法；
标号说明：
1、衬底层；2、第一N型氮化镓层；3、第一多层量子阱层；4、第一P型氮化镓层；5、刻蚀缓冲层；6、第二N型氮化镓层；7、第二多层量子阱层；8、第二P型氮化镓层。
 本发明的实施方式
为详细说明本发明的技术内容、所实现目的及效果，以下结合实施方式并配合附图予以说明。
请参照图1和图2，一种芯片外延层结构，包括衬底层、下层外延层、上层外延层及刻蚀缓冲层；
所述下层外延层位于所述衬底层一端，所述下层外延层远离所述衬底层的一端设置有所述刻蚀缓冲层，所述刻蚀缓冲层远离所述衬底层的一端设置有所述上层外延层；
所述刻蚀缓冲层的刻蚀速率低于所述上层外延层的刻蚀速率。
从上述描述可知，本发明的有益效果在于：在上层外延层和下层外延层之间加入刻蚀缓冲层，且刻蚀缓冲层的刻蚀速率小于上层外延层，即在对上层外延层进行刻蚀的过程中，刻蚀缓冲层的磨损速度低于上层外延层，从而在对上层外延层的刻蚀过程中起到对下层外延层的保护作用，即使刻蚀操作的精度低，也只会损伤到刻蚀缓冲层而不会损伤到下层外延层，保证了LED芯片的显色效果，上层外延层和下层外延层可设置不同的颜色，实现高质量的LED双色芯片外延结构的制造。
进一步地，所述下层外延层包括第一N型氮化镓层、第一多层量子阱层及第一P型氮化镓层；
所述第一N型氮化镓层、所述第一多层量子阱层及所述第一P型氮化镓层自靠近所述衬底层一端至远离所述衬底层一端依次排布。
由上述描述可知，下层外延层包括N型氮化镓层、P型氮化镓层及量子阱层，实现下层外延层的显色效果。
进一步地，所述上层外延层包括第二N型氮化镓层、第二多层量子阱层及第二P型氮化镓层；
所述第二N型氮化镓层、所述第二多层量子阱层及所述第二P型氮化镓层自靠近所述衬底层一端至远离所述衬底层一端依次排布。
由上述描述可知，上层外延层包括N型氮化镓层、P型氮化镓层及量子阱层，实现上层外延层的显色效果。
进一步地，刻蚀缓冲层上设置有刻蚀孔，所述刻蚀孔的深度小于所述刻蚀缓冲层的厚度。
由上述描述可知，在刻蚀缓冲层上设置刻蚀孔，刻蚀孔未穿透刻蚀缓冲层，在其上方形成凹坑结构，保证了上层外延层的生长质量，使得刻蚀缓冲层的加入不影响上层缓冲层的生长。
进一步地，刻蚀缓冲层的厚度为2000-20000埃。
由上述描述可知，设置刻蚀缓冲层的厚度为2000-20000埃，在实现对下层外延层的保护作用的同时，不会使得芯片整体过厚影响芯片实际使用。
进一步地，所述刻蚀孔的深度为3800埃，所述刻蚀孔的直径为1-10微米。
由上述描述可知，该尺寸的刻蚀孔在起到保护作用的同时，利于上层外延层的生长。
进一步地，所述刻蚀缓冲层为Si02或Si2N4。
由上述描述可知，使用Si02或Si2N4作为刻蚀缓冲层，材料成本较低，且易于生产；
请参照图3，一种芯片外延层制造方法，可以制造上述的一种芯片外延结构，包括步骤：
S1、在衬底层上生长下层外延层；
S2、在所述下层外延层上生长初始刻蚀缓冲层；
S3、在所述初始刻蚀缓冲层上刻蚀出刻蚀孔得到刻蚀缓冲层；
S4、在所述刻蚀缓冲层上生长上层外延层。
进一步地，所述S4之后还包括：
S5、根据预设的芯片图纸刻蚀所述上层外延层，直至接触到所述刻蚀缓冲层；
S6、通过湿法腐蚀去除暴露的所述刻蚀缓冲层。
请参照图1和图2，本发明的实施例一为：
一种芯片外延层结构，包括衬底层1、下层外延层（由2-4组成）、上层外延层（由6-8组成）及刻蚀缓冲层5；
在一种可选的试试方式中，所述衬底层1为蓝宝石；
所述下层外延层位于所述衬底层1一端，所述下层外延层远离所述衬底层1的一端设置有所述刻蚀缓冲层5，所述刻蚀缓冲层5远离所述衬底层1的一端设置有所述上层外延层；
所述刻蚀缓冲层5的刻蚀速率低于所述上层外延层的刻蚀速率；所述刻蚀缓冲层5上设置有刻蚀孔，所述刻蚀孔的深度小于所述刻蚀缓冲层5的厚度；
在一种可选的实施方式中，刻蚀缓冲层5的厚度x为2000≤x≤20000埃，刻蚀孔的深度y为2000＜y＜20000埃，刻蚀孔的直径为1-10微米；
在一种可选的实施方式中，刻蚀缓冲层5的厚度为4000埃，刻蚀孔的深度为3800埃，刻蚀孔的直径为3微米；
4000埃的厚度、3800埃的深度和3微米的直径是目前容易实现的一套典型工艺参数；
在一种可选的实施方式中，刻蚀缓冲层5的厚度为2000埃，刻蚀孔的深度为1900埃，刻蚀孔的直径为1微米；
在一种可选的实施方式中，刻蚀缓冲层5的厚度为20000埃，刻蚀孔的深度为19900埃，刻蚀孔的直径为10微米；
在一种可选的实施方式中，刻蚀缓冲层5为Si02或Si2N4；
其中，下层外延层包括第一N型氮化镓层2、第一多层量子阱层3及第一P型氮化镓层4；所述第一N型氮化镓层2、所述第一多层量子阱层3及所述第一P型氮化镓层4自靠近所述衬底层1一端至远离所述衬底层1一端依次排布；
在一种可选的实施方式中，下层外延层为波长520纳米的绿光发光膜层；
上层外延层包括第二N型氮化镓层6、第二多层量子阱层7及第二P型氮化镓层8；所述第二N型氮化镓层6、所述第二多层量子阱层7及所述第二P型氮化镓层8自靠近所述衬底层1一端至远离所述衬底层1一端依次排布；
在一种可选的实施方式中，上层外延层为波长460纳米的蓝光发光膜层。
请参照图3，本发明的实施例二为：
一种芯片外延层制造方法，可制造实施例一种所述的一种芯片外延层结构，包括步骤：
S1、在衬底层上生长下层外延层；
S2、在所述下层外延层上生长初始刻蚀缓冲层；
S3、在所述初始刻蚀缓冲层上刻蚀出刻蚀孔得到刻蚀缓冲层；
S4、在所述刻蚀缓冲层上生长上层外延层；
S5、根据预设的芯片图纸刻蚀所述上层外延层，直至接触到所述刻蚀缓冲层；
在一种可选的实施方式中，使用ICP刻蚀根据预设的芯片图纸刻蚀上层外延层；
S6、通过湿法腐蚀去除暴露的所述刻蚀缓冲层；
在一种可选的实施方式中，湿法腐蚀包括酸蚀及碱蚀；
在一种可选的实施方式中，使用氟化氢去除暴露的刻蚀缓冲层。
综上所述，本发明提供了一种芯片外延层结构及其制造方法，基于蓝宝石衬底的GaN发光材料，其双层外延一般为垂直叠层，下层外延层为发绿光的外延层，上层外延层为发蓝光的外延层（下层外延层和上层外延层可互相交换发光颜色），在两层外延层之间，使用SiO2或Si3N4作为缓冲层，缓冲层的特点是在ICP刻蚀的时候其刻蚀速率比GaN低，同时其可以被湿法腐蚀掉（酸蚀或碱蚀），此湿法腐蚀不会对GaN造成影响。这样在需要刻蚀掉上层GaN露出下层GaN的时候，利用缓冲层的刻蚀速率低的特点可以保证在上层GaN刻蚀干净时，缓冲层还没有消耗完，起到保护下层GaN的作用。在生长时，缓冲层生长在下层GaN的上面，缓冲层使用的材料是便于上层GaN继续生长的物质，同时在缓冲层上进行图形化开洞，有利于上层GaN生长时获得更好的晶体质量；使用此结构的外延片可用于加工蓝绿双色集成式芯片进一步再配合荧光粉或量子点的情况下可以加工全彩色集成式LED芯片，包含全彩色集成式Micro LED芯片。在芯片加工刻蚀时，使用ICP刻蚀方式，在将上层蓝色外延层刻蚀完成后，刻蚀速率会在遇到SiO2缓冲层时候慢下来，在保证上层GaN被刻蚀干净后，SiO2缓冲层还没有被完全消耗掉，保证了下层绿色GaN膜层的完好。此缓冲层可以保证集成工艺刻蚀窗口很宽，使此工艺的规模化生产成为可行。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等同变换，或直接或间接运用在相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种芯片外延层结构，其特征在于，包括衬底层、下层外延层、上层外延层及刻蚀缓冲层；
    所述下层外延层位于所述衬底层一端，所述下层外延层远离所述衬底层的一端设置有所述刻蚀缓冲层，所述刻蚀缓冲层远离所述衬底层的一端设置有所述上层外延层；
    所述刻蚀缓冲层的刻蚀速率低于所述上层外延层的刻蚀速率。
  2. 根据权利要求1所述的一种芯片外延层结构，其特征在于，所述下层外延层包括第一N型氮化镓层、第一多层量子阱层及第一P型氮化镓层；
    所述第一N型氮化镓层、所述第一多层量子阱层及所述第一P型氮化镓层自靠近所述衬底层一端至远离所述衬底层一端依次排布。
  3. 根据权利要求1所述的一种芯片外延层结构，其特征在于，所述上层外延层包括第二N型氮化镓层、第二多层量子阱层及第二P型氮化镓层；
    所述第二N型氮化镓层、所述第二多层量子阱层及所述第二P型氮化镓层自靠近所述衬底层一端至远离所述衬底层一端依次排布。
  4. 根据权利要求1所述的一种芯片外延层结构，其特征在于，所述刻蚀缓冲层上设置有刻蚀孔，所述刻蚀孔的深度小于所述刻蚀缓冲层的厚度。
  5. 根据权利要求1所述的一种芯片外延层结构，其特征在于，所述刻蚀缓冲层的厚度为2000-20000埃。
  6. 根据权利要求1所述的一种芯片外延层结构，其特征在于，所述下层外延层为波长520纳米的绿光发光膜层；
    所述上层外延层为波长460纳米的蓝光发光膜层。
  7. 根据权利要求4所述的一种芯片外延层结构，其特征在于，所述刻蚀孔的深度为2000-20000埃，所述刻蚀孔的直径为1-10微米；
    所述刻蚀缓冲层上设置有多个顺序排列的所述刻蚀孔。
  8. 根据权利要求1所述的一种芯片外延层结构，其特征在于，所述刻蚀缓冲层为Si02或Si2N4。
  9. 一种芯片外延层制造方法，可制造权利要求1-8任一所述的一种芯片外延层结构，其特征在于，包括步骤：
    S1、在衬底层上生长下层外延层；
    S2、在所述下层外延层上生长初始刻蚀缓冲层；
    S3、在所述初始刻蚀缓冲层上刻蚀出刻蚀孔得到刻蚀缓冲层；
    S4、在所述刻蚀缓冲层上生长上层外延层。
  10. 根据权利要求9所述的一种芯片外延层制造方法，其特征在于，所述S4之后还包括：
    S5、根据预设的芯片图纸刻蚀所述上层外延层，直至接触到所述刻蚀缓冲层；
    S6、通过湿法腐蚀去除暴露的所述刻蚀缓冲层。
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