WO2022174429A1 - 一种llc转换器、控制电路、软启动方法、装置及芯片 - Google Patents

一种llc转换器、控制电路、软启动方法、装置及芯片 Download PDF

Info

Publication number
WO2022174429A1
WO2022174429A1 PCT/CN2021/077115 CN2021077115W WO2022174429A1 WO 2022174429 A1 WO2022174429 A1 WO 2022174429A1 CN 2021077115 W CN2021077115 W CN 2021077115W WO 2022174429 A1 WO2022174429 A1 WO 2022174429A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
current
driving signal
logic
drive signal
Prior art date
Application number
PCT/CN2021/077115
Other languages
English (en)
French (fr)
Inventor
区寿松
蒋正东
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180093486.6A priority Critical patent/CN116848772A/zh
Priority to PCT/CN2021/077115 priority patent/WO2022174429A1/zh
Priority to EP21926147.6A priority patent/EP4280442A4/en
Publication of WO2022174429A1 publication Critical patent/WO2022174429A1/zh
Priority to US18/451,963 priority patent/US20230396176A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/01—Resonant DC/DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33571—Half-bridge at primary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33573—Full-bridge at primary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present application relates to the field of circuit technology, and in particular, to an LLC converter, a control circuit, a soft-start method, an apparatus, and a chip.
  • inductor-inductor-capacitor (inductor-inductor-capacitor, LLC) converter is a widely used DC/DC conversion circuit.
  • LLC converters Soft-switching techniques are easily implemented in LLC converters to reduce losses in power switches in the circuit.
  • LLC converters are easy to increase in frequency and reduce the volume of magnetic components, so LLC converters have the advantages of higher conversion efficiency and higher power density.
  • the frequency of the power switches in the LLC converter is close to the natural resonant frequency of the resonant tank, and the duty ratio of the driving signal of each power switch is close to 50%.
  • the LLC converter works in the start-up phase, it is required that the output capacitor voltage reach the output voltage smoothly in a short period of time, so as to quickly complete the start-up phase and avoid damage to the power switch.
  • the present application provides an LLC converter, a control circuit, a soft-start method, a device and a chip, which are used to reduce the start-up time of the LLC converter and avoid current impact in the resonance tank.
  • an embodiment of the present application provides an inductance-inductance-capacitor LLC converter, including: a control circuit 407, a switch circuit 402 and a resonance tank 403 coupled and connected in sequence, and the switch circuit includes a power switch; the The control circuit 407 is respectively coupled to the switch circuit 402 and the resonance tank 403; the control circuit 407 is used for: detecting the current of the resonance tank 403; generating a second driving signal according to the current and the first driving signal, The first drive signal is a pulse signal with a fixed frequency and a fixed duty cycle, the second drive signal is a pulse signal, and in the period when the current is greater than or equal to the current threshold, the second drive signal is a pre-pulse signal.
  • the second drive signal of the preset level is used to turn off the power switch in the switch circuit 402, and in the time period when the current is less than the current threshold, the second drive signal and the The first drive signal is the same; the second drive signal is output to the switch circuit 402 , and the second drive signal is used to drive the power switch in the switch circuit 402 .
  • the control circuit 407 can generate a second drive signal for driving the power switch in the switch circuit 402 according to whether the current in the resonant tank 403 exceeds the current threshold and the first drive signal.
  • the level of the second driving signal is a preset level for driving the power switch, which can make The power switch is turned off to avoid current surge in the resonant tank 403 and protect the components in the LLC converter.
  • the control circuit 407 can generate a second drive signal that is the same as the first drive signal, and the control circuit 407 uses the second drive signal that is the same as the first drive signal during the LLC resonant tank startup phase
  • the drive signal drives the power switch, so that the switch in the switch circuit 402 can be turned on for a long time, the output voltage can be quickly established, the start-up time of the LLC converter is shortened, and the start-up speed is improved.
  • the control circuit 407 can flexibly adjust the driving signal of the power switch according to the current in the resonant tank 403 , and avoid current impact in the resonant tank 403 by means of closed-loop control, so as to ensure the components of the LLC converter.
  • the control circuit 407 includes a current acquisition unit 407A, a logic signal generation unit 407B, a first drive signal generation unit 407C and a second drive signal generation unit 407D;
  • the current acquisition unit 407A is used for Detecting the current of the resonant tank 403;
  • the first driving signal generating unit 407C for generating the first driving signal;
  • the logic signal generating unit 407B for generating according to the current and the current threshold A logic signal, wherein the logic signal is a pulse signal, the current is less than the current threshold within the time corresponding to the width of the pulse in the logic signal, and the time interval between two adjacent pulses in the logic signal Inside, the current is greater than or equal to the current threshold;
  • the second driving signal generating unit 407D is configured to generate the second driving signal based on the logic signal and the first driving signal.
  • the second driving signal generating unit 407D is specifically used for:
  • the level of the logic signal is high during the time when the current is less than the current threshold If the current is equal to or greater than the current threshold, the level of the logic signal is a low level.
  • the second driving signal generating unit 407D in the control circuit 407 may generate the second driving signal by performing logical AND operation processing on the logic signal and the first driving signal.
  • the second driving signal generating unit 407 may be an analog signal circuit or a digital signal circuit, so that the driving process of the power switch in the switching circuit 402 by the control circuit 407 is easy to implement.
  • the logic signal is a pulse signal
  • the control circuit 407 further includes a delay unit 407E; the delay unit 407E is used to detect the rising edge or the falling edge of the pulse in the logic signal. At least one of the delays is delayed by a preset time period; the second driving signal generating unit 407D is further configured to: generate the second driving signal based on the delayed logic signal and the first driving signal.
  • the delay unit 407E in the control circuit 407 can perform delay processing on the logic signal, and can delay the start time of each pulse in the second driving signal, thereby realizing the conduction of the delay switch.
  • the fixed frequency is the resonance frequency corresponding to the resonance slot 403 .
  • the first driving signal is the resonant frequency corresponding to the resonant tank
  • the control circuit 407 can perform the same operation in the LLC startup phase and the steady-state phase.
  • the current in the resonant tank 403 is less than the current threshold, and the control circuit 407 generates the second drive signal which is the same as the first drive signal according to the current in the resonant tank 403 and the first drive signal.
  • an embodiment of the present application provides a control circuit, which is applied to drive an inductance-inductance-capacitor LLC converter.
  • the LLC converter includes a switch circuit 402 and a resonance tank 403.
  • the control circuit includes a current acquisition unit 407A, The logic signal generation unit 407B, the first drive signal generation unit 407C and the second drive signal generation unit 407D; the current acquisition unit 407A is used to detect the current of the resonance tank 403; the first drive signal generation unit 407C, with For generating a first driving signal, the first driving signal is a pulse signal with a fixed frequency and a fixed duty cycle; the logic signal generating unit 407B is used to generate a logic signal, wherein the logic signal is a pulse signal, and the During the time corresponding to the width of the pulse in the logic signal, the current is less than the current threshold, and in the time interval between two adjacent pulses in the logic signal, the current is greater than or equal to the current threshold; the The second driving signal generating unit 407D is
  • the second driving signal generating unit 407D is specifically configured to: perform logical AND operation processing on the logic signal and the first driving signal to obtain the second driving signal, wherein, When the current is less than the current threshold, the level of the logic signal is high, and when the current is greater than or equal to the current threshold, the logic signal is low.
  • the logic signal is a pulse signal
  • the control circuit 407 further includes a delay unit 407E;
  • the delay unit 407E is configured to delay at least one of the rising edge or the falling edge of the pulse in the logic signal by a preset time period
  • the second driving signal generating unit 407D is further configured to: generate the second driving signal based on the delayed logic signal and the first driving signal.
  • the fixed frequency is the resonance frequency corresponding to the resonance slot 403 .
  • the logic signal generating unit 407B includes a comparator, the first input of the comparator is connected to the output of the current acquisition unit 407A, and the second input of the comparator is connected A fixed level, the fixed level is a level corresponding to the current threshold, and the output end of the comparator is connected to the second driving signal generating power supply 407D, or is connected to the delay unit 407E.
  • an embodiment of the present application provides a soft-start method for an inductance-inductance-capacitor LLC converter, the LLC converter includes a resonant tank and a switch circuit, and the method includes: detecting the current of the resonant tank; The current and the first drive signal generate a second drive signal, the first drive signal is a pulse signal with a fixed frequency and a fixed duty cycle, the second drive signal is a pulse signal, when the current is greater than or equal to the current threshold During the period of time, the second drive signal is at a preset level, and the second drive signal of the preset level is used to turn off the power switch in the switch circuit, and when the current is less than the current threshold During the time period, the second drive signal is the same as the first drive signal; the second drive signal is output to the switch circuit, and the second drive signal is used to drive the power switch in the switch circuit .
  • the method before the generating the second driving signal according to the current and the first driving signal, the method further includes: generating a logic signal according to the current and the current threshold, wherein the The logic signal is a pulse signal. During the time corresponding to the width of the pulse in the logic signal, the current is less than the current threshold, and within the time interval between two adjacent pulses in the logic signal, the current is greater than or equal to the current threshold.
  • the generating the second drive signal according to the current and the first drive signal includes: performing a logical AND operation on the logic signal and the first drive signal to obtain the second drive signal, wherein the current During the time less than the current threshold value, the level of the logic signal is at the high level, and during the time when the current is greater than or equal to the current threshold value, the level of the logic signal is at the low level.
  • the logic signal is a pulse signal; before generating the first driving signal according to the current and the second driving signal, the method further includes: increasing the pulse in the logic signal At least one of the edge or the falling edge is delayed by a preset time period.
  • the fixed frequency is a resonance frequency corresponding to the resonance slot.
  • embodiments of the present application provide an inductance-inductance-capacitor LLC converter control device, the device includes a processor and a memory, the memory is used for storing programs, instructions or codes, and the processor is used for executing all the The program, instruction or code in the memory is used to complete the method according to any one of the third aspect and any possible designs thereof.
  • an embodiment of the present application provides an inductance-inductance-capacitor LLC converter control device, the device includes an acquisition module, a processor, and a memory.
  • the acquisition module is used to detect the current of the resonant tank;
  • the memory is used to store programs, instructions or codes, and the processor is used to execute the programs, instructions or codes in the memory, and execute the program according to the current and the first code.
  • a driving signal generates a second driving signal
  • the first driving signal is a pulse signal with a fixed frequency and a fixed duty cycle
  • the second driving signal is a pulse signal
  • the second drive signal is a preset level
  • the second drive signal of the preset level is used to turn off the power switch in the switch circuit, within the time period when the current is less than the current threshold , the second drive signal is the same as the first drive signal;
  • the second drive signal is output to the switch circuit, and the second drive signal is used to drive the power switch in the switch circuit.
  • the processor is further configured to: before generating the second driving signal according to the current and the first driving signal, generate a logic signal according to the current and the current threshold, wherein , the logic signal is a pulse signal, the current is less than the current threshold within the time corresponding to the width of the pulse in the logic signal, and within the time interval between two adjacent pulses in the logic signal, the The current is greater than or equal to the current threshold; when the processor generates a second drive signal according to the current and the first drive signal, the processor is specifically configured to: perform logical AND operation processing on the logic signal and the first drive signal , to obtain the second drive signal, wherein, within the time when the current is less than the current threshold, the level of the logic signal is a high level, and within the time when the current is greater than or equal to the current threshold, the The level of the logic signal is low.
  • the logic signal is a pulse signal; and the processor is further configured to, before generating the first drive signal according to the current and the second drive signal, perform a change in the pulse signal in the logic signal. At least one of the rising edge or the falling edge is delayed by a preset time period.
  • the fixed frequency is a resonance frequency corresponding to the resonance slot.
  • embodiments of the present application provide a non-volatile computer-readable storage medium for storing a computer program, the computer program is loaded by a processor to execute the third aspect and any possible designs thereof. any of the methods described.
  • an embodiment of the present application provides a chip, which can be coupled with a memory for invoking and executing computer program instructions stored in the memory, so as to make the device as described in the third aspect and any possible design thereof. The described method is executed.
  • the chip includes at least one memory, and computer program instructions stored in the at least one memory enable the chip to execute any of the third aspect and any of its possible designs. method described.
  • 1 is a schematic diagram of a circuit structure of an LLC converter
  • Fig. 2 is the schematic diagram of the switching frequency and gain curve of LLC converter
  • FIG. 3 is a schematic diagram of the resonant tank current, the voltage of the resonant capacitor, and the voltage of the output capacitor;
  • Fig. 4 is a kind of LLC converter structural representation
  • Fig. 5 is a kind of LLC converter structural representation
  • FIG. 6 is a schematic diagram of a drive signal of a switch
  • Fig. 7 is a kind of LLC converter structural representation
  • FIG. 8 is a schematic diagram of a delay processing process
  • FIG. 9 is a schematic diagram of a drive signal of a switch
  • FIG. 10 is a schematic diagram of a drive signal of a switch
  • FIG. 11 is a schematic diagram of a delay processing process
  • FIG. 13 is a schematic structural diagram of an LLC converter
  • 15 is a schematic flowchart of a soft-start method for an LLC converter
  • 16 is a schematic diagram of a control flow of a soft-start method for an LLC converter
  • 17 is a schematic diagram of the resonant tank current, the voltage of the resonant capacitor, and the voltage of the output capacitor in the startup phase;
  • FIG. 18 is a schematic diagram of the resonant tank current, the voltage of the resonant capacitor, and the voltage of the output capacitor in the startup phase;
  • FIG. 19 is a schematic diagram of the drive signal of the switch in the startup phase of the LLC converter.
  • 20 is a schematic diagram of the resonant tank current, the voltage of the resonant capacitor, and the voltage of the output capacitor in the steady state stage;
  • FIG. 21 is a schematic diagram of the driving signal of the switch in the steady state stage of the LLC converter
  • FIG. 22 is a schematic structural diagram of an LLC converter control device.
  • LLC converters include resonant inductors, resonant capacitors and excitation inductors, which have good soft-switching characteristics, which can greatly reduce switching losses and improve energy transmission efficiency. It is one of the more commonly used power topologies.
  • the power switching frequency in the LLC converter is close to the natural frequency of the resonant tank.
  • the duty cycle of the signal driving each power switch is close to 50%.
  • the driving mode of each power switch in the start-up stage is different from the power switch in the steady-state stage If the driving method is the same, when the LLC converter is in the startup phase, the current in the resonant tank will be very large, which will easily exceed the current range that the power switch can withstand, resulting in damage to the power switch.
  • the LLC converter includes an input source Vin and a switch circuit 102 , a resonance tank 103 , a conversion circuit 104 , a rectifier circuit 105 and an output circuit 106 connected in sequence.
  • the switch circuit 102 includes a power switch S1 and a power switch S2 connected in series.
  • the power switch S1 and the power switch S2 are connected in series between the two poles of the input source Vin.
  • the resonant tank 103 includes a resonant capacitor Cr, a resonant inductance Lr, and an excitation inductance Lp that are connected in series in sequence.
  • the conversion circuit 104 includes a primary winding Pr, a transformer Tr and a secondary winding Sr coupled in sequence.
  • the primary winding Pr is connected in parallel with the excitation inductance Lp.
  • the secondary winding Sr includes a first winding Sr1 and a second winding Sr2 connected in series.
  • the rectifier circuit 105 includes two diodes, denoted as diode D1 and diode D2, respectively.
  • the output circuit 106 includes an output capacitor C1.
  • the cathode of the diode D1 and the cathode of the diode D2 are connected to the first end of the output capacitor C1, and the second end of the output capacitor C1 is connected to the connection point between the first winding Sr1 and the second winding Sr2.
  • One end of the first winding Sr1 not connected to the second winding Sr2 is connected to the anode of the diode D1, and one end of the second winding Sr2 not connected to the first winding Sr1 is connected to the anode of the diode D2.
  • the load 107 is connected in parallel with the output capacitor C1.
  • the output voltage of the output capacitor C1 is denoted as Vout.
  • the LLC converter can convert the voltage provided by the input source Vin to the output voltage Vou and provide it to the electrical load 107.
  • the switching frequency and gain curves of LLC converters with different loads are shown in Figure 2.
  • the physical quantity on the horizontal axis represents the ratio of the switching frequency fs to the resonant frequency fo (denoted as fn), and the physical quantity on the vertical axis represents the output gain.
  • Figure 2 shows the curves of 7 kinds of loads (the curves L1 to L7 in the figure represent the corresponding curves of the 7 kinds of loads respectively).
  • the curve gains of all the loads reach the maximum, and the LLC converter
  • Each power switch (such as the power switch S1 and the power switch S2 in FIG. 1 ) can be driven at the switching frequency fo, so that the LLC converter is in a steady state stage.
  • the resonant frequency fo is a fixed value, so the larger the switching frequency fs, the smaller the output gain.
  • the related art is based on this characteristic.
  • a high-frequency driving signal is applied to the power switch S1 and the power switch S2, that is, a larger switching frequency fs is used to control the two powers. switch.
  • the output gain corresponding to a larger switching frequency fs is small, so that the energy provided by the input source Vin is slowly input into the resonant tank to limit the current in the resonant tank. After the energy is slowly input into the resonant tank, it is slowly input into the output capacitor C1 through components such as the converter.
  • the switching frequency fs is gradually reduced, for example, to the resonant frequency fo, to ensure the maximum output gain of the output capacitor C1, so that the LLC converter ends the startup phase and enters the steady-state phase.
  • the voltage of the resonant capacitor Cr The variation of VCr and the variation of the output voltage Vo of the output capacitor C1 are shown in FIG. 3 .
  • the output voltage Vo of the output capacitor C1 increases slowly to the maximum output voltage, but during this period, a current surge still occurs in the resonant tank, as shown in the elliptical dotted box area in Figure 3 . To avoid the current impact, it is necessary to increase the switching frequency fs.
  • embodiments of the present application provide an LLC converter and a soft-start method, device, and medium for the LLC converter. Applied to LLC converters, it can reduce or avoid current impact in the resonant tank, shorten the start-up time, and improve the soft-start speed, thereby ensuring circuit safety.
  • an embodiment of the present application provides an LLC converter.
  • the LLC converter may include a switch circuit 402 , a resonance tank 403 and a control circuit 407 .
  • the control circuit 407 is coupled with the switch circuit 402
  • the control circuit 407 is coupled with the resonance tank 403 .
  • the resonance tank 403 includes at least a resonance capacitor Cr and a resonance inductance Lr connected in series.
  • the resonant tank 403 can make the power switch in the switch circuit 402 work in a soft switching state.
  • the LLC converter provided in the embodiment of the present application is applied to a relatively wide range of LLC converters or LLC circuits.
  • the LLC converter may further include a conversion circuit 404 connected to the resonant tank 403, and the conversion circuit 404 may be used for voltage conversion, current conversion, isolation, voltage regulation, and other purposes.
  • the LLC converter may also include a rectifier circuit 405 connected to the conversion circuit 404 .
  • the rectifier circuit 405 may be connected to the output circuit 406 .
  • the rectifier circuit 405 converts the alternating current provided by the conversion circuit into a direct current, and supplies it to the output circuit 406 .
  • the output circuit 406 may include an output capacitor, and the load may be connected in parallel with the output capacitor.
  • the LLC converter can convert the first voltage provided by the first power supply 401 and provide the converted second voltage to the load.
  • the control circuit 407 can detect the current in the resonant tank 403 .
  • the control circuit 407 can generate a second drive signal according to the current and the first drive signal, and then output the second drive signal to the switch circuit 402, where the second drive signal is used to drive the switch circuit 402. power switch.
  • the first driving signal may be a pulse signal with a fixed frequency and a fixed duty cycle.
  • the second driving signal is a pulse signal.
  • the second driving signal is a preset level, and the second driving signal of the preset level is For turning off the power switch in the switch circuit 402 , the second driving signal is the same as the first driving signal during the time period when the current in the resonant tank 403 is less than the current threshold in the resonant tank 403 .
  • the power switch in the switch circuit 402 may be driven by the first level signal, so that the power switch is in a conducting state, that is, the first level signal may be used to turn on the power switch.
  • the power switch is driven by the second level signal, so that the power switch is in an off state, that is, the second level signal can be used to turn off the power switch.
  • the first level can be a high level
  • the second level can be a low level, that is, a high-level signal can drive the power switch to be in an on state
  • a low-level signal can drive the power switch to be in an open state (off) state.
  • the first level can be a low level
  • the second level can be a high level, that is, a low-level signal can drive the switch to be in an on state
  • a high-level signal can drive the power switch to be in an off state.
  • the first level signal is high level and can be used to drive the power switch to be in an on state
  • the second level signal is low level and can be used to drive the power switch to an off state as an example. That is, the preset level is the second level as an example for introduction.
  • the control circuit 407 can generate a second driving signal for driving the power switch in the switching circuit 402 according to whether the current in the resonant tank 403 exceeds the current threshold and the condition of the first driving signal.
  • the second driving signal is at the second level, and the power switch can be driven to turn off to avoid the resonant tank.
  • a current surge occurs in 403 to protect the components in the LLC converter.
  • the second driving signal may be the same as the first driving signal, that is, if the first driving signal is at the second level, the second driving signal is also at the second level , if the first driving signal is at the first level, the second driving signal is also at the first level.
  • control circuit 407 may generate the second drive signal at the first level according to the fact that the first drive signal is at the first level and the current in the resonant tank 403 is less than the current threshold.
  • the control circuit 407 can generate the second drive signal at the second level when the first drive signal is at the first level and the current in the resonance tank 403 is greater than or equal to the current threshold.
  • the control circuit 407 may generate the second driving signal to be the second level according to the first driving signal being the second level. It can be seen that the second driving signal is a pulse signal, and in the period corresponding to the pulse width when the current is less than the current threshold, the amplitude of the pulse can be the first level, and the current is greater than or equal to the current threshold.
  • the second driving signal is at a low level.
  • control circuit 407 can perform the foregoing operations for both the driving manner of the LLC converter in the startup phase and the driving manner in the steady state phase.
  • the control circuit 407 may generate the first drive signal according to a fixed frequency and a fixed duty cycle, so that the first drive signal is a pulse signal with a fixed frequency and a fixed duty cycle, the amplitude of the pulse is the first level, and the phase The level between two adjacent pulses is the second level.
  • the first drive signal may be used to drive the power switches in the switching circuit 402 during the steady state phase.
  • the switch circuit 402 may include a plurality of power switches, and the control circuit 407 may generate a first driving signal corresponding to each switch.
  • the corresponding first driving signals of each switch are different, for example, the turn-on times of the first driving signals corresponding to each switch are different, or the first driving signals corresponding to each switch are out of phase.
  • the fixed frequency corresponding to the first driving signal may be the resonance frequency corresponding to the resonance slot 403 . If the switch circuit 402 includes two switches connected in series, the duty cycle of the first driving signal may be 50%.
  • the control circuit 407 may apply the first drive signal to the switch circuit 402 . If the current in the resonance tank 403 is greater than the current threshold, the control circuit 407 can generate a second driving signal according to the current in the resonance tank 403 and the first driving signal, and the first level pulse in the second driving signal In the time period corresponding to the width, the current of the resonant tank 403 is less than the current threshold and the level of the first driving signal is the first level, at the time corresponding to the pulse width of the second level of the second driving signal In the segment, the current of the resonant tank 403 is greater than or equal to the current threshold or the level of the first driving signal is the second level.
  • the control circuit 407 can be implemented in various ways or circuits to generate the second driving signal with the aforementioned characteristics.
  • the control circuit 407 can make the switch in an off state according to the time period corresponding to the current of the resonance tank 403 being greater than or equal to the current threshold, and the level of the second driving signal is the second level.
  • Such a design can make the switch in the switch circuit 402 turn on for less time, reduce the current flowing into the resonant tank 403, avoid current impact in the resonant tank 403, and protect the components in the LLC converter.
  • the control circuit 407 may generate the second driving signal with the same level as the first driving signal according to the current in the resonance tank 403 being less than the current threshold.
  • the control circuit 407 If the level of the first drive signal is at the first level and the current in the resonant tank 403 is less than the current threshold, the control circuit 407 generates the second drive signal at the first level, and applies the second drive signal to the switch circuit 402 In the above, the on-time of the switch in the switch circuit 402 can be made longer, so that the output circuit 406 can quickly establish the output voltage, shorten the start-up time of the LLC converter, and improve the start-up speed.
  • the control circuit 407 may include a current collecting unit 407A, a logic signal generating unit 407B, a first driving signal generating unit 407C and a second driving signal generating unit 407D.
  • the current acquisition unit 407A is coupled to the resonant tank 403, and the current acquisition unit 407A can acquire the current iLr in the resonant tank 403, and transmit the acquired current to the logic signal generation unit 407B.
  • the current collection unit 407A may collect the current iLr in the resonance tank 403 in real time.
  • the logic signal generating unit 407B may generate the logic signal Sr based on the current threshold Imax and the current iLr of the resonance tank 407B, and transmit the generated logic signal Sr to the second driving signal generating unit 407D.
  • the logic signal generating unit 407B may perform overcurrent detection on the current iLr in the resonance tank 403 . If the current iLr is greater than the current threshold Imax, a signal with an amplitude of a third voltage is generated. If the current iLr is less than or equal to the current threshold value Imax, a signal having an amplitude of a fourth voltage is generated.
  • the third voltage is at a low level, and the fourth voltage is at a high level. In this embodiment of the present application, a low level may be represented by 0, and a high level may be represented by 1. It can be seen that the signal generated by the logic signal generating unit 407B is a pulse signal.
  • the current in the resonant tank 403 is less than the current threshold, and in the time interval between two adjacent pulses, the current in the resonant tank 403 greater than or equal to the current threshold.
  • the current collecting unit 407A can collect the current iLr in the resonance tank 403 in real time, and transmit the current iLr to the logic signal generating unit 407B. Therefore, the logic signal generating unit 407B can also perform overcurrent detection on the current iLr in real time, and generate a logic signal that can characterize whether there is an overcurrent.
  • the logic signal generated by the logic signal generating unit 407B may be a signal whose amplitude is the third voltage, and the duration of the signal is the first duration. If the duration of the current iLr less than or equal to the current threshold Imax is the second duration, the logic signal generated by the logic signal generating unit 407B may be a signal with an amplitude of the fourth voltage, and the duration of the signal is the second duration.
  • the third voltage may be 0, the fourth voltage may be 1, and the signal generated by the logic signal generating unit 407B may be regarded as a logic signal.
  • the first drive signal generation unit 407C may generate a first drive signal S1 (a drive signal for each switch in the LLC converter steady state phase), and provide the first drive signal S1 to the second drive signal generation unit 407D.
  • the switching frequency fs corresponding to the first driving signal S1 may be equal to the resonant frequency fo.
  • the first driving signal generating unit 407C may generate a corresponding first driving signal for each switch in the switch circuit 402 .
  • the first driving signal S1 generated by the first driving signal generating unit 407C can be used as a signal for driving each switch in the steady state stage of the LLC converter.
  • the first driving signal generating unit 407C may generate the corresponding driving signals for each switch according to the preset switching frequency fs and the preset duty cycle.
  • the preset switching frequency fs may be the same as the resonant frequency fo.
  • the switching frequency fs may be 10 Hz. If the switch circuit 402 includes two switches, the preset duty cycle may be 50%.
  • the first driving signal generated by the first driving signal generating unit 407C is a signal with a fixed frequency and a fixed duty cycle, and can be used to drive switches in the switching circuit 402 in a steady state stage.
  • the control circuit 407 may transmit the first driving signal generated by the first driving signal generating unit 407C to the switch circuit 402 to drive the switch, or may transmit the first driving signal generated by the second driving signal generating unit 407D to the switch circuit 402 . Two driving signals are transmitted to the switch circuit 402 to drive the switch.
  • the second driving signal generating unit 407D may generate the second driving signal S2 based on the logic signal Sr and the first driving signal S1. Then, the second driving signal S2 is sent to each switch in the switch circuit 402 to drive each switch.
  • the second driving signal generating unit 407D may have the function of a logical AND (AND) operation.
  • the second driving signal generating unit 407D may include a logic gate circuit, such as an AND gate circuit, or a logic AND gate circuit.
  • the logic AND gate circuit can realize the function of logic AND in digital logic. If there is at most one high level input to the logic AND gate circuit, the logic AND gate circuit outputs a low level.
  • the signal input to the logical AND gate circuit may also be regarded as a signal received by the logical AND gate circuit.
  • 1 means high level and 0 means low level.
  • the input signal of the logic AND gate circuit is 1, then the output signal of the logic AND gate circuit is 1.
  • the input logic AND gate circuit signal includes 0 and 1, then the output signal of the logic AND gate circuit is 0.
  • the input signal of the logic AND gate circuit is 0, then the output signal of the logic AND gate circuit is 0.
  • the second driving signal generating unit 407D may use the result of performing a logical AND (AND) operation on the low-level logic signal Sr and the first driving signal S1 as the second driving signal S2, that is, the second driving signal S2 is the amplitude is a low level signal.
  • the second driving signal generating unit 407D when the first driving signal generating unit 407C generates the first driving signal S1 for driving the switch to be in an on state (that is, the level of the first driving signal S1 is a high level), if For the low level signal of the logic signal Sr generated by the logic signal generating unit 407B, the second driving signal generating unit 407D can generate the second driving signal S2 with a low level.
  • the second driving signal generating unit 407D may perform a logical AND (AND) operation on the driving signal S2 generated by the first driving signal generating unit 407C and the logic signal Sr generated by the logic signal generating unit 407B to obtain the second driving signal S2 .
  • the switch circuit 402 includes multiple switches, and the second driving signal generating unit 407D may include the same number of logic AND gate circuits as the multiple switches.
  • Multiple switches and multiple logical AND gate circuits can be in one-to-one correspondence, and each logical AND gate circuit can receive the logical signal Sr generated by the logical signal generating unit 407B and the first driving signal generated by the first driving signal generating unit 407C to convert the corresponding switch. S1, and based on the two received signals, a second drive signal S2 of the corresponding switch is generated.
  • the second driving signal generating unit 407D may not The first driving signal S1 generated by the first driving signal generating unit 407C is adjusted or the second driving signal generating unit 407D may stop generating the second driving signal S2.
  • the second driving signal S2 generated by the second driving signal generating unit 407D may be the same as the first driving signal S1, that is, the generated second driving signal S2 is at a low level, which may be used to drive the switch to be in an open state.
  • the second driving signal generating unit 407D may use the result of performing a logical AND (AND) operation on the logic signal Sr and the low-level first driving signal S1 as the second driving signal S2, that is, the generated second driving signal S2
  • the amplitude is low level.
  • the second driving signal generating unit 407D may generate the second driving signal S2 according to the logic signal Sr provided in real time by the logic signal generating unit 407B and the first driving signal S1 provided in real time by the first driving signal generating unit 407C, The generated second driving signal S2 is transmitted to the switches in the switch circuit 402 to drive the switches.
  • the second driving signal generating unit 407D may use the result of performing a logical AND (AND) operation on the logic signal Sr and the first driving signal S1 as the second driving signal S2.
  • the control circuit 407 can detect the current in the resonant tank 403 and adjust the driving signal applied to the switch circuit 402 according to whether the current is greater than the current threshold, so as to flexibly adjust the driving according to the current in the resonant tank 403 Signal, through the closed-loop control method, avoid the current impact in the resonance tank 403, and protect the components of the LLC converter.
  • the second driving signal generating unit 407D uses the logic signal Sr of a low level and the first driving signal S1 of a high level to generate a second driving signal S2 of a low level to drive the switch, which can shorten the length of the switch. Continuous on time.
  • the control circuit 407 can adjust the driving mode of the switching circuit 402 from applying a driving signal with a constant frequency and a constant duty cycle to applying a driving signal based on the resonant tank 403 A drive signal method with a non-constant frequency and non-constant duty cycle generated by the current greater than the current threshold for a continuous period of time.
  • the switch circuit 402 including two switches can be denoted as switch K1 and switch K2, respectively.
  • the first driving signal generated by the first driving signal generating unit 407C is denoted as K1-S1 corresponding to the first driving signal generated by the switch K1
  • the first driving signal corresponding to the generated switch K2 is denoted as K2-S1.
  • the duty cycle of switch K1 and switch K2 is 50%. Both switches can be driven high in an on state and driven low in an off state.
  • the low level corresponds to the third voltage
  • the high level corresponds to the fourth voltage
  • the logic signal Sr may include a signal having an amplitude of the third voltage and a continuous signal having an amplitude of the fourth voltage.
  • the second driving signal K1-S2 of the switch K1 can be obtained, as shown in the third row of waveforms in FIG. 6 .
  • the amplitude of the waveform marked with oblique lines is a high level, and this signal can drive the switch K1 to be in a conducting state.
  • the signal between the two slashed waveforms is low, which drives switch K1 in an open state.
  • a driving cycle of the switch K1 includes a high-level signal in the first half of the cycle, which can make the switch K1 in a conductive state, that is, the first half of a driving cycle is a conductive cycle, then the second half of a driving cycle
  • the period is the off period (or off period).
  • the second drive signal K1-S2 in the second half of a drive cycle is at a low level, which can make the switch K1 in an open state.
  • the logic signal Sr generated by the logic signal generating unit 407B may include multiple amplitudes with a third level signal and a plurality of signals whose amplitude is the fourth level.
  • the logic signal generating unit 407B can perform a logical AND (AND) operation on the low-level logic signal Sr and the high-level first driving signals K1-S1 to generate a low-level first drive signal K1-S1.
  • the two driving signals K1-S2 are implemented to turn off the switch in the switching circuit when the current overcurrent occurs in the resonant tank 403 , so as to avoid current impact in the resonant tank 403 .
  • the logic signal generating unit 407B may perform a logical AND (AND) operation on the high-level logic signal Sr and the high-level first driving signals K1-S1, and then generate the high-level second driving signals K1-S2 to realize the resonance.
  • the switches in the switch circuit are turned on when no current overcurrent occurs in the slot 403 .
  • a driving cycle of the switch K1 is used as a reference to describe the relationship among the logic signal Sr, the first driving signal K1-S1, and the second driving signal K1-S2, and is not used as a second driving signal generating unit 407D processing cycle limitation.
  • the second driving signal generating unit 407D may perform a logical AND (AND) operation on the logic signal Sr and the first driving signals K1-S1 in real time to generate the second driving signals K1-S2.
  • the control circuit 407 may further include a delay unit 407E.
  • the delay unit 407E may be connected between the logic signal generating unit 407B and the second driving signal generating unit 407D.
  • the delay unit 407E is configured to generate a delay logic signal Sd based on the logic signal Sr generated by the logic signal generation unit 407B.
  • the delay unit 407E provides the generated delay logic signal Sdr to the second drive signal generation unit 407D.
  • the second driving signal generating unit 407D may generate the second driving signal S2 according to the delayed logic signal Sd and the first driving signal S1 generated by the first driving signal generating unit 407C.
  • the delay unit 407E may perform delay processing on the logic signal Sr generated by the logic signal generation unit 407B.
  • the delay unit 407E when the delay unit 407E can perform delay processing on the logic signal Sr, after receiving the logic signal Sr, the delay unit 407E can provide the received logic signal Sr to the first delay time t1 after the first delay time t1.
  • Two driving signal generating units 407D as shown in FIG. 8 .
  • the signal sent by the delay unit 407E and provided to the signal adjustment unit 407 is denoted as the delay logic signal Sdr.
  • the second driving signal generating unit 407D generates the second driving signal S2 according to the delayed logic signal Sdr and the first driving signal S1 generated by the first driving signal generating unit 407C.
  • the signal adjustment unit 407 may perform a logical AND (AND) operation on the delayed logic signal Sdr and the driving signal S1 to obtain the second driving signal S2*.
  • the delay unit 407E adjusts the first driving signal S1 generated by the first driving signal generating unit 407C according to the logic signal Sr to generate the second driving signals K1-S2.
  • the second driving signal generating unit 407D adjusts the first driving signal S1 generated by the first driving signal generating unit 407C according to the delayed logic signal Sdr to generate the second driving signals K1-S2*.
  • the first driving signal K1-S1 generated by the first driving signal generating unit 407C is used to drive the switch K1 in the period corresponding to the ON state (the period corresponding to the high-level signal), that is, the first driving signal K1-S1 in FIG. 9 .
  • the delay logic signal Sdr is delayed by the first delay time t1
  • the on-time of each switch is delayed by the first delay time t1.
  • the start time when the switch is turned on is also delayed by the first delay time t1.
  • the delayed logic signal Sdr is a signal generated by delaying the logic signal Sr for a first delay time period t1. Therefore, in the second drive signal S2 generated by the second drive signal generating unit 407D, the start timing of the high-level signal is delayed, and the turn-on timing of each switch can be delayed. Delaying the turn-on time of each switch can delay the time of the energy provided by the first power supply 401 , reducing the energy entering the resonant tank 403 and reducing the current in the resonant tank 403 .
  • the second driving signal generating unit 407D generates the total duration corresponding to the high level in the second driving signal S2 according to the delay logic signal Sdr and the first driving signal S1 generated by the first driving signal generating unit 407C. smaller, further shortening the on-time of each switch. As shown in FIG. 10 , after the delay unit 407E performs delay processing on the logic signal Sr, the portion of the low-level logic signal Sr falling within the period corresponding to the high-level signal in the first driving signals K1-S1 is reduced.
  • the second driving signal generating unit 407D performs a logical AND (AND) operation on the delayed logic signal Sdr and the first driving signals K1-S1 generated by the first driving signal generating unit 407C, the generated second driving signals K1-S2 *In the middle, the duration of the high-level signal is reduced, the duration of the switch K1 being on is shortened, and the duration of the switch K1 being off is increased.
  • the logic signal Sr may include a pulse signal
  • the delay unit 407E performs delay processing on the logic signal Sr, and when generating the delayed logic signal Sdr, it may detect the rising edge or the falling edge of the pulse in the logic signal. at least one lag preset duration.
  • the delay processing process for the rising edge of the pulse signal may be independent from the delay processing process for the falling edge of the pulse signal.
  • the delay unit 407E may delay the rising edge of the pulse signal in the logic signal Sr by the first delay time period t1 to generate the delayed logic signal Sdr.
  • the delay unit 407E may also delay the falling edge of the pulse signal in the logic signal Sr by a second delay time period t2 to generate the delayed logic signal Sdr.
  • the delay unit 407E may further delay the rising edge of the pulse signal in the logic signal Sr by a first delay time period t1, and delay the falling edge by a second delay time period t2.
  • the delay unit 407E can delay the rising edge of the signal Sr with the amplitude of the third voltage by a first delay time t1, and delay the falling edge of the logic signal Sr by a second delay duration t2.
  • the duration of the signal Sr whose amplitude is the third voltage is d1.
  • the falling edge delay duration is greater than the rising edge delay duration
  • the duration of the low-level signal will become longer
  • the duration d2 of the delay logic signal Sdr generated by the delay unit 407E may be greater than the amplitude.
  • a signal with an amplitude of the fourth voltage is between the two signals with the amplitude of the third voltage.
  • the duration of the logic signal with the amplitude of the fourth voltage will decrease.
  • the signal adjustment unit 407 may perform a logical AND (AND) operation on the delayed logic signal Sdr and the first driving signal S1 to obtain the second driving signal S2, so that the on-time of each switch can be delayed by the first With the delay time t1, the turn-on time is further reduced.
  • AND logical AND
  • the LLC converter provided herein may be a half-bridge LLC resonant circuit.
  • the switch circuit 402 may include two switches connected in series, such as a first switch Q1 and a second switch Q2 connected in series. As shown in FIG. 12 , the first switch Q1 and the second switch Q2 may be connected in series between the positive and negative electrodes of the first power supply 401 .
  • the control circuit 407 can be connected to the first switch Q1 and the second switch Q2 respectively, and is used for driving the first switch Q1 and the second switch Q2.
  • the switch circuit 402 may include a primary side switch of a full-bridge resonant converter.
  • the switches in switching circuit 402 may be insulated gate bipolar transistors, integrated gate commutated thyristors, gate turn-off thyristors, silicon controlled rectifier devices, junction field effect transistor devices, metal oxide semiconductor field effect transistor control thyristor devices, gallium nitride-based power devices, etc.
  • the resonant tank 403 mainly includes a resonant inductor Lr and a resonant capacitor Cr. According to some embodiments, the excitation inductance Lp may also be included in the resonant tank 403 . As shown in FIG. 12 , one end of the resonance tank 403 may be connected to the first node M1 , and the other end may be connected to the conversion circuit 404 .
  • the first node M1 is a connection point between the first switch Q1 and the second switch Q2.
  • the resonance tank 403 may be connected to one pole of the first power supply 401 via the conversion circuit 404 and the control circuit 407 , and to the other pole of the first power supply 401 via the switch circuit 402 .
  • the conversion circuit 404 may include a primary winding Np, a transformer Tr, and a secondary winding Nr.
  • the switching circuit 404 may include one or more secondary windings Sr.
  • One end of the primary winding Np is connected to the resonance tank 403, and the other end is connected to the control circuit 407.
  • the rectifier circuit 405 can convert the alternating current provided by the conversion circuit 404 into direct current.
  • the rectifier circuit 405 may be composed of multiple diodes, or may be composed of multiple switches.
  • the two input terminals of the rectifier circuit 405 can be connected to the secondary winding Nr in the conversion circuit 404 .
  • the rectifier circuit 405 shown in FIG. 12 can be two parallel branches, each branch includes two diodes connected in series, wherein the cathode of the first diode and the anode of the second diode of the two diodes Connection, the connection point between the first diode and the second diode is the input terminal of the rectifier circuit 405 .
  • the cathodes of the first diodes on the two branches are connected, and the anodes of the second diodes on the two branches are connected.
  • the output circuit 406 may include an output capacitor C1.
  • One end of the output capacitor C1 can be connected to the cathodes of the first diodes in the two branches of the rectifier circuit 405 respectively, and the other end of the output capacitor C1 can be connected to the second diodes of the two branches of the rectifier circuit 405 respectively. the anode.
  • the output circuit 406 may stably provide the second voltage to the load 408 .
  • the output circuit 406 at least includes an output capacitor, and the output capacitor can be connected between two ends of the rectifier circuit 405 .
  • the output circuit 406 may include an output filter composed of capacitors.
  • the current acquisition unit 407A may include a current transformer (current transformer, CT) sampling circuit, which is coupled to the resonant tank 403 .
  • the CT sampling circuit may include a first winding Nr1, a second winding Nr2, and a plurality of diodes. One end of the first winding Nr1 may be connected to the primary winding Np in the conversion circuit 404 , and the other end may be connected to the first power source 401 .
  • the plurality of diodes may be in two branches, and each branch may include two diodes in series, wherein the cathode of the third diode of the two diodes is connected to the anode of the fourth diode, and the fourth diode
  • the cathode of the third diode is connected to the logic signal generating power supply 407B, and the anode of the third diode is connected to the ground.
  • the cathode of diode D7 in FIG. 12 is connected to the anode of diode D5, and the cathode of diode D8 is connected to the anode of diode D6.
  • Two ends of the second winding Nr2 are respectively connected to the connection points between the two diodes on each branch.
  • the CT sampling circuit may also be any type of current transformer. This application does not limit this too much.
  • the logic signal generating unit 407B may include at least one comparator, and the first input terminal of the comparator is connected to the output terminal of the CT sampling circuit.
  • the cathodes of the fourth diodes on the two branches of the CT sampling circuit are the output terminals of the CT sampling circuit, and the first input terminal of the comparator can be connected to the cathodes of the fourth diodes on the two branches. connect.
  • the second input terminal of the comparator is connected to a fixed level corresponding to the current threshold.
  • the first driving signal generating unit 407C may include a pulse width modulation (PWM) circuit.
  • the second driving signal generating unit 407D may include a plurality of logic gate circuits, such as a logic AND gate circuit. The first input terminal of each logical AND gate circuit is connected to the output terminal of the comparator, the second input terminal of each logical AND gate circuit is connected to the output terminal of the PWM circuit, and the output terminal of each logical AND gate circuit can be connected with the corresponding switch connection.
  • PWM pulse width modulation
  • the delay unit 407E may include a delay circuit. As shown in FIG. 13 , the input end of the delay circuit may be connected to the output end of the comparator, and the output end of the delay circuit may be connected to the first input end of the logic AND gate circuit.
  • the multiple units included in the control circuit 407 may be implemented as integrated circuits, for example, a programmable gate array (field programmable gate array, FPGA) circuit or a digital signal processing (digital signal processing, DSP) circuit.
  • the control circuit 407 may include an FPGA circuit or a DSP circuit, and the delay unit 407E, the first driving signal generating unit 407C, the second driving signal generating unit 407D, etc. are implemented by the FPGA circuit or the DSP circuit. function and function.
  • the specific constituent elements of the output circuit 406 , the rectifier circuit 405 , the conversion circuit 404 , the resonant tank 403 , the switch circuit 402 , the first power supply 401 and other parts in the embodiment of the present application and the connection method between the elements are only used for illustration. , not as a specific limitation of the multiple parts.
  • the soft-start method of the LLC converter provided in the embodiment of the present application can be applied to a relatively wide range of LLC converters or LLC circuits. Those skilled in the art can adjust the specific constituent elements of the multiple parts in the LLC converter and the connection mode between the elements according to the actual application scenario, so as to realize the functions and functions of the multiple parts in the embodiments of the present application.
  • Embodiments of the present application further provide a soft-start method for an LLC converter, which can be applied to any of the foregoing LLC converters.
  • the method can be performed by a controller or a control circuit, as shown in FIG. 15 , and the method can include the following steps:
  • Step S1501 the controller detects the current of the resonance tank.
  • Step S1502 the controller generates a second drive signal according to the current and the first drive signal, the first drive signal is a pulse signal with a fixed frequency and a fixed duty cycle, the second drive signal is a pulse signal, During the period when the current is greater than or equal to the current threshold, the second drive signal is at a preset level, and the second drive signal at the preset level is used to turn off the power switch in the switch circuit, and in the During the time period when the current is less than the current threshold, the second driving signal is the same as the first driving signal.
  • Step S1503 the controller outputs the second drive signal to the switch circuit, where the second drive signal is used to drive the power switch in the switch circuit.
  • the controller may generate the second driving signal according to the current in the resonance tank and the level of the first driving signal, and output the second driving signal to the switch circuit, and perform the operation on the switches in the switch circuit. drive.
  • a signal of the first level can drive the switch to be in an on state
  • a signal of the second level can drive the switch to be in an off state. If the current of the resonance tank is less than the current threshold and the first driving signal is at the first level, the level of the generated second driving signal is the first level. If the current in the resonance tank is greater than or equal to the current threshold and the first driving signal is at the first level, the level of the generated second driving signal is the second level.
  • the controller can use the second drive signal of the second level to make the switch in an open-circuit state to avoid current impact in the resonant tank and protect the power switch in the LLC converter . If the first drive signal is at the second level, regardless of whether the current in the resonant tank is greater than the current threshold, the level of the second drive signal generated by the controller is at the second level, which also makes the switch in an open state.
  • the fixed frequency is a resonance frequency corresponding to the resonance slot.
  • the soft start method provided in the embodiments of the present application can be applied not only to the start-up phase, but also to the steady-state phase. Since the LLC converter enters the steady-state stage, there is usually no large current surge in the resonant tank, so the second driving signal generated by the controller is the same as the first driving signal, that is, a fixed frequency and a fixed duty cycle. Pulse signal.
  • the controller may further perform the following operations:
  • a logic signal is generated, wherein the logic signal is a pulse signal, and within a time corresponding to the width of the pulse in the logic signal, the current is less than the current threshold, and the logic signal In the time interval between two adjacent pulses, the current is greater than or equal to the current threshold.
  • the generating the second drive signal according to the current and the first drive signal includes:
  • a logical AND operation is performed on the logic signal and the first drive signal to obtain the second drive signal.
  • the controller may perform a logical AND (AND) operation on the logic signal and the first driving signal, and use the operation result as the second driving signal.
  • NOR logical AND
  • the LLC converter may include a PWM circuit for generating a driving signal for the switch in the steady state stage.
  • the PWM circuit generates a first driving signal with a constant frequency and a constant duty cycle in the LLC converter startup phase and steady state phase.
  • the controller can obtain the drive signal of the switch in the start-up stage by adjusting the driving signal of the switch in the steady state stage, and does not change the working mode of the PWM circuit, which can reduce the control complexity of the LLC converter and improve the control efficiency.
  • the logic signal is a pulse signal; before the controller generates the first drive signal according to the current and the second drive signal, the controller may also detect the rising edge of the pulse in the logic signal or At least one of the falling edges is delayed by a preset amount of time.
  • the controller performs delay processing on the logic signal, so that when the controller adjusts the first driving signal according to the logic signal, the start of the conduction period in the second driving signal time is delayed, thereby delaying the turn-on of the switches in the LLC converter.
  • the controller or control circuit shown in FIG. 16 implements the control process of the method, and the control circuit 407 is used as an example for description below.
  • the current acquisition unit 407A in the control circuit 407 can detect the current signal of the resonance tank 403 of the LLC converter, and transmit the current signal to the logic signal generation unit 407B.
  • the current acquisition unit 407A may include a CT sampling circuit.
  • the logic signal generating unit 407B may include a comparator.
  • the logic signal generating unit 407B may compare the current signal with a current threshold and output a logic signal. For example, a low level indicates overcurrent, and a high level indicates no overcurrent. As shown in FIG. 16 , in the signal output by the logic signal generating unit, the signal amplitude between time A and time B is high level, and the signal amplitude between time B and time C is low level.
  • the logic signal generating unit 407B can output in real time a signal representing whether the current in the resonant tank 403 is over-current.
  • the delay unit 407E performs delay processing on the signal. For example, the rising edge of the signal SA-B with a high amplitude is delayed by the first delay time t1, or the falling edge of the signal SA-B is delayed by the second delay time t2.
  • the delay unit 407E may also delay the rising edge of the signal SA-B for a first delay time period t1, and also delay the falling edge of the signal SA-B for a second delay time period t2.
  • the first delay duration t1 and the second delay duration t2 may be configured into the delay unit 407E.
  • the first drive signal generating unit 407C in the control circuit 407 may include a PWM circuit capable of generating a PWM signal with a constant frequency and a constant duty cycle.
  • This PWM signal can be used to drive the switches in switching circuit 402 during the steady state phase of the LLC converter.
  • the frequency at which the PWM circuit generates the PWM signal may be approximately the natural frequency of the resonance tank of the LLC converter.
  • the switch circuit 402 includes two switches.
  • the PWM circuit can respectively generate the corresponding first driving signals for the two switches, and the duty cycle of the driving signals can be about 50%. As shown in FIG. 16 , there are two first driving signals generated by the first driving signal generating unit 407C.
  • the second driving signal generating unit 407D in the control circuit 407 can adjust the steady state driving signals of each switch generated by the first driving signal generating unit 407C according to the logic signal generated by the delay unit 407E.
  • the second driving signal generating unit 407D may include two logic AND gate (AND) circuits, and one logic AND gate (AND) circuit may combine the logic signal generated by the delay unit 407E with the first switch corresponding to the first switch of the two switches. The driving signal is processed to generate a second driving signal corresponding to the first switch. Another logical AND gate (AND) circuit may also process the logic signal generated by the delay unit 407E and the second driving signal of the second switch to generate a corresponding second driving signal for the second switch.
  • AND logic AND gate
  • the second driving signal generating unit 407D may also include a driving unit 407F for applying the second driving signal generated by the AND circuit to the corresponding switches to drive each switch. It can be seen that the control circuit 407 can flexibly adjust the turn-on time and turn-on time of each switch according to the current overcurrent condition in the resonant tank 403 , and through closed-loop control, avoid the current impact of the resonant tank 403 from affecting the performance of each switch.
  • the switch circuit 402 includes two switches.
  • the current threshold is configured to be twice the rated current of the resonant tank 403 .
  • the first delay time period t1 is configured to be 5% of the resonance frequency (natural frequency) of the resonant tank 403 , and the second delay time period is configured to be zero.
  • the duty cycle of the first driving signal is configured to be 50%, and the frequency of the first driving signal is equal to the resonance frequency corresponding to the resonance tank 403 .
  • control circuit 407 can execute the LLC converter soft-start method provided by the embodiment of the present application, the current (I_Resonant) in the resonance tank 403 changes, the voltage of the resonance capacitor Cr ( V_Resonant) and the output voltage (Vout) of the output capacitor C1, as shown in Figure 17.
  • FIG. 18 shows the change of the current (I_Resonant) in the resonance tank 403 in a local time during the start-up phase of the LLC converter during the process of the control circuit 407 executing the soft-start method of the LLC converter provided by the embodiment of the present application, the resonance capacitor Cr The variation of the voltage (V_Resonant) and the variation of the output voltage (Vout) of the output capacitor C1.
  • FIG. 19 shows the signal (corresponding to the second driving signal generated by the second driving signal generating unit 407D in the foregoing embodiment) of the control circuit 407 driving the switch tube in the LLC converter startup stage.
  • FIG. 20 shows the variation of the current (I_Resonant) in the resonant tank 403, the variation of the voltage of the resonance capacitor Cr (V_Resonant), and the variation of the output voltage (Vout) of the output capacitor C1 during the steady state stage of the LLC converter in a local time .
  • the current in the resonant tank 403 enters a steady state, and the current wave forms a sinusoidal waveform.
  • FIG. 21 shows the signal of the control circuit 407 driving the switch tube in the steady state stage of the LLC converter (corresponding to the driving signal generated by the steady-state driving unit signal generating unit 407C in the foregoing embodiment).
  • the output voltage rises steadily to a steady state value within 55ms.
  • the time is 40% of the soft-start time in the aforementioned related art.
  • the current in the resonant tank 403 is limited within a certain range (current threshold), so that the current in the resonant tank 403 is as large as possible without damaging the device, so that the output voltage can be quickly established.
  • An embodiment of the present application further provides a startup device for an LLC converter.
  • the device may include a collection module 2201 , a memory 2202 , and a processor 2203 .
  • the acquisition module 2201 is coupled to the resonant tank 403 in the LLC converter for detecting the current in the resonant tank 403 .
  • the acquisition module 2201 may include a CT sampling circuit, and transmit the detected current signal to the processor 2203 .
  • memory 2202 coupled to processor 2203 for program instructions or codes
  • the processor 2203 is coupled to the sampling module 2201, and can execute program instructions or codes stored in the memory 2201 to implement the process of generating the second driving signal according to the current in the resonance tank in the foregoing embodiment.
  • the collection module 2201 may be integrated in the processor 2203 , that is, the processor 2203 may include the collection module 2201 , so that the processor 2203 has the function of the collection module 2201 .
  • embodiments of the present application also provide a computer program product, including program instructions or codes, when the program instructions are executed on the processor or the controller, the program instructions are used to make the processor or the controller execute the above-described method according to the present application. Steps in a soft-start method of an LLC converter of various exemplary embodiments.
  • the embodiments of the present application also provide a readable storage medium storing the aforementioned computer program product.
  • the readable storage medium provided by the embodiments of the present application may be, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本申请提供一种LLC转换器、控制电路、软启动方法、装置及芯片，用以降低LLC转换器的启动时长，避免谐振槽中产生电流冲击。LLC转换器包括：控制电路，以及依次耦合连接的开关电路、谐振槽，开关电路中包括功率开关；控制电路用于：检测谐振槽的电流；根据电流和第一驱动信号生成第二驱动信号，第一驱动信号为具有固定频率和固定占空比的脉冲信号，第二驱动信号为脉冲信号，在电流大于或等于电流阈值的时段内，第二驱动信号为预设电平，预设电平的第二驱动信号用于关断开关电路中的功率开关，在电流小于电流阈值的时间段内，第二驱动信号与第一驱动信号相同；将第二驱动信号输出给开关电路，第二驱动信号用于驱动开关电路中的功率开关。

Description

一种LLC转换器、控制电路、软启动方法、装置及芯片 技术领域
本申请涉及电路技术领域，尤其涉及一种LLC转换器、控制电路、软启动方法、装置及芯片。
背景技术
在电力变换领域中，将一种电压的直流电变换为另一种电压的直流电并为负载提供电能(也即直流-直流变换)，是一种常见的电力变换需求。目前，有很多电路拓扑可以实现直流-直流变换功能。其中，电感-电感-电容(inductor-inductor-capacitor，LLC)转换器，是一种被广泛应用的直流/直流变换电路。
在LLC转换器中容易实现软开关技术，降低电路中功率开关的损耗。并且LLC转换器易于高频化，减少磁性元器件的体积，因而LLC转换器具有较高变换效率和较高功率密度等优点。
通常，LLC转换器工作在稳态阶段时，LLC转换器中的功率开关的频率接近谐振槽的固有谐振频率，各功率开关的驱动信号的占空比接近50％。在LLC转换器工作在启动阶段，要求在较短时间内输出电容电压平稳地达到输出电压，从而快速完成启动阶段并避免功率开关损坏。
发明内容
本申请提供一种LLC转换器、控制电路、软启动方法、装置及芯片，用以降低LLC转换器的启动时长，避免谐振槽中产生电流冲击。
第一方面，本申请实施例提供一种电感-电感-电容LLC转换器，包括：控制电路407，以及依次耦合连接的开关电路402、谐振槽403，所述开关电路中包括功率开关；所述控制电路407分别与所述开关电路402和所述谐振槽403耦合；所述控制电路407用于：检测所述谐振槽403的电流；根据所述电流和第一驱动信号生成第二驱动信号，所述第一驱动信号为具有固定频率和固定占空比的脉冲信号，所述第二驱动信号为脉冲信号，在所述电流大于或等于电流阈值的时段内，所述第二驱动信号为预设电平，所述预设电平的第二驱动信号用于关断所述开关电路402中的功率开关，在所述电流小于所述电流阈值的时间段内，所述第二驱动信号与所述第一驱动信号相同；将所述第二驱动信号输出给所述开关电路402，所述第二驱动信号用于驱动所述开关电路402中的功率开关。
上述技术方案中，控制电路407可以根据谐振槽403中的电流是否超过电流阈值的情况，以及第一驱动信号的情况，生成用于驱动开关电路402中的功率开关的第二驱动信号。在谐振槽403中的电流大于或等于电流阈值的时段内，也即谐振槽403中发生过流的情形下，第二驱动信号的电平为用于驱动功率开关的预设电平，可以使功率开关关断，以避免谐振槽403中产生电流冲击，保护LLC转换器中的元件。在谐振槽403中的电流小于电流阈值的情形下，控制电路407可以生成与第一驱动信号相同的第二驱动信号，在LLC谐振槽启动阶段控制电路407利用与第一驱动信号相同的第二驱动信号驱动功率开关，可使开关电路402中的开关导通时长较长，可以快速建立输出电压，缩短LLC转换器的启动时长， 提升启动速度。控制电路407可以根据谐振槽403中的电流情况，灵活地调整功率开关的驱动信号，通过闭环控制的方式避免谐振槽403中产生电流冲击，保障LLC转换器的元件。
一种可能的实施方式中，所述控制电路407包括电流采集单元407A、逻辑信号生成单元407B、第一驱动信号生成单元407C和第二驱动信号生成单元407D；所述电流采集单元407A，用于检测所述谐振槽403的电流；所述第一驱动信号生成单元407C，用于生成所述第一驱动信号；所述逻辑信号生成单元407B，用于根据所述电流和所述电流阈值，生成逻辑信号，其中，所述逻辑信号为脉冲信号，所述逻辑信号中脉冲的宽度对应的时间内，所述电流小于所述电流阈值，所述逻辑信号中相邻两个脉冲之间的时间间隔内，所述电流大于或等于所述电流阈值；所述第二驱动信号生成单元407D，用于基于所述逻辑信号和所述第一驱动信号，生成所述第二驱动信号。
一种可能的实施方式中，所述第二驱动信号生成单元407D，具体用于：
对所述逻辑信号和所述第一驱动信号进行逻辑与运算处理，得到所述第二驱动信号，其中，所述电流小于所述电流阈值的时间内，所述逻辑信号的电平为高电平，所述电流大于或等于所述电流阈值的时间内，所述逻辑信号的电平为低电平。
上述技术方案中，控制电路407中第二驱动信号生成单元407D可以为通过对所述逻辑信号和第一驱动信号进行逻辑与运算处理，生成第二驱动信号。第二驱动信号生成单元407可以为模拟信号电路，也可以为数字信号电路，使得控制电路407对开关电路402中的功率开关的驱动过程易于实现。
一种可能的实施方式中，所述逻辑信号为脉冲信号，所述控制电路407还包括延时单元407E；所述延时单元407E，用于对所述逻辑信号中脉冲的上升沿或者下降沿中的至少一个滞后预设时长；所述第二驱动信号生成单元407D，还用于：基于延时后的所述逻辑信号和所述第一驱动信号，生成所述第二驱动信号。
上述技术方案中，控制电路407中的延时单元407E可以对逻辑信号进行延时处理，可以滞后第二驱动信号中各脉冲的起始时刻，从而实现延时开关导通。
一种可能的实施方式中，所述固定频率为所述谐振槽403对应的谐振频率。
上述技术方案中，第一驱动信号为谐振槽对应的谐振频率，控制电路407可以在LLC启动阶段及稳态阶段执行相同的操作。稳态阶段中谐振槽403中的电流小于电流阈值，控制电路407根据谐振槽403中的电流和第一驱动信号，生成的第二驱动信号与第一驱动信号相同。
第二方面，本申请实施例提供一种控制电路，应用于驱动电感-电感-电容LLC转换器，所述LLC转换器包括开关电路402和谐振槽403，所述控制电路包括电流采集单元407A、逻辑信号生成单元407B、第一驱动信号生成单元407C和第二驱动信号生成单元407D；所述电流采集单元407A用于检测所述谐振槽403的电流；所述第一驱动信号生成单元407C，用于生成第一驱动信号，所述第一驱动信号为具有固定频率和固定占空比的脉冲信号；所述逻辑信号生成单元407B，用生成逻辑信号，其中，所逻辑信号为脉冲信号，所述逻辑信号中脉冲的宽度对应的时间内，所述电流小于所述电流阈值，所述逻辑信号中相邻两个脉冲之间的时间间隔内，所述电流大于或等于所述电流阈值；所述第二驱动信号生成单元407D，用于基于所述逻辑信号和所述第一驱动信号，生成所述第二驱动信号，所述第二驱动信号为第二脉冲信号，在所述电流大于或等于电流阈值的时段内，所述第二驱动信号为预设电平，所述预设电平的第二驱动信号用于关断所述开关电路402中的功率开关， 在所述电流小于所述电流阈值的时间段内，所述第二驱动信号与所述第一驱动信号相同。
一种可能的实施方式中，所述第二驱动信号生成单元407D，具体用于：对所述逻辑信号和所述第一驱动信号进行逻辑与运算处理，得到所述第二驱动信号，其中，所述电流小于所述电流阈值的时间内，所述逻辑信号的电平为高电平，所述电流大于或等于所述电流阈值的时间内，所述逻辑信号的电平为低电平。
一种可能的实施方式中，所述逻辑信号为脉冲信号，所述控制电路407还包括延时单元407E；
所述延时单元407E，用于对所述逻辑信号中脉冲的上升沿或者下降沿中的至少一个滞后预设时长；
所述第二驱动信号生成单元407D，还用于：基于延时后的所述逻辑信号和所述第一驱动信号，生成所述第二驱动信号。
一种可能的实施方式中，所述固定频率为所述谐振槽403对应的谐振频率。
一种可能的实施方式中，所述逻辑信号生成单元407B包括比较器，所述比较器的第一输入端与所述电流采集单元407A的输出端连接，所述比较器的第二输入端连接固定电平，所述固定电平为所述电流阈值对应的电平，所述比较器的输出端与所述第二驱动信号生成电源407D连接，或者与所述延时单元407E连接。
第三方面，本申请实施例提供一种电感-电感-电容LLC转换器的软启动方法，LLC转换器包括谐振槽和开关电路，所述方法包括：检测所述谐振槽的电流；根据所述电流和第一驱动信号生成第二驱动信号，所述第一驱动信号为具有固定频率和固定占空比的脉冲信号，所述第二驱动信号为脉冲信号，在所述电流大于或等于电流阈值的时段内，所述第二驱动信号为预设电平，所述预设电平的第二驱动信号用于关断所述开关电路中的功率开关，在所述电流小于所述电流阈值的时间段内，所述第二驱动信号与所述第一驱动信号相同；将所述第二驱动信号输出给所述开关电路，所述第二驱动信号用于驱动所述开关电路中的功率开关。
一种可能的实施方式中，在所述根据所述电流和第一驱动信号生成第二驱动信号之前，所述方法还包括：根据所述电流和所述电流阈值，生成逻辑信号，其中，所述逻辑信号为脉冲信号，所述逻辑信号中脉冲的宽度对应的时间内，所述电流小于所述电流阈值，所述逻辑信号中相邻两个脉冲之间的时间间隔内，所述电流大于或等于所述电流阈值。所述根据所述电流和第一驱动信号生成第二驱动信号，包括：对所述逻辑信号和所述第一驱动信号进行逻辑与运算处理，得到所述第二驱动信号，其中，所述电流小于所述电流阈值的时间内，所述逻辑信号的电平为高电平，所述电流大于或等于所述电流阈值的时间内，所述逻辑信号的电平为低电平。
一种可能的实施方式中，所述逻辑信号为脉冲信号；在所述根据所述电流和第二驱动信号生成第一驱动信号之前，所述方法还包括：对所述逻辑信号中脉冲的上升沿或者下降沿中的至少一个滞后预设时长。
一种可能的实施方式中，所述固定频率为所述谐振槽对应的谐振频率。
第四方面，本申请实施例提供一种电感-电感-电容LLC转换器控制装置，所述装置包括处理器和存储器，所述存储器用于存储程序、指令或代码，所述处理器用于执行所述存储器中的程序、指令或代码，完成如第三方面及其任一可能的设计中任一所述的方法。
第五方面，本申请实施例提供一种电感-电感-电容LLC转换器控制装置，所述装置包 括采集模块、处理器和存储器。所述采集模块用于检测所述谐振槽的电流；所述存储器用于存储程序、指令或代码，所述处理器用于执行所述存储器中的程序、指令或代码，执行根据所述电流和第一驱动信号生成第二驱动信号，所述第一驱动信号为具有固定频率和固定占空比的脉冲信号，所述第二驱动信号为脉冲信号，在所述电流大于或等于电流阈值的时段内，所述第二驱动信号为预设电平，所述预设电平的第二驱动信号用于关断所述开关电路中的功率开关，在所述电流小于所述电流阈值的时间段内，所述第二驱动信号与所述第一驱动信号相同；将所述第二驱动信号输出给所述开关电路，所述第二驱动信号用于驱动所述开关电路中的功率开关。
一种可能的实施方式中，所述处理器还用于：在所述根据所述电流和第一驱动信号生成第二驱动信号之前，根据所述电流和所述电流阈值，生成逻辑信号，其中，所述逻辑信号为脉冲信号，所述逻辑信号中脉冲的宽度对应的时间内，所述电流小于所述电流阈值，所述逻辑信号中相邻两个脉冲之间的时间间隔内，所述电流大于或等于所述电流阈值；所述处理器在根据所述电流和第一驱动信号生成第二驱动信号时具体用于：对所述逻辑信号和所述第一驱动信号进行逻辑与运算处理，得到所述第二驱动信号，其中，所述电流小于所述电流阈值的时间内，所述逻辑信号的电平为高电平，所述电流大于或等于所述电流阈值的时间内，所述逻辑信号的电平为低电平。
一种可能的实施方式中，所述逻辑信号为脉冲信号；所述处理器还用于在所述根据所述电流和第二驱动信号生成第一驱动信号之前，对所述逻辑信号中脉冲的上升沿或者下降沿中的至少一个滞后预设时长。
一种可能的实施方式中，所述固定频率为所述谐振槽对应的谐振频率。
第六方面，本申请实施例提供一种非易失性计算机可读存储介质，用于存储计算机程序，所述计算机程序通过处理器进行加载来执行如第三方面及其任一可能的设计中任一所述的方法。
第七方面，本申请实施例提供一种芯片，芯片可以与存储器耦合，用于调用执行所述存储器中存储的计算机程序指令，以使如第三方面及其任一可能的设计中任一所述的方法被执行。
一种可能的实施方式中，所述芯片包括至少一个存储器，所述至少一个存储器中存储的计算机程序指令，以使所述芯片可以执行如第三方面及其任一可能的设计中任一所述的方法。
上述第二方面和第七方面可以达到的技术效果请参照上述第一方面中相应设计可以达到的技术效果描述，这里不再重复赘述。
附图说明
图1为一种LLC转换器的电路结构示意图；
图2为LLC转换器的开关频率与增益曲线的示意图；
图3为谐振槽电流、谐振电容的电压、输出电容的电压的示意图；
图4为一种LLC转换器结构示意图；
图5为一种LLC转换器结构示意图；
图6为开关的驱动信号的示意图；
图7为一种LLC转换器结构示意图；
图8为一种延时处理过程的示意图；
图9为开关的驱动信号的示意图；
图10为开关的驱动信号的示意图；
图11为一种延时处理过程的示意图；
图12为一种LLC转换器结构示意图；
图13为一种LLC转换器结构示意图；
图14为一种LLC转换器结构示意图；
图15为一种LLC转换器软启动方法的示意流程图；
图16为一种LLC转换器软启动方法的控制流示意图；
图17为启动阶段谐振槽电流、谐振电容的电压、输出电容的电压的示意图；
图18为启动阶段谐振槽电流、谐振电容的电压、输出电容的电压的示意图；
图19为LLC转换器启动阶段开关的驱动信号示意图；
图20为稳态阶段谐振槽电流、谐振电容的电压、输出电容的电压的示意图；
图21为LLC转换器稳态阶段开关的驱动信号示意图；
图22为LLC转换器控制装置的结构示意图。
具体实施方式
通常，LLC转换器中包括谐振电感、谐振电容和励磁电感，具有较好的软开关特性，可以大幅减小开关损耗，提高能量的传输效率，是目前使用较为普遍的功率拓扑之一。
LLC转换器工作在稳态阶段时，LLC转换器中的功率开关频率接近谐振槽的固有频率。驱动各功率开关管的信号占空比接近50％。但在LLC转换器工作在启动阶段时，由于LLC转换器中的输出电容还没建立起稳态的电压，若启动阶段中对各功率开关的驱动方式，与稳态阶段中对各功率开关的驱动方式相同，那么LLC转换器在启动阶段时，谐振槽中电流将非常大，容易超过功率开关所能承受的电流范围，导致功率开关损坏。
因此，LLC转换器在启动阶段，使输出电容电压平稳地达到输出电压，并且避免功率开关损坏，具有重要的工程意义。
图1中示出了一种LLC转换器的电路结构。LLC转换器包括输入源Vin和依次连接的开关电路102、谐振槽103、转换电路104、整流电路105和输出电路106。开关电路102中包括串联连接的功率开关S1和功率开关S2。功率开关S1和功率开关S2串联连接在输入源Vin的两极之间。谐振槽103中包括依次串联连接的谐振电容Cr、谐振电感Lr、励磁电感Lp。其中，谐振电容Cr的一端与开关S1与开关S2之间的连接点相连，谐振电容Cr的另一端与谐振电感Lr连接。励磁电感Lp的一端与谐振电感Lr连接，另一端与输入源Vin的负极连接。转换电路104包括依次耦合的原极绕组Pr、变压器Tr和副极绕组Sr。原极绕组Pr与励磁电感Lp并联。副极绕组Sr包括串联连接的第一绕组Sr1和第二绕组Sr2。
整流电路105包括两个二极管，分别记为二极管D1和二极管D2。输出电路106包括输出电容C1。其中，二极管D1的阴极和二极管D2的阴极连接在输出电容C1的第一端，输出电容C1的第二端连接在第一绕组Sr1与第二绕组Sr2之间的连接点。第一绕组Sr1不与第二绕组Sr2连接的一端与二极管D1的阳极连接，第二绕组Sr2不与第一绕组Sr1连接的一端与二极管D2的阳极连接。
负载107与输出电容C1并联。输出电容C1的输出电压记为Vout。LLC转换器可以 将输入源Vin提供的电压转换为输出电压Vou，并提供给用电负载107。
不同负载的LLC转换器的开关频率与增益曲线如图2所示，横轴的物理量表征开关频率fs与谐振频率fo的比值(记为fn)，纵轴的物理量表征输出增益。图2中示出了7种负载的曲线(如图中曲线L1至L7，分别表示7种负载对应的曲线)，通常在fn接近1附近时，所有的负载的曲线增益达到最大，LLC转换器可以以开关频率fo驱动各功率开关(如图1中的功率开关S1和功率开关S2)，使LLC转换器处于稳态阶段。并且，从图2中可以直观的看出，fn＝fs/fo的取值越大，输出增益越小。通常谐振频率fo是固定数值，因而开关频率fs越大，输出增益越小。
为避免开关管损坏，相关技术基于该特性，在LLC转换器处于启动阶段过程中，对功率开关S1和功率开关S2施加高频驱动信号，也即用一个较大的开关频率fs控制两个功率开关。根据图2中的曲线，较大的开关频率fs对应的输出增益很小，从而使输入源Vin提供的能量缓慢输入谐振槽，以限制谐振槽中的电流。能量缓缓输入谐振槽后，经过变换器等元件，缓慢输入至输出电容C1中。随着输出电容C1的输出电压Vout增大，再逐渐减小开关频率fs，例如，减小至谐振频率fo，保障输出电容C1的输出增益最大，使LLC变换器结束启动阶段进入稳态阶段。
在LLC转换器启动阶段，使用开关频率fs＝5fo的驱动信号对功率开关进行控制，并线性地降低开关频率直至等于谐振频率的过程中，谐振槽中的电流iLr变化情况，谐振电容Cr的电压VCr变化情况以及输出电容C1的输出电压Vo变化情况，如图3所示。输出电容C1的输出电压Vo是缓慢增加到最大输出电压，但在这个期间，谐振槽中仍出现电流冲击，如图3中椭圆虚线框区域所示。避免该电流冲击，还需提高开关频率fs。可见，相关技术中采用避免谐振槽中产生冲击电流需要在启动阶段采用更高的开关频率。但在启动阶段选用更高的开关频率，会使输出电容C1的输出电压增加到最大输出电压的时长更长，也即LLC转换器启动时长变长。
为解决前述问题，本申请实施例提供一种LLC转换器以及LLC转换器软启动方法、装置及介质。应用于LLC转换器，可以减少或避免谐振槽中出现电流冲击，缩短启动时长，提升软启动速度，从而保障电路安全。
首先，本申请实施例提供一种LLC转换器，如图4所示，LLC转换器可以包括开关电路402、谐振槽403以及控制电路407。其中，控制电路407与开关电路402耦合，控制电路407与谐振槽403耦合。谐振槽403中至少包括串联连接的谐振电容Cr、谐振电感Lr。谐振槽403可使开关电路402中的功率开关工作在软开关状态。本申请实施例提供的LLC转换器应用于较为广泛的LLC转换器或者LLC电路中。
一种可能的设计中，LLC转换器还可以包括与谐振槽403连接转换电路404，转换电路404可以用于进行电压变换，电流变换、隔离、稳压等用途。LLC转换器还可以包括与转换电路404连接的整流电路405。整流电路405可以与输出电路406连接。整流电路405将转换电路提供的交流电流转换为直流电流，提供给输出电路406。输出电路406中可以包括输出电容，负载可以与输出电容并联。LLC转换器可以对第一电源401提供的第一电压进行转换，并将转换后的第二电压提供给负载。应理解的是，本申请实施例中输出电路406、整流电路405、转换电路404、谐振槽403、开关电路402、第一电源401等多个部分的具体构成元件以及元件之间的连接方式，仅用于举例说明，并不作为所述多个部分的具体限定。
控制电路407可以检测所述谐振槽403中的电流。控制电路407可以根据所述电流和第一驱动信号生成第二驱动信号，然后将所述第二驱动信号输出给所述开关电路402，所述第二驱动信号用于驱动所述开关电路402中的功率开关。所述第一驱动信号可以为具有固定频率和固定占空比的脉冲信号。所述第二驱动信号为脉冲信号，在谐振槽403中的电流大于或等于电流阈值的时段内，所述第二驱动信号为预设电平，所述预设电平的第二驱动信号用于关断所述开关电路402中的功率开关，在谐振槽403中的电流小于谐振槽403中的电流阈值的时间段内，所述第二驱动信号与所述第一驱动信号相同。
本申请实施例中，开关电路402中的功率开关可以由第一电平信号驱动，使功率开关处于导通状态，即第一电平信号可以用于导通该功率开关。功率开关由第二电平信号驱动，使功率开关处于断开状态，即第二电平信号可以用于关断该功率开关。作为一种举例，第一电平可为高电平，第二电平可为低电平，也即高电平信号可驱动功率开关处于导通状态，低电平信号可驱动功率开关处于断路(关断)状态。另一举例中，第一电平可为低电平，第二电平可为高电平，也即低电平信号可驱动开关处于导通状态，高电平信号可驱动功率开关处于断路状态。下面以第一电平信号为高电平，可以用于驱动功率开关处于导通状态，第二电平信号为低电平，可以用于驱动功率开关处于断开状态为例进行介绍。也即，所述预设电平为第二电平为例作为介绍。
控制电路407可以根据谐振槽403中的电流是否超过电流阈值的情况，以及第一驱动信号的情况，生成用于驱动开关电路402中的功率开关的第二驱动信号。在谐振槽403中的电流大于或等于电流阈值的时段内，也即谐振槽403中发生过流的情形下，第二驱动信号为第二电平，可以驱动功率开关关断，以避免谐振槽403中产生电流冲击，保护LLC转换器中的元件。在谐振槽403中的电流小于电流阈值的时段内，第二驱动信号可以与第一驱动信号相同，也即若第一驱动信号为第二电平，则第二驱动信号也为第二电平，若第一驱动信号为第一电平，则第二驱动信号也为第一电平。
或者说，控制电路407可以根据第一驱动信号为第一电平，谐振槽403中的电流小于电流阈值，则生成的第二驱动信号为第一电平。控制电路407可以第一驱动信号为第一电平，谐振槽403中的电流大于或等于电流阈值，生成第二驱动信号为第二电平。控制电路407可以根据第一驱动信号为第二电平，生成第二驱动信号为第二电平。可见，第二驱动信号为脉冲信号，并且脉冲宽度对应的时段内所述电流小于电流阈值的时段内，脉冲的幅值可以为第一电平，所述电流大于或等于电流阈值的时段内，第二驱动信号为低电平。
本申请实施例中，控制电路407对LLC转换器启动阶段的驱动方式与稳态阶段的驱动方式均可以执行前述操作。
一个示例中，控制电路407可以按照固定频率和固定占空比生成第一驱动信号，使第一驱动信号为固定频率和固定占空比的脉冲信号，脉冲的幅值为第一电平，相邻两个脉冲之间的电平为第二电平。该第一驱动信号可以用于在稳态阶段驱动开关电路402中的功率开关上。开关电路402可以包括多个功率开关，控制电路407可以生成各开关相应的第一驱动信号。每个开关相应的第一驱动信号不同，例如每个开关相应的第一驱动信号中的导通时刻不同，或者说每个开关相应的第一驱动信号是异相的。可选的，第一驱动信号对应的固定频率可以是谐振槽403对应的谐振频率。若开关电路402包括两个串联的开关，第一驱动信号的占空比可为50％。
一种可能的实施方式中，若谐振槽403中的电流小于或等于电流阈值，控制电路407 可以将第一驱动信号施加到开关电路402。若谐振槽403中的电流大于电流阈值，控制电路407可以根据所述谐振槽403中的电流和第一驱动信号生成第二驱动信号，并且在所述第二驱动信号中的第一电平脉冲宽度对应的时间段内，所述谐振槽403的电流小于电流阈值且所述第一驱动信号的电平为第一电平，在所述第二驱动信号的第二电平脉冲宽度对应的时间段内，所述谐振槽403的电流大于或等于所述电流阈值或所述第一驱动信号的电平为第二电平。控制电路407可以通过多种方式或者电路实现，生成具有前述特性的第二驱动信号。
本申请实施例中，控制电路407可以根据谐振槽403的电流大于或等于电流阈值对应的时间段内，第二驱动信号的电平为第二电平，使得开关处于断开状态。这样的设计，可使开关电路402中的开关导通时长较少，可以减少流入谐振槽403中的电流，避免谐振槽中403产生电流冲击，保护LLC转换器中的元件。控制电路407可以根据谐振槽403中的电流小于电流阈值，生成的第二驱动信号的电平和第一驱动信号的电平相同。如第一驱动信号的电平为第一电平并且谐振槽403中的电流小于电流阈值，控制电路407生成的第二驱动信号为第一电平，并将第二驱动信号施加在开关电路402上，可使开关电路402中的开关导通时长较长，使得输出电路406可以快速建立输出电压，缩短LLC转换器的启动时长，提升启动速度。
一种可能的实施方式中，如图5所示，控制电路407可以包括电流采集单元407A、逻辑信号生成单元407B、第一驱动信号生成单元407C和第二驱动信号生成单元407D。电流采集单元407A与谐振槽403耦合，电流采集单元407A可以采集谐振槽403中的电流iLr，并将采集的电流传输给逻辑信号生成单元407B。本申请实施例中，电流采集单元407A可以实时采集谐振槽403中的电流iLr。
逻辑信号生成单元407B可以基于电流阈值Imax和谐振槽407B的电流iLr，生成逻辑信号Sr，并将生成的逻辑信号Sr传输至第二驱动信号生成单元407D。
一个示例中，逻辑信号生成单元407B可以对谐振槽403中的电流iLr进行过流检测。若电流iLr大于电流阈值Imax，则生成幅值为第三电压的信号。若电流iLr小于或等于电流阈值Imax，则生成幅值为第四电压的信号。可选地，第三电压为低电平，第四电压为高电平。本申请实施例中，低电平可以用0表示，高电平可以用1表示。可见，逻辑信号生成单元407B生成的信号为脉冲信号，信号中脉冲的宽度对应的时间内，谐振槽403中电流小于电流阈值，相邻两个脉冲之间的时间间隔内，谐振槽403中电流大于或等于电流阈值。
电流采集单元407A可以实时采集谐振槽403中的电流iLr，并将电流iLr传输给逻辑信号生成单元407B。从而使逻辑信号生成单元407B也可以实时对电流iLr进行过流检测，生成可以表征是否过流的逻辑信号。
若iLr大于电流阈值Imax的持续时长为第一时长，那么逻辑信号生成单元407B生成的逻辑信号可以是幅值为第三电压的信号，该信号的时长为所述第一时长。若电流iLr小于或等于电流阈值Imax的持续时长为第二时长，那么逻辑信号生成单元407B生成的逻辑信号可以是幅值为第四电压的信号，该信号的时长为所述第二时长。可选地，第三电压可以是0，第四电压可以是1，逻辑信号生成单元407B生成的信号可以视为逻辑信号。
第一驱动信号生成单元407C可以生成第一驱动信号S1(用于在LLC转换器稳态阶段中各开关的驱动信号)，并将第一驱动信号S1提供给第二驱动信号生成单元407D。可选 地，第一驱动信号S1对应的开关频率fs可以等于谐振频率fo。第一驱动信号生成单元407C可以生成开关电路402中每个开关相应的第一驱动信号。
由于第一驱动信号生成单元407C所生成的第一驱动信号S1可以用于在LLC转换器稳态阶段中对各开关进行驱动的信号。通常，第一驱动信号生成单元407C可以按照预设开关频率fs和预设占空比，生成各开关相应的驱动信号。例如，预设开关频率fs可以和谐振频率fo相同。示例性的，开关频率fs可以是10Hz。若开关电路402中包括两个开关，预设占空比可为50％。
应理解的是，第一驱动信号生成单元407C生成的第一驱动信号为固定频率和固定占空比的信号，可以用于在稳态阶段驱动开关电路402中开关。在LLC转换器稳态阶段，控制电路407可以将第一驱动信号生成单元407C生成的第一驱动信号传输至开关电路402，对开关进行驱动，也可以将第二驱动信号生成单元407D生成的第二驱动信号传输至开关电路402，对开关进行驱动。
第二驱动信号生成单元407D可以基于逻辑信号Sr和第一驱动信号S1，生成第二驱动信号S2。然后将第二驱动信号S2发送给开关电路402中的各开关，对各开关进行驱动。
一种可能的实施方式中，第二驱动信号生成单元407D可以具有逻辑与(AND)运算的功能。第二驱动信号生成单元407D可以包括逻辑门电路，如与门电路，或称逻辑与门电路。逻辑与门电路可以实现数字逻辑中逻辑与的功能。若向逻辑与门电路输入至多有一个高电平，则逻辑与门电路输出低电平。本申请实施例中，输入逻辑与门电路的信号，也可以视为逻辑与门电路接收的信号。
例如，1表示高电平，0表示低电平。输入逻辑与门电路信号均为1，则逻辑与门电路输出信号为1。输入逻辑与门电路信号包括0和1，则逻辑与门电路输出信号为0。输入逻辑与门电路信号均为0，则逻辑与门电路输出信号为0。
逻辑信号生成单元407B生成的逻辑信号Sr的幅值为低电平时，也是谐振槽403中电流大于或等于电流阈值Imax的情形，可以反映出谐振槽403中的电流过大，可能对开关电路402中的开关造成冲击。第二驱动信号生成单元407D可以将幅值为低电平逻辑信号Sr和第一驱动信号S1进行逻辑与(AND)运算的结果，作为第二驱动信号S2，即第二驱动信号S2为幅值为低电平的信号。
一种可能的实施方式中，第一驱动信号生成单元407C生成用于驱动开关处于导通状态的第一驱动信号S1的情形下(即第一驱动信号S1的电平为高电平)，若逻辑信号生成单元407B生成的逻辑信号Sr的低电平信号，第二驱动信号生成单元407D可以生成电平为低电平的第二驱动信号S2。例如，第二驱动信号生成单元407D可以将第一驱动信号生成单元407C生成的驱动信号S2和逻辑信号生成单元407B生成的逻辑信号Sr进行逻辑与(AND)运算，可以得到成第二驱动信号S2。
一种可能的实施方式中，开关电路402中包括多个开关，第二驱动信号生成单元407D中可以包括与所述多个开关数量相同的逻辑与门电路。多个开关和多个逻辑与门电路可以一一对应，各逻辑与门电路可以接收逻辑信号生成单元407B生成的逻辑信号Sr和第一驱动信号生成单元407C生成的将相应开关的第一驱动信S1，并基于接收的这两个信号，生成相应开关的第二驱动信号S2。
在第一驱动信号生成单元407C生成的第一驱动信号S1用于驱动开关处于断路状态的情形下(即第二驱动信号S2的电平为低电平)，第二驱动信号生成单元407D可以不对第 一驱动信号生成单元407C生成的第一驱动信号S1进行调整或者说第二驱动信号生成单元407D可以停止生成第二驱动信号S2。
或者，第二驱动信号生成单元407D生成的第二驱动信号S2可以与第一驱动信号S1相同，即生成的第二驱动信号S2为低电平，可以用于驱动开关处于断路状态。
再或者，第二驱动信号生成单元407D可以将逻辑信号Sr和低电平的第一驱动信号S1进行逻辑与(AND)运算的结果，作为第二驱动信号S2，即生成的第二驱动信号S2的幅值为低电平。
本申请实施例中，第二驱动信号生成单元407D可以根据逻辑信号生成单元407B实时提供的逻辑信号Sr和第一驱动信号生成单元407C实时提供的第一驱动信号S1，生成第二驱动信号S2，并将生成的第二驱动信号S2传输给开关电路402中的开关，对开关进行驱动。
例如，第二驱动信号生成单元407D可以将逻辑信号Sr和第一驱动信号S1进行逻辑与(AND)运算的结果，作为第二驱动信号S2。控制电路407可以通过对谐振槽403中的电流进行检测，并依据电流是否大于电流阈值的情况，调整施加在开关电路402上的驱动信号，实现根据谐振槽403中的电流情况，灵活地调整驱动信号，通过闭环控制的方式避免谐振槽403中产生电流冲击，保障LLC转换器的元件。
本申请实施例中，第二驱动信号生成单元407D利用低电平的逻辑信号Sr和高电平的第一驱动信号S1，生成低电平的第二驱动信号S2对开关进行驱动，可以缩短开关持续导通时长。这样的设计中，在谐振槽403中出现电流过大的情形下，控制电路407将开关电路402的驱动方式由施加定频定占空比的驱动信号方式，可以调整为施加基于谐振槽403中电流大于电流阈值持续时长生成的非定频非定占空比的驱动信号方式。
下面以开关电路402中包括两个开关为例进行说明。两个开关可以分别记为开关K1和开关K2。如图6所示，第一驱动信号生成单元407C生成开关K1相应的第一驱动信号记为K1-S1，生成开关K2相应的第一驱动信号记为K2-S1。开关K1和开关K2的占空比为50％。两个开关可由高电平驱动处于导通状态，以及由低电平驱动处于断路状态。
逻辑信号生成单元407B生成的逻辑信号Sr中低电平对应第三电压，高电平对应第四电压。逻辑信号Sr可以包括幅值为第三电压的信号和幅值为第四电压的连续信号。
以开关K1为例，当开关K1的第一驱动信号K1-S1与逻辑信号Sr进行逻辑与(AND)运算可获得开关K1的第二驱动信号K1-S2，如图6中第三行波形。其中，第二驱动信号K1-S2中，带有斜线标记的波形幅值为高电平，该信号可驱动开关K1处于导通状态。两个带有斜线标记的波形之间的信号为低电平，该信号可驱动开关K1处于断路状态。
开关K1的一个驱动周期中包括前半个周期为高电平信号，可以使开关K1处于导通状态，也即一个驱动周期中的前半个周期为导通周期，则一个驱动周期中的后半个周期为断路周期(或者关断周期)。
由图6可见，在一个驱动周期内的后半个周期内的第二驱动信号K1-S2为低电平，可使开关K1处于断路状态。而在一个驱动周期内的前半个周期内，若发生多次谐振槽403中的电流大于电流阈值的情形，逻辑信号生成单元407B生成的逻辑信号Sr可为包括多个幅值为第三电平的信号和多个幅值为第四电平的信号。在一个驱动周期内的前半个周期内逻辑信号生成单元407B可以低电平的逻辑信号Sr与高电平的第一驱动信号K1-S1进行逻辑与(AND)运算后，生成低电平的第二驱动信号K1-S2，实现在谐振槽403发生电流过 流的情形下，关断开关电路中的开关，避免谐振槽403中产生电流冲击。逻辑信号生成单元407B可以高电平的逻辑信号Sr与高电平的第一驱动信号K1-S1进行逻辑与(AND)运算后，生成高电平的第二驱动信号K1-S2，实现在谐振槽403未发生电流过流的情形下，导通开关电路中的开关。
本申请实施例中，利用开关K1的一个驱动周期作为参照，描述逻辑信号Sr、第一驱动信号K1-S1、第二驱动信号K1-S2之间的关系，并不作为第二驱动信号生成单元407D处理周期的限定。第二驱动信号生成单元407D可以实时对逻辑信号Sr和第一驱动信号K1-S1进行逻辑与(AND)运算，生成第二驱动信号K1-S2。
一种可能的实施方式中，控制电路407还可以包括延时单元407E。如图7所示，延时单元407E可以连接在逻辑信号生成单元407B和第二驱动信号生成单元407D之间。延时单元407E用于基于逻辑信号生成单元407B生成的逻辑信号Sr，生成延时逻辑信号Sd。延时单元407E将生成的延时逻辑信号Sdr提供给第二驱动信号生成单元407D。第二驱动信号生成单元407D可以根据延时逻辑信号Sd和第一驱动信号生成单元407C生成的第一驱动信号S1生成第二驱动信号S2。
本申请实施例中，延时单元407E可以对逻辑信号生成单元407B生成的逻辑信号Sr进行延时处理。
一个示例中，延时单元407E可以对逻辑信号Sr进行延时处理时，延时单元407E接收到逻辑信号Sr后，可以在经过第一延迟时长t1后，将接收到的逻辑信号Sr提供给第二驱动信号生成单元407D，如图8所示。便于区分，本申请实施例中，将延时单元407E发送提供给信号调整单元407的信号记为延时逻辑信号Sdr。
第二驱动信号生成单元407D根据延时逻辑信号Sdr和第一驱动信号生成单元407C生成的第一驱动信号S1，生成第二驱动信号S2。可选地，信号调整单元407可以将延时逻辑信号Sdr和驱动信号S1进行逻辑与(AND)运算，得到第二驱动信号S2*。
如图9所示，以生成开关K1的第二驱动信号为例。延时单元407E根据逻辑信号Sr，对第一驱动信号生成单元407C生成的第一驱动信号S1进行调整，生成第二驱动信号K1-S2。第二驱动信号生成单元407D根据延时逻辑信号Sdr，对第一驱动信号生成单元407C生成的第一驱动信号S1进行调整，生成第二驱动信号K1-S2*。
在第一驱动信号生成单元407C生成的第一驱动信号K1-S1用于驱动开关K1处于导通状态对应的时段内(高电平信号对应的时段)，也即图9中K1-S1的第一驱动信号为高电平的时段内，由于延时逻辑信号Sdr被延时第一延迟时长t1，使各开关的导通时刻被滞后第一延迟时长t1。相比于启动第一驱动信号K1-S1中开关处于导通状态的起始时刻，在第二驱动信号K1-S2*中，开关处于导通的起始时刻也被滞后第一延迟时长t1。
本申请实施例中，延时逻辑信号Sdr是对逻辑信号Sr进行延时第一延迟时长t1处理生成的信号。因而，第二驱动信号生成单元407D生成的第二驱动信号S2中，高电平信号的起始时刻被滞后，可以延迟各开关的导通时刻。延迟各开关的导通时刻，可使第一电源401提供的能量的时刻被延迟，减少进入谐振槽403中的能量，以使谐振槽403中的电流降低。
一种可能的情形中，第二驱动信号生成单元407D根据延时逻辑信号Sdr和第一驱动信号生成单元407C生成的第一驱动信号S1，生成的第二驱动信号S2中高电平对应的总时长更小，进一步缩短各开关的导通时间。如图10所示，延时单元407E对逻辑信号Sr 进行延时处理后，使得低电平的逻辑信号Sr落在第一驱动信号K1-S1中高电平信号对应时段内的部分减少。从而，第二驱动信号生成单元407D对延时逻辑信号Sdr和第一驱动信号生成单元407C生成的第一驱动信号K1-S1进行逻辑与(AND)运算后，生成的第二驱动信号K1-S2*中，高电平信号的时长减少，开关K1处于导通的时长缩短，开关K1处于断路的时长增加。
本申请实施例中，逻辑信号Sr可以包括脉冲信号，延时单元407E对逻辑信号Sr进行延时处理，生成延时逻辑信号Sdr时，可以对所述逻辑信号中脉冲的上升沿或者下降沿中的至少一个滞后预设时长。本申请实施例中，对于脉冲信号的上升沿的延时处理过程，与对脉冲信号的下降沿的延时处理过程可以是独立的。例如，延时单元407E可以将逻辑信号Sr中脉冲信号的上升沿延时第一延迟时长t1，生成延时逻辑信号Sdr。延时单元407E也可以将逻辑信号Sr中脉冲信号的下降沿延时第二延迟时长t2，生成延时逻辑信号Sdr。
延时单元407E还可以将逻辑信号Sr中脉冲信号的上升沿延时第一延迟时长t1，以及将下降沿延时第二延迟时长t2。作为一种举例，如图11所示，延时单元407E可以对幅值为第三电压的信号Sr的上升沿延时第一延迟时长t1，以及对逻辑信号Sr的下降沿延时第二延迟时长t2。幅值为第三电压的信号Sr的持续时长为d1。可选地，若t2小于t1，下降沿延时时长大于上升沿延时时长，低电平信号持续时长会变大，延时单元407E生成的延时逻辑信号Sdr的持续时长d2可以大于幅值为第三电压的信号Sr的持续时长d1，持续时长增加量为△t＝t1-t2。
在实际场景中，两个幅值为第三电压的信号之间为幅值为第四电压的信号。延时单元407E增大幅值为第三电压的逻辑信号的持续时长的操作中，会使幅值为第四电压的逻辑信号的持续时长减少。
本申请实施例中，信号调整单元407可以将延时逻辑信号Sdr和第一驱动信号S1进行逻辑与(AND)运算，得到第二驱动信号S2，可使各开关的导通时刻被滞后第一延迟时长t1，导通时长也被进一步减少。
根据一些实施例，本申请提供的LLC转换器可以为半桥LLC谐振电路。其中，开关电路402可以包括串联连接的两个开关，如串联连接的第一开关Q1和第二开关Q2。如图12所示，第一开关Q1和第二开关Q2可以串联连接在第一电源401的正负极之间。控制电路407可以分别与第一开关Q1和第二开关Q2连接，用于驱动第一开关Q1和第二开关Q2。
本申请提供的LLC转换器中，开关电路402可以包括全桥谐振转换器的原边开关。开关电路402中的开关可以是绝缘栅极双极型晶体管、集成门极换流晶闸管、门极可关断晶闸管、硅控整流器器件、结型场效应管器件、金属氧化物半导体场效应管控制的晶闸管器件、基于氮化镓的功率器件等。
谐振槽403主要包括谐振电感Lr、谐振电容Cr。根据一些实施例，谐振槽403中也可以包括励磁电感Lp。如图12所示，谐振槽403的一端可以与第一节点M1连接，另一端可以与转换电路404连接。其中，第一节点M1为第一开关Q1和第二开关Q2之间的连接点。谐振槽403可以经由转换电路404和控制电路407与第一电源401的一极连接，以及经由开关电路402与第一电源401的另一极连接。
转换电路404可以包括原极绕组Np、变压器Tr和副极绕组Nr。在一些实施例中，转换电路404可以包括一个或多个副极绕组Sr。其中，原极绕组Np的一端与谐振槽403连 接，另一端与控制电路407连接。
整流电路405可以将转换电路404提供的交流电流转换为直流电流。整流电路405中可以由多个二极管组成，或者由多个开关组成。整流电路405的两个输入端可以与转换电路404中的副极绕组Nr绕组连接。如图12中示出的整流电路405可以两个并联的支路，每个支路包括串联的两个二极管，其中，两个二极管中第一二极管的阴极与第二二极管的阳极连接，第一二极管和第二二极管之间的连接点为整流电路405的输入端。两个支路上的第一二极管的阴极相连，两个支路上的第二二极管的阳极相连。
输出电路406可以包括输出电容C1。输出电容C1的一端可以分别连接整流电路405两个支路中的各第一二极管的阴极，输出电容C1的另一端可以分别连接整流电路405两个支路中的各第二二极管的阳极。
LLC转换器处于稳态阶段时，输出电路406可以为稳定地为负载408提供第二电压。输出电路406至少包括输出电容，输出电容更可以连接在整流电路405的两端之间。在不同的应用场景中，输出电路406可以包括由电容组成的输出滤波器。
控制电路407中，电流采集单元407A可以包括电流互感器(current transformer，CT)采样电路，与谐振槽403耦合。CT采样电路可以包括第一绕组Nr1、第二绕组Nr2以及多个二极管。第一绕组Nr1的一端可以与转换电路404中原极绕组Np连接，另一端与第一电源401连接。多个二极管可以在两个支路上，每个支路上可以包括串联的两个二极管，其中两个二极管中的第三二极管的阴极和第四二极管的阳极连接，第四二极管的阴极与逻辑信号生成电源407B连接，第三二极管的阳极与地线连接。例如图12中的二极管D7的阴极与二极管D5的阳极连接，二极管D8的阴极与二极管D6的阳极连接。第二绕组Nr2的两端分别连接每个支路上的两个二极管之间的连接点。根据一些实施例，CT采样电路也可以是任意一种电流互感器。本申请对此不作过多限定。
逻辑信号生成单元407B可以包括至少一个比较器，比较器的第一输入端与CT采样电路的输出端连接。如图12所示，CT采样电路两个支路上的第四二极管的阴极为CT采样电路的输出端，比较器的第一输入端可以与两个支路上的第四二极管的阴极连接。比较器的第二输入端连接与电流阈值对应的固定电平。
第一驱动信号生成单元407C可以包括脉宽调制(pulse width modulation，PWM)电路。第二驱动信号生成单元407D可以包括多个逻辑门电路，如逻辑与门电路。每个逻辑与门电路的第一输入端与比较器的输出端连接，每个逻辑与门电路的第二输入端与PWM电路的输出端连接，各逻辑与门电路的输出端可以与相应的开关连接。
延时单元407E可以包括延时电路，如图13所示，延时电路的输入端可以与比较器的输出端连接，延时电路的输出端可以与逻辑与门电路的第一输入端连接。
一种可能的实施方式中，控制电路407包括的多个单元可以实施为集成电路，例如，例如可编程门阵列(field programmable gate array，FPGA)电路或者数字信号处理(digital signal processing，DSP)电路。示例性的，如图14所示，控制电路407可以包括FPGA电路或者DSP电路，利用FPGA电路或者DSP电路实施延时单元407E、第一驱动信号生成单元407C、第二驱动信号生成单元407D等的功能及作用。
本申请实施例中输出电路406、整流电路405、转换电路404、谐振槽403、开关电路402、第一电源401等多个部分的具体构成元件以及元件之间的连接方式，仅用于举例说明，并不作为所述多个部分的具体限定。本申请实施例提供的LLC转换器的软启动方法可 以应用于较为广泛的LLC转换器或者LLC电路中。本领域技术人员可以根据实际应用场景，调整LLC转换器中所述多个部分的具体构成元件及元件之间的连接方式，以实现本申请实施例中所述多个部分的功能及作用。
本申请实施例还提供一种LLC转换器软启动方法，可以应用于前述任意一种LLC转换器。该方法可以由控制器或控制电路执行，如图15所示，该方法可以包括如下步骤：
步骤S1501，控制器检测所述谐振槽的电流。
步骤S1502，控制器根据所述电流和第一驱动信号生成第二驱动信号，所述第一驱动信号为具有固定频率和固定占空比的脉冲信号，所述第二驱动信号为脉冲信号，在所述电流大于或等于电流阈值的时段内，所述第二驱动信号为预设电平，所述预设电平的第二驱动信号用于关断所述开关电路中的功率开关，在所述电流小于所述电流阈值的时间段内，所述第二驱动信号与所述第一驱动信号相同。
步骤S1503，控制器将所述第二驱动信号输出给所述开关电路，所述第二驱动信号用于驱动所述开关电路中的功率开关。
本申请实施例中，控制器可以根据谐振槽中的电流情况以及第一驱动信号的电平情况，生成第二驱动信号，并将第二驱动信号输出给开关电路，对开关电路中的开关进行驱动。下面以第一电平的信号可以驱动开关处于导通状态，第二电平的信号可以驱动开关处于断路状态作为举例。若谐振槽的电流小于电流阈值并且第一驱动信号为第一电平时，生成的第二驱动信号的电平为第一电平。若谐振槽中的电流大于或等于电流阈值并且第一驱动信号为第一电平时，生成的第二驱动信号的电平为第二电平。可见，控制器可以在谐振槽中的电流大于或等于电流阈值时，用第二电平的第二驱动信号使开关处于断路状态，避免谐振槽中产生电流冲击，保护LLC转换器中的功率开关。若第一驱动信号为第二电平时，不论谐振槽中的电流是否大于电流阈值，控制器生成的第二驱动信号的电平为第二电平，也使得开关处于断路状态。可选地，所述固定频率为所述谐振槽对应的谐振频率。
应理解的是，本申请实施例提供的软启动方法，不仅可以应用于启动阶段，还可以用于稳态阶段。由于LLC转换器进入稳态阶段后，谐振槽中通常不会产生较大的电流冲击，因而控制器生成的第二驱动信号与第一驱动信号相同，也即具有固定频率和固定占空比的脉冲信号。
一种可能的实施方式中，控制器在所述根据所述电流和第一驱动信号生成第二驱动信号之前，还可以执行如下操作：
根据所述电流和所述电流阈值，生成逻辑信号，其中，所述逻辑信号为脉冲信号，所述逻辑信号中脉冲的宽度对应的时间内，所述电流小于所述电流阈值，所述逻辑信号中相邻两个脉冲之间的时间间隔内，所述电流大于或等于所述电流阈值。
所述根据所述电流和第一驱动信号生成第二驱动信号，包括：
对所述逻辑信号和所述第一驱动信号进行逻辑与运算处理，得到所述第二驱动信号。
例如，控制器可以将所述逻辑信号和所述第一驱动信号进行逻辑与(AND)运算，将运算结果作为所述第二驱动信号。
本申请实施例中，LLC转换器中可以包括一个PWM电路，用于生成稳态阶段开关的驱动信号。PWM电路在LLC转换器启动阶段和稳态阶段生成定频定占空比的第一驱动信号。由控制器可以通过调整对稳态阶段开关的驱动信号，得到启动阶段开关的驱动信号，并且不改变PWM电路的工作模式，可以降低LLC转换器控制复杂度，提升控制效率。
一种可能的实施方式中，所述逻辑信号为脉冲信号；控制器在所述根据所述电流和第二驱动信号生成第一驱动信号之前，还可以对所述逻辑信号中脉冲的上升沿或者下降沿中的至少一个滞后预设时长。
本申请实施例中，控制器通过将逻辑信号进行延时处理，使控制器在根据所述逻辑信号对所述第一驱动信号进行调整时，所述第二驱动信号中导通时段的起始时刻被滞后，从而延迟LLC转换器中开关导通。
为便于理解本申请提供的LLC转换器软启动方法，图16所示控制器或者控制电路实施该方法的控制过程，下面以控制电路407为例进行说明。
控制电路407中电流采集单元407A可以检测LLC转换器的谐振槽403的电流信号，并将电流信号传输至逻辑信号生成单元407B。示例性的，电流采集单元407A可以包括CT采样电路。逻辑信号生成单元407B可以包括比较器。逻辑信号生成单元407B可以将电流信号和电流阈值进行比较，并输出逻辑信号。例如，低电平表示过流，高电平表示不过流。如图16所示，逻辑信号生成单元输出的信号中A时刻与B时刻之间的信号幅值为高电平，B时刻与C时刻之间的信号幅值为低电平。
逻辑信号生成单元407B可以实时输出表征谐振槽403中电流是否出现过流情况的信号。延时单元407E对该信号进行延时处理。例如，将幅值为高电平的信号SA-B的上升沿延迟第一延迟时长t1，或者，将所述信号SA-B的下降沿延迟第二延迟时长t2。延时单元407E还可以即对所述信号SA-B的上升沿延时第一延时时长t1，也对所述信号SA-B的下降沿延时第二延时时长t2。根据一些实施例，第一延时时长t1和第二延时时长t2可以配置到延时单元407E中。
控制电路407中的第一驱动信号生成单元407C可以包括PWM电路，能够生成定频定占空比的PWM信号。该PWM信号可用于在LLC转换器稳态阶段驱动开关电路402中的开关。其中，PWM电路生成PWM信号的频率可以约为LLC转换器谐振槽的固有频率。假设，开关电路402中包括两个开关。PWM电路可以分别生成两个开关相应的第一驱动信号，驱动信号的占空比可以约为50％。如图16所示，第一驱动信号生成单元407C生成的两路第一驱动信号。
控制电路407中的第二驱动信号生成单元407D可以将根据延时单元407E生成的逻辑信号，对第一驱动信号生成单元407C生成的各开关的稳态阶段驱动信号进行调整。
第二驱动信号生成单元407D可以包括两个逻辑与门(AND)电路，一个逻辑与门(AND)电路可以将延时单元407E生成的逻辑信号和两个开关中的第一开关相应的第一驱动信号进行处理，生成第一开关相应的第二驱动信号。另一个逻辑与门(AND)电路可以将延时单元407E生成的逻辑信号和第二开关的第二驱动信号也进行处理，生成第二开关相应的第二驱动信号。
第二驱动信号生成单元407D也可以包括驱动单元407F，用于将逻辑与门(AND)电路生成的第二驱动信号施加到相应的开关上，实现驱动各开关。可见，控制电路407可以依据谐振槽403中的电流过流情况，灵活地调整各开关的导通时长以及导通时刻，通过闭环控制，避免谐振槽403产生电流冲击影响各开关的性能。
在一应用场景中，开关电路402中包括两个开关。电流阈值被配置为谐振槽403的额定电流的2倍。第一延时时长t1被配置为谐振槽403对应谐振频率(固有频率)的5％，第二延时时长被配置为0。第一驱动信号的占空比被配置为50％，第一驱动信号的频率与 谐振槽403对应的谐振频率相等。
在LLC转换器启动阶段和稳态阶段，控制电路407都可以执行本申请实施例提供的LLC转换器软启动方法过程中，谐振槽403中的电流(I_Resonant)变化情况，谐振电容Cr的电压(V_Resonant)变化情况以及输出电容C1的输出电压(Vout)变化情况，如图17所示。
图18示出控制电路407执行本申请实施例提供的LLC转换器软启动方法过程中，在LLC转换器启动阶段中，局部时间内的谐振槽403中的电流(I_Resonant)变化情况，谐振电容Cr的电压(V_Resonant)变化情况以及输出电容C1的输出电压(Vout)变化情况。图19示出在LLC转换器启动阶段中，控制电路407驱动开关管的信号(对应前述实施例中第二驱动信号生成单元407D生成的第二驱动信号)。
图20示出LLC转换器稳态阶段中，局部时间内的谐振槽403中的电流(I_Resonant)变化情况，谐振电容Cr的电压(V_Resonant)变化情况以及输出电容C1的输出电压(Vout)变化情况。谐振槽403中的电流进入稳态，电流波形成正弦波形。图21示出在LLC转换器稳态阶段中，控制电路407驱动开关管的信号(对应前述实施例中稳态驱动单元信号生成单元407C生成的驱动信号)。
本申请实施例中，在LLC转换器启动阶段，输出电压在55ms内平稳上升到稳态值，相比于相关技术用软启动阶段利用高频开关频率的软启动方法，本申请实施例中软启动时间是前述相关技术中软启动时间的40％。并且，谐振槽403中的电流被限制在一定范围(电流阈值)内，使得谐振槽403中的具有尽可能地大，但不损坏器件的电流，从而使输出电压得以快速建立起来。
本申请实施例还提供一种LLC转换器的启动装置，如图22所示，装置可以包括采集模块2201、存储器2202、处理器2203。
采集模块2201与LLC转换器中谐振槽403耦合，用于检测谐振槽403中的电流。采集模块2201可以包括CT采样电路，并将检测到的电流信号传输至处理器2203。
存储器2202与处理器2203耦合，用于程序指令或代码；
处理器2203与采样模块2201耦合，可以执行存储器2201存储的程序指令或代码，实现前述实施例根据谐振槽中的电流，生成第二驱动信号的过程。
一种可能的设计中，采集模块2201可以集成在处理器2203中，也即处理器2203可以包括采集模块2201，使得处理器2203具有采集模块2201的功能。
另外，本申请实施例还提供一种计算机程序产品，包括程序指令或代码，当程序指令在处理器或控制器上运行时，程序指令用于使处理器或控制器执行上述描述的根据本申请各种示例性实施方式的一种LLC转换器的软启动方法中的步骤。
本申请实施例还提供存储前述计算机程序产品的可读存储介质。本申请实施例提供的可读存储介质可以是，但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内， 则本申请也意图包含这些改动和变型在内。

Claims (17)

  1. 一种电感-电感-电容LLC转换器，其特征在于，包括：控制电路，以及依次耦合连接的开关电路、谐振槽，所述开关电路中包括功率开关；
    所述控制电路分别与所述开关电路和所述谐振槽耦合；
    所述控制电路用于：
    检测所述谐振槽的电流；
    根据所述电流和第一驱动信号生成第二驱动信号，所述第一驱动信号为具有固定频率和固定占空比的脉冲信号，所述第二驱动信号为脉冲信号，在所述电流大于或等于电流阈值的时段内，所述第二驱动信号为预设电平，所述预设电平的第二驱动信号用于关断所述开关电路中的功率开关，在所述电流小于所述电流阈值的时间段内，所述第二驱动信号与所述第一驱动信号相同；
    将所述第二驱动信号输出给所述开关电路，所述第二驱动信号用于驱动所述开关电路中的功率开关。
  2. 如权利要求1所述的转换器，其特征在于，所述控制电路包括电流采集单元、逻辑信号生成单元、第一驱动信号生成单元和第二驱动信号生成单元；
    所述电流采集单元，用于检测所述谐振槽的电流；
    所述第一驱动信号生成单元，用于生成所述第一驱动信号；
    所述逻辑信号生成单元，用于根据所述电流和所述电流阈值，生成逻辑信号，其中，所述逻辑信号为脉冲信号，所述逻辑信号中脉冲的宽度对应的时间内，所述电流小于所述电流阈值，所述逻辑信号中相邻两个脉冲之间的时间间隔内，所述电流大于或等于所述电流阈值；
    所述第二驱动信号生成单元，用于基于所述逻辑信号和所述第一驱动信号，生成所述第二驱动信号。
  3. 如权利要求2所述的转换器，其特征在于，所述第二驱动信号生成单元，具体用于：
    对所述逻辑信号和所述第一驱动信号进行逻辑与运算处理，得到所述第二驱动信号，其中，所述电流小于所述电流阈值的时间内，所述逻辑信号的电平为高电平，所述电流大于或等于所述电流阈值的时间内，所述逻辑信号的电平为低电平。
  4. 如权利要求2所述的转换器，其特征在于，所述逻辑信号为脉冲信号，所述控制电路还包括延时单元；
    所述延时单元，用于对所述逻辑信号中脉冲的上升沿或者下降沿中的至少一个滞后预设时长；
    所述第二驱动信号生成单元，还用于：基于延时后的所述逻辑信号和所述第一驱动信号，生成所述第二驱动信号。
  5. 如权利要求1-4任一所述的转换器，其特征在于，所述固定频率为所述谐振槽对应的谐振频率。
  6. 一种控制电路，其特征在于，应用于驱动电感-电感-电容LLC转换器，所述LLC转换器包括开关电路和谐振槽，所述控制电路包括电流采集单元、逻辑信号生成单元、第一驱动信号生成单元和第二驱动信号生成单元；
    所述电流采集单元用于检测所述谐振槽的电流；
    所述第一驱动信号生成单元，用于生成第一驱动信号，所述第一驱动信号为具有固定频率和固定占空比的脉冲信号；
    所述逻辑信号生成单元，用生成逻辑信号，其中，所逻辑信号为脉冲信号，所述逻辑信号中脉冲的宽度对应的时间内，所述电流小于所述电流阈值，所述逻辑信号中相邻两个脉冲之间的时间间隔内，所述电流大于或等于所述电流阈值；
    所述第二驱动信号生成单元，用于基于所述逻辑信号和所述第一驱动信号，生成所述第二驱动信号，所述第二驱动信号为第二脉冲信号，在所述电流大于或等于电流阈值的时段内，所述第二驱动信号为预设电平，所述预设电平的第二驱动信号用于关断所述开关电路中的功率开关，在所述电流小于所述电流阈值的时间段内，所述第二驱动信号与所述第一驱动信号相同。
  7. 如权利要求6所述的电路，其特征在于，所述第二驱动信号生成单元，具体用于：
    对所述逻辑信号和所述第一驱动信号进行逻辑与运算处理，得到所述第二驱动信号，其中，所述电流小于所述电流阈值的时间内，所述逻辑信号的电平为高电平，所述电流大于或等于所述电流阈值的时间内，所述逻辑信号的电平为低电平。
  8. 如权利要求6所述的电路，其特征在于，所述控制电路还包括延时单元；
    所述延时单元，用于对所述逻辑信号中脉冲的上升沿或者下降沿中的至少一个滞后预设时长；
    所述第二驱动信号生成单元，还用于：基于延时后的所述逻辑信号和所述第一驱动信号，生成所述第二驱动信号。
  9. 如权利要求6-8任一所述的电路，其特征在于，所述固定频率为所述谐振槽对应的谐振频率。
  10. 如权利要求6-8任一所述的电路，其特征在于，所述逻辑信号生成单元包括比较器，所述比较器的第一输入端与所述电流采集单元的输出端连接，所述比较器的第二输入端连接固定电平，所述固定电平为所述电流阈值对应的电平，所述比较器的输出端与所述第二驱动信号生成电源连接，或者与所述延时单元连接。
  11. 一种电感-电感-电容LLC转换器软启动方法，其特征在于，所述LLC转换器包括谐振槽和开关电路，所述方法包括：
    检测所述谐振槽的电流；
    根据所述电流和第一驱动信号生成第二驱动信号，所述第一驱动信号为具有固定频率和固定占空比的脉冲信号，所述第二驱动信号为脉冲信号，在所述电流大于或等于电流阈值的时段内，所述第二驱动信号为预设电平，所述预设电平的第二驱动信号用于关断所述开关电路中的功率开关，在所述电流小于所述电流阈值的时间段内，所述第二驱动信号与所述第一驱动信号相同；
    将所述第二驱动信号输出给所述开关电路，所述第二驱动信号用于驱动所述开关电路中的功率开关。
  12. 如权利要求11所述的方法，其特征在于，在所述根据所述电流和第一驱动信号生成第二驱动信号之前，所述方法还包括：
    根据所述电流和所述电流阈值，生成逻辑信号，其中，所述逻辑信号为脉冲信号，所述逻辑信号中脉冲的宽度对应的时间内，所述电流小于所述电流阈值，所述逻辑信号中相 邻两个脉冲之间的时间间隔内，所述电流大于或等于所述电流阈值；
    所述根据所述电流和第一驱动信号生成第二驱动信号，包括：
    对所述逻辑信号和所述第一驱动信号进行逻辑与运算处理，得到所述第二驱动信号，其中，所述电流小于所述电流阈值的时间内，所述逻辑信号的电平为高电平，所述电流大于或等于所述电流阈值的时间内，所述逻辑信号的电平为低电平。
  13. 如权利要求11所述的方法，其特征在于，在所述根据所述电流和第二驱动信号生成第一驱动信号之前，所述方法还包括：
    对所述逻辑信号中脉冲的上升沿或者下降沿中的至少一个滞后预设时长。
  14. 如权利要求11-13任一所述的方法，其特征在于，所述固定频率为所述谐振槽对应的谐振频率。
  15. 一种电感-电感-电容LLC转换器控制装置，其特征在于，所述装置包括处理器和存储器，所述存储器用于存储程序、指令或代码，所述处理器用于执行所述存储器中的程序、指令或代码，完成如权利要求11-13任一项所述的方法。
  16. 一种非易失性计算机可读存储介质，其特征在于，用于存储计算机程序，所述计算机程序通过处理器进行加载来执行如权利要求11-13任一项所述的方法。
  17. 一种芯片，其特征在于，所述芯片与存储器耦合，用于调用执行所述存储器中存储的计算机程序指令，以使如权利要求11-13任一项所述的方法被执行。
PCT/CN2021/077115 2021-02-20 2021-02-20 一种llc转换器、控制电路、软启动方法、装置及芯片 WO2022174429A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202180093486.6A CN116848772A (zh) 2021-02-20 2021-02-20 一种llc转换器、控制电路、软启动方法、装置及芯片
PCT/CN2021/077115 WO2022174429A1 (zh) 2021-02-20 2021-02-20 一种llc转换器、控制电路、软启动方法、装置及芯片
EP21926147.6A EP4280442A4 (en) 2021-02-20 2021-02-20 LLC CONVERTER, CONTROL CIRCUIT, SOFT STARTING METHOD AND APPARATUS, AND CHIP
US18/451,963 US20230396176A1 (en) 2021-02-20 2023-08-18 Llc converter, control circuit, soft start method, apparatus, and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/077115 WO2022174429A1 (zh) 2021-02-20 2021-02-20 一种llc转换器、控制电路、软启动方法、装置及芯片

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/451,963 Continuation US20230396176A1 (en) 2021-02-20 2023-08-18 Llc converter, control circuit, soft start method, apparatus, and chip

Publications (1)

Publication Number Publication Date
WO2022174429A1 true WO2022174429A1 (zh) 2022-08-25

Family

ID=82931962

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/077115 WO2022174429A1 (zh) 2021-02-20 2021-02-20 一种llc转换器、控制电路、软启动方法、装置及芯片

Country Status (4)

Country Link
US (1) US20230396176A1 (zh)
EP (1) EP4280442A4 (zh)
CN (1) CN116848772A (zh)
WO (1) WO2022174429A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101656465A (zh) * 2008-08-22 2010-02-24 通嘉科技股份有限公司 控制电路、电源转换器以及控制方法
CN101666823A (zh) * 2008-09-04 2010-03-10 力博特公司 一种用于llc谐振电路的电流检测方法及装置
CN101969267A (zh) * 2010-09-20 2011-02-09 中国电子科技集团公司第五十八研究所 一种兆赫兹级全桥软开关变换器
CN103066853A (zh) * 2012-12-24 2013-04-24 成都芯源系统有限公司 控制电路、开关电源及其控制方法
CN103647461A (zh) * 2013-12-06 2014-03-19 西南交通大学 一种ac-dc串联谐振矩阵变换器的控制方法及装置
CN105099157A (zh) * 2015-08-12 2015-11-25 阳光电源股份有限公司 一种llc谐振变换器及其软启动方法
EP3553929A1 (en) * 2018-04-11 2019-10-16 Vestel Elektronik Sanayi ve Ticaret A.S. Circuit and method for driving a resonant converter

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506929B (zh) * 2011-11-15 2015-11-01 Green Solution Tech Co Ltd 諧振式轉換電路及諧振控制器
CN103138590B (zh) * 2011-12-02 2017-02-08 中兴通讯股份有限公司 谐振电路限流保护方法和装置
JP6135271B2 (ja) * 2013-04-19 2017-05-31 富士電機株式会社 スイッチング電源装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101656465A (zh) * 2008-08-22 2010-02-24 通嘉科技股份有限公司 控制电路、电源转换器以及控制方法
CN101666823A (zh) * 2008-09-04 2010-03-10 力博特公司 一种用于llc谐振电路的电流检测方法及装置
CN101969267A (zh) * 2010-09-20 2011-02-09 中国电子科技集团公司第五十八研究所 一种兆赫兹级全桥软开关变换器
CN103066853A (zh) * 2012-12-24 2013-04-24 成都芯源系统有限公司 控制电路、开关电源及其控制方法
CN103647461A (zh) * 2013-12-06 2014-03-19 西南交通大学 一种ac-dc串联谐振矩阵变换器的控制方法及装置
CN105099157A (zh) * 2015-08-12 2015-11-25 阳光电源股份有限公司 一种llc谐振变换器及其软启动方法
EP3553929A1 (en) * 2018-04-11 2019-10-16 Vestel Elektronik Sanayi ve Ticaret A.S. Circuit and method for driving a resonant converter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4280442A4 *

Also Published As

Publication number Publication date
EP4280442A1 (en) 2023-11-22
US20230396176A1 (en) 2023-12-07
EP4280442A4 (en) 2024-03-13
CN116848772A (zh) 2023-10-03

Similar Documents

Publication Publication Date Title
CN107979288B (zh) 强迫式零电压开关反激变换器
CN107979287B (zh) 用于主开关切换转换的零电压开关式逆变器
US10164536B2 (en) Voltage conversion circuit and method, and multiphase parallel power system
US8456868B2 (en) Controller for a resonant switched-mode power converter
CN101604910B (zh) 功率因数校正电路
JP6706811B2 (ja) スナバ回路及びそれを用いた電力変換システム
US9735686B2 (en) Device for avoiding hard switching in resonant converter and related method
EP2365622A1 (en) Method and circuit for controlling a switched-mode power converter with fast transient response
US10910953B2 (en) Welding power supply with extended voltage characteristic
JPWO2013146340A1 (ja) インバータ装置
CN111953204B (zh) 高电压增益直流升压变换器及其控制方法
Lim et al. Energy recovery snubber circuit for a dc–dc push–pull converter
US11239746B2 (en) Two-stage converter and method for starting the same, LLC converter, and application system
CN107134929B (zh) 双向直流变换器及双向直流变换控制方法
US6744647B2 (en) Parallel connected converters apparatus and methods using switching cycle with energy holding state
JPH07163139A (ja) 高効率スイッチング方式レギュレータ
US10826377B2 (en) Power converter, control circuit and control method for the same
Duarte et al. Single-stage high power factor step-up/step-down isolated AC/DC converter
WO2022174429A1 (zh) 一种llc转换器、控制电路、软启动方法、装置及芯片
CN107659155B (zh) 双向直流变换器及双向直流变换控制方法
TWI653813B (zh) 強迫式零電壓開關返馳變換器及其運行方法
CN107147325B (zh) 电流馈电型高功率脉冲电流源
CN113922653A (zh) 一种隔离Boost全桥变换器的全数字软起动控制方法
Delshad et al. A new active clamping soft switching weinberg converter
Khan et al. Dual-Buck Three-Phase AC-AC Converter Without Commutation Problems

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21926147

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180093486.6

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 2021926147

Country of ref document: EP

Effective date: 20230817

NENP Non-entry into the national phase

Ref country code: DE