WO2022172642A1 - Élément d'imagerie à semi-conducteur, procédé d'imagerie et dispositif électronique - Google Patents

Élément d'imagerie à semi-conducteur, procédé d'imagerie et dispositif électronique Download PDF

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Publication number
WO2022172642A1
WO2022172642A1 PCT/JP2021/048923 JP2021048923W WO2022172642A1 WO 2022172642 A1 WO2022172642 A1 WO 2022172642A1 JP 2021048923 W JP2021048923 W JP 2021048923W WO 2022172642 A1 WO2022172642 A1 WO 2022172642A1
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electrodes
charge
transfer direction
electrode
substantially perpendicular
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PCT/JP2021/048923
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English (en)
Japanese (ja)
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博亮 村上
直子 石川
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022172642A1 publication Critical patent/WO2022172642A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present technology relates to a solid-state imaging device, an imaging method, and an electronic device, and more particularly to a solid-state imaging device, an imaging method, and an electronic device capable of improving charge transfer efficiency.
  • CMOS Complementary Metal Oxide Semiconductor
  • the global shutter function is realized by simultaneously transferring the charge (electrons) obtained by the PD (Photodiode) in each pixel to the memory of the charge holding section and holding it.
  • the electric charge held in the memory is further transferred to an FD (Floating Diffusion) and converted into an electric signal, and the obtained electric signal is read out.
  • This technology has been developed in view of this situation, and is intended to improve the transfer efficiency of electric charges.
  • a solid-state imaging device includes a photoelectric conversion unit that converts incident light into charges, and a charge holding unit that holds the charges and transfers the held charges,
  • the charge holding section has a plurality of electrodes for applying a voltage to the charge holding section, arranged in a direction substantially perpendicular to the charge transfer direction.
  • a solid-state imaging device is provided with a photoelectric conversion unit that converts incident light into electric charges, and a charge holding unit that holds the charges and transfers the held charges.
  • the charge holding portion is provided with a plurality of electrodes for applying a voltage to the charge holding portion, which are aligned in a direction substantially perpendicular to the transfer direction of the charge.
  • An imaging method includes a photoelectric conversion unit that converts incident light into an electric charge, and an electric charge holding unit that holds the electric charge and transfers the electric charge.
  • a holding section has a plurality of electrodes for applying a voltage to the charge holding section arranged in a direction substantially perpendicular to the charge transfer direction. At the time, among the plurality of electrodes arranged in a direction substantially perpendicular to the transfer direction, each of the electrodes is turned on in order from the central electrode to the outer electrodes with a higher voltage applied. including several steps.
  • a photoelectric conversion unit that converts incident light into electric charge
  • a charge holding unit that holds the charge and transfers the held charge
  • the charge holding unit is a solid-state imaging device having a plurality of electrodes for applying a voltage to the charge holding portion arranged in a direction substantially perpendicular to the charge transfer direction, wherein the charge is transferred in the charge transfer direction and Among the plurality of electrodes arranged in a substantially vertical direction, each electrode is turned on by applying a higher voltage in order from the central electrode to the outer electrodes.
  • An electronic device is a solid-state imaging device that includes a photoelectric conversion unit that converts incident light into electric charges, and a charge holding unit that holds the charges and transfers the held charges. and the charge holding section has a plurality of electrodes for applying a voltage to the charge holding section arranged in a direction substantially perpendicular to the charge transfer direction.
  • a solid-state imaging device in a third aspect of the present technology, includes a photoelectric conversion unit that converts incident light into electric charges, and an electric charge holding unit that holds the electric charges and transfers the held electric charges.
  • the charge holding portion is provided with a plurality of electrodes for applying a voltage to the charge holding portion, which are aligned in a direction substantially perpendicular to the charge transfer direction.
  • FIG. 3A and 3B are diagrams showing a configuration of a pixel and an arrangement example of electrodes; FIG. It is a figure explaining transfer of an electron. It is a figure which shows the structural example of the cross section of a pixel. It is a figure which shows the circuit structural example of a pixel. It is a figure explaining the drive of an electrode. 4 is a flowchart for explaining imaging processing; It is a figure which shows the circuit structural example of a pixel. It is a figure which shows the example of arrangement
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system;
  • FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;
  • a plurality of electrodes for applying a voltage to the memory of the charge holding unit are divided in a direction substantially perpendicular to the charge transfer direction, and the edge of the memory in the direction substantially perpendicular to the charge transfer direction is provided. It is possible to realize a drive that moves charges (electrons) from the memory to the center of the memory. As a result, the charge transfer efficiency can be improved, and more charges can be transferred to the FD.
  • FIG. 1 is a diagram showing a configuration example of an embodiment of a solid-state imaging device to which the present technology is applied.
  • the solid-state imaging device 11 is composed of a solid-state imaging device such as a CMOS image sensor having a global shutter function, and has a pixel array section 21, a vertical driving section 22, a column signal processing section 23, and a control section 24.
  • the pixel array section 21 has a plurality of pixels 31 that are two-dimensionally arranged in row and column directions. It should be noted that only some of the pixels 31 are denoted by reference numerals in order to make the drawing easier to see. Also, the row direction here is the horizontal direction in the drawing, and the column direction is the vertical direction in the drawing.
  • a control line 32 wired along the pixel row is provided for each pixel row composed of a plurality of pixels 31 arranged in the row direction. are connected by a control line 32 .
  • the pixels 31 and the vertical driving section 22 are connected by one control line 32 here for the sake of clarity, the pixels 31 and the vertical driving section 22 are actually connected by a plurality of control lines 32. It is
  • a vertical signal line 33 wired along the pixel column is provided for each pixel column composed of a plurality of pixels 31 arranged in the column direction. It is connected to the signal processing unit 23 by a vertical signal line 33 .
  • Each pixel 31 receives and photoelectrically converts incident light to generate a pixel signal, which is an electrical signal having a magnitude corresponding to the amount of received light, and outputs the pixel signal to the vertical signal line 33 .
  • the vertical driving section 22 controls driving of each pixel 31 via the control line 32 .
  • the vertical driving section 22 realizes a global shutter function by simultaneously starting and ending exposure operations for all the pixels 31 .
  • the column signal processing unit 23 performs various signal processing such as AD (Analog to Digital) conversion on the pixel signal output from each pixel 31, thereby generating an image signal composed of digital pixel signals of each pixel. and output.
  • AD Analog to Digital
  • the control unit 24 includes a timing generator or the like, generates a timing signal, and controls the vertical driving unit 22 and the column signal processing unit 23 based on the generated timing signal.
  • Each pixel 31 is provided with, for example, a PD (photodiode) 61, an overflow gate 62, a charge holding section 63, an FD (floating diffusion) 64, and a signal generation section 65, as shown in FIG.
  • a PD photodiode
  • an overflow gate 62 a charge holding section 63
  • an FD floating diffusion
  • a signal generation section 65 as shown in FIG. 2
  • the horizontal direction (X direction) indicates the row direction
  • the vertical direction (Y direction) indicates the column direction.
  • the PD 61 functions as a photoelectric conversion unit that converts (photoelectric conversion) incident light into charges, more specifically, electrons, according to the amount of incident light. A charge generated by photoelectric conversion in the PD 61 is transferred from the PD 61 to the charge holding unit 63 .
  • the overflow gate 62 is made up of a transistor and is turned on (conducting state) by a driving signal OFG supplied from the vertical driving section 22 via the control line 32 .
  • the overflow gate 62 discharges excess charges generated by the PD 61 .
  • the charge holding section 63 has a memory (not shown) formed on the semiconductor substrate constituting the pixel array section 21, and electrodes 71a to 74c arranged above the memory on the surface of the semiconductor substrate. .
  • the charge holding unit 63 temporarily holds the charges (electrons) transferred from the PD 61 in memory, and transfers (outputs) the charges held in the memory to the FD 64 .
  • the FD 64 functions as an output charge holding section that holds charges transferred from the memory of the charge holding section 63 .
  • the signal generation unit 65 is a pixel transistor unit composed of a transistor or the like, and functions as a charge-voltage conversion unit that outputs a voltage signal corresponding to the amount of charge held (accumulated) in the FD 64 to the vertical signal line 33 as a pixel signal. do. That is, the signal generation unit 65 generates a pixel signal by converting the charge held in the FD 64 into a pixel signal.
  • a structure in which a charge holding portion 63 is provided between the PD 61 and the FD 64 in each pixel 31 (hereinafter also referred to as a GS (Global Shutter) structure) enables realization of a global shutter function. .
  • Electrodes 71a to 74c are provided.
  • the right direction in the figure is the direction of charge transfer from the memory to the FD 64, and a plurality of electrode groups consisting of a plurality of electrodes arranged in a direction substantially perpendicular to the charge transfer direction are arranged in the transfer direction. are placed.
  • rectangular electrodes 71a to 71c are arranged in a direction substantially perpendicular to the transfer direction (in the drawing, the electrode closest to the PD 61 in the transfer direction, that is, the electrode closest to the PD 61 in the charge transfer path). in the vertical direction). More specifically, the electrodes 71a to 71c are arranged in a direction substantially perpendicular to the transfer direction and parallel to the surface of the semiconductor substrate on which the pixels 31 are formed.
  • the electrode 71a is arranged in the center (center), and the electrodes 71b and 71c are arranged in a direction substantially perpendicular to the transfer direction. , that is, at both ends of the electrode 71a.
  • a rectangular region is formed by these three electrodes 71a to 71c.
  • one rectangular electrode is divided into three in the direction substantially perpendicular to the transfer direction to form the electrodes 71a to 71c.
  • the vertical driving section 22 supplies gate signals TR1a to TR1c to the electrodes 71a to 71c via the control line 32, thereby turning the electrodes 71a to 71c on or off.
  • the electrodes 71a to 71c are simply referred to as the electrodes 71 when there is no particular need to distinguish between them.
  • the gate signals TR1a to TR1c are simply referred to as the gate signal TR1 when there is no particular need to distinguish them.
  • the ON state means that the gate signal TR1 is set to a higher level, and a voltage higher than a predetermined reference voltage such as the GND level is applied to the electrode 71, that is, the region immediately below the electrode 71 in the memory. It is in the applied state.
  • the off state means that the gate signal TR1 is set to a lower low level and a predetermined reference voltage (lower voltage) is applied to the electrode 71, that is, the region immediately below the electrode 71 in the memory. state.
  • a predetermined reference voltage lower voltage
  • rectangular electrodes 72a to 72c, electrodes 73a to 73c, and electrodes 74a to 74c are arranged in the same manner as the electrodes 71a to 71c.
  • the electrodes 72a to 72c are arranged adjacent to the electrodes 71a to 71c in the charge transfer direction, and these three electrodes 72a to 72c form a rectangular region.
  • the electrode 72a is arranged in the center, and the electrodes 72b and 72c are arranged in a direction substantially perpendicular to the transfer direction with respect to the electrode 72a. are arranged on the outside (both ends) of
  • the vertical driving section 22 supplies gate signals TR2a to TR2c to the electrodes 72a to 72c via the control line 32, thereby turning the electrodes 72a to 72c on or off.
  • the electrodes 72a to 72c are also simply referred to as the electrodes 72 when there is no particular need to distinguish between the electrodes 72a to 72c.
  • the gate signals TR2a to TR2c are simply referred to as gate signals TR2 when there is no particular need to distinguish them.
  • the electrodes 73a to 73c are arranged adjacent to the electrodes 72a to 72c in the charge transfer direction, and these three electrodes 73a to 73c form a rectangular region. ing.
  • the electrode 73a is arranged in the center, and the electrodes 73b and 73c are arranged in a direction substantially perpendicular to the transfer direction with respect to the electrode 73a. are arranged on the outside (both ends) of
  • the vertical drive unit 22 supplies the gate signals TR3a to TR3c to the electrodes 73a to 73c via the control line 32, thereby turning the electrodes 73a to 73c on or off.
  • the electrodes 73a to 73c are also simply referred to as the electrodes 73 when there is no particular need to distinguish between them.
  • the gate signals TR3a to TR3c will be simply referred to as the gate signal TR3 when there is no particular need to distinguish them.
  • the electrodes 74a to 74c are arranged adjacent to the electrodes 73a to 73c in the charge transfer direction, and these three electrodes 74a to 74c form a rectangular region.
  • the electrodes 74 a to 74 c are positioned closest to the FD 64 (transfer direction side) in the transfer direction among the electrodes provided in the charge holding unit 63 .
  • the electrode 74a is arranged in the center, and the electrodes 74b and 74c are arranged outside the electrode 74a in a direction substantially perpendicular to the transfer direction. (both ends).
  • the vertical driving section 22 supplies gate signals TR4a to TR4c to the electrodes 74a to 74c via the control line 32, thereby turning the electrodes 74a to 74c on or off.
  • the electrodes 74a to 74c are simply referred to as the electrodes 74 when there is no particular need to distinguish between them.
  • the gate signals TR4a to TR4c will be simply referred to as the gate signal TR4 when there is no particular need to distinguish them.
  • the position near the center (center) of the charge holding portion 63 in the direction substantially perpendicular to the charge transfer direction is simply referred to as the center or the central position.
  • the positions away from the center of the charge holding portion 63 in the direction substantially perpendicular to the charge transfer direction are also referred to as the outer and outer positions.
  • each pixel 31 not only are a plurality of electrodes for transferring charges (electrons) held in the memory of the charge holding portion 63 arranged in the transfer direction, but also the electrodes are arranged in the transfer direction. A plurality of them are also arranged in a substantially vertical direction (hereinafter also simply referred to as a vertical direction).
  • the electrodes 72 and 73 are shown enlarged.
  • the circles marked with the letter "e-" represent electrons (charges), and the diagonal arrows in the figure represent the direction of the electric field produced in the region of the memory.
  • a rightward arrow drawn in the left part indicates the transfer direction.
  • the vertical drive unit 22 supplies gate signals such that, for example, the center electrode is turned on first, and the outer electrodes are turned on after a short delay.
  • FIG. 3 shows a cross-sectional view of the memory portion of the charge holding portion 63 when viewed from the column direction.
  • portions corresponding to those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the horizontal direction indicates the row direction, that is, the X direction (horizontal direction) in FIG. 2, and the vertical direction in FIG. 3 indicates the potential depth.
  • the area between the PD 61 and the FD 64 is the memory area of the charge holding unit 63, and particularly the areas indicated by the arrows Q11 to Q14 are the areas directly below the electrodes 71 to 74.
  • the gate signal TR1 is set to low level (Low), and the gate signals TR2 to TR4 are set to high level (High). Therefore, compared to the area directly under the electrode 71 indicated by the arrow Q11, the potential in the area directly under the electrodes 72 to 74 indicated by the arrows Q12 to Q14 is deeper, and a gradient is formed. .
  • a region adjacent to the FD 64 is an inter-pixel barrier region and is electrically separated from the adjacent pixels 31 .
  • the vertical drive unit 22 once turns on the electrodes 72 to 74 in the transfer direction, and then turns off the electrodes 71 to 74 in order, thereby transferring electrons (charges) to the FD 64. Forward.
  • the vertical driving unit 22 turns on the central electrodes such as the electrodes 72a and 73a, and then turns on the electrodes 72b, 72c, 73b and 73c. is turned on from the off state.
  • the electrodes 71 to 74 are not divided in the vertical direction. That is, for example, the electrodes 71a to 71c are one electrode 71 that is not divided, that is, one electrode 71 in which the electrodes 71a to 71c are connected. shall be one electrode.
  • the electrodes are rectangular, electrons (charges) are less likely to be transferred in the end regions between the electrodes arranged in the transfer direction, such as the region between the electrodes 71 and 72 in the outer portion (end portion) of the memory. turn into.
  • the present technology provides a plurality of electrodes in the vertical direction, it is possible to generate a sufficiently large electric field from the outside of the memory area toward the center.
  • the cross-sectional configuration of the pixel 31 is as shown in FIG. 4, for example.
  • portions corresponding to those in FIG. 1 or 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • a PD 61 and the like are formed in a P-type well region 152 formed on an N-type semiconductor substrate 151 to form a pixel 31 .
  • an N-type semiconductor region 153 and an N-type semiconductor region 154 are formed in the well region 152 .
  • a PD 61 is formed by the N-type semiconductor region 154 and the P-type semiconductor region (well region 152) surrounding the N-type semiconductor region 154. As shown in FIG.
  • the upper surface of the pixel 31 in the figure is the incident surface of light.
  • Charges (electrons) are generated at the PN junction at the interface with the N-type semiconductor region and accumulated in the N-type semiconductor region 154 .
  • a P-type semiconductor region 155 is formed above the N-type semiconductor region 154 in the figure, and pinning by the P-type semiconductor region 155 suppresses generation of dark current.
  • a region between the N-type semiconductor region 153 and the N-type semiconductor region 154 in the well region 152 and the silicon oxide film and the gate formed on the upper side of the region in the drawing constitute the overflow gate 62 . Excess charges accumulated in the N-type semiconductor region 154 are discharged to the signal line OFD connected to the N-type semiconductor region 153 via the overflow gate 62 and the N-type semiconductor region 153 .
  • an N-type semiconductor region 156 is formed adjacent to the N-type semiconductor region 154, and this N-type semiconductor region 156 serves as a charge holding portion that holds charges (electrons) transferred from the PD 61. 63 memory. Furthermore, a P-type semiconductor region 157 for pinning a semiconductor interface in the N-type semiconductor region 156 is formed on the upper side of the N-type semiconductor region 156 in the well region 152 in the figure.
  • an N-type semiconductor region 158 is formed near the N-type semiconductor region 156
  • an N-type semiconductor region 159 is formed near the N-type semiconductor region 158 .
  • a portion of the N-type semiconductor region 158 in the well region 152 functions as the FD64. Therefore, a pixel signal corresponding to the amount of charge transferred from the N-type semiconductor region 156 as a memory and held in the N-type semiconductor region 158 as the FD 64 is generated by the signal generation unit 65 connected to the N-type semiconductor region 158. and output to the vertical signal line 33 .
  • Silicon oxide films 161 to 164 are provided on the semiconductor substrate, more specifically, on the surface of the well region 152 on the light incident side, and the upper portions of the silicon oxide films 161 to 164 are provided. , electrodes 71 to 74 are provided.
  • the electrodes 71 to 74 are arranged above the N-type semiconductor region 156 and the P-type semiconductor region 157 .
  • the N-type semiconductor region 156 as a memory is positioned directly below the electrodes 71 to 74 . More specifically, in FIG. 4, for example, the electrodes 71c, 71a, and 71b are arranged in order from the front side to the depth direction.
  • the vertical drive unit 22 supplies high-level (High) gate signals TR1 to TR4 to the electrodes 71 to 74 through the control line 32 to turn on the electrodes 71 to 74, the N-type A higher voltage is applied to the semiconductor region 156 by the electrodes 71 to 74 .
  • the electrodes 71 to 74, the silicon oxide films 161 to 164, the N-type semiconductor region 156, and the P-type semiconductor region 157 constitute the charge holding portion 63.
  • a reset transistor 165 is formed by a region between the N-type semiconductor region 158 and the N-type semiconductor region 159 in the well region 152 and a silicon oxide film and a gate formed on the upper side of the region in the drawing.
  • the reset transistor 165 is turned on (conduction state) or off (non-conduction state) by a reset signal RST supplied from the vertical driving section 22 via the control line 32 .
  • the reset transistor 165 When the reset transistor 165 is turned on, the charges held in the N-type semiconductor regions 158 and 156 are transferred to the signal line Vrst connected to the N-type semiconductor region 159 via the N-type semiconductor region 159 . , that is, discharged to the constant voltage source VDD.
  • the solid-state imaging device 11 having the pixels 31 configured as shown in FIG. It is a surface-type solid-state imaging device in which electrodes 71 to 74 are formed.
  • FIG. 5 is a diagram showing the circuit configuration (circuit diagram) of the pixel 31 having the configuration shown in FIG.
  • portions corresponding to those in FIG. 2 or 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the PD 61 is connected to the overflow gate 62 and the charge holding portion 63 .
  • the PD 61 receives incident light and photoelectrically converts it, and when the electrode 71 of the charge holding portion 63 is turned on, stores the charges (electrons) generated by the photoelectric conversion in the memory (N-type semiconductor) of the charge holding portion 63 . area 156).
  • the charge holding unit 63 has electrodes 71a to 74c and an N-type semiconductor region 156, temporarily holds charges (electrons) transferred from the PD 61, and transfers the held charges to the FD 64. Forward.
  • each of the electrodes 74c is depicted as a transistor. In this case, more specifically, each of the electrodes 71a to 74c functions as a gate (gate electrode) of the transistor.
  • the FD 64 is connected to the charge holding section 63 and holds charges transferred from the memory (N-type semiconductor region 156) of the charge holding section 63.
  • the reset transistor 165 and the amplification transistor 191 are connected to the FD64, and in particular the FD64 is connected to the gate of the amplification transistor 191.
  • a selection transistor 192 is connected to the amplification transistor 191 .
  • the amplification transistor 191 and the selection transistor 192 constitute the signal generation section 65 described above.
  • the amplification transistor 191 forms a source follower circuit with a constant current source connected via the vertical signal line 33, and outputs a pixel signal corresponding to the amount of charge held in the FD 64, that is, the potential.
  • the selection transistor 192 is turned on (conduction state) or off (non-conduction state) by a selection signal SEL supplied from the vertical driving section 22 via the control line 32 .
  • a pixel signal indicating a level corresponding to the charge accumulated in the FD 64 is transmitted from the amplification transistor 191 to the column via the selection transistor 192 and the vertical signal line 33 . It is output to the signal processing unit 23 .
  • polygonal lines L11 to L22 indicate the gate signals TR1a to TR4c supplied to the electrodes 71a to 74c.
  • the polygonal lines L11 through L22 indicate the ON/OFF states of the electrodes 71a through 74c.
  • the upwardly convex portions of the polygonal lines L11 to L22 in the drawing indicate sections in which the gate signal is at a high level (High), that is, sections in which the electrodes are in an ON state.
  • the downwardly convex portions of the polygonal lines L11 to L22 in the drawing indicate sections in which the gate signal is at a low level (Low), that is, sections in which the electrodes are in an off state. .
  • the vertical drive unit 22 first moves the electrodes 71a, 72a, 73a, and 74a located in the center at time t1. is turned on.
  • the electrodes 71b, 72b, 73b, 74b, 71c, 72c, 73c, and 74c positioned on the end side (outside) in the vertical direction substantially perpendicular to the transfer direction remain off. It is
  • the vertical drive section 22 moves the electrodes 71b, 72b, 73b, 74b, 71c, 72c, 73c, and 71b, 72b, 73b, 74b, 71c, 72c, 73c, and 71b, 72b, 73b, 74b, 71c, 72c, 73c, 71b, 72b, 73b, 74b, 71b, 72b, 73b, 73c, 73c, 71b, 71c, 71c, 72c, 73c, and 73c.
  • 74c is turned on.
  • the vertical driving section 22 sequentially turns on the plurality of electrodes 71a to 74c arranged in the vertical direction, from the center electrode to the outer electrodes, during charge transfer. That is, when each electrode is turned on, the vertical drive unit 22 controls both ends of the center electrode, that is, the electrodes located outside in the vertical direction, with respect to the timing at which the center electrode is turned on. is turned on.
  • an oblique electric field is generated from the end portion of the memory (N-type semiconductor region 156) in the vertical direction toward the center, and electrons (charges) on the outside are generated. It will be transferred in the transfer direction while being drawn to the center.
  • the vertical driving section 22 turns off the electrode 71b and the electrode 71c, which are positioned closest to the PD 61 and are positioned on the outer side of the three electrodes 71 arranged in the vertical direction.
  • the vertical driving section 22 turns off the electrode 71a located in the center.
  • the outer electrode 71 to the central electrode 71 are sequentially turned off. That is, in the region immediately below the electrodes 71, all the electrodes 71 are turned off while the charges (electrons) are attracted from the outside to the center, that is, the charges are prevented from moving outward.
  • the memory (N-type semiconductor region 156) of the charge holding portion 63 and the PD 61 are electrically separated, so that the exposure operation (exposure period) in the PD 61 is It is finished.
  • the vertical driving section 22 turns off the electrodes 72b and 72c, which are located on the outer side of the three electrodes 72 adjacent to the electrode 71 turned off and arranged in the vertical direction. , the vertical driving section 22 turns off the central electrode 72a.
  • the vertical driving unit 22 turns off the electrodes 73b and 73c, which are located outside of the three electrodes 73 adjacent to the electrode 72 turned off. 22 turns off the central electrode 73a.
  • the vertical driving section 22 turns off the electrodes 74b and 74c, which are located outside the three electrodes 74 adjacent to the electrode 73 that has been turned off. turns off the central electrode 74a.
  • these electrodes are turned off in order from the electrode 71 closest to the PD 61 to the electrode 74 closest to the FD 64 . By doing so, it is possible to prevent the charge in the memory (N-type semiconductor region 156) from moving in the direction opposite to the transfer direction, thereby improving the charge transfer efficiency.
  • the vertical drive unit 22 turns off the electrodes arranged in the vertical direction in order from the outer electrode to the center electrode. That is, when turning off each electrode, the vertical driving section 22 delays the timing of turning off the electrode positioned in the center with respect to the timing of turning off the electrode positioned on the outer side.
  • the charge transfer efficiency can be improved and more charges can be transferred to the FD 64 .
  • step S11 the vertical driving section 22 starts imaging.
  • the vertical driving unit 22 supplies high-level gate signals TR1 to TR4 to the electrodes 71 to 74 through the control line 32, and supplies high-level gate signals TR1 to TR4 to the reset transistor 165 through the control line 32. of reset signal RST.
  • the electrodes 71 to 74 and the reset transistor 165 are turned on, and the charges held in the PD 61, the memory (N-type semiconductor region 156) of the charge holding section 63, and the FD 64 are discharged. That is, the PD 61, the memory of the charge holding unit 63, and the FD 64 are reset. Note that the PD 61 may be reset by turning on the overflow gate 62 .
  • the electrodes 71 to 74 and the reset transistor 165 are turned off, and the exposure (exposure period) of the PD 61, that is, the imaging of an image by the PD 61 is started.
  • the PD 61 During the exposure period, the PD 61 generates charges (electrons) by photoelectrically converting light incident from the outside, and accumulates the obtained charges.
  • the vertical drive unit 22 supplies a high-level (High) selection signal SEL to the selection transistor 192 via the control line 32 at an appropriate timing to turn on the selection transistor 192, thereby setting the pixel 31 to the selected state.
  • step S12 the vertical drive unit 22 supplies high-level gate signals TR1 to TR4 to the electrodes 71 to 74 via the control line 32, thereby turning on the electrodes in order from the central electrode. state.
  • step S12 the driving at time t1 and time t2 described with reference to FIG. 6 is performed.
  • charges (electrons) generated by the PD 61 are transferred to the memory (N-type semiconductor region 156) of the charge holding section 63 and held.
  • step S13 the vertical driving unit 22 supplies low-level gate signals TR1 to TR4 to the electrodes 71 to 74 through the control line 32, thereby turning off the electrodes in order from the electrode on the PD 61 side. state.
  • step S13 driving from time t3 to time t10 described with reference to FIG. 6 is performed.
  • the exposure in the PD 61 is completed, and the charge held in the memory (N-type semiconductor region 156) of the charge holding section 63 is transferred to the FD 64.
  • the signal generation unit 65 supplies pixel signals corresponding to the amount of charges accumulated in the FD 64 to the column signal processing unit 23 via the vertical signal line 33 .
  • step S14 the column signal processing unit 23 generates an image signal by performing various signal processing such as AD conversion on the pixel signal supplied from the signal generation unit 65 of each pixel 31 via the vertical signal line 33. and output.
  • various signal processing such as AD conversion
  • the image signal is output in this manner, the imaging process ends.
  • the solid-state imaging device 11 appropriately turns on and off the electrodes 71 to 74 that are arranged in the transfer direction and in a direction substantially perpendicular to the transfer direction. transfer to By doing so, the charge transfer efficiency can be improved.
  • ⁇ Modification 1 of the first embodiment> ⁇ Example of pixel circuit configuration>
  • the vertical driving section 22 and each of the electrodes 71a to 74c are individually connected by the control line 32 in order to realize the driving described with reference to FIG. .
  • the number of control lines 32 and gate signals corresponding to the number of electrodes provided in the charge holding portion 63 is required.
  • the vertical drive unit 22 generates gate signals for the number of electrodes and supplies them to each electrode, the number of transistors provided inside the vertical drive unit 22 increases.
  • the circuit scale of the solid-state imaging device 11 may be reduced by reducing the number of transistors and wiring by shifting the timing of supplying the gate signal, that is, the timing of turning on and off the electrode using a resistor. .
  • a resistor is connected to the outer electrode.
  • a pixel 31 shown in FIG. 8 has a PD 61, an overflow gate 62, a charge holding portion 63, an FD 64, a reset transistor 165, an amplification transistor 191, and a selection transistor 192.
  • the circuit configuration of the pixel 31 is shown in FIG. is the same as the previous example.
  • resistors 211 to 214 are provided between the electrodes provided outside in the vertical direction and the vertical driving section 22 . These resistors 211 to 214 may be provided inside the vertical driving section 22 , or may be provided inside the pixel array section 21 or the pixels 31 .
  • the vertical driving section 22 and the electrodes 71a to 71c are basically connected by one control line 32 (hereinafter also referred to as a control line 32A).
  • a resistor 211 is provided between each of 71b and electrode 71c.
  • a resistor 211 is provided between each of the electrodes 71b and 71c and the vertical drive section 22, but the electrode 71a is directly connected to the vertical drive section 22 via the control line 32A. No resistor is provided between 71 a and the vertical driving section 22 .
  • the vertical driving section 22 outputs one gate signal TR1 to the control line 32A.
  • the gate signal TR1 output from the vertical driving section 22 is supplied to the electrode 71a via the control line 32A and is also supplied to the electrodes 71b and 71c via the control line 32A and the resistor 211.
  • the timing at which the gate signal TR1 changes at the electrodes 71b and 71c is different from the timing at which the gate signal TR1 changes at the electrode 71a. Different from the changing timing. That is, when the gate signal TR1 is supplied via the resistor 211, the rise of the gate signal TR1 is slowed down and the fall of the gate signal TR1 is sped up.
  • the vertical driving section 22 outputs the gate signal TR1 indicated by the polygonal line L11 in FIG.
  • the electrode 71a is supplied with the gate signal TR1 having the waveform indicated by the polygonal line L11. That is, at the electrode 71a, the gate signal TR1 rises at time t1 and falls at time t4.
  • the gate signal TR1 when the vertical drive unit 22 outputs the gate signal TR1 indicated by the polygonal line L11 in FIG. 6, the gate signal TR1 having the waveforms indicated by the polygonal line L12 and the polygonal line L13 in FIG. 6 is observed at the electrode 71b and the electrode 71c. be done. That is, at the electrodes 71b and 71c, the gate signal TR1 rises at time t2 and falls at time t3.
  • the resistor 211 is provided between the electrodes 71b and 71c and the vertical driving section 22, and the same gate signal TR1 is supplied from the vertical driving section 22 to the electrodes 71a to 71c.
  • the same control can be achieved as in the configuration shown.
  • resistors 212 to 214 are provided for the electrodes 72 to 74, respectively.
  • control line 32 (hereinafter also referred to as the control line 32B).
  • a resistor 212 is provided between the control line 32B and each of the electrodes 72b and 72c, but no resistor is provided between the electrode 72a and the vertical driving section 22.
  • control line 32C one control line 32 (hereinafter also referred to as control line 32C).
  • a resistor 213 is provided between the control line 32C and each of the electrodes 73b and 73c, but no resistor is provided between the electrode 73a and the vertical driving section 22.
  • control line 32D The vertical driving section 22 and the electrodes 74a to 74c are connected by one control line 32 (hereinafter also referred to as control line 32D).
  • a resistor 214 is provided between the control line 32D and each of the electrodes 74b and 74c, but no resistor is provided between the electrode 74a and the vertical driving section 22.
  • the vertical drive unit 22 outputs gate signals having waveforms shown in broken lines L11, L14, L17, and L20 in FIG. 6 to the control lines 32A to 32D. By doing so, the driving described with reference to FIG. 6 can be realized.
  • the number of transistors and wiring can be reduced, so the circuit scale of the solid-state imaging device 11 can be reduced as a whole.
  • each electrode is not limited to this, and the shape formed by a plurality of electrodes arranged in the vertical direction may be a shape other than a rectangle.
  • the charge holding portion 63 when the charge holding portion 63 is viewed from the direction perpendicular to the surface of the semiconductor substrate on which the charge holding portion 63 is provided, the plurality of charge holding portions provided in the charge holding portion 63 The electrodes may form an arrow-shaped shape that protrudes toward the charge transfer direction.
  • the structure of the pixel 31 shown in FIG. 9 is different from the structure of the pixel 31 shown in FIG. 2 in that electrodes 241a to 244c are provided instead of the electrodes 71 to 74, and the other points are shown in FIG. It has the same configuration as the pixel 31 .
  • electrodes 241a to 244c for applying a voltage to the memory (N-type semiconductor region 156) of the charge holding portion 63 according to the gate signal supplied from the vertical driving portion 22 through the control line 32 are Located at the top of memory.
  • the electrodes 241a to 241c are arranged in a direction substantially perpendicular to the transfer direction (vertical direction) on the side of the PD 61 closest to the transfer direction in the charge holding portion 63 . More specifically, the electrodes 241a to 241c are arranged in a direction substantially perpendicular to the transfer direction and parallel to the surface of the semiconductor substrate on which the pixels 31 are formed.
  • the electrode 241a is arranged in the center (center), and the electrodes 241b and 241c are arranged outside in the vertical direction, that is, at both ends of the electrode 241a.
  • the positions of the ends of the electrodes 241a to 241c in the transfer direction are positioned closer to the transfer direction as they are closer to the central position.
  • the right end portion of the electrode 241a in the drawing has a triangular shape convex toward the transfer direction.
  • the right end portion of the electrode 241b in the drawing is inclined downward to the right in the drawing.
  • the electrodes 241a to 241c are also simply referred to as the electrodes 241 when there is no particular need to distinguish between them.
  • the electrodes 242a to 242c are arranged adjacent to the electrodes 241a to 241c in the charge transfer direction. Particularly, among the three electrodes 242a to 242c arranged in the vertical direction, the electrode 242a is arranged in the center, and the electrodes 242b and 242c are arranged outside in the vertical direction, that is, at both ends of the electrode 242a.
  • These three electrodes 242a to 242c form an arrow-shaped shape convex in the transfer direction.
  • the positions of the ends of the electrodes 242a to 242c on the transfer direction side are positioned closer to the transfer direction side as they are closer to the center.
  • the positions of the ends of the electrodes 242a to 242c on the opposite side to the transfer direction are positioned closer to the transfer direction as they are closer to the center.
  • the electrodes 242a to 242c are also simply referred to as the electrodes 242 when there is no particular need to distinguish between them.
  • the electrodes 243a to 243c are arranged adjacent to the electrodes 242a to 242c in the charge transfer direction.
  • the electrode 243a is arranged in the center, and the electrodes 243b and 243c are arranged outside in the vertical direction.
  • Each of these three electrodes 243a to 243c has the same shape as each of the electrodes 242a to 242c, and the electrodes 243a to 243c form an arrow-shaped shape convex toward the transfer direction. ing.
  • the electrodes 243a to 243c are also simply referred to as the electrodes 243 when there is no particular need to distinguish between them.
  • the electrodes 244a to 244c are arranged adjacent to the electrodes 243a to 243c in the charge transfer direction.
  • the electrode 244a is arranged in the center, and the electrodes 244b and 244c are arranged outside in the vertical direction.
  • Each of these three electrodes 244a to 244c has the same shape as each of the electrodes 242a to 242c, and the electrodes 244a to 244c form an arrow-shaped shape convex toward the transfer direction. ing.
  • the electrodes 244a to 244c are also simply referred to as the electrodes 244 when there is no particular need to distinguish between them.
  • the vertically arranged electrodes form an arrow shape.
  • the ends of the electrodes are convex in the transfer direction.
  • the shapes of the ends of the electrodes 241 to 244 in the direction parallel to the transfer direction in the memory are shown on the left side of the figure, for example.
  • An electric field is formed along
  • the electrode 242 and the electrode 243 are shown enlarged on the left side of FIG.
  • the circles marked with the letter "e-" represent electrons (charges), and the diagonal arrows in the figure represent the direction of the electric field produced in the region of the memory.
  • a rightward arrow drawn in the left part indicates the transfer direction.
  • the vertical driving unit 22 performs the same driving as described with reference to FIG.
  • the vertical driving section 22 supplies the gate signals TR1a to TR4c having the waveforms shown in FIG.
  • the overflow gate 62 and the electrodes 71 to 74 described above are arranged on the layer on which the PD 61 and the FD 64 of the semiconductor substrate are formed, opposite to the light incident side. adjacent to the side.
  • the PD 61 and the charge holding portion 63 are stacked on the semiconductor substrate so as to be aligned in the direction perpendicular to the semiconductor substrate. That is, the PD 61 and the charge holding portion 63 are formed in different layers.
  • FIG. 10 shows a configuration example of the cross section of the pixel 31 when the solid-state imaging device 11 has a laminated GS structure.
  • parts corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the semiconductor substrate is provided with at least layers LY0 to LY2, and an on-chip lens 301 is formed adjacent to layer LY0 on the lowest side in the drawing.
  • a color filter is formed on layer LY0.
  • a layer LY1 made of a semiconductor material is formed on the surface of the layer LY0 opposite to the on-chip lens 301 side, and the PD 61 is formed on this layer LY1.
  • light from the outside enters from the bottom to the top in the figure. That is, light from the outside enters the PD 61 through the on-chip lens 301 and color filters.
  • a layer LY2 is provided on the opposite side of the layer LY1 to the layer LY0, and the layer LY2 includes at least the above-described overflow gate 62, charge holding unit 63, FD 64, reset transistor 165, and amplification transistor 191. is formed.
  • a vertical trench gate 302 is connected to the PD 61 , and charges (electrons) accumulated in the PD 61 are transferred to the memory 303 of the charge holding unit 63 by the vertical trench gate 302 .
  • the memory 303 corresponds to the N-type semiconductor region 156 in the example of FIG. 4 and temporarily holds the charges transferred from the PD 61. Further, electrodes 71 to 74 are formed on the upper side of the memory 303 in the drawing, for example, in the same arrangement as in FIG.
  • the vertical driving section 22 applies voltages to the electrodes 71 to 74 by the gate signals TR1 to TR4, an electric field similar to that in FIG. Charge is transferred to FD64.
  • the electrodes 241 to 244 illustrated in FIG. 9 may be provided over the memory 303 .
  • a light shielding film 304 for preventing light from entering the memory 303 is provided between the PD 61 and the memory 303 .
  • the charge transfer efficiency can be improved as in the case of the solid-state imaging device 11 having the surface-type GS structure.
  • the present technology is not limited to application to solid-state imaging devices.
  • this technology can be applied to solid-state imaging devices such as digital still cameras and video cameras, portable terminal devices with imaging functions, and copiers that use solid-state imaging devices as image reading units. It is applicable to all electronic devices that use imaging devices.
  • the solid-state imaging device may be formed as a single chip, or may be a module having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together.
  • FIG. 11 is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.
  • An imaging device 401 in FIG. 11 includes an optical unit 411 including a lens group, etc., a solid-state imaging device (imaging device) 412 adopting the configuration of the solid-state imaging device 11 in FIG. Processor) circuit 413 .
  • the imaging device 401 also includes a frame memory 414 , a display section 415 , a recording section 416 , an operation section 417 and a power supply section 418 .
  • DSP circuit 413 , frame memory 414 , display unit 415 , recording unit 416 , operation unit 417 , and power supply unit 418 are interconnected via bus line 419 .
  • the optical unit 411 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 412 .
  • the solid-state imaging device 412 converts the amount of incident light imaged on the imaging surface by the optical unit 411 into an electric signal on a pixel-by-pixel basis, and outputs the electric signal as a pixel signal.
  • the display unit 415 is composed of a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays moving images or still images captured by the solid-state imaging device 412 .
  • a recording unit 416 records a moving image or still image captured by the solid-state imaging device 412 in a recording medium such as a hard disk or a semiconductor memory.
  • the operation unit 417 issues operation commands for various functions of the imaging device 401 under the user's operation.
  • the power supply unit 418 appropriately supplies various power supplies as operating power supplies for the DSP circuit 413, the frame memory 414, the display unit 415, the recording unit 416, and the operation unit 417 to these supply targets.
  • FIG. 12 is a diagram showing a usage example of an image sensor using the solid-state imaging device 11 described above.
  • An image sensor using the solid-state imaging device 11 described above can be used, for example, in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays as follows.
  • ⁇ Devices that capture images for viewing purposes, such as digital cameras and mobile devices with camera functions.
  • Devices used for transportation such as in-vehicle sensors that capture images behind, around, and inside the vehicle, surveillance cameras that monitor running vehicles and roads, and ranging sensors that measure the distance between vehicles.
  • Devices used in home appliances such as TVs, refrigerators, air conditioners, etc., to take pictures and operate devices according to gestures ⁇ Endoscopes, devices that perform angiography by receiving infrared light, etc.
  • Equipment used for medical and healthcare purposes such as surveillance cameras for crime prevention and cameras for personal authentication
  • microscopes used for beauty such as microscopes used for beauty
  • Sports such as action cameras and wearable cameras for use in sports ⁇ Cameras, etc. for monitoring the condition of fields and crops , agricultural equipment
  • the technology (the present technology) according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure is implemented as a device mounted on any type of moving object such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 13 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on information on the inside and outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs coordinated control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 14 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield in the vehicle interior, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • Forward images acquired by the imaging units 12101 and 12105 are mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 14 shows an example of the imaging range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the course of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the configurations described above.
  • the solid-state imaging device 11 shown in FIG. 1 can be used as the imaging unit 12031, and the charge transfer efficiency can be improved.
  • this technology is not limited to application to solid-state imaging devices that detect the distribution of the amount of incident visible light and capture an image. In a broad sense, it can be applied to solid-state imaging devices (physical quantity distribution detectors) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture images. be.
  • solid-state imaging devices physical quantity distribution detectors
  • fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture images.
  • the present technology is applicable not only to solid-state imaging devices but also to semiconductor devices in general having other semiconductor integrated circuits.
  • Embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.
  • this technology can also be configured as follows.
  • a photoelectric conversion unit that converts incident light into an electric charge
  • a charge holding unit that holds the charge and transfers the held charge
  • the charge holding section has a plurality of electrodes for applying a voltage to the charge holding section arranged in a direction substantially perpendicular to the charge transfer direction.
  • the drive section turns on the electrodes during the transfer of the charge, and then, among the plurality of electrodes arranged in a direction substantially perpendicular to the transfer direction, turns on the electrodes from the outer electrode to the central electrode.
  • the solid-state imaging device according to (2) in which the electrodes are sequentially turned off by applying a lower voltage to the electrodes.
  • (3) The solid-state imaging device according to (3), wherein the plurality of electrodes arranged in a direction substantially perpendicular to the transfer direction are arranged in the transfer direction.
  • the drive unit turns on the electrodes, and then turns off the plurality of electrodes arranged in the transfer direction in order from the electrode on the photoelectric conversion unit side.
  • a resistor is provided between the outer electrode of the plurality of electrodes arranged in a direction substantially perpendicular to the transfer direction and the driving section, (3) to (5), wherein the driving unit turns on or off the plurality of electrodes by supplying the same signal to the plurality of electrodes arranged in a direction substantially perpendicular to the transfer direction; ).
  • (1) to (1) to ( 6) The solid-state imaging device according to any one of items.
  • (8) The solid-state imaging device according to any one of (1) to (7), wherein three or more electrodes are provided as the plurality of electrodes arranged in a direction substantially perpendicular to the transfer direction.
  • a photoelectric conversion unit that converts incident light into an electric charge
  • a charge holding unit that holds the charge and transfers the held charge
  • the charge holding section has a plurality of electrodes for applying a voltage to the charge holding section arranged in a direction substantially perpendicular to the charge transfer direction. During the charge transfer, a higher voltage is applied to each of the electrodes in order from the central electrode to the outer electrodes among the plurality of electrodes arranged in a direction substantially perpendicular to the transfer direction.
  • a resistor is provided between a driving unit that applies a voltage to the electrode and the outer electrode among the plurality of electrodes arranged in a direction substantially perpendicular to the transfer direction; (10) or (11), wherein the driving unit supplies the same signal to the plurality of electrodes arranged in a direction substantially perpendicular to the transfer direction to turn on or off the plurality of electrodes; ).
  • (13) (9) to (9) to ( 12) The imaging method according to any one of items.
  • a photoelectric conversion unit that converts incident light into an electric charge
  • a solid-state imaging device comprising: a charge holding unit that holds the charge and transfers the held charge; The electronic device, wherein the charge holding section has a plurality of electrodes for applying a voltage to the charge holding section arranged in a direction substantially perpendicular to the charge transfer direction.
  • 11 solid-state imaging device 21 pixel array section, 22 vertical driving section, 23 column signal processing section, 31 pixel, 32 control line, 33 vertical signal line, 61 PD, 63 charge holding section, 64 FD, 71a to 71c, 71 electrode , 72a to 72c, 72 electrodes, 73a to 73c, 73 electrodes, 74a to 74c, 74 electrodes, 156 N-type semiconductor region

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Abstract

La présente technologie concerne un élément d'imagerie à semi-conducteur, un procédé d'imagerie et un dispositif électronique qui permettent d'obtenir une augmentation de l'efficacité de transfert de charge. L'élément d'imagerie à semi-conducteur comprend une unité de conversion photoélectrique pour convertir une lumière entrée en charge, et une unité de maintien de charge pour maintenir une charge et transférer la charge maintenue. L'unité de maintien de charge comprend une pluralité d'électrodes agencées dans une direction sensiblement perpendiculaire à la direction de transfert de charge pour appliquer une tension à l'unité de maintien de charge. La présente technologie peut être appliquée à des dispositifs électroniques.
PCT/JP2021/048923 2021-02-15 2021-12-28 Élément d'imagerie à semi-conducteur, procédé d'imagerie et dispositif électronique WO2022172642A1 (fr)

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Citations (5)

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JP2005050951A (ja) * 2003-07-31 2005-02-24 Toshiba Corp 固体撮像装置および電荷転送装置
JP2009021316A (ja) * 2007-07-11 2009-01-29 Brainvision Inc 固体撮像素子の画素構造
JP2010182759A (ja) * 2009-02-04 2010-08-19 Panasonic Corp 電荷転送装置
JP2015065271A (ja) * 2013-09-25 2015-04-09 ソニー株式会社 固体撮像素子およびその動作方法、並びに電子機器およびその動作方法

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