WO2022166126A1 - 标准单元版图模板以及半导体结构 - Google Patents

标准单元版图模板以及半导体结构 Download PDF

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Publication number
WO2022166126A1
WO2022166126A1 PCT/CN2021/107779 CN2021107779W WO2022166126A1 WO 2022166126 A1 WO2022166126 A1 WO 2022166126A1 CN 2021107779 W CN2021107779 W CN 2021107779W WO 2022166126 A1 WO2022166126 A1 WO 2022166126A1
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Prior art keywords
gate
electrical connection
pattern
standard cell
connection structure
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PCT/CN2021/107779
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English (en)
French (fr)
Inventor
汪配焕
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长鑫存储技术有限公司
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Priority to EP21859332.5A priority Critical patent/EP4060738A4/en
Priority to KR1020227027198A priority patent/KR20220124767A/ko
Priority to JP2022546369A priority patent/JP7446446B2/ja
Priority to US17/505,683 priority patent/US11853673B2/en
Publication of WO2022166126A1 publication Critical patent/WO2022166126A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a standard cell layout template and a semiconductor structure.
  • the standard cell library is the basis of integrated circuit design.
  • the integrated circuit design based on the standard cell library can carry out logic synthesis and layout layout and wiring, and improve the design efficiency of the circuit.
  • the standard cell library includes several pre-designed standard cell layout templates.
  • the integrated circuit designer or circuit design synthesis tool can call the standard cell layout template in the standard cell library according to the design requirements to complete the layout design of the integrated circuit. .
  • the present disclosure provides a standard cell layout template and a semiconductor structure.
  • a first aspect of the present disclosure provides a standard cell layout template, including a first well region and a second well region arranged along a first direction; a first gate pattern is located in the first well region and along the first well region. extending in one direction for defining a first gate; a second gate pattern located in the second well region and extending along the first direction for defining a second gate; a gate electrical connection pattern located in the Between the first gate pattern and the second gate pattern, a gate electrical connection structure is defined, and the gate electrical connection structure is arranged in the same layer as the first gate and the second gate to electrically The first gate and/or the second gate are connected.
  • a second aspect of the present disclosure provides a semiconductor structure, comprising: a substrate having a first well and a second well arranged in a first direction; a first gate located at the first well of the first well a second gate on the substrate and extending along the first direction; a second gate on the substrate of the second well and extending along the first direction; a gate electrical connection structure on the substrate and connected to the second well
  • the first gate and the second gate are disposed in the same layer to electrically connect the first gate and/or the second gate.
  • the standard cell layout template includes a first well region and a second well region, and the first gate pattern located in the first well region and extending along the first direction is located in the first well region.
  • the second gate pattern in the second well region and extending along the first direction further includes a gate electrical connection pattern located between the first gate pattern and the second gate pattern, where the gate electrical connection pattern is used to define the gate electrical connection structure, and the gate electrical connection structure is arranged in the same layer as the first gate electrode and the second gate electrode.
  • the electrical connection with the first gate and/or the second gate can be achieved through the gate electrical connection structure in the same layer as the first gate and the second gate, thereby reducing the length of the electrical connection path and reducing the electrical connection.
  • the resistance corresponding to the connection path and, there is no need to provide a contact hole structure for realizing the electrical connection between the upper and lower layers, so as to avoid adverse effects caused by the contact hole structure with large resistance and reduce the resistance corresponding to the electrical connection path. Therefore, the semiconductor structure fabricated by using the standard cell layout die provided by the embodiments of the present disclosure can improve the running speed, reduce the power consumption of the semiconductor structure, and also improve the signal quality, such as the signal delay on the gate, Signal rise time and/or signal fall time are improved.
  • the standard cell layout template provided by the embodiment of the present disclosure can be used as a circuit layout design template for other chips such as DRAM chips.
  • the layout of the grid electrical connection pattern can make the circuit layout layout more regular, and different layouts follow the same principle. Due to the optimized circuit layout design, the efficiency of layout design is improved and the time of chip design is shortened.
  • Fig. 1 is the structural representation of a kind of standard cell layout template
  • Fig. 2 is the partial cross-sectional structure schematic diagram of the semiconductor structure that adopts the standard cell layout template of Fig. 1 to make;
  • FIG. 3 is a schematic structural diagram of a standard cell layout template provided by an embodiment of the present disclosure.
  • FIG. 4 is another schematic structural diagram of a standard cell layout model provided by an embodiment of the present disclosure.
  • FIG. 5 is another schematic structural diagram of a standard cell layout template provided by an embodiment of the present disclosure.
  • FIG. 6 is still another schematic structural diagram of a standard cell layout template provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a standard cell layout template provided by another embodiment of the present disclosure.
  • FIG. 8 is another schematic structural diagram of a standard cell layout template provided by another embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a standard cell layout template provided by another embodiment of the present disclosure.
  • FIG. 10 is a schematic top-view structural diagram of a semiconductor structure provided by still another embodiment of the present disclosure.
  • Fig. 11 is a kind of sectional structure schematic diagram along CC1 direction in Fig. 9;
  • FIG. 12 is another schematic cross-sectional structure diagram of a semiconductor structure provided by yet another embodiment of the present disclosure.
  • FIG. 13 is another schematic cross-sectional structure diagram of a semiconductor structure provided by still another embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a standard cell layout template
  • FIG. 2 is a partial cross-sectional structural schematic diagram of a semiconductor structure fabricated by using the standard cell layout template of FIG. 1 .
  • the standard cell layout template includes: an N-type well region 11 and a P-type well region 12 arranged adjacently; at least one first gate pattern 13, located in the N-type well region 11, is used to define a first gate 23; at least one second gate pattern 14 located in the P-type well region 12 for defining the second gate 24; a first contact hole pattern 15 located on the first gate pattern 13 for Define the first contact hole structure 25 electrically connected to the first gate 23; the second contact hole pattern 16, located on the second gate pattern 14, is used to define the second contact hole structure electrically connected to the second gate 24 26;
  • the electrical connection pattern 17 spans the N-type well region 11 and the P-type well region 12, and connects the first contact hole pattern 15 and the second contact hole pattern 16 for defining an electrical connection layer 27, the electrical connection layer 27 It is electrically connected to the first contact hole structure 25 and the second contact hole structure 26 , and the electrical connection layer 27 is a metal layer, so as to realize the electrical connection between the first gate electrode 23 and the second gate electrode 24 .
  • the electrical connection path between the first gate 23 and the second gate 24 is: the first contact hole structure 25 , the electrical connection layer 27 and the second contact hole structure 26 .
  • the paths are opposite to each other. Longer makes the electrical connection path have greater resistance.
  • the electrical connection layer 27 , the first contact hole structure 25 and the second contact hole structure 26 themselves have a greater sheet resistance.
  • An embodiment of the present disclosure provides a standard cell layout template, the layout is used to define a gate electrical connection pattern of a gate electrical connection structure, and the gate electrical connection structure and the first gate and/or the second gate are arranged in the same layer.
  • the standard cell layout template to perform actual layout layout, it is not necessary to layout the contact hole structure for realizing the electrical connection between the upper and lower layers, thereby reducing the resistance of the semiconductor structure corresponding to the layout.
  • the grid connection pattern is defined in the standard cell layout template.
  • the layout of the grid connection pattern in the layout is more uniform and regular, which is beneficial to reduce the difficulty and time of layout design. , the area of the layout is reduced, and the process deviation in the semiconductor structure corresponding to the manufacturing layout is reduced.
  • FIG. 3 is a schematic structural diagram of a standard cell layout template provided by an embodiment of the present disclosure.
  • the standard cell layout template includes: a first well region I and a second well region II arranged along the first direction Y; a first gate pattern 101, located in the first well region I and along the The first direction Y extends to define the first gate; the second gate pattern 102 is located in the second well region II and extends along the first direction Y to define the second gate; the gate electrical connection pattern 103 is located in Between the first gate pattern 101 and the second gate pattern 102 is used to define a gate electrical connection structure, and the gate electrical connection structure is arranged in the same layer as the first gate and the second gate to electrically connect the first gate and the second gate. /or second gate.
  • the standard cell layout template provided in this embodiment is the basis for making a layout.
  • an actual layout structure is designed on the basis of the standard cell layout template based on the specific circuit structure.
  • the circuit structure corresponding to the designed layout needs to satisfy the electrical connection of the first gate and/or the second gate, since the electrical connection structure of the gate is arranged in the same layer as the first gate and the second gate, there is no need to set it for realizing
  • the contact hole structure electrically connecting the upper and lower layers is beneficial to shorten the electrical connection path between the gate electrical connection structure and the first gate and/or the second gate, and avoid the resistance caused by the large sheet resistance of the contact hole structure too big a problem. Therefore, using the standard cell layout template provided in this embodiment can reduce the power consumption of the circuit structure and improve the RC delay effect, for example, the signal quality on the first gate and/or the second gate can be improved.
  • the standard cell layout template provided in this embodiment can be applied to memory, and the memory can be DRAM, SRAM (Static Random-Access Memory, static random access memory), MRAM (Magneto resistive Random Access Memory, magnetic random access memory), FeRAM (Ferroelectric RAM) , ferroelectric random access memory), PCRAM (Phase Change RAM, phase change random access memory), HBM (High Bandwidth Memory, high bandwidth) memory, NAND flash memory or NOR flash memory and other memories.
  • the DRAM memory can be DDR (Double Data Rate) memory, LPDDR (Low Power Double Data Rate) memory or GDDR (Graphics Double Data Rate) memory.
  • the standard cell layout template defines two MOS transistors, the first well region I is used to define the well (Well) of one of the MOS transistors, and the second well region II is used to define the well of the other MOS transistor.
  • an N-type well is defined in the first well region I and a P-type well is defined in the second well region II as an example, that is, the types of the two MOS transistors are different.
  • the two MOS transistors may be of the same type, for example, both are NMOS transistors or both are PMOS transistors.
  • the first well region I and the second well region II are adjacent to each other, that is, a boundary of the first well region I coincides with a boundary of the second well region II.
  • the standard cell layout template may also consider the layout of the isolation structure, so that the first well region and the second well region are spaced apart, and the first well region and the second well region are spaced apart.
  • the area of is the isolation area, which is used to define the isolation structure.
  • the first well region I defines an N-type well and the second well region II defines a P-type well
  • the first well region I has a first height greater than the second height of the second well region II. It can be understood that, the first height and the second height both refer to the width along the first direction Y direction.
  • the first gate pattern 101 is strip-shaped and located in a part of the first well region I
  • the second gate pattern 102 is strip-shaped and located in a part of the second well region II.
  • the first well region I includes: a first MOS region i, and the first gate pattern 101 spans the first MOS region i, or in other words, along the first direction Y, the region where the first gate pattern 101 is located is defined as
  • the first MOS region i the first MOS region i may also be called the first active region; and along the first direction Y, the width of the first MOS region i is the same as the width of the first gate pattern 101 .
  • the second well region II includes: the second MOS region ii, and the second gate pattern 102 spans the second MOS region ii; or, in the first direction Y, the region where the second gate pattern 102 is located is defined as
  • the second MOS region ii, the second MOS region ii may also be referred to as the second active region; and along the first direction, the width of the second MOS region ii is the same as the width of the second gate pattern 102 .
  • the standard cell layout template further includes: an intermediate region iii, the intermediate region iii is located between the first MOS region i and the second MOS region ii.
  • the first well region I has a direction toward the first well region I.
  • the first boundary B1 of the two well region II, and the first boundary B1 is located in the middle of the intermediate region iii, that is, along the first direction Y, the distance from the first boundary B1 to the boundary of the adjacent first MOS region i is the first distance, the distance from the first boundary B1 to the boundary of the adjacent second MOS region ii is the second distance, and the second distance is equal to the first distance.
  • the layout design rule Layout Design Rule, LDR
  • DRC Design Rule Check
  • the standard cell layout template may further include: a first gate extension pattern 111, the first gate extension pattern 111 is located in the first well region I and connected to the end of the first gate pattern 101 for defining The first gate extension structure.
  • the first gate extension pattern 111 is located outside the first MOS region i, and the first gate extension pattern 111 is strip-shaped and its extension direction is different from the first direction Y.
  • the extension direction of the first gate extension pattern 111 may be The second direction X, and the second direction X may be perpendicular to the first direction Y.
  • the first gate extension pattern 111 is arranged so that the first gate and the gate electrical connection structure are electrically connected through the first gate extension structure, therefore, the electrical connection window between the first gate and the gate electrical connection structure is increased , thereby reducing the technological difficulty of the corresponding manufacturing process, such as reducing the alignment accuracy.
  • the width of the first gate extension pattern 111 is greater than the width of the first gate pattern 101 ; compared to laying out the first auxiliary pattern directly between the first gate pattern 101 and the gate electrical connection pattern 103
  • the layout space for laying out the first auxiliary pattern between the first gate extension pattern 111 and the gate electrical connection pattern 103 is significantly larger, and along the second direction X, the width of the layout space is determined by the first The width of the gate pattern 101 increases to the width of the first gate extension pattern 111 .
  • the standard cell layout template may further include: a second gate extension pattern 112, the second gate extension pattern 112 is located in the second well region II and is connected to the end of the second gate pattern 102 for defining the second gate pattern 102. Gate extension structure. And along the second direction X, the width of the second gate extension pattern 112 is greater than the width of the second gate pattern 102 .
  • the second gate extension pattern 112 reference may be made to the corresponding description of the first gate extension pattern 111 , which will not be repeated here.
  • the standard cell layout template may not be provided with the first gate extension pattern and the second gate extension pattern.
  • the gate electrical connection structure defined by the gate electrical connection pattern 103 is arranged in the same layer as the first gate and the second gate, when the gate electrical connection structure is electrically connected with the first gate and/or the second gate structure, no need to be provided
  • the contact hole structure with high resistance in this way, shortens the electrical connection path and avoids the problem of high resistance caused by the contact hole structure, thereby helping to reduce the power consumption and RC effect of the circuit structure corresponding to the standard cell layout template.
  • the circuit structure is applied to the memory, the power consumption of the memory can be reduced and the storage speed can be improved.
  • the material of the gate electrical connection structure may be the same as the material of the first gate electrode and the material of the second gate electrode.
  • the gate electrical connection structure can be simultaneously manufactured by using the manufacturing processes of the first gate and the second gate, so as to reduce the number of process steps and reduce the production cost; in addition, the materials of the first gate and the second gate are When it is polysilicon, the material of the gate electrical connection structure is polysilicon.
  • the resistivity of polysilicon is smaller than that of metal, so the gate electrical connection structure made of polysilicon is conducive to reducing the resistance.
  • the gate electrical connection pattern 103 includes: at least two electrical connection patterns spaced apart, and each electrical connection pattern extends along the second direction X, the second direction X is different from the first direction Y, and each electrical connection pattern extends along the second direction X. Connection patterns are used to define an electrical connection structure. Wherein, the second direction X may be perpendicular to the first direction Y. It can be understood that, in other embodiments, on the premise of satisfying LDR and DRC, the included angle between the second direction and the first direction may also be in other suitable ranges.
  • the gate electrical connection structure includes at least two mutually spaced electrical connection structures, so that the number of specific circuits to which the standard cell layout template can be applied can be increased, and the applicable scenarios of the standard cell layout template can be increased.
  • the at least two spaced-apart electrical connection patterns include: a first electrical connection pattern 113 located in the first well region I for defining a first electrical connection structure to electrically connect the first gate electrode; a second electrical connection pattern 123 located in the first well region I
  • the second well region II is used to define a second electrical connection structure to electrically connect the second gate electrode. Since the first electrical connection pattern 113 is located in the first well region I, it is beneficial to reduce the distance between the first electrical connection structure and the first gate, thereby reducing the electrical connection between the first electrical connection structure and the first gate. connection paths, thereby reducing resistance on the electrical connection paths.
  • the second electrical connection pattern 123 is located in the second well region II, which is beneficial to reduce the resistance on the electrical connection path between the second electrical connection structure and the second gate.
  • the gate electrical connection pattern 103 is located in the middle region iii. In this way, the gate electrical connection pattern 103 will not interfere with the layout of the first MOS region i and the second MOS region ii, ensuring that the corresponding semiconductor structure has relatively long first and second active region widths. In other embodiments, if an isolation region is arranged between the first well region and the second well region, the gate electrical connection pattern can be arranged in the isolation region.
  • the gate electrical connection pattern may further include three or more electrical connection patterns.
  • FIG. 4 is another schematic structural diagram of the standard cell layout model provided in this embodiment.
  • the gate electrical connection pattern 103 may also include an electrical connection pattern.
  • the electrical connection pattern extends along the second direction X, and the second direction X is different from the first direction Y.
  • Part of the electrical connection patterns are located in the first well region I, and the remaining part of the electrical connection patterns are located in the second well region II.
  • half of the electrical connection patterns occupy part of the space in the first well region I, and the other half of the electrical connection patterns occupy the second well region II. Partial space location.
  • the standard cell layout template can be applied not only to the electrical connection between the first gate and the second gate, but also to the gate electrical connection structure and the first gate structure or the second gate.
  • One of the two gate structures is electrically connected, and the standard cell layout template can be used for auxiliary layout without design, and auxiliary layout is performed during the design of the specific layout.
  • the following will describe the standard cell layout template in combination with the specific layout of the design:
  • auxiliary electrical connection structure makes the gate electrical connection structure electrically connect the first gate and the second gate through the auxiliary electrical connection structure.
  • the specific circuit structure corresponding to the layout is that the gate electrical connection pattern is electrically connected to the first gate
  • an additional auxiliary pattern is designed to define the auxiliary electrical connection structure, so that the gate is electrically connected
  • the structure is electrically connected to the first gate through an auxiliary electrical connection structure.
  • FIG. 5 is another schematic structural diagram of the standard cell layout template provided in this embodiment.
  • the gate electrical connection pattern 103 of the standard cell layout template may further include: a first auxiliary pattern 104 , which is connected to the first gate pattern 101
  • the electrical connection pattern toward the first gate pattern 101 is used to define the first auxiliary electrical connection structure to electrically connect the first gate with the electrical connection structure toward the first gate;
  • the second auxiliary pattern 105 is used to connect the second gate
  • the gate pattern 102 and the electrical connection pattern toward the second gate pattern 102 are used to define a second auxiliary electrical connection structure to electrically connect the second gate and the electrical connection structure toward the second gate.
  • first auxiliary electrical connection structure and the first gate and/or the second gate are arranged in the same layer, and the material of the first auxiliary electrical connection structure and the first gate and/or the second gate may be the same; the second gate The auxiliary electrical connection structure and the first gate electrode and/or the second gate electrode are disposed in the same layer, and the material of the second auxiliary electrical connection structure and the first gate electrode and/or the second gate electrode can be the same.
  • the layout of the first auxiliary pattern 104 is such that in the specific circuit structure corresponding to the standard cell layout template, the first gate is electrically connected to the gate electrical connection structure; the layout of the second auxiliary pattern 105 is such that the specific circuit structure corresponding to the standard cell layout template is wherein, the second gate is electrically connected to the gate electrical connection structure.
  • the layout engineer or the automatic layout layout tool does not need to additionally lay out the first auxiliary graphics and the second auxiliary graphics.
  • FIG. 6 is another schematic structural diagram of the standard cell layout template provided in this embodiment.
  • the gate electrical connection pattern 103 may further include: a third auxiliary pattern 106 located between adjacent electrical connection patterns for A third auxiliary electrical connection structure is defined to electrically connect adjacent electrical connection structures.
  • the third auxiliary electrical connection structure may be disposed in the same layer as the first gate electrode and/or the second gate electrode, and the material may be the same.
  • the gate electrical connection pattern may include both the first auxiliary pattern and the second auxiliary pattern, and may also include the third auxiliary pattern.
  • the gate electrical connection pattern 103 may also be located on the side of the first gate pattern 101 away from the second gate pattern 102, and the second gate pattern 102 away from the first gate One side of graphic 101. That is to say, the grid electrical connection patterns 103 are also arranged on the top and bottom of the standard cell layout template, so that the applicable scenes of the standard cell layout template can be increased to facilitate more complex layout design using the standard cell layout.
  • the standard cell layout template may further include: a first well connection pattern 131, located in the first well region I, for defining a first well plug; a second well connection pattern 132, located in the second well region II, for Define the second well plug.
  • the first well connection pattern 131 is located at the edge of the first well region I away from the second well region II
  • the second well connection pattern 132 is located at the edge of the second well region II away from the first well region I.
  • the standard cell layout template has a second boundary B2 away from the second well region II.
  • the two circuit layouts may be symmetrical with respect to the axis of the second boundary B2.
  • the two circuit layouts share the second boundary B2, define the boundary of the first well region I of one circuit layout towards the second boundary B2 as the third boundary, and define the boundary of the first well region I of another circuit layout towards the second boundary B2 is the fourth boundary, and the second boundary B2 is located in the middle position between the third boundary and the fourth boundary.
  • Standard cell layout templates can be designed based on Layout Design Rule (LDR). For example: each standard cell layout template is the same height; standard cell layout template includes all design rules and routing guidelines; standard cell layout template boundaries need to be considered to ensure that different standard cell layout templates can pass DRC when placed together (Design Rule Check) and Layout Versus Schematics (LVS); in order to facilitate block level routing, the input/output positions of standard cell layout templates also need to be considered.
  • LDR Layout Design Rule
  • the standard cell layout template can also be designed considering the P/N ratio and the standard cell delay parameter (tPD).
  • This embodiment provides a standard cell layout template, and a layout engineer can use the standard cell layout template to design a layout. Since the standard cell layout template has a gate electrical connection pattern, the gate electrical connection pattern is used to define a gate electrical connection structure arranged in the same layer as the first gate and/or the second gate, and the gate electrical connection structure can be used to connect with the first gate and/or the second gate. Therefore, the electrical connection of the first gate and/or the second gate does not need to provide a contact hole structure for realizing the electrical connection between the upper and lower layers, thereby reducing the resistance of the electrical connection path of the corresponding semiconductor structure, thereby reducing the circuit structure corresponding to the semiconductor structure. power consumption and improve RC delay effect.
  • the standard cell layout template provided in this embodiment does not need to reserve space for defining the pattern layer (ie, M0) electrically connected to the first gate and/or the second gate, so that the use of the standard cell layout can be reduced.
  • the area of the circuit layout designed by the template for example, the area of the logic area in the circuit layout can be reduced; in addition, when the layout engineer uses the standard cell layout template to design the layout, it can be defined for the first gate and/or the second gate.
  • the area of the electrically connected pattern layer is designed to be small, thereby helping to reduce the load of the circuit structure corresponding to the layout.
  • the standard cell layout template can be used as a layout design template for other chips such as DRAM chips, so that the corresponding circuit layout layout is more regular, and different circuit layouts follow consistent rules, so as to optimize the layout design, improve the efficiency of layout design, and shorten the chip. Design time.
  • Another embodiment of the present disclosure further provides a standard cell layout template.
  • the standard cell layout template is substantially the same as the previous embodiment, and the main differences include: a power supply graphic is also laid out.
  • the standard cell layout template provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the previous embodiment, reference may be made to the description of the previous embodiment, which will not be repeated here. .
  • FIG. 7 is a schematic structural diagram of a standard cell layout template provided by another embodiment of the present disclosure
  • FIG. 8 is another structural schematic diagram of a standard cell layout template provided by another embodiment of the present disclosure.
  • the standard cell layout template corresponding to FIG. 7 can be applied to high-speed memory, and the standard cell layout template corresponding to FIG. 8 can be applied to low-power consumption memory.
  • the standard cell layout template further includes: a first power supply pattern 201 for defining a first power supply wiring, and the first power supply wiring is used to connect the first power supply; the second power supply The graph 202 is used to define the second power supply line, the second power supply line is used to connect the second power supply, and the voltage of the first power supply is greater than the voltage of the second power supply; wherein, along the first direction Y, the first power supply The width of the pattern 201 is larger than the width of the second power pattern 202 .
  • the first well region I defines the well of the PMOS transistor
  • the second well region II defines the well of the NMOS transistor. Since the width dimension of the PMOS transistor and the NMOS transistor is generally 2:1, the first power supply line used for powering the PMOS transistor is wider than the second power supply line used for powering the NMOS transistor.
  • the standard cell layout template may include: a third power supply pattern 203 for defining a third power supply wiring, and the third power supply wiring is used for connecting the third power supply; a fourth power supply pattern 204 , is used to define the fourth power supply line, the fourth power supply line is used to connect the fourth power supply, and the voltage of the third power supply is greater than the voltage of the fourth power supply.
  • the width of the third power pattern 203 is greater than the width of the fourth power pattern 204 .
  • the standard cell layout template may also include: signal line patterns 205 for defining signal lines, and the number of signal line patterns 205 is at least two, one signal line pattern 205 corresponds to the first well region I, and the other signal line pattern 205 Corresponds to the second well region II.
  • a plurality of signal lines can be arranged in the area corresponding to each signal line pattern 205 .
  • the corresponding circuit structure requires at least two high-level power supplies
  • at least two adjacent signal lines in the area defined by the signal line pattern 205 can be used to combine as a connection for the second type of power supply. Power traces for high-level power supplies.
  • the circuit layouts working in different power domains can be placed in the same row, that is, they can be arranged adjacently; since the power traces of the first high-level power supply are defined by the first power supply pattern 201, The power traces of the power supply are merged by at least two adjacent signal lines in the area defined by the signal line pattern 205, so the power traces of the two power sources do not appear on the same channel (ie, track), so there is no short circuit problems, thus improving the application scenarios of standard cell layout templates.
  • metal switch graphics can be laid out in the standard cell layout template, and the standard cell layout template can be applied to the following two application scenarios through the metal switch graphics:
  • the metal switch pattern is connected with the power supply wiring, and other circuit structures connected by the structure defined by the metal switch pattern are connected with the power supply, so as to realize the first circuit function; 2.
  • the metal switch pattern is connected with the signal wiring, and the metal switch pattern The other circuit structures connected by the defined structure are connected with the signal traces, thereby realizing the second circuit function.
  • the standard cell layout template includes: a power graphic, used to define a power trace, which is used to connect the power supply; a signal graphic 207, used to define a signal trace; a first gate graphic 208, used to define the first gate switch, the first gate switch is used to realize the electrical connection or disconnection with the power supply wiring; the second gate pattern 209 is used to define the second gate switch, and the second gate switch is used to realize the electrical connection with the signal wiring. Electrically connected or disconnected; wherein, the signal pattern 207, the first gate pattern 208 and the second gate pattern 209 are located on the same side of the power supply pattern.
  • the power pattern may include at least one of the first power pattern 201 or the second power pattern 202.
  • the first gate pattern 208 and the second gate pattern 209 constitute a metal switch pattern, and one of the first gate pattern 208 and the second gate pattern 209 participates in the actual wiring.
  • the first gate pattern 208 participates in the wiring and The second gate pattern 209 does not participate in the wiring, then the first gate switch is connected to the power wiring and the second gate switch is disconnected; the first gate pattern 208 does not participate in the wiring and the second gate pattern 209 participates in the wiring, then the first gate pattern 209 A gating switch is turned off and the second gating switch is connected to signal transmission.
  • the signal pattern 207 includes: two sub-signal patterns 217 arranged along the third direction, and there is an interval between the two sub-signal patterns 217; the first gate pattern 208 is connected to one of the sub-signal patterns 217, and The first gate pattern 208 is located between the sub-signal pattern 217 and the power supply pattern; the second gate pattern 209 is located between the two sub-signal patterns 217, and parallel to the third direction, the length of the second gate pattern 209 is greater than or equal to the length of the interval.
  • the third direction may be the same as the second direction X.
  • the signal pattern may only include a single sub-gating pattern.
  • the standard cell layout template provided in this embodiment increases the applicable scenarios of the standard cell layout template by reasonably arranging the power supply graphics, the signal graphics, the first gating graphics, and the second gating graphics. Taking into account the actual chip design, the actual layout can be adjusted redundantly according to the standard cell layout template, for example, the circuit structure corresponding to the layout can be changed through the first gate pattern or the second gate pattern, thereby adjusting the delay corresponding to the circuit structure. parameter.
  • Another embodiment of the present disclosure also provides a standard cell layout template, which is substantially the same as the previous embodiment, with the main differences including: the standard cell layout template provided in the previous embodiment can be used for manual wiring (custom layout, ie custom layout), this The standard cell layout template provided by the embodiment can be applied to automatic routing, that is, a full-chip automatic physical design (auto-PR, place route) can be used to perform layout layout using the standard cell layout template.
  • FIG. 9 is a schematic structural diagram of a standard cell layout template provided by yet another embodiment of the present disclosure.
  • the standard cell layout template further includes: a metal layer pattern 30, the metal layer pattern 30 is electrically connected across the gate pattern 103, the first gate pattern 101 and/or the second gate pattern 102, using For defining the metal layer, the metal layer is located on the upper layer of the first gate and the second gate to electrically connect the first gate and/or the second gate.
  • the metal layer pattern 30 is electrically connected across the gate pattern 103, the first gate pattern 101 and/or The second gate pattern 102 actually refers to: the metal layer pattern 30 is electrically connected across the gate pattern 103 , the first gate extension pattern 111 and/or the second gate extension pattern 112 .
  • the metal layer provides conditions for automatic routing.
  • the metal layer pattern 30 spans the first gate extension pattern 111 , the gate electrical connection pattern 103 and the second gate extension pattern 112 . It can be understood that if the metal layer is only electrically connected to the first gate, the overlapping area of the metal layer pattern 30 and the gate electrical connection pattern 103 corresponds to the layout of the contact hole structure, and the gate electrical connection structure defined by the gate electrical connection pattern 103 is connected to the first gate.
  • a gate is electrically connected; if the metal layer is only electrically connected to the second gate, the overlapping area of the metal layer pattern 30 and the gate electrical connection pattern 103 corresponds to the layout of the contact hole structure, and the gate electrical connection structure defined by the gate electrical connection pattern 103 corresponds to the The second gate is electrically connected.
  • the standard cell layout template has a custom layout area AA, the first well area I and the second well area II are located in the custom layout area AA, and part of the metal layer pattern 30 is located in the custom layout area AA, and the rest of the graphics are located in the custom layout area AA. Outside the custom layout area AA.
  • the metal layer pattern 30 includes: a first metal layer pattern 31, the first metal layer pattern 31 extends along the first direction Y, and is electrically connected to the gate pattern 103, the first gate extension pattern 111 and/or the second gate extension pattern 112 has an overlapping portion; the second metal layer pattern 32 is connected to the first metal layer pattern 31 and extends outside the custom layout area AA along the second direction X; the third metal layer pattern 33 is located outside the custom layout area AA and Connected to the second metal layer pattern 32, the third metal layer pattern 33 extends along the first direction Y.
  • the metal layer pattern is electrically connected across the gate pattern, the first gate pattern and/or the gate pattern.
  • the second gate pattern that is, the metal layer pattern has an overlapping portion with the first gate pattern and/or the second gate pattern.
  • the standard cell layout template provided in this embodiment provides conditions for realizing automatic layout by laying out metal layer graphics.
  • FIG. 10 is a schematic top-view structural diagram of a semiconductor structure provided by still another embodiment of the present disclosure
  • FIG. 11 is a schematic cross-sectional structural diagram of FIG. 10 along the CC1 direction.
  • the semiconductor structure includes: a substrate 400 with a first well 41 and a second well 42 arranged in a first direction in the substrate 400 ; a first gate 401 located in the first well 41 on the substrate 400 and extending in the first direction Y; the second gate 402 is located on the substrate 400 of the second well 42 and extends in the first direction Y; the gate electrical connection structure 403 is located on the substrate 400 and is connected with the first A gate 401 and a second gate 402 are disposed in the same layer to electrically connect the first gate 401 and/or the second gate 402 .
  • the semiconductor structure can be memory such as DRAM, SRAM, MRAM, FeRAM, PCRAM, HBM memory, NAND flash memory, or NOR flash memory.
  • the gate electrical connection structure 403 is in the same layer as the first gate 401 and the second gate 402 , the gate electrical connection structure 403 and the first gate 401 can be realized without a contact hole structure for realizing electrical connection between the upper and lower layers.
  • the electrical connection between the second gate 402 compared with the solution in which the gate electrical connection structure is located above the first gate and the second gate, this embodiment can shorten the distance between the gate electrical connection structure 403 and the first gate 401.
  • the electrical connection path between the gate electrical connection structure 403 and the second gate 402 is shortened, thereby reducing the resistance corresponding to the electrical connection path, thereby reducing the power consumption of the semiconductor structure and improving the RC delay effect.
  • the gate electrical connection structure 403 may be formed simultaneously in the process steps of forming the first gate 401 and/or the second gate 402 .
  • the top of the gate electrical connection structure 403 may be flush with the top of the first gate 401 and the top of the second gate 402 .
  • the bottom of the gate electrical connection structure 403 can also be flush with the bottom of the first gate 401 and the bottom of the second gate 402, so that the gate electrical connection structure 403 has a relatively thick thickness, which is beneficial to reduce the gate electrical connection structure 403 overall resistance, thereby reducing the power consumption of the semiconductor structure and the effect of RC delay.
  • the “top” here refers to the top surface away from the substrate 400
  • the “bottom” here refers to the bottom surface facing the substrate 400 .
  • the material of the gate electrical connection structure 403 may also be the same as the material of the first gate 401 and the second gate 402 .
  • the material of the gate electrical connection structure 403, the material of the first gate 401 and the material of the second gate 402 are all polysilicon; generally, the resistivity of polysilicon is lower than that of metal, such as polysilicon The resistivity is lower than that of copper, so using polysilicon as the material of the gate electrical connection structure 403 can reduce the resistance of the electrical connection path, thereby reducing the power consumption of the semiconductor structure.
  • the semiconductor structure may further include: a first auxiliary gate 411 connected to the end of the first gate 401 and extending along the second direction X; a second auxiliary gate 412 connected to the end of the second gate 402 The parts are connected and extend along the second direction X.
  • the first auxiliary gate 411 and the first gate 401 are disposed in the same layer and made of the same material, and the second auxiliary gate 412 and the second gate 402 are disposed in the same layer and made of the same material.
  • the width of the first auxiliary gate 411 is larger than that of the first gate 401
  • the width of the second auxiliary gate 412 is larger than that of the second gate 402 .
  • the arrangement of the first auxiliary gate 411 is beneficial to increase the process window for the electrical connection between the first gate 401 and the gate electrical connection structure 403 ; the arrangement of the second auxiliary gate 412 is beneficial to increase the second gate 402
  • the process window electrically connected to the gate electrical connection structure 403 reduces the requirement of process alignment precision and reduces the fabrication difficulty of the semiconductor structure.
  • the gate electrical connection structure 403 includes at least two electrical connection structures, and each electrical connection structure extends along the second direction X, and the second direction X is different from the first direction Y.
  • the at least two electrical connection structures include: a first electrical connection structure 413 located on the substrate 400 of the first well 41 , the first electrical connection structure 413 and the first gate 401 and the second gate 402 are disposed in the same layer; the second electrical connection The connection structure 423 is located on the substrate 400 of the second well 42 , and the second electrical connection structure 423 is disposed in the same layer as the first gate 401 and the second gate 402 .
  • the first electrical connection structure 413 can be used to electrically connect the first gate 401 through the first auxiliary gate 411
  • the second electrical connection structure 423 can be used to electrically connect the second gate 402 through the second auxiliary gate 412 .
  • FIG. 12 is another schematic cross-sectional structure diagram of the semiconductor structure provided in this embodiment.
  • the gate electrical connection structure 403 may further include: a first auxiliary electrical connection structure 433 located between the first gate 401 and the electrical connection structure facing the first gate 401 to electrically connect the first gate 401 with the The electrical connection structure toward the first gate 401; the second auxiliary electrical connection structure 443 is located between the second gate 402 and the electrical connection structure toward the second gate 402 to electrically connect the second gate 402 with the electrical connection toward the second gate 402.
  • the electrical connection structure of the two gates may further include: a first auxiliary electrical connection structure 433 located between the first gate 401 and the electrical connection structure facing the first gate 401 to electrically connect the first gate 401 with the The electrical connection structure toward the first gate 401;
  • the second auxiliary electrical connection structure 443 is located between the second gate 402 and the electrical connection structure toward the second gate 402 to electrically connect the second gate 402 with the electrical connection toward the second gate 402.
  • the first auxiliary electrical connection structure 433 is in contact with the first electrical connection structure 413 and the first auxiliary gate 411 and is electrically connected
  • the second auxiliary electrical connection structure 443 is in contact with the second electrical connection structure 423 and the second auxiliary gate 412 and electrically connected.
  • the first auxiliary electrical connection structure 433 and the second auxiliary electrical connection structure 443 are in the same layer as the first gate electrode 401 and the second gate electrode 402 .
  • FIG. 13 is another schematic cross-sectional structure diagram of the semiconductor structure provided in this embodiment.
  • the gate electrical connection structure 403 may further include: a third auxiliary electrical connection structure 453 located between adjacent electrical connection structures to electrically connect the adjacent electrical connection structures. In this way, the specific circuit corresponding to the semiconductor structure is electrically connected to adjacent electrical connection structures.
  • the gate electrical connection structure may also include only one electrical connection structure, and according to the specific circuit structure corresponding to the semiconductor structure, the electrical connection structure may be electrically connected to the first gate, or the The electrical connection structure may be electrically connected to the second gate, or the electrical connection structure may be electrically connected to the first gate and the second gate.
  • the electrical connection with the first gate 401 and/or the second gate 402 can be realized through the gate electrical connection structure 403 provided in the same layer, which not only reduces the electrical connection path, There is no need to provide a contact hole structure with a large resistance, so it is beneficial to reduce the resistance of the semiconductor structure, thereby reducing the power consumption of the semiconductor structure and the RC delay effect. If the semiconductor structure is a memory, the storage speed of the memory can also be improved.
  • a gate electrical connection structure with the first gate and/or the second gate may be implemented through a gate electrical connection structure in the same layer as the first gate and/or the second gate. electrical connection, thereby reducing the length of the electrical connection path and reducing the resistance corresponding to the electrical connection path; and, there is no need to set up a contact hole structure to realize the electrical connection between the upper and lower layers, so as to avoid the adverse effects caused by the contact hole structure with high resistance, Reduce the resistance corresponding to the electrical connection path.
  • the semiconductor structure fabricated by using the standard cell layout die provided by the embodiments of the present disclosure can improve the running speed, reduce the power consumption of the semiconductor structure, and also improve the signal quality, such as the signal delay on the gate, Signal rise time and/or signal fall time are improved.
  • the standard cell layout template provided by the embodiment of the present disclosure can be used as a circuit layout design template for other chips such as DRAM chips.
  • the layout of the grid electrical connection pattern can make the circuit layout layout more regular, and different layouts follow the same principle. Due to the optimized circuit layout design, the efficiency of layout design is improved and the time of chip design is shortened.

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Abstract

本公开提供一种标准单元版图模板以及半导体结构，其中，标准单元版图模板包括：沿第一方向排布的第一阱区和第二阱区；第一栅极图形，位于所述第一阱区且沿所述第一方向延伸，用于定义第一栅极；第二栅极图形，位于所述第二阱区且沿所述第一方向延伸，用于定义第二栅极；栅电连接图形，位于所述第一栅极图形与所述第二栅极图形之间，用于定义栅电连接结构，所述栅电连接结构与所述第一栅极以及所述第二栅极同层设置，以电连接所述第一栅极和/或所述第二栅极。

Description

标准单元版图模板以及半导体结构
本公开基于申请号为202110163720.X，申请日为2021年02月05日，申请名称为“标准单元版图模板以及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种标准单元版图模板以及半导体结构。
背景技术
标准单元库是集成电路设计的基础，基于标准单元库的集成电路设计能够进行逻辑综合和版图布局布线，提高电路的设计效率。
标准单元库包括若干预先设计好的标准单元版图模板(Standard Cell template)，集成电路设计者或者电路设计综合工具根据设计要求，调用标准单元库中的标准单元版图模板来完成集成电路的版图布局设计。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种标准单元版图模板以及半导体结构。
本公开的第一方面提供一种标准单元版图模板，包括沿第一方向排布的第一阱区和第二阱区；第一栅极图形，位于所述第一阱区且沿所述第一方向延伸，用于定义第一栅极；第二栅极图形，位于所述第二阱区且沿所述第一方向延伸，用于定义第二栅极；栅电连接图形，位于所述第一栅极图形与所述第二栅极图形之间，用于定义栅电连接结构，所述栅电连接结构与所述第一栅极以及所述第二栅极同层设置，以电连接所述第一栅极和/或所述第二栅极。
本公开的第二方面提供一种半导体结构，包括：基底，所述基底内具有 沿第一方向排布的第一阱和第二阱；第一栅极，位于所述第一阱的所述基底上且沿所述第一方向延伸；第二栅极，位于所述第二阱的所述基底上且沿所述第一方向延伸；栅电连接结构，位于所述基底上，且与所述第一栅极以及所述第二栅极同层设置，以电连接所述第一栅极和/或所述第二栅极。
本公开实施例所提供的标准单元版图模板以及半导体结构中，标准单元版图模板包括第一阱区和第二阱区，位于第一阱区且沿第一方向延伸的第一栅极图形，位于第二阱区且沿第一方向延伸的第二栅极图形，还包括位于第一栅极图形与第二栅极图形之间的栅电连接图形，该栅电连接图形用于定义栅电连接结构，且该栅电连接结构与第一栅极以及第二栅极同层设置。如此，可通过与第一栅极和第二栅极处于同层的栅电连接结构实现与第一栅极和/或第二栅极的电连接，从而减小电连接路径长度，减小电连接路径对应的电阻；并且，无需设置为实现上下层电连接的接触孔结构，从而避免具有大电阻的接触孔结构带来的不良影响，减小电连接路径对应的电阻。因此，采用本公开实施例提供的标准单元版图模制作的半导体结构，其运行速度能够得到提升，且能够降低半导体结构的功耗，且还能够改善信号质量，例如栅极上的信号延时、信号上升时间和/或信号下降时间得到改善。
另外，本公开实施例提供的标准单元版图模板，可作为DRAM芯片等其他芯片的电路版图设计模板，通过栅电连接图形的布局，使得电路版图布局能够更规整，且不同版图遵循一致的原则，由于优化电路版图的设计，提高版图设计的效率，缩短芯片设计的时间。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为一种标准单元版图模板的结构示意图；
图2为采用图1的标准单元版图模板制作的半导体结构的局部剖面结 构示意图；
图3为本公开一实施例提供的标准单元版图模板的一种结构示意图；
图4为本公开一实施例提供的标准单元版图模型的另一种结构示意图；
图5为本公开一实施例提供的标准单元版图模板的又一种结构示意图；
图6为本公开一实施例提供的标准单元版图模板的再一种结构示意图；
图7为本公开另一实施例提供的标准单元版图模板的一种结构示意图；
图8为本公开另一实施例提供的标准单元版图模板的另一结构示意图；
图9为本公开又一实施例提供的标准单元版图模板的一种结构示意图；
图10为本公开再一实施例提供的半导体结构的俯视结构示意图；
图11为图9中沿CC1方向的一种剖面结构示意图；
图12为本公开再一实施例提供的半导体结构的另一种剖面结构示意图；
图13为本公开再一实施例提供的半导体结构的又一种剖面结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
目前存在采用标准单元版图模板制作的半导体结构功耗大且影响信号质量的问题。
图1为一种标准单元版图模板的结构示意图，图2为采用图1的标准单元版图模板制作的半导体结构的局部剖面结构示意图。
结合参考图1和图2，标准单元版图模板包括：相邻设置的N型阱区11以及P型阱区12；至少一条第一栅极图形13，位于N型阱区11内，用于定义第一栅极23；至少一条第二栅极图形14，位于P型阱区12内，用于定义第二栅极24；第一接触孔图形15，位于第一栅极图形13上，用于定义与第一栅极23电连接的第一接触孔结构25；第二接触孔图形16，位于第二栅极图形14上，用于定义与第二栅极24电连接的第二接触孔结构26；电连接图形17，横跨N型阱区11以及P型阱区12，且连接第一接触孔图形15和第二接触孔图形16，用于定义电连接层27，该电连接层27与第一接触孔结构25以及第二接触孔结构26电连接，且电连接层27为金属层，从而实现第一栅极23与第二栅极24之间的电连接。
如图2所示，第一栅极23与第二栅极24之间的电连接路径为：第一接触孔结构25、电连接层27以及第二接触孔结构26，一方面，该路径相对较长使得该电连接路径具有较大的电阻，另一方面，电连接层27、第一接触孔结构25以及第二接触孔结构26本身具有较大的片电阻值(sheet resistance)。这两方面的问题将导致半导体结构的RC延迟效应增加，半导体结构的功耗增加且运行速度慢，影响第一栅极23和/或第二栅极24上的信号质量，信号质量包括信号延时、信号的上升时间或者信号的下降时间等。若存储器利用该半导体结构，则存储器将面临功耗大且存储速度慢的问题。
此外，采用上述标准单元版图模板进行电路版图布局，电路版图的规整性有待提高，使得版图设计的效率低。
本公开实施例提供一种标准单元版图模板，布局用于定义栅电连接结构的栅电连接图形，且栅电连接结构与第一栅极和/或第二栅极同层设置。利用该标准单元版图模板进行实际版图布局，无需再布局为实现上下层电连接的接触孔结构，从而降低版图对应的半导体结构的电阻。此外，在标准单元版图模板中定义栅电连接图形，在利用该标准单元版图模板进行版图设计时，版图中的栅电连接图形的排布更为统一规整，有利于减少版图设计的难度和时间，减小版图的面积，且减小制造版图对应的半导体结构中的工艺偏差。
图3为本公开一实施例提供的标准单元版图模板的一种结构示意图。
参考图3，本实施例中，标准单元版图模板包括：沿第一方向Y排布的第一阱区I和第二阱区II；第一栅极图形101，位于第一阱区I且沿第一方向Y延伸，用于定义第一栅极；第二栅极图形102，位于第二阱区II且沿第一方向Y延伸，用于定义第二栅极；栅电连接图形103，位于第一栅极图形101与第二栅极图形102之间，用于定义栅电连接结构，栅电连接结构与第一栅极以及第二栅极同层设置，以电连接第一栅极和/或第二栅极。
本实施例提供的标准单元版图模板为制作版图的基础，在实际制作版图期间，基于具体电路结构，在该标准单元版图模板的基础上设计出实际的版图结构。
当设计的版图对应的电路结构需要满足第一栅极和/或第二栅极电连接时，由于栅电连接结构与第一栅极以及第二栅极同层设置，因此无需设置用于实现上下层电连接的接触孔结构，从而有利于缩短栅电连接结构与第一栅极和/或第二栅极之间的电连接路径，且避免接触孔结构的片电阻值大带来的电阻过大的问题。因此，采用本实施例提供的标准单元版图模板，能够减小电路结构的功耗且改善RC延迟效应，例如可改善第一栅极和/或第二栅极上的信号质量。
以下将结合图3对本实施例提供的标准单元版图模板进行详细说明。
本实施例提供的标准单元版图模板可应用于存储器，该存储器可以为DRAM、SRAM(Static Random-Access Memory，静态随机存储器)、MRAM(Magneto resistive Random Access Memory，磁性随机存储器)、FeRAM(Ferroelectric RAM，铁电随机存储器)、PCRAM(Phase Change RAM，相变随机存储器)、HBM(High Bandwidth Memory，高带宽)存储器、NAND闪存或者NOR闪存等存储器。DRAM存储器可以为DDR(Double Data Rate)存储器、LPDDR(Low Power Double Data Rate)存储器或者GDDR(Graphics Double Data Rate)存储器。
标准单元版图模板定义两个MOS管，第一阱区I用于定义其中一MOS管的阱(Well)，第二阱区II用于定义另一MOS管的阱。本实施例中，以第一阱区I定义N型阱且第二阱区II定义P型阱作为示例，即两个MOS管的类型不同。在其他实施例中，两个MOS管的类型可以相同，例如均为NMOS管或者均为PMOS管。
本实施例中，第一阱区I与第二阱区II相邻接，也就是说，第一阱区I的一边界与第二阱区II的一边界重合。可以理解的是，在其他实施例中，标准单元版图模板也可以考虑隔离结构的布局，则第一阱区与第二阱区之间相间隔，且第一阱区与第二阱区之间的区域为隔离区，用于定义隔离结构。
第一阱区I定义N型阱且第二阱区II定义P型阱，则第一阱区I具有的第一高度大于第二阱区II具有的第二高度。可以理解的是，第一高度和第二高度均是指的沿第一方向Y方向的宽度。
第一栅极图形101为条状且位于部分第一阱区I内，第二栅极图形102为条状且位于部分第二阱区II内。
第一阱区I包括：第一MOS区i，且第一栅极图形101横跨第一MOS区i，或者说，在沿第一方向Y上，第一栅极图形101所在的区域定义为第一MOS区i，该第一MOS区i也可称为第一有源区；且沿第一方向Y上，第一MOS区i的宽度与第一栅极图形101的宽度相同。
第二阱区II包括：第二MOS区ii，且第二栅极图形102横跨第二MOS区ii；或者说，在沿第一方向Y上，第二栅极图形102所在的区域定义为第二MOS区ii，该第二MOS区ii也可称为第二有源区；且在沿第一方向上，第二MOS区ii的宽度与第二栅极图形102的宽度相同。
标准单元版图模板还包括：中间区iii，该中间区iii位于第一MOS区i与第二MOS区ii之间。为了降低利用该标准单元版图模板制作的版图位置偏差，提高利用同一标准单元版图模板的不同电路版图的第一阱区I的位置高度一致性，本实施例中，第一阱区I具有朝向第二阱区II的第一边界B1，且第一边界B1位于中间区iii的正中间位置，即，在沿第一方向Y上，第一边界B1至邻近的第一MOS区i的边界的距离为第一距离，第一边界B1至邻近的第二MOS区ii的边界的距离为第二距离，该第二距离与第一距离相等。可以理解的是，在其他实施例中，在满足版图设计规则(Layout Design Rule，LDR)和DRC(Design Rule Check)的情况下，第一边界也可以有其他的位置关系。
本实施例中，标准单元版图模板还可以包括：第一栅极延伸图形111，第一栅极延伸图形111位于第一阱区I且与第一栅极图形101的端部相连，用于定义第一栅极延伸结构。第一栅极延伸图形111位于第一MOS区i之外， 且第一栅极延伸图形111为条状且其延伸方向与第一方向Y不同，第一栅极延伸图形111的延伸方向可以为第二方向X，且第二方向X可以与第一方向Y相垂直。
第一栅极延伸图形111的设置，使得第一栅极与栅电连接结构之间通过第一栅极延伸结构电连接，因此，第一栅极与栅电连接结构之间的电连接窗口增加，从而降低相应的制作工艺的工艺难度，如降低对准精度。在沿第二方向X上，第一栅极延伸图形111的宽度大于第一栅极图形101的宽度；相较于直接在第一栅极图形101与栅电连接图形103之间布局第一辅助图形的方案而言，在第一栅极延伸图形111与栅电连接图形103之间布局第一辅助图形的布局空间明显更大，在沿第二方向X上，该布局空间的宽度由第一栅极图形101的宽度增大至第一栅极延伸图形111的宽度。
同样的，标准单元版图模板还可以包括：第二栅极延伸图形112，第二栅极延伸图形112位于第二阱区II且与第二栅极图形102的端部相连，用于定义第二栅极延伸结构。且在沿第二方向X上，第二栅极延伸图形112的宽度大于第二栅极图形102的宽度。有关第二栅极延伸图形112的效果，可参考第一栅极延伸图形111的相应描述，在此不再赘述。
需要说明的是，在其他实施例中，标准单元版图模板也可以不设置第一栅极延伸图形和第二栅极延伸图形。
由于栅电连接图形103定义的栅电连接结构与第一栅极以及第二栅极同层设置，当栅电连接结构与第一栅极和/或第二栅极结构电连接时，无需设置具有大电阻的接触孔结构，如此，即缩短了电连接路径又避免了接触孔结构带来的电阻大的问题，从而有利于降低该标准单元版图模板对应的电路结构的功耗以及RC效应。当该电路结构应用于存储器，则能够降低存储器的功耗以及提高存储速度。
此外，栅电连接结构的材料可以与第一栅极的材料以及第二栅极的材料相同。这样，在工艺制作过程中，可利用第一栅极以及第二栅极的制造工艺同时制造栅电连接结构，以减少工艺步骤降低生产成本；此外，第一栅极与第二栅极的材料为多晶硅时，栅电连接结构的材料为多晶硅，一般的，相较于金属如铜而言，多晶硅的电阻率比金属的电阻率更小，因此材料为多晶硅的栅电连接结构有利于减小电阻。
本实施例中，栅电连接图形103包括：至少两条相间隔的电连接图形，且每条电连接图形均沿第二方向X延伸，第二方向X与第一方向Y不同，每一电连接图形用于定义一电连接结构。其中，第二方向X可以与第一方向Y相垂直。可以理解的是，在其他实施例中，在满足LDR和DRC前提下，第二方向与第一方向之间的夹角可以也在其他合适范围内。
相应的，栅电连接结构包括至少两个相互间隔的电连接结构，这样，可提高标准单元版图模板可应用的具体电路的数量，增加标准单元版图模板的可应用场景。
至少两条相间隔的电连接图形包括：第一电连接图形113，位于第一阱区I，用于定义第一电连接结构，以电连接第一栅极；第二电连接图形123，位于第二阱区II，用于定义第二电连接结构，以电连接第二栅极。由于第一电连接图形113位于第一阱区I，有利于减小第一电连接结构与第一栅极之间的距离，从而减小第一电连接结构与第一栅极之间的电连接路径，进而减小电连接路径上的电阻。同样的，第二电连接图形123位于第二阱区II，有利于减小第二电连接结构与第二栅极之间的电连接路径上的电阻。
本实施例中，栅电连接图形103位于中间区iii。这样，栅电连接图形103不会对第一MOS区i和第二MOS区ii的布局造成干扰，保证对应的半导体结构具有相对较长的第一有源区宽度和第二有源区宽度。在其他实施例中，若第一阱区与第二阱区之间布局有隔离区，则栅电连接图形可布局在隔离区。
需要说明的是，在其他实施例中，根据标准单元版图模板适用的电路结构的复杂程度的不同，栅电连接图形还可以包括三条及以上数量的电连接图形。
图4为本实施例提供的标准单元版图模型的另一种结构示意图，还需要说明的是，在其他实施例中，如图4所示，栅电连接图形103也可以包括一条电连接图形，且电连接图形沿第二方向X延伸，第二方向X与第一方向Y不同。部分电连接图形位于第一阱区I，剩余部分电连接图形位于第二阱区II，例如，一半电连接图形占据第一阱区I部分空间位置，另一半电连接图形占据第二阱区II部分空间位置。
为了增加标准单元版图模板的应用场景，使得标准单元版图模板既可适用于第一栅极与第二栅极之间的电连接，还可以适用于栅电连接结构与第一 栅极结构或者第二栅极结构中的一者电连接，该标准单元版图模板可无需设计用于辅助图形，在设计具体版图期间再进行辅助布局。以下将结合设计具体版图对标准单元版图模板进行说明：
在一个例子中，利用该标准单元版图模板设计版图时，若版图对应的具体电路结构为第一栅极与第二栅极电连接，则在该标准单元版图基础上，额外设计辅助图形以定义辅助电连接结构，使得栅电连接结构通过辅助电连接结构电连接第一栅极以及第二栅极。在另一例子中，若版图对应的具体电路结构为栅电连接图形与第一栅极电连接，则在该标准单元版图基础上，额外设计辅助图形以定义辅助电连接结构，使得栅电连接结构通过辅助电连接结构与第一栅极电连接。
可以理解的是，也可以根据标准单元版图模板对应的具体电路结构的不同，预先在标准单元版图模板中布局辅助图形。图5为本实施例提供的标准单元版图模板的又一种结构示意图，参考图5，标准单元版图模板的栅电连接图形103还可以包括：第一辅助图形104，连接第一栅极图形101与朝向第一栅极图形101的电连接图形，用于定义第一辅助电连接结构，以电连接第一栅极与朝向第一栅极的电连接结构；第二辅助图形105，连接第二栅极图形102与朝向第二栅极图形102的电连接图形，用于定义第二辅助电连接结构，以电连接第二栅极与朝向第二栅极的电连接结构。
其中，第一辅助电连接结构与第一栅极和/或第二栅极同层设置，且第一辅助电连接结构与第一栅极和/或第二栅极的材料可以相同；第二辅助电连接结构与第一栅极和/或第二栅极同层设置，且第二辅助电连接结构与第一栅极和/或第二栅极的材料可以相同。
第一辅助图形104的布局，使得标准单元版图模板对应的具体电路结构中，第一栅极与栅电连接结构电连接；第二辅助图形105的布局，使得标准单元版图模板对应的具体电路结构中，第二栅极与栅电连接结构电连接。如此，在利用该标准单元版图模板设计版图期间，版图工程师或者自动版图布局工具无需再额外布局第一辅助图形和第二辅助图形。
图6为本实施例提供的标准单元版图模板的再一种结构示意图，参考图6，栅电连接图形103还可以包括：第三辅助图形106，位于相邻的电连接图形之间，用于定义第三辅助电连接结构，以电连接相邻的电连接结构。如此， 该标准单元版图模板对应的具体电路中，相邻的电连接结构之间电连接。第三辅助电连接结构可以与第一栅极和/或第二栅极同层设置，且材料可以相同。
此外，在另一些实施例中，栅电连接图形可以既包括第一辅助图形和第二辅助图形，还可以包括第三辅助图形。
本实施例中，如图3所示，栅电连接图形103还可以位于，第一栅极图形101远离第二栅极图形102的一侧，以及，第二栅极图形102远离第一栅极图形101的一侧。也就是说，栅电连接图形103还布局在标准单元版图模板的顶部和底部，这样，可以增加标准单元版图模板适用的场景，以便于利用该标准单元版图进行更为复杂的版图设计。
标准单元版图模板还可以包括：第一阱连接图形131，位于第一阱区I，用于定义第一阱插塞(plug)；第二阱连接图形132，位于第二阱区II，用于定义第二阱插塞。其中，第一阱连接图形131位于第一阱区I远离第二阱区II的边缘，第二阱连接图形132位于第二阱区II远离第一阱区I的边缘。
本实施例中，沿第一方向Y上，标准单元版图模板具有远离第二阱区II的第二边界B2。在利用该标准单元版图模板设计版图时，两个电路版图可相对于第二边界B2的轴对称。两个电路版图共用第二边界B2，定义一电路版图的第一阱区I朝向第二边界B2的边界为第三边界，定义另一电路版图的第一阱区I朝向第二边界B2的边界为第四边界，且第二边界B2位于第三边界与第四边界之间的正中间位置。
可基于版图设计规则(Layout Design Rule，LDR)来设计标准单元版图模板。例如：每个标准单元版图模板的高度相同；标准单元版图模板包括所有的设计规则和布线指南；需要考虑标准单元版图模板的边界，以确保将不同的标准单元版图模板放置在一起时能够通过DRC(Design Rule Check)以及版图原理图一致性检查(Layout Versus Schematics，LVS)；为了便于块级布线(block level routing)，还需要考虑标准单元版图模板的输入/输出位置。
此外，还可以考虑P/N比例以及标准单元延时参数(tPD)来设计标准单元版图模板。
本实施例提供一种标准单元版图模板，版图工程师可利用该标准单元版图模板设计版图。由于标准单元版图模板中布局有栅电连接图形，该栅电连 接图形用于定义与第一栅极和/或第二栅极同层设置的栅电连接结构，可利用该栅电连接结构与第一栅极和/或第二栅极的电连接因此无需设置实现上下层电连接的接触孔结构，从而减小了相应半导体结构的电连接路径的电阻，进而减小半导体结构对应的电路结构的功耗，改善RC延迟效应。
另外，本实施例提供的标准单元版图模板，无需为定义与第一栅极和/或第二栅极电连接的图形层(即M0)预留空间位置，因而能够减小利用该标准单元版图模板设计的电路版图的面积，例如可减小电路版图中逻辑区的面积；此外，版图工程师利用该标准单元版图模板设计版图时，可将为定义与第一栅极和/或第二栅极电连接的图形层的面积设计的较小，从而有利于减小版图对应的电路结构的负载。同时，该标准单元版图模板可作为DRAM芯片等其他芯片的版图设计模板，使得相应的电路版图布局更规整，不同的电路版图遵循一致的规则，以优化版图设计，提高版图设计的效率，缩短芯片设计的时间。
本公开另一实施例还提供一种标准单元版图模板，该标准单元版图模板与前一实施例大致相同，主要区别包括：还布局有电源图形。以下将结合附图对本公开另一实施例提供的标准单元版图模板进行详细说明，需要说明的是，与前一实施例相同或者相应的部分，可参考前述实施例的说明，在此不再赘述。
图7为本公开另一实施例提供的标准单元版图模板的一种结构示意图，图8为本公开另一实施例提供的标准单元版图模板的另一结构示意图。
图7对应的标准单元版图模板可应用于高速存储器，图8对应的标准单元版图模板可应用于低功耗存储器。
结合参考图7及图8，本实施例中，标准单元版图模板还包括：第一电源图形201，用于定义第一电源走线，第一电源走线用于连接第一电源；第二电源图形202，用于定义第二电源走线，第二电源走线用于连接第二电源，且第一电源的电压大于第二电源的电压；其中，在沿第一方向Y上，第一电源图形201的宽度大于第二电源图形202的宽度。
第一阱区I定义PMOS管的阱，第二阱区II定义NMOS管的阱。由于PMOS管与NMOS管的宽度尺寸一般是2:1，因此用来为PMOS管供电的第一电源走线比用来为NMOS管供电的第二电源走线更宽。
在一个例子中，如图8所示，标准单元版图模板可以包括：第三电源图形203，用于定义第三电源走线，第三电源走线用于连接第三电源；第四电源图形204，用于定义第四电源走线，第四电源走线用于连接第四电源，且第三电源的电压大于第四电源的电压。在沿第一方向Y上，第三电源图形203的宽度大于第四电源图形204的宽度。
标准单元版图模板还可以包括：信号线图形205，用于定义信号线，且信号线图形205的数量为至少两个，一信号线图形205与第一阱区I对应，另一信号线图形205与第二阱区II对应。每一信号线图形205对应的区域内可布局多条信号线。
在利用标准单元版图模板设计版图时，若对应的电路结构需要至少两种高电平电源，则可利用信号线图形205定义的区域内的至少两条相邻信号线合并，作为连接第二种高电平电源的电源走线。这样，工作在不同电源域下的电路版图可同排放置，即可相邻排布；由于第一种高电平电源的电源走线由第一电源图形201定义，第二种高电平电源的电源走线由信号线图形205定义的区域内的至少两条相邻信号线合并，因此这两种电源的电源走线不会出现在同一条通道(即track)上，因此不会出现短路的问题，从而提高了标准单元版图模板的应用场景。
此外，标准单元版图模板内还可布局设计金属开关图形，通过该金属开关图形使得该标准单元版图模板可适用于如下两种应用场景：
一、该金属开关图形与电源走线连接，金属开关图形定义的结构连接的其他电路结构与电源连接，从而实现第一种电路功能；二、该金属开关图形与信号走线连接，金属开关图形定义的结构连接的其他电路结构与信号走线连接，从而实现第二种电路功能。
标准单元版图模板包括：电源图形，用于定义电源走线，该电源走线用于连接电源；信号图形207，用于定义信号走线；第一选通图形208，用于定义第一选通开关，第一选通开关用于实现与电源走线的电连接或者断开；第二选通图形209，用于定义第二选通开关，第二选通开关用于实现与信号走线的电连接或者断开；其中，信号图形207、第一选通图形208以及第二选通图形209位于电源图形的同一侧。
电源图形可以包括第一电源图形201或者第二电源图形202中的至少一 者。第一选通图形208以及第二选通图形209构成金属开关图形，第一选通图形208和第二选通图形209中的一者参与实际布线，例如，第一选通图形208参与布线且第二选通图形209不参与布线，则第一选通开关连接电源走线且第二选通开关断开；第一选通图形208不参与布线且第二选通图形209参与布线，则第一选通开关断开且第二选通开关连接信号走信。
本实施例中，信号图形207包括：沿第三方向排布的两个子信号图形217，且两个子信号图形217之间具有间隔；第一选通图形208与其中一子信号图形217相连，且第一选通图形208位于子信号图形217与电源图形之间；第二选通图形209位于两个子信号图形217之间，且在平行于第三方向上，第二选通图形209的长度大于或等于间隔的长度。其中，第三方向可以与第二方向X相同。
可以理解的是，在其他实施例中，信号图形也可以仅包括单个子选通图形。
本实施例提供的标准单元版图模板，通过合理布局电源图形、信号图形、第一选通图形以及第二选通图形，增加了标准单元版图模板的可应用场景。考虑到实际芯片设计中，可冗余的根据标准单元版图模板调节实际的版图，例如通过第一选通图形或者第二选通图形以改变版图对应的电路结构，从而调整电路结构对应的延时参数。
本公开又一实施例还提供一种标准单元版图模板，与前述实施例大致相同，主要区别包括：前述实施例提供的标准单元版图模板可用于人工布线(custom layout，即自定义布局)，本实施例提供的标准单元版图模板可应用自动布线，即可采用全芯片的自动化物理设计(auto-PR，place route)以利用标准单元版图模板进行版图布局。图9为本公开又一实施例提供的标准单元版图模板的一种结构示意图。
以下将结合附图对本公开又一实施例提供的标准单元版图模板进行详细说明，需要说明的是，与前述实施例相同或者相应的部分，以下将不做详细赘述。
参考图9，本实施例中，标准单元版图模板还包括：金属层图形30，金属层图形30横跨栅电连接图形103、第一栅极图形101和/或第二栅极图形102，用于定义金属层，金属层位于第一栅极与第二栅极的上层，以电连接第 一栅极和/或第二栅极。
需要说明的是，若标准单元版图模板还包括第一栅极延伸图形111和第二栅极延伸图形112，则金属层图形30横跨栅电连接图形103、第一栅极图形101和/或第二栅极图形102实际指的是：金属层图形30横跨栅电连接图形103、第一栅极延伸图形111和/或第二栅极延伸图形112。
金属层为实现自动布线提供条件。本实施例中，以金属层电连接第一栅极以及第二栅极作为示例，则金属层图形30横跨第一栅极延伸图形111、栅电连接图形103以及第二栅极延伸图形112。可以理解的是，若金属层仅电连接第一栅极，则金属层图形30与栅电连接图形103交叠区域对应布局接触孔结构，该栅电连接图形103定义的栅电连接结构与第一栅极电连接；若金属层仅电连接第二栅极，则金属层图形30与栅电连接图形103交叠区域对应布局接触孔结构，该栅电连接图形103定义的栅电连接结构与第二栅极电连接。
标准单元版图模板具有自定义布局区域AA，第一阱区I和第二阱区II位于自定义布局区域AA内，且金属层图形30的部分图形位于自定义布局区域AA内，其余部分图形位于自定义布局区域AA外。
金属层图形30包括：第一金属层图形31，第一金属层图形31沿第一方向Y延伸，且与栅电连接图形103、第一栅极延伸图形111和/或第二栅极延伸图形112具有重叠部分；第二金属层图形32，与第一金属层图形31连接且沿第二方向X延伸至自定义布局区域AA外；第三金属层图形33，位于自定义布局区域AA外且与第二金属层图形32连接，第三金属层图形33沿第一方向Y延伸。
需要说明的是，在其他实施例中，若标准单元版图模板未布局第一栅极延伸图形和第二栅极延伸图形，则金属层图形横跨栅电连接图形、第一栅极图形和/或第二栅极图形，即金属层图形与第一栅极图形和/或第二栅极图形具有重叠部分。
本实施例提供的标准单元版图模板，通过布局金属层图形，为实现自动化布局提供条件。
本公开再一实施例还提供一种半导体结构，可利用上述实施例提供的标准单元版图模板制作。图10为本公开再一实施例提供的半导体结构的俯视结 构示意图，图11为图10中沿CC1方向的一种剖面结构示意图。
参考图10及图11，本实施例中，半导体结构包括：基底400，基底400内具有沿第一方向排布的第一阱41和第二阱42；第一栅极401，位于第一阱41的基底400上且沿第一方向Y延伸；第二栅极402，位于第二阱42的基底400上且沿第一方向Y延伸；栅电连接结构403，位于基底400上，且与第一栅极401以及第二栅极402同层设置，以电连接第一栅极401和/或第二栅极402。
半导体结构可以为DRAM、SRAM、MRAM、FeRAM、PCRAM、HBM存储器、NAND闪存或者NOR闪存等存储器。
由于栅电连接结构403与第一栅极401以及第二栅极402处于同层，因此无需设置为实现上下层电连接的接触孔结构，就能够实现栅电连接结构403与第一栅极401或者第二栅极402之间的电连接，与栅电连接结构位于第一栅极和第二栅极上方的方案相比，本实施例能够缩短栅电连接结构403与第一栅极401之间的电连接路径，缩短栅电连接结构403与第二栅极402之间的电连接路径，从而减小电连接路径对应的电阻，进而降低半导体结构的功耗且改善RC延迟效应。
例如，可以在形成第一栅极401和/或第二栅极402的工艺步骤中，同时形成栅电连接结构403。相应的，栅电连接结构403顶部可以与第一栅极401顶部以及第二栅极402顶部齐平。此外，栅电连接结构403底部也可以与第一栅极401底部以及第二栅极402底部齐平，这样，栅电连接结构403具有相对较厚的厚度，从而有利于减小栅电连接结构403的整体电阻，从而减小半导体结构的功耗以及RC延迟效应。可以理解的是，此处的“顶部”指的是远离基底400的顶面，此处的“底部”指的是朝向基底400的底面。
此外，本实施例中，栅电连接结构403的材料也可以为与第一栅极401以及第二栅极402的材料相同。在一个具体例子中，栅电连接结构403的材料、第一栅极401的材料以及第二栅极402的材料均为多晶硅；一般的，多晶硅的电阻率较金属的电阻率更低，例如多晶硅的电阻率比铜的电阻率更低，因此采用多晶硅作为栅电连接结构403的材料，能够降低电连接路径的电阻，从而降低半导体结构的功耗。
本实施例中，半导体结构还可以包括：第一辅助栅极411，与第一栅极 401端部相连，且沿第二方向X延伸；第二辅助栅极412，与第二栅极402端部相连，且沿第二方向X延伸。其中，第一辅助栅极411与第一栅极401同层设置且材料相同，第二辅助栅极412与第二栅极402同层设置且材料相同。且在沿第二方向X上，第一辅助栅极411的宽度大于第一栅极401的宽度，第二辅助栅极412的宽度大于第二栅极402的宽度。第一辅助栅极411的设置，有利于增加第一栅极401与栅电连接结构403电连接的工艺窗口(process window)；第二辅助栅极412的设置，有利于增加第二栅极402与栅电连接结构403电连接的工艺窗口，从而降低工艺对准精度的需求，降低半导体结构的制作难度。
本实施例中，栅电连接结构403包括至少两个电连接结构，且每个电连接结构均沿第二方向X延伸，且第二方向X与第一方向Y不同。
至少两个电连接结构包括：第一电连接结构413，位于第一阱41的基底400上，第一电连接结构413与第一栅极401以及第二栅极402同层设置；第二电连接结构423，位于第二阱42的基底400上，第二电连接结构423与第一栅极401以及第二栅极402同层设置。
第一电连接结构413可用于通过第一辅助栅极411电连接第一栅极401，第二电连接结构423可用于通过第二辅助栅极412电连接第二栅极402。
图12为本实施例提供的半导体结构的另一种剖面结构示意图。
参考图12，栅电连接结构403还可以包括：第一辅助电连接结构433，位于第一栅极401与朝向第一栅极401的电连接结构之间，以电连接第一栅极401与朝向第一栅极401的电连接结构；第二辅助电连接结构443，位于第二栅极402与朝向第二栅极402的电连接结构之间，以电连接第二栅极402与朝向第二栅极的电连接结构。
第一辅助电连接结构433与第一电连接结构413以及第一辅助栅极411相接触且电连接，第二辅助电连接结构443与第二电连接结构423以及第二辅助栅极412相接触且电连接。
第一辅助电连接结构433以及第二辅助电连接结构443与第一栅极401以及第二栅极402处于同层。
图13为本实施例提供的半导体结构的又一种剖面结构示意图。
参考图13，本实施例中，栅电连接结构403还可以包括：第三辅助电连 接结构453，位于相邻的电连接结构之间，以电连接相邻的电连接结构。这样，该半导体结构对应的具体电路为相邻的电连接结构电连接。
可以理解的是，在其他实施例中，栅电连接结构也可以仅包括一个电连接结构，且根据半导体结构对应的具体电路结构，该电连接结构可以与第一栅极电连接，或者，该电连接结构可以与第二栅极电连接，或者，该电连接结构与第一栅极以及第二栅极电连接。
本实施例提供的半导体结构的技术方案中，可通过同层设置的栅电连接结构403实现与第一栅极401和/或第二栅极402的电连接，既减小了电连接路径，又无需设置具有大电阻的接触孔结构，因此有利于减小半导体结构的电阻，从而减小半导体结构的功耗以及RC延迟效应。半导体结构为存储器，则还能够提高存储器的存储速度。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清 楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的标准单元版图模板以及半导体结构中，可通过与第一栅极和第二栅极处于同层的栅电连接结构实现与第一栅极和/或第二栅极的电连接，从而减小电连接路径长度，减小电连接路径对应的电阻；并且，无需设置为实现上下层电连接的接触孔结构，从而避免具有大电阻的接触孔结构带来的不良影响，减小电连接路径对应的电阻。因此，采用本公开实施例提供的标准单元版图模制作的半导体结构，其运行速度能够得到提升，且能够降低半导体结构的功耗，且还能够改善信号质量，例如栅极上的信号延时、信号上升时间和/或信号下降时间得到改善。另外，本公开实施例提供的标准单元版图模板，可作为DRAM芯片等其他芯片的电路版图设计模板，通过栅电连接图形的布局，使得电路版图布局能够更规整，且不同版图遵循一致的原则，由于优化电路版图的设计，提高版图设计的效率，缩短芯片设计的时间。

Claims (18)

  1. 一种标准单元版图模板，包括：
    沿第一方向排布的第一阱区和第二阱区；
    第一栅极图形，位于所述第一阱区且沿所述第一方向延伸，用于定义第一栅极；
    第二栅极图形，位于所述第二阱区且沿所述第一方向延伸，用于定义第二栅极；
    栅电连接图形，位于所述第一栅极图形与所述第二栅极图形之间，用于定义栅电连接结构，所述栅电连接结构与所述第一栅极以及所述第二栅极同层设置，以电连接所述第一栅极和/或所述第二栅极。
  2. 如权利要求1所述的标准单元版图模板，其中，所述栅电连接图形包括：
    至少两条相间隔的电连接图形，且每条所述电连接图形均沿第二方向延伸，所述第二方向与所述第一方向不同，每一所述电连接图形用于定义一电连接结构。
  3. 如权利要求2所述的标准单元版图模板，其中，至少两条相间隔的所述电连接图形包括：
    第一电连接图形，位于所述第一阱区，用于定义第一电连接结构，以电连接所述第一栅极；
    第二电连接图形，位于所述第二阱区，用于定义第二电连接结构，以电连接所述第二栅极。
  4. 如权利要求2所述的标准单元版图模板，所述栅电连接图形还包括：
    第一辅助图形，连接所述第一栅极图形与朝向所述第一栅极图形的所述电连接图形，用于定义第一辅助电连接结构，以电连接所述第一栅极与朝向所述第一栅极的所述电连接结构；
    第二辅助图形，连接所述第二栅极图形与朝向所述第二栅极图形的所述电连接图形，用于定义第二辅助电连接结构，以电连接所述第二栅极与朝向所述第二栅极的所述电连接结构。
  5. 如权利要求2所述的标准单元版图模板，所述栅电连接图形还包括：
    第三辅助图形，位于相邻的所述电连接图形之间，用于定义第三辅助电连接结构，以电连接相邻的所述电连接结构。
  6. 如权利要求1所述的标准单元版图模板，其中，所述栅电连接图形包括：一条电连接图形，且所述电连接图形沿第二方向延伸，所述第二方向与所述第一方向不同。
  7. 如权利要求6所述的标准单元版图模板，其中，部分所述电连接图形位于所述第一阱区，剩余部分所述电连接图形位于所述第二阱区。
  8. 如权利要求1所述的标准单元版图模板，所述栅电连接图形还位于，所述第一栅极图形远离所述第二栅极图形的一侧，以及，位于所述第二栅极图形远离所述第一栅极图形的一侧。
  9. 如权利要求1所述的标准单元版图模板，还包括：
    金属层图形，所述金属层图形横跨所述栅电连接图形、所述第一栅极图形和/或所述第二栅极图形，用于定义金属层，所述金属层位于所述第一栅极与所述第二栅极的上层，以电连接所述第一栅极和/或所述第二栅极。
  10. 如权利要求1所述的标准单元版图模板，其中，所述第一阱区包括：第一MOS区，且所述第一栅极图形横跨所述第一MOS区；
    所述第二阱区包括：第二MOS区，且所述第二栅极图形横跨所述第二MOS区；
    所述标准单元版图模板还包括：中间区，所述中间区位于所述第一MOS区与所述第二MOS区之间，其中，所述栅电连接图形位于所述中间区。
  11. 如权利要求10所述的标准单元版图模板，其中，所述第一阱区具有朝向所述第二阱区的第一边界，且所述第一边界位于所述中间区的正中间位置。
  12. 如权利要求1所述的标准单元版图模板，还包括：
    第一电源图形，用于定义第一电源走线，所述第一电源走线用于连接第一电源；
    第二电源图形，用于定义第二电源走线，所述第二电源走线用于连接第二电源，且所述第一电源的电压大于所述第二电源的电压；
    其中，在沿所述第一方向上，所述第一电源图形的宽度大于所述第二电 源图形的宽度。
  13. 如权利要求1所述的标准单元版图模板，还包括：
    电源图形，用于定义电源走线，所述电源走线用于连接电源；
    信号图形，用于定义信号走线，所述信号走线用于连接信号；
    第一选通图形，用于定义第一选通开关，所述第一选通开关用于实现与所述电源走线的电连接或者断开；
    第二选通图形，用于定义第二选通开关，所述第二选通开关用于实现与所述信号走线的电连接或者断开；其中，所述信号图形、所述第一选通图形以及所述第二选通图形位于所述电源图形的同一侧。
  14. 一种半导体结构，包括：
    基底，所述基底内具有沿第一方向排布的第一阱和第二阱；
    第一栅极，位于所述第一阱的所述基底上且沿所述第一方向延伸；
    第二栅极，位于所述第二阱的所述基底上且沿所述第一方向延伸；
    栅电连接结构，位于所述基底上，且与所述第一栅极以及所述第二栅极同层设置，以电连接所述第一栅极和/或所述第二栅极。
  15. 如权利要求14所述的半导体结构，其中，所述栅电连接结构包括：
    至少两个电连接结构，且每个所述电连接结构均沿第二方向延伸，所述第二方向与所述第一方向不同。
  16. 如权利要求15所述的半导体结构，其中，至少两个所述电连接结构包括：
    第一电连接结构，位于所述第一阱的所述基底上；
    第二电连接结构，位于所述第二阱的所述基底上。
  17. 如权利要求15所述的半导体结构，所述栅电连接结构还包括：
    第一辅助电连接结构，位于所述第一栅极与朝向所述第一栅极的所述电连接结构之间，以电连接所述第一栅极与朝向所述第一栅极的所述电连接结构；
    第二辅助电连接结构，位于所述第二栅极与朝向所述第二栅极的所述电连接结构之间，以电连接所述第二栅极与朝向所述第二栅极的所述电连接结构。
  18. 如权利要求15所述的半导体结构，所述栅电连接结构还包括：第三 辅助电连接结构，位于相邻的所述电连接结构之间，以电连接相邻的所述电连接结构。
PCT/CN2021/107779 2021-02-05 2021-07-22 标准单元版图模板以及半导体结构 WO2022166126A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024093124A1 (zh) * 2022-11-04 2024-05-10 长鑫存储技术有限公司 开关标准单元、开关以及版图设计方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4060738A4 (en) 2021-02-05 2022-11-30 Changxin Memory Technologies, Inc. STANDARD CELL TEMPLATE AND SEMICONDUCTOR STRUCTURE
CN112992892B (zh) * 2021-02-05 2022-04-22 长鑫存储技术有限公司 标准单元版图模板以及半导体结构
US20230009090A1 (en) * 2021-07-12 2023-01-12 Changxin Memory Technologies, Inc. Semiconductor device layout structure and method of forming semiconductor device
CN115810371A (zh) * 2021-09-15 2023-03-17 长鑫存储技术有限公司 读出电路架构
CN117688889A (zh) * 2022-09-02 2024-03-12 长鑫存储技术有限公司 版图结构、半导体结构以及存储器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009176968A (ja) * 2008-01-24 2009-08-06 Sony Corp 半導体集積回路装置
CN103035577A (zh) * 2011-10-09 2013-04-10 中国科学院微电子研究所 一种半导体结构及其制造方法
CN103928402A (zh) * 2013-01-11 2014-07-16 中芯国际集成电路制造(上海)有限公司 共用栅极的半导体结构及对应的形成方法
CN112992892A (zh) * 2021-02-05 2021-06-18 长鑫存储技术有限公司 标准单元版图模板以及半导体结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009176968A (ja) * 2008-01-24 2009-08-06 Sony Corp 半導体集積回路装置
CN103035577A (zh) * 2011-10-09 2013-04-10 中国科学院微电子研究所 一种半导体结构及其制造方法
CN103928402A (zh) * 2013-01-11 2014-07-16 中芯国际集成电路制造(上海)有限公司 共用栅极的半导体结构及对应的形成方法
CN112992892A (zh) * 2021-02-05 2021-06-18 长鑫存储技术有限公司 标准单元版图模板以及半导体结构

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4060738A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024093124A1 (zh) * 2022-11-04 2024-05-10 长鑫存储技术有限公司 开关标准单元、开关以及版图设计方法

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