WO2022166126A1 - 标准单元版图模板以及半导体结构 - Google Patents
标准单元版图模板以及半导体结构 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- the present disclosure relates to, but is not limited to, a standard cell layout template and a semiconductor structure.
- the standard cell library is the basis of integrated circuit design.
- the integrated circuit design based on the standard cell library can carry out logic synthesis and layout layout and wiring, and improve the design efficiency of the circuit.
- the standard cell library includes several pre-designed standard cell layout templates.
- the integrated circuit designer or circuit design synthesis tool can call the standard cell layout template in the standard cell library according to the design requirements to complete the layout design of the integrated circuit. .
- the present disclosure provides a standard cell layout template and a semiconductor structure.
- a first aspect of the present disclosure provides a standard cell layout template, including a first well region and a second well region arranged along a first direction; a first gate pattern is located in the first well region and along the first well region. extending in one direction for defining a first gate; a second gate pattern located in the second well region and extending along the first direction for defining a second gate; a gate electrical connection pattern located in the Between the first gate pattern and the second gate pattern, a gate electrical connection structure is defined, and the gate electrical connection structure is arranged in the same layer as the first gate and the second gate to electrically The first gate and/or the second gate are connected.
- a second aspect of the present disclosure provides a semiconductor structure, comprising: a substrate having a first well and a second well arranged in a first direction; a first gate located at the first well of the first well a second gate on the substrate and extending along the first direction; a second gate on the substrate of the second well and extending along the first direction; a gate electrical connection structure on the substrate and connected to the second well
- the first gate and the second gate are disposed in the same layer to electrically connect the first gate and/or the second gate.
- the standard cell layout template includes a first well region and a second well region, and the first gate pattern located in the first well region and extending along the first direction is located in the first well region.
- the second gate pattern in the second well region and extending along the first direction further includes a gate electrical connection pattern located between the first gate pattern and the second gate pattern, where the gate electrical connection pattern is used to define the gate electrical connection structure, and the gate electrical connection structure is arranged in the same layer as the first gate electrode and the second gate electrode.
- the electrical connection with the first gate and/or the second gate can be achieved through the gate electrical connection structure in the same layer as the first gate and the second gate, thereby reducing the length of the electrical connection path and reducing the electrical connection.
- the resistance corresponding to the connection path and, there is no need to provide a contact hole structure for realizing the electrical connection between the upper and lower layers, so as to avoid adverse effects caused by the contact hole structure with large resistance and reduce the resistance corresponding to the electrical connection path. Therefore, the semiconductor structure fabricated by using the standard cell layout die provided by the embodiments of the present disclosure can improve the running speed, reduce the power consumption of the semiconductor structure, and also improve the signal quality, such as the signal delay on the gate, Signal rise time and/or signal fall time are improved.
- the standard cell layout template provided by the embodiment of the present disclosure can be used as a circuit layout design template for other chips such as DRAM chips.
- the layout of the grid electrical connection pattern can make the circuit layout layout more regular, and different layouts follow the same principle. Due to the optimized circuit layout design, the efficiency of layout design is improved and the time of chip design is shortened.
- Fig. 1 is the structural representation of a kind of standard cell layout template
- Fig. 2 is the partial cross-sectional structure schematic diagram of the semiconductor structure that adopts the standard cell layout template of Fig. 1 to make;
- FIG. 3 is a schematic structural diagram of a standard cell layout template provided by an embodiment of the present disclosure.
- FIG. 4 is another schematic structural diagram of a standard cell layout model provided by an embodiment of the present disclosure.
- FIG. 5 is another schematic structural diagram of a standard cell layout template provided by an embodiment of the present disclosure.
- FIG. 6 is still another schematic structural diagram of a standard cell layout template provided by an embodiment of the present disclosure.
- FIG. 7 is a schematic structural diagram of a standard cell layout template provided by another embodiment of the present disclosure.
- FIG. 8 is another schematic structural diagram of a standard cell layout template provided by another embodiment of the present disclosure.
- FIG. 9 is a schematic structural diagram of a standard cell layout template provided by another embodiment of the present disclosure.
- FIG. 10 is a schematic top-view structural diagram of a semiconductor structure provided by still another embodiment of the present disclosure.
- Fig. 11 is a kind of sectional structure schematic diagram along CC1 direction in Fig. 9;
- FIG. 12 is another schematic cross-sectional structure diagram of a semiconductor structure provided by yet another embodiment of the present disclosure.
- FIG. 13 is another schematic cross-sectional structure diagram of a semiconductor structure provided by still another embodiment of the present disclosure.
- FIG. 1 is a schematic structural diagram of a standard cell layout template
- FIG. 2 is a partial cross-sectional structural schematic diagram of a semiconductor structure fabricated by using the standard cell layout template of FIG. 1 .
- the standard cell layout template includes: an N-type well region 11 and a P-type well region 12 arranged adjacently; at least one first gate pattern 13, located in the N-type well region 11, is used to define a first gate 23; at least one second gate pattern 14 located in the P-type well region 12 for defining the second gate 24; a first contact hole pattern 15 located on the first gate pattern 13 for Define the first contact hole structure 25 electrically connected to the first gate 23; the second contact hole pattern 16, located on the second gate pattern 14, is used to define the second contact hole structure electrically connected to the second gate 24 26;
- the electrical connection pattern 17 spans the N-type well region 11 and the P-type well region 12, and connects the first contact hole pattern 15 and the second contact hole pattern 16 for defining an electrical connection layer 27, the electrical connection layer 27 It is electrically connected to the first contact hole structure 25 and the second contact hole structure 26 , and the electrical connection layer 27 is a metal layer, so as to realize the electrical connection between the first gate electrode 23 and the second gate electrode 24 .
- the electrical connection path between the first gate 23 and the second gate 24 is: the first contact hole structure 25 , the electrical connection layer 27 and the second contact hole structure 26 .
- the paths are opposite to each other. Longer makes the electrical connection path have greater resistance.
- the electrical connection layer 27 , the first contact hole structure 25 and the second contact hole structure 26 themselves have a greater sheet resistance.
- An embodiment of the present disclosure provides a standard cell layout template, the layout is used to define a gate electrical connection pattern of a gate electrical connection structure, and the gate electrical connection structure and the first gate and/or the second gate are arranged in the same layer.
- the standard cell layout template to perform actual layout layout, it is not necessary to layout the contact hole structure for realizing the electrical connection between the upper and lower layers, thereby reducing the resistance of the semiconductor structure corresponding to the layout.
- the grid connection pattern is defined in the standard cell layout template.
- the layout of the grid connection pattern in the layout is more uniform and regular, which is beneficial to reduce the difficulty and time of layout design. , the area of the layout is reduced, and the process deviation in the semiconductor structure corresponding to the manufacturing layout is reduced.
- FIG. 3 is a schematic structural diagram of a standard cell layout template provided by an embodiment of the present disclosure.
- the standard cell layout template includes: a first well region I and a second well region II arranged along the first direction Y; a first gate pattern 101, located in the first well region I and along the The first direction Y extends to define the first gate; the second gate pattern 102 is located in the second well region II and extends along the first direction Y to define the second gate; the gate electrical connection pattern 103 is located in Between the first gate pattern 101 and the second gate pattern 102 is used to define a gate electrical connection structure, and the gate electrical connection structure is arranged in the same layer as the first gate and the second gate to electrically connect the first gate and the second gate. /or second gate.
- the standard cell layout template provided in this embodiment is the basis for making a layout.
- an actual layout structure is designed on the basis of the standard cell layout template based on the specific circuit structure.
- the circuit structure corresponding to the designed layout needs to satisfy the electrical connection of the first gate and/or the second gate, since the electrical connection structure of the gate is arranged in the same layer as the first gate and the second gate, there is no need to set it for realizing
- the contact hole structure electrically connecting the upper and lower layers is beneficial to shorten the electrical connection path between the gate electrical connection structure and the first gate and/or the second gate, and avoid the resistance caused by the large sheet resistance of the contact hole structure too big a problem. Therefore, using the standard cell layout template provided in this embodiment can reduce the power consumption of the circuit structure and improve the RC delay effect, for example, the signal quality on the first gate and/or the second gate can be improved.
- the standard cell layout template provided in this embodiment can be applied to memory, and the memory can be DRAM, SRAM (Static Random-Access Memory, static random access memory), MRAM (Magneto resistive Random Access Memory, magnetic random access memory), FeRAM (Ferroelectric RAM) , ferroelectric random access memory), PCRAM (Phase Change RAM, phase change random access memory), HBM (High Bandwidth Memory, high bandwidth) memory, NAND flash memory or NOR flash memory and other memories.
- the DRAM memory can be DDR (Double Data Rate) memory, LPDDR (Low Power Double Data Rate) memory or GDDR (Graphics Double Data Rate) memory.
- the standard cell layout template defines two MOS transistors, the first well region I is used to define the well (Well) of one of the MOS transistors, and the second well region II is used to define the well of the other MOS transistor.
- an N-type well is defined in the first well region I and a P-type well is defined in the second well region II as an example, that is, the types of the two MOS transistors are different.
- the two MOS transistors may be of the same type, for example, both are NMOS transistors or both are PMOS transistors.
- the first well region I and the second well region II are adjacent to each other, that is, a boundary of the first well region I coincides with a boundary of the second well region II.
- the standard cell layout template may also consider the layout of the isolation structure, so that the first well region and the second well region are spaced apart, and the first well region and the second well region are spaced apart.
- the area of is the isolation area, which is used to define the isolation structure.
- the first well region I defines an N-type well and the second well region II defines a P-type well
- the first well region I has a first height greater than the second height of the second well region II. It can be understood that, the first height and the second height both refer to the width along the first direction Y direction.
- the first gate pattern 101 is strip-shaped and located in a part of the first well region I
- the second gate pattern 102 is strip-shaped and located in a part of the second well region II.
- the first well region I includes: a first MOS region i, and the first gate pattern 101 spans the first MOS region i, or in other words, along the first direction Y, the region where the first gate pattern 101 is located is defined as
- the first MOS region i the first MOS region i may also be called the first active region; and along the first direction Y, the width of the first MOS region i is the same as the width of the first gate pattern 101 .
- the second well region II includes: the second MOS region ii, and the second gate pattern 102 spans the second MOS region ii; or, in the first direction Y, the region where the second gate pattern 102 is located is defined as
- the second MOS region ii, the second MOS region ii may also be referred to as the second active region; and along the first direction, the width of the second MOS region ii is the same as the width of the second gate pattern 102 .
- the standard cell layout template further includes: an intermediate region iii, the intermediate region iii is located between the first MOS region i and the second MOS region ii.
- the first well region I has a direction toward the first well region I.
- the first boundary B1 of the two well region II, and the first boundary B1 is located in the middle of the intermediate region iii, that is, along the first direction Y, the distance from the first boundary B1 to the boundary of the adjacent first MOS region i is the first distance, the distance from the first boundary B1 to the boundary of the adjacent second MOS region ii is the second distance, and the second distance is equal to the first distance.
- the layout design rule Layout Design Rule, LDR
- DRC Design Rule Check
- the standard cell layout template may further include: a first gate extension pattern 111, the first gate extension pattern 111 is located in the first well region I and connected to the end of the first gate pattern 101 for defining The first gate extension structure.
- the first gate extension pattern 111 is located outside the first MOS region i, and the first gate extension pattern 111 is strip-shaped and its extension direction is different from the first direction Y.
- the extension direction of the first gate extension pattern 111 may be The second direction X, and the second direction X may be perpendicular to the first direction Y.
- the first gate extension pattern 111 is arranged so that the first gate and the gate electrical connection structure are electrically connected through the first gate extension structure, therefore, the electrical connection window between the first gate and the gate electrical connection structure is increased , thereby reducing the technological difficulty of the corresponding manufacturing process, such as reducing the alignment accuracy.
- the width of the first gate extension pattern 111 is greater than the width of the first gate pattern 101 ; compared to laying out the first auxiliary pattern directly between the first gate pattern 101 and the gate electrical connection pattern 103
- the layout space for laying out the first auxiliary pattern between the first gate extension pattern 111 and the gate electrical connection pattern 103 is significantly larger, and along the second direction X, the width of the layout space is determined by the first The width of the gate pattern 101 increases to the width of the first gate extension pattern 111 .
- the standard cell layout template may further include: a second gate extension pattern 112, the second gate extension pattern 112 is located in the second well region II and is connected to the end of the second gate pattern 102 for defining the second gate pattern 102. Gate extension structure. And along the second direction X, the width of the second gate extension pattern 112 is greater than the width of the second gate pattern 102 .
- the second gate extension pattern 112 reference may be made to the corresponding description of the first gate extension pattern 111 , which will not be repeated here.
- the standard cell layout template may not be provided with the first gate extension pattern and the second gate extension pattern.
- the gate electrical connection structure defined by the gate electrical connection pattern 103 is arranged in the same layer as the first gate and the second gate, when the gate electrical connection structure is electrically connected with the first gate and/or the second gate structure, no need to be provided
- the contact hole structure with high resistance in this way, shortens the electrical connection path and avoids the problem of high resistance caused by the contact hole structure, thereby helping to reduce the power consumption and RC effect of the circuit structure corresponding to the standard cell layout template.
- the circuit structure is applied to the memory, the power consumption of the memory can be reduced and the storage speed can be improved.
- the material of the gate electrical connection structure may be the same as the material of the first gate electrode and the material of the second gate electrode.
- the gate electrical connection structure can be simultaneously manufactured by using the manufacturing processes of the first gate and the second gate, so as to reduce the number of process steps and reduce the production cost; in addition, the materials of the first gate and the second gate are When it is polysilicon, the material of the gate electrical connection structure is polysilicon.
- the resistivity of polysilicon is smaller than that of metal, so the gate electrical connection structure made of polysilicon is conducive to reducing the resistance.
- the gate electrical connection pattern 103 includes: at least two electrical connection patterns spaced apart, and each electrical connection pattern extends along the second direction X, the second direction X is different from the first direction Y, and each electrical connection pattern extends along the second direction X. Connection patterns are used to define an electrical connection structure. Wherein, the second direction X may be perpendicular to the first direction Y. It can be understood that, in other embodiments, on the premise of satisfying LDR and DRC, the included angle between the second direction and the first direction may also be in other suitable ranges.
- the gate electrical connection structure includes at least two mutually spaced electrical connection structures, so that the number of specific circuits to which the standard cell layout template can be applied can be increased, and the applicable scenarios of the standard cell layout template can be increased.
- the at least two spaced-apart electrical connection patterns include: a first electrical connection pattern 113 located in the first well region I for defining a first electrical connection structure to electrically connect the first gate electrode; a second electrical connection pattern 123 located in the first well region I
- the second well region II is used to define a second electrical connection structure to electrically connect the second gate electrode. Since the first electrical connection pattern 113 is located in the first well region I, it is beneficial to reduce the distance between the first electrical connection structure and the first gate, thereby reducing the electrical connection between the first electrical connection structure and the first gate. connection paths, thereby reducing resistance on the electrical connection paths.
- the second electrical connection pattern 123 is located in the second well region II, which is beneficial to reduce the resistance on the electrical connection path between the second electrical connection structure and the second gate.
- the gate electrical connection pattern 103 is located in the middle region iii. In this way, the gate electrical connection pattern 103 will not interfere with the layout of the first MOS region i and the second MOS region ii, ensuring that the corresponding semiconductor structure has relatively long first and second active region widths. In other embodiments, if an isolation region is arranged between the first well region and the second well region, the gate electrical connection pattern can be arranged in the isolation region.
- the gate electrical connection pattern may further include three or more electrical connection patterns.
- FIG. 4 is another schematic structural diagram of the standard cell layout model provided in this embodiment.
- the gate electrical connection pattern 103 may also include an electrical connection pattern.
- the electrical connection pattern extends along the second direction X, and the second direction X is different from the first direction Y.
- Part of the electrical connection patterns are located in the first well region I, and the remaining part of the electrical connection patterns are located in the second well region II.
- half of the electrical connection patterns occupy part of the space in the first well region I, and the other half of the electrical connection patterns occupy the second well region II. Partial space location.
- the standard cell layout template can be applied not only to the electrical connection between the first gate and the second gate, but also to the gate electrical connection structure and the first gate structure or the second gate.
- One of the two gate structures is electrically connected, and the standard cell layout template can be used for auxiliary layout without design, and auxiliary layout is performed during the design of the specific layout.
- the following will describe the standard cell layout template in combination with the specific layout of the design:
- auxiliary electrical connection structure makes the gate electrical connection structure electrically connect the first gate and the second gate through the auxiliary electrical connection structure.
- the specific circuit structure corresponding to the layout is that the gate electrical connection pattern is electrically connected to the first gate
- an additional auxiliary pattern is designed to define the auxiliary electrical connection structure, so that the gate is electrically connected
- the structure is electrically connected to the first gate through an auxiliary electrical connection structure.
- FIG. 5 is another schematic structural diagram of the standard cell layout template provided in this embodiment.
- the gate electrical connection pattern 103 of the standard cell layout template may further include: a first auxiliary pattern 104 , which is connected to the first gate pattern 101
- the electrical connection pattern toward the first gate pattern 101 is used to define the first auxiliary electrical connection structure to electrically connect the first gate with the electrical connection structure toward the first gate;
- the second auxiliary pattern 105 is used to connect the second gate
- the gate pattern 102 and the electrical connection pattern toward the second gate pattern 102 are used to define a second auxiliary electrical connection structure to electrically connect the second gate and the electrical connection structure toward the second gate.
- first auxiliary electrical connection structure and the first gate and/or the second gate are arranged in the same layer, and the material of the first auxiliary electrical connection structure and the first gate and/or the second gate may be the same; the second gate The auxiliary electrical connection structure and the first gate electrode and/or the second gate electrode are disposed in the same layer, and the material of the second auxiliary electrical connection structure and the first gate electrode and/or the second gate electrode can be the same.
- the layout of the first auxiliary pattern 104 is such that in the specific circuit structure corresponding to the standard cell layout template, the first gate is electrically connected to the gate electrical connection structure; the layout of the second auxiliary pattern 105 is such that the specific circuit structure corresponding to the standard cell layout template is wherein, the second gate is electrically connected to the gate electrical connection structure.
- the layout engineer or the automatic layout layout tool does not need to additionally lay out the first auxiliary graphics and the second auxiliary graphics.
- FIG. 6 is another schematic structural diagram of the standard cell layout template provided in this embodiment.
- the gate electrical connection pattern 103 may further include: a third auxiliary pattern 106 located between adjacent electrical connection patterns for A third auxiliary electrical connection structure is defined to electrically connect adjacent electrical connection structures.
- the third auxiliary electrical connection structure may be disposed in the same layer as the first gate electrode and/or the second gate electrode, and the material may be the same.
- the gate electrical connection pattern may include both the first auxiliary pattern and the second auxiliary pattern, and may also include the third auxiliary pattern.
- the gate electrical connection pattern 103 may also be located on the side of the first gate pattern 101 away from the second gate pattern 102, and the second gate pattern 102 away from the first gate One side of graphic 101. That is to say, the grid electrical connection patterns 103 are also arranged on the top and bottom of the standard cell layout template, so that the applicable scenes of the standard cell layout template can be increased to facilitate more complex layout design using the standard cell layout.
- the standard cell layout template may further include: a first well connection pattern 131, located in the first well region I, for defining a first well plug; a second well connection pattern 132, located in the second well region II, for Define the second well plug.
- the first well connection pattern 131 is located at the edge of the first well region I away from the second well region II
- the second well connection pattern 132 is located at the edge of the second well region II away from the first well region I.
- the standard cell layout template has a second boundary B2 away from the second well region II.
- the two circuit layouts may be symmetrical with respect to the axis of the second boundary B2.
- the two circuit layouts share the second boundary B2, define the boundary of the first well region I of one circuit layout towards the second boundary B2 as the third boundary, and define the boundary of the first well region I of another circuit layout towards the second boundary B2 is the fourth boundary, and the second boundary B2 is located in the middle position between the third boundary and the fourth boundary.
- Standard cell layout templates can be designed based on Layout Design Rule (LDR). For example: each standard cell layout template is the same height; standard cell layout template includes all design rules and routing guidelines; standard cell layout template boundaries need to be considered to ensure that different standard cell layout templates can pass DRC when placed together (Design Rule Check) and Layout Versus Schematics (LVS); in order to facilitate block level routing, the input/output positions of standard cell layout templates also need to be considered.
- LDR Layout Design Rule
- the standard cell layout template can also be designed considering the P/N ratio and the standard cell delay parameter (tPD).
- This embodiment provides a standard cell layout template, and a layout engineer can use the standard cell layout template to design a layout. Since the standard cell layout template has a gate electrical connection pattern, the gate electrical connection pattern is used to define a gate electrical connection structure arranged in the same layer as the first gate and/or the second gate, and the gate electrical connection structure can be used to connect with the first gate and/or the second gate. Therefore, the electrical connection of the first gate and/or the second gate does not need to provide a contact hole structure for realizing the electrical connection between the upper and lower layers, thereby reducing the resistance of the electrical connection path of the corresponding semiconductor structure, thereby reducing the circuit structure corresponding to the semiconductor structure. power consumption and improve RC delay effect.
- the standard cell layout template provided in this embodiment does not need to reserve space for defining the pattern layer (ie, M0) electrically connected to the first gate and/or the second gate, so that the use of the standard cell layout can be reduced.
- the area of the circuit layout designed by the template for example, the area of the logic area in the circuit layout can be reduced; in addition, when the layout engineer uses the standard cell layout template to design the layout, it can be defined for the first gate and/or the second gate.
- the area of the electrically connected pattern layer is designed to be small, thereby helping to reduce the load of the circuit structure corresponding to the layout.
- the standard cell layout template can be used as a layout design template for other chips such as DRAM chips, so that the corresponding circuit layout layout is more regular, and different circuit layouts follow consistent rules, so as to optimize the layout design, improve the efficiency of layout design, and shorten the chip. Design time.
- Another embodiment of the present disclosure further provides a standard cell layout template.
- the standard cell layout template is substantially the same as the previous embodiment, and the main differences include: a power supply graphic is also laid out.
- the standard cell layout template provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the previous embodiment, reference may be made to the description of the previous embodiment, which will not be repeated here. .
- FIG. 7 is a schematic structural diagram of a standard cell layout template provided by another embodiment of the present disclosure
- FIG. 8 is another structural schematic diagram of a standard cell layout template provided by another embodiment of the present disclosure.
- the standard cell layout template corresponding to FIG. 7 can be applied to high-speed memory, and the standard cell layout template corresponding to FIG. 8 can be applied to low-power consumption memory.
- the standard cell layout template further includes: a first power supply pattern 201 for defining a first power supply wiring, and the first power supply wiring is used to connect the first power supply; the second power supply The graph 202 is used to define the second power supply line, the second power supply line is used to connect the second power supply, and the voltage of the first power supply is greater than the voltage of the second power supply; wherein, along the first direction Y, the first power supply The width of the pattern 201 is larger than the width of the second power pattern 202 .
- the first well region I defines the well of the PMOS transistor
- the second well region II defines the well of the NMOS transistor. Since the width dimension of the PMOS transistor and the NMOS transistor is generally 2:1, the first power supply line used for powering the PMOS transistor is wider than the second power supply line used for powering the NMOS transistor.
- the standard cell layout template may include: a third power supply pattern 203 for defining a third power supply wiring, and the third power supply wiring is used for connecting the third power supply; a fourth power supply pattern 204 , is used to define the fourth power supply line, the fourth power supply line is used to connect the fourth power supply, and the voltage of the third power supply is greater than the voltage of the fourth power supply.
- the width of the third power pattern 203 is greater than the width of the fourth power pattern 204 .
- the standard cell layout template may also include: signal line patterns 205 for defining signal lines, and the number of signal line patterns 205 is at least two, one signal line pattern 205 corresponds to the first well region I, and the other signal line pattern 205 Corresponds to the second well region II.
- a plurality of signal lines can be arranged in the area corresponding to each signal line pattern 205 .
- the corresponding circuit structure requires at least two high-level power supplies
- at least two adjacent signal lines in the area defined by the signal line pattern 205 can be used to combine as a connection for the second type of power supply. Power traces for high-level power supplies.
- the circuit layouts working in different power domains can be placed in the same row, that is, they can be arranged adjacently; since the power traces of the first high-level power supply are defined by the first power supply pattern 201, The power traces of the power supply are merged by at least two adjacent signal lines in the area defined by the signal line pattern 205, so the power traces of the two power sources do not appear on the same channel (ie, track), so there is no short circuit problems, thus improving the application scenarios of standard cell layout templates.
- metal switch graphics can be laid out in the standard cell layout template, and the standard cell layout template can be applied to the following two application scenarios through the metal switch graphics:
- the metal switch pattern is connected with the power supply wiring, and other circuit structures connected by the structure defined by the metal switch pattern are connected with the power supply, so as to realize the first circuit function; 2.
- the metal switch pattern is connected with the signal wiring, and the metal switch pattern The other circuit structures connected by the defined structure are connected with the signal traces, thereby realizing the second circuit function.
- the standard cell layout template includes: a power graphic, used to define a power trace, which is used to connect the power supply; a signal graphic 207, used to define a signal trace; a first gate graphic 208, used to define the first gate switch, the first gate switch is used to realize the electrical connection or disconnection with the power supply wiring; the second gate pattern 209 is used to define the second gate switch, and the second gate switch is used to realize the electrical connection with the signal wiring. Electrically connected or disconnected; wherein, the signal pattern 207, the first gate pattern 208 and the second gate pattern 209 are located on the same side of the power supply pattern.
- the power pattern may include at least one of the first power pattern 201 or the second power pattern 202.
- the first gate pattern 208 and the second gate pattern 209 constitute a metal switch pattern, and one of the first gate pattern 208 and the second gate pattern 209 participates in the actual wiring.
- the first gate pattern 208 participates in the wiring and The second gate pattern 209 does not participate in the wiring, then the first gate switch is connected to the power wiring and the second gate switch is disconnected; the first gate pattern 208 does not participate in the wiring and the second gate pattern 209 participates in the wiring, then the first gate pattern 209 A gating switch is turned off and the second gating switch is connected to signal transmission.
- the signal pattern 207 includes: two sub-signal patterns 217 arranged along the third direction, and there is an interval between the two sub-signal patterns 217; the first gate pattern 208 is connected to one of the sub-signal patterns 217, and The first gate pattern 208 is located between the sub-signal pattern 217 and the power supply pattern; the second gate pattern 209 is located between the two sub-signal patterns 217, and parallel to the third direction, the length of the second gate pattern 209 is greater than or equal to the length of the interval.
- the third direction may be the same as the second direction X.
- the signal pattern may only include a single sub-gating pattern.
- the standard cell layout template provided in this embodiment increases the applicable scenarios of the standard cell layout template by reasonably arranging the power supply graphics, the signal graphics, the first gating graphics, and the second gating graphics. Taking into account the actual chip design, the actual layout can be adjusted redundantly according to the standard cell layout template, for example, the circuit structure corresponding to the layout can be changed through the first gate pattern or the second gate pattern, thereby adjusting the delay corresponding to the circuit structure. parameter.
- Another embodiment of the present disclosure also provides a standard cell layout template, which is substantially the same as the previous embodiment, with the main differences including: the standard cell layout template provided in the previous embodiment can be used for manual wiring (custom layout, ie custom layout), this The standard cell layout template provided by the embodiment can be applied to automatic routing, that is, a full-chip automatic physical design (auto-PR, place route) can be used to perform layout layout using the standard cell layout template.
- FIG. 9 is a schematic structural diagram of a standard cell layout template provided by yet another embodiment of the present disclosure.
- the standard cell layout template further includes: a metal layer pattern 30, the metal layer pattern 30 is electrically connected across the gate pattern 103, the first gate pattern 101 and/or the second gate pattern 102, using For defining the metal layer, the metal layer is located on the upper layer of the first gate and the second gate to electrically connect the first gate and/or the second gate.
- the metal layer pattern 30 is electrically connected across the gate pattern 103, the first gate pattern 101 and/or The second gate pattern 102 actually refers to: the metal layer pattern 30 is electrically connected across the gate pattern 103 , the first gate extension pattern 111 and/or the second gate extension pattern 112 .
- the metal layer provides conditions for automatic routing.
- the metal layer pattern 30 spans the first gate extension pattern 111 , the gate electrical connection pattern 103 and the second gate extension pattern 112 . It can be understood that if the metal layer is only electrically connected to the first gate, the overlapping area of the metal layer pattern 30 and the gate electrical connection pattern 103 corresponds to the layout of the contact hole structure, and the gate electrical connection structure defined by the gate electrical connection pattern 103 is connected to the first gate.
- a gate is electrically connected; if the metal layer is only electrically connected to the second gate, the overlapping area of the metal layer pattern 30 and the gate electrical connection pattern 103 corresponds to the layout of the contact hole structure, and the gate electrical connection structure defined by the gate electrical connection pattern 103 corresponds to the The second gate is electrically connected.
- the standard cell layout template has a custom layout area AA, the first well area I and the second well area II are located in the custom layout area AA, and part of the metal layer pattern 30 is located in the custom layout area AA, and the rest of the graphics are located in the custom layout area AA. Outside the custom layout area AA.
- the metal layer pattern 30 includes: a first metal layer pattern 31, the first metal layer pattern 31 extends along the first direction Y, and is electrically connected to the gate pattern 103, the first gate extension pattern 111 and/or the second gate extension pattern 112 has an overlapping portion; the second metal layer pattern 32 is connected to the first metal layer pattern 31 and extends outside the custom layout area AA along the second direction X; the third metal layer pattern 33 is located outside the custom layout area AA and Connected to the second metal layer pattern 32, the third metal layer pattern 33 extends along the first direction Y.
- the metal layer pattern is electrically connected across the gate pattern, the first gate pattern and/or the gate pattern.
- the second gate pattern that is, the metal layer pattern has an overlapping portion with the first gate pattern and/or the second gate pattern.
- the standard cell layout template provided in this embodiment provides conditions for realizing automatic layout by laying out metal layer graphics.
- FIG. 10 is a schematic top-view structural diagram of a semiconductor structure provided by still another embodiment of the present disclosure
- FIG. 11 is a schematic cross-sectional structural diagram of FIG. 10 along the CC1 direction.
- the semiconductor structure includes: a substrate 400 with a first well 41 and a second well 42 arranged in a first direction in the substrate 400 ; a first gate 401 located in the first well 41 on the substrate 400 and extending in the first direction Y; the second gate 402 is located on the substrate 400 of the second well 42 and extends in the first direction Y; the gate electrical connection structure 403 is located on the substrate 400 and is connected with the first A gate 401 and a second gate 402 are disposed in the same layer to electrically connect the first gate 401 and/or the second gate 402 .
- the semiconductor structure can be memory such as DRAM, SRAM, MRAM, FeRAM, PCRAM, HBM memory, NAND flash memory, or NOR flash memory.
- the gate electrical connection structure 403 is in the same layer as the first gate 401 and the second gate 402 , the gate electrical connection structure 403 and the first gate 401 can be realized without a contact hole structure for realizing electrical connection between the upper and lower layers.
- the electrical connection between the second gate 402 compared with the solution in which the gate electrical connection structure is located above the first gate and the second gate, this embodiment can shorten the distance between the gate electrical connection structure 403 and the first gate 401.
- the electrical connection path between the gate electrical connection structure 403 and the second gate 402 is shortened, thereby reducing the resistance corresponding to the electrical connection path, thereby reducing the power consumption of the semiconductor structure and improving the RC delay effect.
- the gate electrical connection structure 403 may be formed simultaneously in the process steps of forming the first gate 401 and/or the second gate 402 .
- the top of the gate electrical connection structure 403 may be flush with the top of the first gate 401 and the top of the second gate 402 .
- the bottom of the gate electrical connection structure 403 can also be flush with the bottom of the first gate 401 and the bottom of the second gate 402, so that the gate electrical connection structure 403 has a relatively thick thickness, which is beneficial to reduce the gate electrical connection structure 403 overall resistance, thereby reducing the power consumption of the semiconductor structure and the effect of RC delay.
- the “top” here refers to the top surface away from the substrate 400
- the “bottom” here refers to the bottom surface facing the substrate 400 .
- the material of the gate electrical connection structure 403 may also be the same as the material of the first gate 401 and the second gate 402 .
- the material of the gate electrical connection structure 403, the material of the first gate 401 and the material of the second gate 402 are all polysilicon; generally, the resistivity of polysilicon is lower than that of metal, such as polysilicon The resistivity is lower than that of copper, so using polysilicon as the material of the gate electrical connection structure 403 can reduce the resistance of the electrical connection path, thereby reducing the power consumption of the semiconductor structure.
- the semiconductor structure may further include: a first auxiliary gate 411 connected to the end of the first gate 401 and extending along the second direction X; a second auxiliary gate 412 connected to the end of the second gate 402 The parts are connected and extend along the second direction X.
- the first auxiliary gate 411 and the first gate 401 are disposed in the same layer and made of the same material, and the second auxiliary gate 412 and the second gate 402 are disposed in the same layer and made of the same material.
- the width of the first auxiliary gate 411 is larger than that of the first gate 401
- the width of the second auxiliary gate 412 is larger than that of the second gate 402 .
- the arrangement of the first auxiliary gate 411 is beneficial to increase the process window for the electrical connection between the first gate 401 and the gate electrical connection structure 403 ; the arrangement of the second auxiliary gate 412 is beneficial to increase the second gate 402
- the process window electrically connected to the gate electrical connection structure 403 reduces the requirement of process alignment precision and reduces the fabrication difficulty of the semiconductor structure.
- the gate electrical connection structure 403 includes at least two electrical connection structures, and each electrical connection structure extends along the second direction X, and the second direction X is different from the first direction Y.
- the at least two electrical connection structures include: a first electrical connection structure 413 located on the substrate 400 of the first well 41 , the first electrical connection structure 413 and the first gate 401 and the second gate 402 are disposed in the same layer; the second electrical connection The connection structure 423 is located on the substrate 400 of the second well 42 , and the second electrical connection structure 423 is disposed in the same layer as the first gate 401 and the second gate 402 .
- the first electrical connection structure 413 can be used to electrically connect the first gate 401 through the first auxiliary gate 411
- the second electrical connection structure 423 can be used to electrically connect the second gate 402 through the second auxiliary gate 412 .
- FIG. 12 is another schematic cross-sectional structure diagram of the semiconductor structure provided in this embodiment.
- the gate electrical connection structure 403 may further include: a first auxiliary electrical connection structure 433 located between the first gate 401 and the electrical connection structure facing the first gate 401 to electrically connect the first gate 401 with the The electrical connection structure toward the first gate 401; the second auxiliary electrical connection structure 443 is located between the second gate 402 and the electrical connection structure toward the second gate 402 to electrically connect the second gate 402 with the electrical connection toward the second gate 402.
- the electrical connection structure of the two gates may further include: a first auxiliary electrical connection structure 433 located between the first gate 401 and the electrical connection structure facing the first gate 401 to electrically connect the first gate 401 with the The electrical connection structure toward the first gate 401;
- the second auxiliary electrical connection structure 443 is located between the second gate 402 and the electrical connection structure toward the second gate 402 to electrically connect the second gate 402 with the electrical connection toward the second gate 402.
- the first auxiliary electrical connection structure 433 is in contact with the first electrical connection structure 413 and the first auxiliary gate 411 and is electrically connected
- the second auxiliary electrical connection structure 443 is in contact with the second electrical connection structure 423 and the second auxiliary gate 412 and electrically connected.
- the first auxiliary electrical connection structure 433 and the second auxiliary electrical connection structure 443 are in the same layer as the first gate electrode 401 and the second gate electrode 402 .
- FIG. 13 is another schematic cross-sectional structure diagram of the semiconductor structure provided in this embodiment.
- the gate electrical connection structure 403 may further include: a third auxiliary electrical connection structure 453 located between adjacent electrical connection structures to electrically connect the adjacent electrical connection structures. In this way, the specific circuit corresponding to the semiconductor structure is electrically connected to adjacent electrical connection structures.
- the gate electrical connection structure may also include only one electrical connection structure, and according to the specific circuit structure corresponding to the semiconductor structure, the electrical connection structure may be electrically connected to the first gate, or the The electrical connection structure may be electrically connected to the second gate, or the electrical connection structure may be electrically connected to the first gate and the second gate.
- the electrical connection with the first gate 401 and/or the second gate 402 can be realized through the gate electrical connection structure 403 provided in the same layer, which not only reduces the electrical connection path, There is no need to provide a contact hole structure with a large resistance, so it is beneficial to reduce the resistance of the semiconductor structure, thereby reducing the power consumption of the semiconductor structure and the RC delay effect. If the semiconductor structure is a memory, the storage speed of the memory can also be improved.
- a gate electrical connection structure with the first gate and/or the second gate may be implemented through a gate electrical connection structure in the same layer as the first gate and/or the second gate. electrical connection, thereby reducing the length of the electrical connection path and reducing the resistance corresponding to the electrical connection path; and, there is no need to set up a contact hole structure to realize the electrical connection between the upper and lower layers, so as to avoid the adverse effects caused by the contact hole structure with high resistance, Reduce the resistance corresponding to the electrical connection path.
- the semiconductor structure fabricated by using the standard cell layout die provided by the embodiments of the present disclosure can improve the running speed, reduce the power consumption of the semiconductor structure, and also improve the signal quality, such as the signal delay on the gate, Signal rise time and/or signal fall time are improved.
- the standard cell layout template provided by the embodiment of the present disclosure can be used as a circuit layout design template for other chips such as DRAM chips.
- the layout of the grid electrical connection pattern can make the circuit layout layout more regular, and different layouts follow the same principle. Due to the optimized circuit layout design, the efficiency of layout design is improved and the time of chip design is shortened.
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Abstract
Description
Claims (18)
- 一种标准单元版图模板,包括:沿第一方向排布的第一阱区和第二阱区;第一栅极图形,位于所述第一阱区且沿所述第一方向延伸,用于定义第一栅极;第二栅极图形,位于所述第二阱区且沿所述第一方向延伸,用于定义第二栅极;栅电连接图形,位于所述第一栅极图形与所述第二栅极图形之间,用于定义栅电连接结构,所述栅电连接结构与所述第一栅极以及所述第二栅极同层设置,以电连接所述第一栅极和/或所述第二栅极。
- 如权利要求1所述的标准单元版图模板,其中,所述栅电连接图形包括:至少两条相间隔的电连接图形,且每条所述电连接图形均沿第二方向延伸,所述第二方向与所述第一方向不同,每一所述电连接图形用于定义一电连接结构。
- 如权利要求2所述的标准单元版图模板,其中,至少两条相间隔的所述电连接图形包括:第一电连接图形,位于所述第一阱区,用于定义第一电连接结构,以电连接所述第一栅极;第二电连接图形,位于所述第二阱区,用于定义第二电连接结构,以电连接所述第二栅极。
- 如权利要求2所述的标准单元版图模板,所述栅电连接图形还包括:第一辅助图形,连接所述第一栅极图形与朝向所述第一栅极图形的所述电连接图形,用于定义第一辅助电连接结构,以电连接所述第一栅极与朝向所述第一栅极的所述电连接结构;第二辅助图形,连接所述第二栅极图形与朝向所述第二栅极图形的所述电连接图形,用于定义第二辅助电连接结构,以电连接所述第二栅极与朝向所述第二栅极的所述电连接结构。
- 如权利要求2所述的标准单元版图模板,所述栅电连接图形还包括:第三辅助图形,位于相邻的所述电连接图形之间,用于定义第三辅助电连接结构,以电连接相邻的所述电连接结构。
- 如权利要求1所述的标准单元版图模板,其中,所述栅电连接图形包括:一条电连接图形,且所述电连接图形沿第二方向延伸,所述第二方向与所述第一方向不同。
- 如权利要求6所述的标准单元版图模板,其中,部分所述电连接图形位于所述第一阱区,剩余部分所述电连接图形位于所述第二阱区。
- 如权利要求1所述的标准单元版图模板,所述栅电连接图形还位于,所述第一栅极图形远离所述第二栅极图形的一侧,以及,位于所述第二栅极图形远离所述第一栅极图形的一侧。
- 如权利要求1所述的标准单元版图模板,还包括:金属层图形,所述金属层图形横跨所述栅电连接图形、所述第一栅极图形和/或所述第二栅极图形,用于定义金属层,所述金属层位于所述第一栅极与所述第二栅极的上层,以电连接所述第一栅极和/或所述第二栅极。
- 如权利要求1所述的标准单元版图模板,其中,所述第一阱区包括:第一MOS区,且所述第一栅极图形横跨所述第一MOS区;所述第二阱区包括:第二MOS区,且所述第二栅极图形横跨所述第二MOS区;所述标准单元版图模板还包括:中间区,所述中间区位于所述第一MOS区与所述第二MOS区之间,其中,所述栅电连接图形位于所述中间区。
- 如权利要求10所述的标准单元版图模板,其中,所述第一阱区具有朝向所述第二阱区的第一边界,且所述第一边界位于所述中间区的正中间位置。
- 如权利要求1所述的标准单元版图模板,还包括:第一电源图形,用于定义第一电源走线,所述第一电源走线用于连接第一电源;第二电源图形,用于定义第二电源走线,所述第二电源走线用于连接第二电源,且所述第一电源的电压大于所述第二电源的电压;其中,在沿所述第一方向上,所述第一电源图形的宽度大于所述第二电 源图形的宽度。
- 如权利要求1所述的标准单元版图模板,还包括:电源图形,用于定义电源走线,所述电源走线用于连接电源;信号图形,用于定义信号走线,所述信号走线用于连接信号;第一选通图形,用于定义第一选通开关,所述第一选通开关用于实现与所述电源走线的电连接或者断开;第二选通图形,用于定义第二选通开关,所述第二选通开关用于实现与所述信号走线的电连接或者断开;其中,所述信号图形、所述第一选通图形以及所述第二选通图形位于所述电源图形的同一侧。
- 一种半导体结构,包括:基底,所述基底内具有沿第一方向排布的第一阱和第二阱;第一栅极,位于所述第一阱的所述基底上且沿所述第一方向延伸;第二栅极,位于所述第二阱的所述基底上且沿所述第一方向延伸;栅电连接结构,位于所述基底上,且与所述第一栅极以及所述第二栅极同层设置,以电连接所述第一栅极和/或所述第二栅极。
- 如权利要求14所述的半导体结构,其中,所述栅电连接结构包括:至少两个电连接结构,且每个所述电连接结构均沿第二方向延伸,所述第二方向与所述第一方向不同。
- 如权利要求15所述的半导体结构,其中,至少两个所述电连接结构包括:第一电连接结构,位于所述第一阱的所述基底上;第二电连接结构,位于所述第二阱的所述基底上。
- 如权利要求15所述的半导体结构,所述栅电连接结构还包括:第一辅助电连接结构,位于所述第一栅极与朝向所述第一栅极的所述电连接结构之间,以电连接所述第一栅极与朝向所述第一栅极的所述电连接结构;第二辅助电连接结构,位于所述第二栅极与朝向所述第二栅极的所述电连接结构之间,以电连接所述第二栅极与朝向所述第二栅极的所述电连接结构。
- 如权利要求15所述的半导体结构,所述栅电连接结构还包括:第三 辅助电连接结构,位于相邻的所述电连接结构之间,以电连接相邻的所述电连接结构。
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EP21859332.5A EP4060738A4 (en) | 2021-02-05 | 2021-07-22 | STANDARD CELL TEMPLATE AND SEMICONDUCTOR STRUCTURE |
KR1020227027198A KR20220124767A (ko) | 2021-02-05 | 2021-07-22 | 표준 셀 레이아웃 템플릿 및 반도체 구조물 |
JP2022546369A JP7446446B2 (ja) | 2021-02-05 | 2021-07-22 | スタンダードセルレイアウトテンプレート及び半導体構造 |
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EP4060738A4 (en) | 2021-02-05 | 2022-11-30 | Changxin Memory Technologies, Inc. | STANDARD CELL TEMPLATE AND SEMICONDUCTOR STRUCTURE |
CN112992892B (zh) * | 2021-02-05 | 2022-04-22 | 长鑫存储技术有限公司 | 标准单元版图模板以及半导体结构 |
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