WO2022165900A1 - 一种半导体有源与无源集成耦合方法 - Google Patents

一种半导体有源与无源集成耦合方法 Download PDF

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Publication number
WO2022165900A1
WO2022165900A1 PCT/CN2021/079321 CN2021079321W WO2022165900A1 WO 2022165900 A1 WO2022165900 A1 WO 2022165900A1 CN 2021079321 W CN2021079321 W CN 2021079321W WO 2022165900 A1 WO2022165900 A1 WO 2022165900A1
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conductive material
laser diode
matching
pillars
contact
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PCT/CN2021/079321
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English (en)
French (fr)
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陈伯庄
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桂林雷光科技有限公司
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Publication of WO2022165900A1 publication Critical patent/WO2022165900A1/zh

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    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/023Mount members, e.g. sub-mount members
    • H01S5/02325Mechanically integrated components on mount members or optical micro-benches
    • H01S5/02326Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/0235Method for mounting laser chips
    • H01S5/02375Positioning of the laser chips

Definitions

  • the invention relates to the field of semiconductor components and chip manufacturing, in particular to a semiconductor active and passive integrated coupling method.
  • silicon photonics has been working on how to integrate discrete laser diodes made of semiconductor III-V materials with circuits on silicon.
  • the light emitted by the laser diode must be precisely aligned with the optical waveguide element on the silicon substrate for its technical efficacy to be precise.
  • the laser diode can be made of InP or GaAs substrate or other semiconductor materials.
  • the wavelength of the laser can be in the range of 1.1-1.7um or other wavelengths.
  • some passive alignment techniques in the prior art use steps etched on the laser diode and silicon substrate to precisely position the structural schematic diagram of the laser diode chip.
  • Other prior techniques require bonding of thin laser materials in order to slowly transfer optical modes from the laser waveguide to the silicon waveguide through mode leakage. All of these technologies require very fine dimensional control and sub-micron precision positioning technology, which is very technically difficult.
  • it is impossible to reposition the laser diode chip the yield of silicon wafers is low, and the manufacturing cost is extremely high.
  • the present invention provides an active integrated coupling method of a laser diode and a passive waveguide, allowing initial alignment accuracy up to several microns, and then repositioning the laser diode with sub-micron accuracy to achieve the desired Location. This is done with the laser diode powered on to actively monitor the coupling process. Once positioned, the laser diode chip can be repositioned.
  • the object of the present invention is to provide a semiconductor active and passive integrated coupling method for aligning and coupling a laser diode (1) with a passive waveguide on a silicon substrate (4) with high precision, comprising the following steps:
  • Step 1 forming a plurality of conductive material columns (2) on the surface of the laser diode (1);
  • Step 2 forming a plurality of matching pillars (3) on the side of the silicon substrate (4) that matches the surface of the laser diode (1);
  • step 3 the conductive material column (2) and the matching column (3) move in opposite directions for dynamic assembly, so as to complete the active integrated coupling of the laser diode (1) and the passive waveguide.
  • the conductive material column (2) is in the shape of a plurality of hairs, thin and made of ductile conductive material, and the bottom of the conductive material column (2) has a P contact (6) and an N contact (5). ), the P-contact (6) and N-contact (5) are on the same laser diode (1) surface, and the conductive material column (2) is built on the P-contact (6) and N-contact The top of (5), the ductile conductive material is pure gold or gold alloy.
  • the matching pillar (3) is prepared from a plurality of hair-like pillars, and the surface of the matching pillar (3) is covered with conductive metal.
  • the conductive material pillars (2) and the matching pillars (3) are distributed at equal intervals.
  • the height of the conductive material column (2) is 4-20 microns, the aspect ratio W/L of the conductive material column (2) is 1/3 or less, and the height of the conductive material column (2) is 1/3 or less. The spacing between them is W-5W.
  • the step 3 includes:
  • Step 31 pressing the conductive material column (2) on the laser diode (1) to the matching column (3) on the silicon substrate (4);
  • Step 32 applying current to the corresponding P contacts and N contacts matched with the P contacts (6) and N contacts (5) formed by the matching pillars (3) on the silicon substrate (4),
  • the laser diode (1) is energized; the positions of said P-contacts (6) and N-contacts (5) of the laser diode (1) can be positioned down to several microns in all directions, and once the desired position is reached, the laser diode ( 1) Hold the fixture in the stated position.
  • the preparation method of the conductive material column (2) of the laser diode (1) comprises:
  • the pillars are formed by plasma etching or chemical etching, and the pillars are in the shape of a circle or a pin, and then a matching pillar (3) is formed on the surface of the pillars by evaporating conductive metal by electrons.
  • the preparation process of the matching pillar (3) on the silicon substrate (4) includes:
  • a contact metal is prepared in a standard wafer, and the contact metal is a multi-layer metal;
  • FIG. 1 is a schematic diagram of the principle of precise alignment of light emitted by a laser diode and an optical waveguide element on a silicon substrate according to the prior art
  • FIG. 3( a ) is a schematic diagram of the principle of an active integrated coupling method of a laser diode and a passive waveguide according to an embodiment of the present invention
  • Figure 3(b) is a diagram showing the structure and parameters of the conductive material column according to an embodiment of the present invention.
  • FIG. 5 is a state diagram of lateral movement of the conductive material column and the matching support during the alignment and coupling assembly process during the matching process.
  • 1-laser diode 2-conductive material pillar; 3-matching pillar; 4-silicon substrate; 5-N contact; 6-P contact; 7-passive waveguide.
  • This embodiment aims to provide a semiconductor active and passive integrated coupling method that allows initial alignment accuracy up to a few microns, and then repositioning the laser diode with sub-micron accuracy to achieve the desired position. This is done with the laser diode powered on to actively monitor the coupling process. Once positioned, the laser diode chip can be repositioned.
  • FIG. 3( a ) a schematic diagram of the principle of the semiconductor active and passive integrated coupling method for aligning and coupling the laser diode 1 and the passive waveguide 7 on the silicon substrate 4 with high precision, including the following steps:
  • Step 1 forming a plurality of conductive material pillars 2 on the surface of the laser diode 1;
  • step 2 a plurality of matching pillars 3 are formed on the side of the silicon substrate 4 that is matched with the surface of the laser diode 1.
  • it can also be in the form of etching silicon nails;
  • Step 3 the conductive material pillar 2 and the matching pillar 3 or the etched silicon nail move in opposite directions for dynamic assembly, thereby completing the active integrated coupling of the laser diode 1 and the passive waveguide, including:
  • Step 32 apply current to the matching pillars 3 on the silicon substrate 4 or the P contacts and N contacts matched with the P contacts 6 and the N contacts 5 formed by etching the silicon nails to energize the laser diode 1;
  • the physical properties of the laser diode 1 are malleable, the position of the contacts of the laser diode 1 can be positioned down to a few microns in all directions, and once the desired position is reached, the laser diode will stay fixed in position.
  • the conductive material columns 2 on the laser diode 1 are in the shape of a plurality of hairs, elongated and made of ductile conductive material.
  • the bottom of the conductive material column 2 has a P contact 6 and an N contact 5, the P contact 6 and the N contact 5 are on the same surface of the laser diode 1, and the conductive material column 2 is constructed on the P contact 6 and the N contact 5. top.
  • the matching pillar 3 is prepared by a hair-shaped round or nail-shaped column, or by a nail-shaped object covered with a ductile conductive material.
  • the three-dimensional shape of the nail-shaped object is a cone, of course, other up and down can also be used.
  • the three-dimensional shapes with different cross-sectional radii are within the protection scope of the present invention as long as the dimensions are within the protection scope defined by the present invention and the geometric matching relationship with the conductive material column is easy to be formed.
  • the conductive material pillars 2, the matching pillars 3 or the etched silicon nails are distributed at equal intervals. Of course, they can also be distributed at approximately equal intervals or in accordance with certain regular intervals, as long as repositioning with sub-micron accuracy can be obtained.
  • the technical indicators of the laser diode are all within the protection scope of the present invention.
  • the ductile conductive material is pure gold, and gold alloy or other similar materials can also be selected, as long as the conductive material has certain ductility and toughness, it is within the protection scope of the present invention.
  • the preferred height of the conductive material pillar 2 is 4-20 microns, and the aspect ratio W/L of the conductive material pillar 2 is 1/3 or less.
  • the spacing between the conductive material pillars 2 is preferably W-5W, or more.
  • Matching pillars 3 or etched silicon nails are sized similarly to pillars 2 of conductive material.
  • the conductive material column 2 is manufactured by standard photolithography technology and electroplating technology.
  • the preparation method of the conductive material column 2 of the laser diode 1 includes:
  • the contact metal is prepared in a standard wafer, and the metal is a multi-layer metal, including a multi-layer metal structure composed of Ti, Pt, Au or other metals; usually three layers of different metals are used, such as Ti (Titanium), Pt (Platinum) , Au (Gold), etc.
  • Ti Ti
  • Pt Platinum
  • Au Gold
  • those skilled in the art can think that other types of metals such as Ti, W (Tungsten) can also be used, and Au also belongs to the protection scope of this field;
  • the conductive material pillars 2, matching pillars 3, or etched silicon nails can also be prepared by electron beam evaporation and lift-off techniques, but electroplating is more economical.
  • electroplating is more economical.
  • Those skilled in the art can prepare micro-columnar materials in other ways, which all belong to the protection scope of the art.
  • the pillars are formed by plasma etching or chemical etching, and the pillars are round or nail-shaped, and then the matching pillars 3 are formed on the surface of the pillars by evaporating conductive metal by electrons;
  • a step of increasing the thickness of the gold by electroplating can also be added.
  • the preparation process of the matching pillars 3 on the silicon substrate 4 may further include:
  • the contact metal is prepared in a standard wafer, and the contact metal is a multilayer metal structure composed of multiple layers of Ti, Pt, Au or other metals; usually three layers of different metals are used, such as Ti (Titanium), Pt (Platinum), Au (Gold), etc.
  • Ti Ti
  • Pt Platinum
  • Au Gold
  • those skilled in the art can think that other types of metals such as Ti, W (Tungsten) can also be used, and Au also belongs to the scope of protection in the art. ;
  • ductile matching pillars 3 are formed in the deep hole by electroplating gold.
  • the conductive material pillars 2 on the laser diode 1 are pressed onto matching pillars 3 or conductive metal-covered etched silicon pins on the silicon substrate. It is preferred that both the P-contact 6 and the N-contact 5 are on the same laser diode 1 surface, and that the column of conductive material 2 is built up on top of the P-contact 6 and the N-contact 5 .
  • the laser diode 1 is energized by applying current through the P and N contacts of the matching P contacts 6 and N contacts 5 on the silicon substrate 4 . Due to the plasticity of the hair-like column, the position of the emission point of the laser diode 1 can be localized to several micrometers in all directions. Once the desired position is reached, the laser diode 1 will remain in that position. Because the diode chip is very thin and light, and the gold pillars on both sides are strong when wrapped around each other, the laser diode 1 is held firmly in place over time.
  • the laser diode 1 chip Since the laser diode 1 chip is very light and thin, and the conductive material post 2 and the matching post 3 are strong when they are intertwined, the laser diode 1 will be firmly fixed in place. There is no need for high temperature cycling, which reduces the stress on the laser diode 1 and improves reliability compared to the prior art using eutectic solder. If alignment is not achieved in the initial attempt, it is still possible to re-align the coupling by moving the laser diode 1 chip position for rework.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Semiconductor Lasers (AREA)

Abstract

本发明提供一种半导体有源与无源集成耦合方法,将激光二极管(1)与硅衬底(4)上的无源波导(7)进行高精度对齐耦合,包括:在激光二极管(1)的表面上形成多个导电材料柱(2);将硅衬底(4)与激光二极管(1)的表面匹配的一侧形成多个匹配支柱(3)或蚀刻硅钉;导电材料柱(2)及匹配支柱(3)沿相反方向移动动态组装,将导电材料柱(2)压到匹配支柱(3)或蚀刻硅钉上;对硅衬底(4)上的匹配支柱(3)形成的P触点和N触点施加电流,为激光二极管(1)通电;激光二极管的P触点(6)和N触点(5)一旦达到所需位置,激光二极管(1)将固定停留在该位置上,从而完成激光二极管(1)与无源波导(7)的有源集成耦合。

Description

一种半导体有源与无源集成耦合方法 技术领域
本发明涉及半导体零部件以及芯片制造领域,特别是涉及一种半导体有源与无源集成耦合方法。
背景技术
如图1所示,硅光子学一直致力于研究如何将半导体III-V材料制成的分立激光二极管与硅上的电路整合起来。激光二极管发出的光必须与硅衬底上的光学波导元件精确对准才能精确发挥其技术功效。其中激光二极管可以用InP或GaAs衬底或其它半导体材料制成。激光的波长可在1.1~1.7um或其它波长范围内。
如图2所示,现有技术的一些无源对准技术使用在激光二极管和硅衬底上蚀刻形成的台阶来精确定位激光二极管芯片的结构示意图。其他现有技术需要对薄激光材料进行粘合,以便通过模式泄漏将光学模式从激光波导缓慢地被转移到硅波导。所有这些技术都需要非常精细的尺寸控制和亚微米级精度的定位技术,技术难度非常大。此外,一旦定位,就不可能重新定位激光二极管芯片,硅片的成品率低,制造成本极高。
发明内容
本发明为了克服现有技术的缺陷,提供一种激光二极管与无源波导的有源集成耦合方法,允许初始对准精度高达几微米,然后以亚微米精度重新定位激光二极管,以达到所需的位置。这是在激光二极管通电以主动监测耦合过程的情况下完成的。定位后,可以重新定位激光二极管芯片。
本发明的目的在于提供一种半导体有源与无源集成耦合方法,用于将激光二极管(1)与硅衬底(4)上的无源波导高精度进行对齐并耦合,包括如下步骤:
步骤1,在激光二极管(1)的表面上形成多个导电材料柱(2);
步骤2,将所述硅衬底(4)与所述激光二极管(1)的表面匹配的一侧形成多个匹配支柱(3);
步骤3,所述导电材料柱(2)以及所述匹配支柱(3)沿着相反方向移动进行动态组装,从而完成所述激光二极管(1)与无源波导的有源集成耦合。
优选的,所述导电材料柱(2)为多个头发状,细薄并且采用延展性导电材料制成,所述导电材料柱(2)底部具有P触点(6)和N触点(5),所述P触点(6)和N触点(5)处于同一激光二极管(1)表面上,并且所述导电材料柱(2)构建在所述P触点(6)和N触点(5)的顶部,所述延展性导电材料为纯金或金合金。
优选的,所述匹配支柱(3)由多个毛发状的柱制备,匹配支柱(3)表面覆盖导电金属。
优选的,所述导电材料柱(2)、匹配支柱(3)为等间距分布。
优选的,所述导电材料柱(2)高度为4-20微米,所述导电材料柱(2)的宽高比W/L为1/3或者更小,所述导电材料柱(2)之间的间距为W-5W。
优选的,所述步骤3包括:
步骤31,将激光二极管(1)上的所述导电材料柱(2)压到所述硅衬底(4)上的匹配支柱(3)上;
步骤32,对硅衬底(4)上的所述匹配支柱(3)形成的与所述P触点(6)和N触点(5)匹配的相应P触点和N触点施加电流,为激光二极管(1)通电;激光二极管(1)的所述P触点(6)和N触点(5)的位置可 以沿各个方向定位到几微米,一旦达到所需的位置,激光二极管(1)将固定停留在所述位置上。
优选的,所述导电材料柱(2)采用标准的光刻技术和电镀技术制备,所述匹配支柱(3)通过化学蚀刻或等离子体蚀刻来制备。
优选的,所述激光二极管(1)的所述导电材料柱(2)的制备方法包括:
首先,在标准晶片中制备接触金属,接触金属为多层金属;
然后,在标准晶片接触金属上旋转一层厚的光刻胶;
此后,通过曝光显影在光刻胶上制备深孔;
最后,通过电镀方式电镀金在所述深孔内形成导电材料柱(2)。
优选的,所述硅衬底(4)上的所述匹配支柱(3)的制备方法包括:
首先:在标准晶片上旋转一层厚的光刻胶;
此后,通过曝光显影在所述光刻胶上制备多点;
最后,通过等离子蚀刻或化学蚀刻方式形成支柱,支柱形状圆形或钉形,再通过电子蒸发导电金属在支柱表面形成匹配支柱(3)。
优选的,所述硅衬底(4)上的所述匹配支柱(3)的制备过程包括:
首先,在标准晶片中制备接触金属,所述接触金属为多层金属;
然后,在标准晶片接触金属上旋转一层厚的光刻胶;
此后,通过曝光显影在所述光刻胶上制备深孔;
最后,通过电镀方式电镀金在所述深孔内形成延展性的匹配支柱(3)。
本发明的有益效果:
(1)由于激光二极管芯片非常轻薄,而且导电材料柱与匹配支柱或蚀刻硅钉相互缠绕时很坚固,所以激光二极管会被牢固地固定在调制后的位置;
(2)无需高温循环,与使用共晶焊料的现有技术相比,减少了对激光 二极管的压力,提高了可靠性。
(3)如果在初始尝试中未达到对准,仍然可以通过移动激光二极管芯片位置进行返工重新对准耦合。
根据下文结合附图对本发明具体实施例的详细描述,本领域技术人员将会更加明了本发明的上述以及其他目的、优点和特征。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本发明的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解,这些附图未必是按比例绘制的。本发明的目标及特征考虑到如下结合附图的描述将更加明显,附图中:
附图1为根据现有技术的激光二极管发出的光与硅衬底上的光学波导元件精确对准的原理示意图;
附图2为根据现有技术的无源对准技术使用在激光二极管和硅衬底上蚀刻形成的台阶来精确定位激光二极管芯片的结构示意图;
附图3(a)为根据本发明实施例的激光二极管与无源波导的有源集成耦合方法的原理示意图;
附图3(b)为根据本发明实施例的导电材料柱结构以及参数图;
附图4为导电材料柱与匹配支柱结合在一起的状态图;
附图5为在匹配过程中,导电材料柱与匹配支柱在对齐和耦合的组装过程中发生横向移动的状态图。
附图标记:
1-激光二极管;2-导电材料柱;3-匹配支柱;4-硅衬底;5-N触点;6-P 触点;7-无源波导。
具体实施方式
本实施例旨在提供一种半导体有源与无源集成耦合方法,允许初始对准精度高达几微米,然后以亚微米精度重新定位激光二极管,以达到所需的位置。这是在激光二极管通电以主动监测耦合过程的情况下完成的。定位后,可以重新定位激光二极管芯片。
参见图3(a),半导体有源与无源集成耦合方法的原理示意图,用于将激光二极管1与硅衬底4上的无源波导7高精度进行对齐并耦合,包括如下步骤:
步骤1,在激光二极管1的表面上形成多个导电材料柱2;
步骤2,将硅衬底4与激光二极管1的表面匹配的一侧形成多个匹配支柱3,当然也可以采用蚀刻硅钉的形式;
步骤3,导电材料柱2以及匹配支柱3或蚀刻硅钉沿着相反方向移动进行动态组装,从而完成激光二极管1与无源波导的有源集成耦合,包括:
步骤31,将激光二极管1上的导电材料柱2压到匹配支柱3或蚀刻硅钉上;
步骤32,对硅衬底4上的匹配支柱3或蚀刻硅钉形成的与P触点6和N触点5匹配P触点和N触点施加电流,为激光二极管1通电;由于导电材料柱的物理特性具有可塑性,激光二极管1的触点的位置可以沿各个方向定位到几微米,一旦达到所需的位置,激光二极管将固定停留在位置上。
本实施例中,在激光二极管1上的导电材料柱2为多个头发状,细长并且采用延展性导电材料制成。导电材料柱2底部具有P触点6和N触点5,P触点6和N触点5处于同一激光二极管1表面上,并且导电材料柱2 构建在P触点6和N触点5的顶部。匹配支柱3由头发状的圆形或钉形柱制备,或者由覆盖有延展性导电材料的钉状物制备,本实施例中,钉状物的立体形状为锥形,当然也可以采用其他上下截面半径不同的立体形状,只要尺寸在本发明限定的保护范围内,并且与导电材料柱易于形成几何匹配关系,均在本发明的保护范围内。其中,作为优选的实施方式,导电材料柱2、匹配支柱3或蚀刻硅钉为等间距分布,当然也可以采用大致等间距分布或者按照一定规律的间距分布方式,只要能够获得亚微米精度重新定位激光二极管的技术指标均在本发明的保护范围内。
本实施例中,延展性导电材料为纯金,也可以选择金合金或其他类似材料,只要该导电材料具有一定的延展性和韧性,均在本发明的保护范围内。
参见图3b,导电材料柱2高度的优选尺寸为4-20微米,导电材料柱2的宽高比W/L为1/3或者更小。导电材料柱2之间的间距优选为W-5W,或者更大。匹配支柱3或蚀刻硅钉的大小设置与导电材料柱2类似。
作为关键的耦合部件,导电材料柱2采用标准的光刻技术和电镀技术制造,激光二极管1的导电材料柱2的制备方法包括:
首先,在标准晶片中制备接触金属,金属为多层金属,包括Ti,Pt,Au或其他金属构成的多层金属结构;通常采用三层不同的金属,例如Ti(Titanium)、Pt(Platinum)、Au(Gold)等,当然本领域技术人员可以想到还可以采用其他类型的金属例如Ti,W(Tungsten),Au也同样属于本领域的保护范围;
然后,在标准晶片接触金属上旋转一层厚的光刻胶;
此后,通过曝光显影在光刻胶上制备深孔;
最后,通过电镀方式在深孔里电镀金形成导电材料柱2。
当然,也可以通过电子束蒸发和剥离技术制备导电材料柱2、匹配支柱 3或蚀刻硅钉,但是电镀更经济。本领域技术人员可以通过其他方式制备微型柱状材料,均属于本领域的保护范围。
作为关键的耦合部件,硅衬底4上的匹配支柱3的制备方法包括:
首先,在在标准晶片上旋转一层厚的光刻胶;
此后,通过曝光显影在光刻胶上制备多点;
最后,通过等离子蚀刻或化学蚀刻方式形成支柱,支柱形状圆形或钉形,再通过电子蒸发导电金属在支柱表面形成匹配支柱3;
当然,还可以增加通过电镀方式加厚金的厚度的步骤。
在另外的优选实施方式中,硅衬底4上匹配支柱3的制备过程还可以包括:
首先,在标准晶片中制备接触金属,接触金属为多层的Ti,Pt,Au或其他金属构成的多层金属结构;通常采用三层不同的金属,例如Ti(Titanium)、Pt(Platinum)、Au(Gold)等,当然本领域技术人员可以想到还可以采用其他类型的金属例如Ti,W(Tungsten),Au也同样属于本领域的保护范围。;
然后,在标准晶片上旋转一层厚的光刻胶;
此后,通过曝光显影在光刻胶上制备深孔;
最后,通过电镀方式电镀金在深孔内形成延展性的匹配支柱3。
当将激光二极管1芯片上带有导电材料柱2的表面压入硅衬底4的表面时,这些导电材料柱2和硅衬底4上的匹配支柱3会啮合在一起。一些导电材料柱2将与匹配支柱3缠结在一起。由于摩擦力,芯片将被牢固稳定地固定。但是,由于导电材料柱1的长度允许弯曲,因此仍然可以在横向和垂直方向上略微移动。
参见图4和图5,其中图4所示为导电材料柱2与匹配支柱3或蚀刻硅钉极为精确的对齐并耦合在一起的状态图,图5所示为在匹配过程中,导 电材料柱2与匹配支柱3在对齐和耦合的组装过程中发生横向移动的状态图,从而确定该组装过程为动态组装过程,即使在初始尝试中未达到对准,仍然可以通过移动激光二极管1芯片位置进行返工重新对准耦合。为了达到本领域期望的效果,导电材料柱2与硅衬底4上的匹配支柱3不需要完全精确的对齐,只要部分对齐即可,其他部分接触即可。
工作原理:
在组装过程中,激光二极管1上的导电材料支柱2被压到匹配支柱3或硅衬底上的导电金属覆盖的蚀刻硅钉上。优选的是P触点6和N触点5都在同一激光二极管1表面上,并且导电材料柱2构建在P触点6与N触点5的顶部。在组装过程中,通过硅衬底4上的匹配P触点6和N触点5的P触点和N触点施加电流,为激光二极管1通电。由于毛发状柱的可塑性,激光二极管1发射点的位置可以在各个方向上定位到几微米。一旦达到所需的位置,激光二极管1将留在该位置。因为二极管芯片非常薄和轻,而且两边的金柱相互缠绕时很坚固,所以随着时间的推移,激光二极管1被牢牢地固定在适当的位置。
由于激光二极管1芯片非常轻薄,而且导电材料柱2与匹配支柱3相互缠绕时很坚固,所以激光二极管1会被牢固地固定在适当的位置。无需高温循环,与使用共晶焊料的现有技术相比,减少了对激光二极管1的压力,提高了可靠性。如果在初始尝试中未达到对准,仍然可以通过移动激光二极管1芯片位置进行返工重新对准耦合。
虽然本发明已经参考特定的说明性实施例进行了描述,但是不会受到这些实施例的限定而仅仅受到附加权利要求的限定。本领域技术人员应当理解可以在不偏离本发明的保护范围和精神的情况下对本发明的实施例能够进行改动和修改。

Claims (10)

  1. 一种半导体有源与无源集成耦合方法,用于将激光二极管(1)与硅衬底(4)上的无源波导高精度进行对齐并耦合,其特征在于包括如下步骤:
    步骤1,在激光二极管(1)的表面上形成多个导电材料柱(2);
    步骤2,将所述硅衬底(4)与所述激光二极管(1)的表面匹配的一侧形成多个匹配支柱(3);
    步骤3,所述导电材料柱(2)以及所述匹配支柱(3)沿着相反方向移动进行动态组装,从而完成所述激光二极管(1)与无源波导的有源集成耦合。
  2. 根据权利要求1所述的一种半导体有源与无源集成耦合方法,其特征在于:所述导电材料柱(2)为多个头发状,细薄并且采用延展性导电材料制成,所述导电材料柱(2)底部具有P触点(6)和N触点(5),所述P触点(6)和N触点(5)处于同一激光二极管(1)表面上,并且所述导电材料柱(2)构建在所述P触点(6)和N触点(5)的顶部,所述延展性导电材料为纯金或金合金。
  3. 根据权利要求1所述的一种半导体有源与无源集成耦合方法,其特征在于:所述匹配支柱(3)由多个毛发状的柱制备,匹配支柱(3)表面覆盖导电金属。
  4. 根据权利要求3所述的一种半导体有源与无源集成耦合方法,其特征在于:所述导电材料柱(2)、匹配支柱(3)为等间距分布。
  5. 根据权利要求1所述的一种半导体有源与无源集成耦合方法,其特征在于:所述导电材料柱(2)高度为4-20微米,所述导电材料柱(2)的宽高比W/L为1/3或者更小,所述导电材料柱(2)之间的间距为W-5W。
  6. 根据权利要求1所述的一种半导体有源与无源集成耦合方法,其特征在于所述步骤3包括:
    步骤31,将激光二极管(1)上的所述导电材料柱(2)压到所述硅衬底(4)上的匹配支柱(3)上;
    步骤32,对硅衬底(4)上的所述匹配支柱(3)形成的与所述P触点(6)和N触点(5)匹配的相应P触点和N触点施加电流,为激光二极管(1)通电;激光二极管(1)的所述P触点(6)和N触点(5)的位置可以沿各个方向定位到几微米,一旦达到所需的位置,激光二极管(1)将固定停留在所述位置上。
  7. 根据权利要求1所述的一种半导体有源与无源集成耦合方法,其特征在于:所述导电材料柱(2)采用标准的光刻技术和电镀技术制备,所述匹配支柱(3)通过化学 蚀刻或等离子体蚀刻来制备。
  8. 根据权利要求7所述的一种半导体有源与无源集成耦合方法,其特征在于所述激光二极管(1)的所述导电材料柱(2)的制备方法包括:
    首先,在标准晶片中制备接触金属,接触金属为多层金属;
    然后,在标准晶片接触金属上旋转一层厚的光刻胶;
    此后,通过曝光显影在光刻胶上制备深孔;
    最后,通过电镀方式电镀金在所述深孔内形成导电材料柱(2)。
  9. 根据权利要求1所述的一种半导体有源与无源集成耦合方法,其特征在于所述硅衬底(4)上的所述匹配支柱(3)的制备方法包括:
    首先:在标准晶片上旋转一层厚的光刻胶;
    此后,通过曝光显影在所述光刻胶上制备多点;
    最后,通过等离子蚀刻或化学蚀刻方式形成支柱,支柱形状圆形或钉形,再通过电子蒸发导电金属在支柱表面形成匹配支柱(3)。
  10. 根据权利要求1所述的一种半导体有源与无源集成耦合方法,其特征在于所述硅衬底(4)上的所述匹配支柱(3)的制备过程包括:
    首先,在标准晶片中制备接触金属,所述接触金属为多层金属;
    然后,在标准晶片接触金属上旋转一层厚的光刻胶;
    此后,通过曝光显影在所述光刻胶上制备深孔;
    最后,通过电镀方式电镀金在所述深孔内形成延展性的匹配支柱(3)。
PCT/CN2021/079321 2021-02-08 2021-03-05 一种半导体有源与无源集成耦合方法 WO2022165900A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030044120A1 (en) * 2001-09-03 2003-03-06 Agilent Technologies, Inc. Method for aligning a passive optical element to an active optical device
US6888989B1 (en) * 2001-12-11 2005-05-03 Phosistor Technologies, Inc. Photonic chip mounting in a recess for waveguide alignment and connection
CN1787304A (zh) * 2004-12-09 2006-06-14 中国科学院半导体研究所 半导体激光器无源对准耦合与高频封装用硅基版
US7213330B2 (en) * 2002-08-08 2007-05-08 Micron Technology, Inc. Method of fabricating an electronic device
US20100034497A1 (en) * 2008-08-05 2010-02-11 Fujitsu Limited Flexible Optical Pillars for an Optical Assembly

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008038993B4 (de) * 2008-08-13 2011-06-22 Karlsruher Institut für Technologie, 76131 Optisches Element und Verfahren zu seiner Herstellung
CN207440345U (zh) * 2017-10-26 2018-06-01 上海矽安光电科技有限公司 一种半导体激光器无源对准耦合封装基板
CN111262132B (zh) * 2018-11-30 2021-08-27 中国科学院半导体研究所 Iii-v族/硅材料开槽键合的激光器结构及其方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030044120A1 (en) * 2001-09-03 2003-03-06 Agilent Technologies, Inc. Method for aligning a passive optical element to an active optical device
US6888989B1 (en) * 2001-12-11 2005-05-03 Phosistor Technologies, Inc. Photonic chip mounting in a recess for waveguide alignment and connection
US7213330B2 (en) * 2002-08-08 2007-05-08 Micron Technology, Inc. Method of fabricating an electronic device
CN1787304A (zh) * 2004-12-09 2006-06-14 中国科学院半导体研究所 半导体激光器无源对准耦合与高频封装用硅基版
US20100034497A1 (en) * 2008-08-05 2010-02-11 Fujitsu Limited Flexible Optical Pillars for an Optical Assembly

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