WO2022165899A1 - 一种半导体制造方法 - Google Patents

一种半导体制造方法 Download PDF

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WO2022165899A1
WO2022165899A1 PCT/CN2021/079320 CN2021079320W WO2022165899A1 WO 2022165899 A1 WO2022165899 A1 WO 2022165899A1 CN 2021079320 W CN2021079320 W CN 2021079320W WO 2022165899 A1 WO2022165899 A1 WO 2022165899A1
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layer
laser
epitaxial
bridge
epitaxy
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French (fr)
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陈伯庄
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桂林雷光科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers

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  • the invention relates to the field of semiconductor parts and chips, in particular to a semiconductor manufacturing method for growing quantum wells with different layer thicknesses in the same plane in a single semiconductor epitaxial deposition process.
  • optical modes In opto-semiconductor integrated structures, optical modes must be able to propagate from one part to another with different properties along the horizontal plane waveguide with minimal loss.
  • epitaxy can complete parts with different properties on the plane by multiple growths, but the cost is high, and the height of waveguides with different properties needs to be strictly controlled.
  • the ability to grow cross-sections with multiple sections of different properties in a single epitaxial growth would be beneficial for reducing cost and complexity and needs to be developed and researched.
  • SAG Selective Area Growth
  • insulating film masks the insulating film mask pattern acting as a mask for modifying the growth rate of layers in predetermined areas.
  • This technique first forms a dielectric insulating film on a semiconductor substrate, lithography it to form a mask pattern, and then uses the MOCVD epitaxial growth method (to grow semiconductor material. No deposition of semiconductor material occurs on top of the insulating film mask. .
  • the growth rate inside the gap between the insulating film masks is improved compared to the area without the interstitial film mask on the periphery.
  • the semiconductor photonic integrated circuit includes first and second optoelectronic devices, The first and second optoelectronic devices are optically connected to each other on a single semiconductor substrate and formed by a selective area growth process including the steps of growing compound semiconductor layers constituting the first and second optoelectronic devices, the first photonic Devices are formed in specific regions on a semiconductor substrate using a set of insulating film masks with open space widths between the insulating film masks ranging from 1.0 to 0.125 times the vapor diffusion length of the Group III species, the masks Arranged in parallel with the optical axis of the first photonic device, the width of each mask being perpendicular to the optical axis, ranging from 16 to 800 ⁇ m, the second optoelectronic device was formed without using an insulating film masks with open space widths between the insulating film masks ranging from 1.0 to 0.125 times the vapor diffusion length of the Group III species, the masks Arranged in parallel with the optical axis of the first photonic device
  • the area of modified growth is smaller compared to the area not modified by any mask pattern.
  • This technique consistently results in a positive rate increase in the modified region compared to the unmodified region, i.e. the epitaxial layer in the modified region is thicker than the unmodified region ( Figure 1).
  • the properties of these regions such as photoluminescence (PL) and lattice matching, must be carefully characterized.
  • an example of an integrated structure is a laser with a passive beam forming section (Beam Forming Section BFS).
  • the key component of this integrated structure is the laser, and this part of the epitaxial layer needs to be directly monitored and characterized during fabrication.
  • the BFS must be formed in the unmodified epitaxial region, while the laser must be formed in the modified epitaxial region. Therefore, it is difficult to monitor and characterize materials for laser components by SAG techniques.
  • the object of the present invention is to provide a semiconductor manufacturing method for growing quantum wells with different layer thicknesses in the same plane in a single semiconductor epitaxial deposition process, the inventive concept is to adopt a method for selective depletion epitaxy (Selective Depletion Epitaxy SDE), It includes the following steps:
  • Step 1 carry out the first layer epitaxy, and grow a basic epitaxial layer structure
  • the basic epitaxial layer structure includes a substrate (1), a sacrificial layer (2) and a bridge layer (3), the sacrificial layer ( 2) between the substrate (1) and the bridging layer (3);
  • Step 2 forming a bridge pattern by photolithography and etching, and forming a wafer with patterned bridge head overhang;
  • step 3 cleaning the wafer processed in step 2;
  • Step 4 sending the cleaned wafer with the patterned bridge head overhanging back to the epitaxy equipment for the second layer epitaxy;
  • Step 5 after the second layer epitaxy, selectively removing the viaduct structure (4), thereby forming a wafer with epitaxial layers of different thicknesses in different regions.
  • the step 1 is performed by metal organic chemical vapor deposition (MOCVD).
  • MOCVD metal organic chemical vapor deposition
  • the material of the substrate in the step 1 is InP, GaAs, GaN or InAs or other semiconductor single crystal materials.
  • the sacrificial layer (2) and the bridging layer (3) have compositions that are completely or approximately matched to the lattice of the material of the substrate (1).
  • material is InP
  • the sacrificial layer (2) material is InGaAs
  • the bridging layer (3) material is InP.
  • the step 2 is implemented by selective depletion epitaxy, so that the bridge pattern is formed on the area to be modified.
  • the step 2 includes:
  • Step 21 etching through the bridge layer (3) outside the pattern
  • Step 22 using selective etching to remove the sacrificial layer (2), but leaving the bridge layer portion within the pattern, so that the bridge is suspended over the area to be modified.
  • the bridge pattern comprises a support structure (5), a viaduct structure (4) and side beams (6) attached to the support structure (5), wherein the support structure (5) is larger than the viaduct structure (4) Width and side member (6) width.
  • the layer is deposited on the wafer, and the area below the viaduct structure is modified to have a negative growth rate to form a layer with a smaller thickness than the area outside the viaduct structure.
  • Another object of the present invention is to provide a method for manufacturing a laser integrated structure for growing quantum wells with different layer thicknesses in the same plane in a single semiconductor epitaxial deposition process. After steps 1-5 are implemented, the method further includes:
  • Step 6 carry out the third epitaxial growth, and complete the preparation of the laser integrated device after forming the electrical contact; or in order to form a distributed feedback (DFB) laser, grow a grating layer in the third epitaxial growth, and then use holographic exposure or electron beam formation After the grating, the fourth epitaxy is performed to form an electrical contact to complete the preparation of the laser integrated device;
  • DFB distributed feedback
  • Step 7 forming a two-dimensional light guide structure by standard processing, the two-dimensional light guide structure comprising a laser (14) with electrical contacts and a beam forming part (13), the laser (14) and the beam forming part (13) ) are combined to form the laser integrated structure.
  • Another object of the present invention is to provide a laser integrated structure for growing quantum wells with different layer thicknesses in the same plane in a single semiconductor epitaxial deposition process, the laser integrated structure comprising lasers (14) and beams formed in different regions respectively forming part (13), the laser (14) is formed in a region outside the viaduct structure (4) of the unmodified epitaxy, the beam forming part (13) is formed under the viaduct structure (4) of the modified epitaxy In the region, the beam forming part (13) is an active waveguide, and the upper and lower parts of the laser (14) have an upper SCH (Separate Confinement Heterostructure, separation confinement heterolayer structure) (7) and a lower separation confinement heterolayer
  • the structure (9) forms two layers of SCH (Separate Confinement Heterostructure) layers, and a multiple quantum well MQW (Multiple Quantum Wells) (8) is formed between the two layers of SCH layers, and the laser (14) is arranged above the A P+-InGaAs contact
  • the resulting far-field pattern is narrower compared to a simple laser device without the beamforming portion.
  • the beamforming part is also Becomes not absorbing the light emitted by the laser part. Since the beamforming part has low loss to the laser mode, and the light exit mirror is also non-absorbing, it is beneficial to the reliability of the device.
  • FIG. 2 is a schematic diagram of a first sub-layer epitaxial structure implemented by MOCVD according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of forming a bridge pattern by photolithography and etching according to an embodiment of the present invention
  • FIG. 4(a) is a schematic cross-sectional structure diagram of epitaxial layer A-A grown by MOCVD after forming a bridge by photolithography and etching according to an embodiment of the present invention
  • 4(b) is a schematic diagram of the cross-sectional structure of the epitaxial layer B-B grown by MOCVD after the bridge is formed by photolithography and etching according to an embodiment of the present invention
  • 4(c) is a schematic diagram of the cross-sectional structure of the epitaxial layer C-C grown by MOCVD after the bridge is formed by photolithography and etching according to an embodiment of the present invention
  • FIG. 5 is an RWG (Ridge Waveguide) laser with a beam-forming partial waveguide according to an embodiment of the present invention.
  • This embodiment provides a semiconductor manufacturing method for growing quantum wells with different layer thicknesses in the same plane in a single semiconductor epitaxial deposition process.
  • a viaduct structure is formed on the area to be modified, as shown in FIG. 3 .
  • the epitaxial layer under the bridge structure is thinner than the epitaxial layer outside the bridge structure due to reduced gas source diffusion under the bridge structure. Therefore, this technique results in a negative layer epitaxy rate in the modified region compared to the unmodified region, as shown in Fig. 4(a)-(c), the inventors refer to this technique as Selective Depletion Epitaxy SDE).
  • the present embodiment relates to a wafer manufacturing method for growing quantum wells with different layer thicknesses in the same plane in a single semiconductor epitaxial deposition process, including the following steps:
  • Step 1 implement the first layer epitaxy by MOCVD (metal-organic chemical vapor deposition, metal organic chemical vapor deposition) mode, thereby growing the basic epitaxial layer structure
  • the basic epitaxial layer structure consists of substrate 1, a
  • the sacrificial layer 2 is composed of a bridging layer 3
  • the sacrificial layer 2 is located between the substrate 1 and the bridging layer 3 .
  • an example of the material of the substrate 1 may be InP.
  • the substrate 1 material can be GaAs, GaN, InAs or other similar materials depending on the application and the laser emission wavelength.
  • the sacrificial layer 2 and the bridging layer 3 have compositions that are perfectly lattice matched or approximately lattice matched to the material of the substrate 1 .
  • the materials of the sacrificial layer 2 and the bridging layer 3 are chosen such that there is a selective chemical etchant that is more selective than the other.
  • the material of the substrate 1 is InP
  • the material of the sacrificial layer 2 can be InGaAs
  • the material of the bridging layer 3 can be InP or other combinations satisfying the above conditions.
  • Step 2 forming a bridge pattern by photolithography and etching, and forming a wafer with patterned bridge head overhang; wherein the photolithography and etching process includes two steps: Step 21, etch through the bridge layer 3 outside the pattern; Step 22, The sacrificial layer 2 is removed using a selective etch, but the portion of the bridging layer 3 within the pattern remains, leaving the bridge overhanging the area to be modified.
  • the viaduct structure 4 is first formed on the area to be modified.
  • the optimal distance between the viaduct and the wafer surface under the bridge is 2-6um, but other sizes are also possible, and the optimal width of the bridge structure is 2-10um but other sizes are also possible.
  • the length of the bridge structure depends on the design integration structure requirements.
  • the width of the bridge structure can also vary along the axis leading to variations in the thickness of the waveguide and quantum well.
  • the structure of the bridge includes a support structure 5 , a viaduct structure 4 and side beams 6 attached to the support structure 5 . There can be more than one side beam 6, and can also be placed on one side or both sides of the viaduct.
  • the support structure 5 is larger than the width of the viaduct 4 structure and the width of the side beams 6, so some of the sacrificial layers 2 are not completely removed during the second etching process.
  • the epitaxial layer under the bridge structure is thinner than the epitaxial layer outside the bridge structure due to reduced gas source diffusion under the bridge structure. Therefore, the SDE technique results in a negative layer epitaxy rate for the modified region compared to the unmodified region.
  • step 3 cleaning the wafer processed in step 2;
  • step 4 the cleaned wafer with the patterned bridge head overhang is sent back to the MOCVD equipment for the second layer epitaxy.
  • layers are deposited on the wafer.
  • the area below the viaduct structure is modified to have a negative growth rate, so the resulting layer is thinner compared to the area outside the viaduct structure.
  • Step 5 after the second sub-layer epitaxy, selectively removing part of the viaduct structure 4, thereby forming a wafer with epitaxial layers of different thicknesses in different regions.
  • the present embodiment provides a method for manufacturing a laser integrated structure for growing quantum wells with different layer thicknesses in the same plane in a single semiconductor epitaxial deposition process. After steps 1-5 are implemented, the method further includes:
  • Step 6 carry out the third epitaxial growth, and complete the preparation of the laser integrated device after the electrical contact is formed; or in order to form a DFB (distributed feedback) laser, a grating layer is epitaxially grown for the third time, and then holographic exposure or electron beam formation is used. After the grating, the fourth epitaxy is performed to form an electrical contact to complete the preparation of the laser integrated device;
  • DFB distributed feedback
  • Step 7 after which standard processing can form a two-dimensional light guide structure. Further processing may form the laser 14 and beam forming portion 13 with electrical contacts.
  • This embodiment uses the complete preparation method constituted by steps 1-7 to prepare a laser integrated structure in which quantum wells with different layer thicknesses are grown in the same plane in a single semiconductor epitaxial deposition process.
  • This embodiment is an RWG (Ridge Waveguide) structure, Referring to FIG.
  • the laser integrated structure includes lasers 14 and beam forming parts 13 respectively formed in different regions, and the inventive concept is to apply the technique of growing quantum wells with different layer thicknesses in the same plane in a single semiconductor epitaxial deposition process to a
  • the laser 14 is formed in the area outside the viaduct structure 4 which is not modified epitaxy
  • the beam forming part 13 is formed in the area of the modified epitaxy under the viaduct structure 4 .
  • the beam forming section 13 is a passive waveguide.
  • the upper and lower parts of the laser 14 have an upper separation confinement heterolayer structure 7 and a lower separation confinement heterolayer structure 9, thereby forming two separation confinement heterolayer structure layers, and multiple quantum quantum layers are formed between the two separation confinement heterolayer structure layers.
  • Well 8 namely MQW, Multiple Quantum Wells.
  • a P+-InGaAs contact layer 11 and an InP transition layer 12 are arranged above the laser 14 , and a contact metal layer 10 is arranged above the P+-InGaAs contact layer 11 .
  • the beamforming portion 13 has thinner layers, so the laser optical mode occupies a larger cross-sectional area.
  • This part can act as a passive waveguide.
  • BH Buried Heterostructure
  • the resulting far-field pattern is narrower compared to a simple laser device without the beamforming portion.
  • This is advantageous for optically coupling the device into an optical fiber.
  • the beamforming portion also becomes non-absorbing of light emitted by the laser portion because the quantum well formed is narrower than the laser portion and thus has a higher bandgap. This is important because the beamforming part has low loss to the laser mode.
  • the light-emitting mirror is also non-absorbing, which is beneficial to the reliability of the device.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本发明提供一种半导体制造方法，在单个半导体外延沉积过程中在同一平面内生长不同层厚度量子阱，包括如下步骤：进行第一次层外延，以生长基本的外延层结构，基本的外延层结构包括衬底、一个牺牲层和一个桥接层，牺牲层位于衬底和桥接层之间；通过光刻和蚀刻形成桥图案，并形成带有图案化桥头悬垂的晶片；清洗晶片；将清洗后带有图案化桥头悬垂的晶片送回外延设备进行第二次层外延；选择性去除部分高架桥结构，从而形成不同区域中具有不同厚度外延层的晶片。还提供了相应的激光器集成结构制造方法及由此制造的激光器集成结构。当该光学模式通过波束形成部分离开集成设备时，所得的远场图案更窄，有利于将设备光耦合到光纤中及设备的可靠性。

Description

一种半导体制造方法 技术领域
本发明涉及半导体零部件以及芯片领域，特别是涉及一种在单次半导体外延沉积过程中在同一平面内生长不同层厚度量子阱的半导体制造方法。
背景技术
在光电半导体集成结构中，光模必须能够沿着水平面波导以最小的损耗从一个部分传播到另一属性不同的部分。一般外延能够以多次生长完成平面上不同属性部分但成本高，不同属性的波导高度需要严格控制。能够以单个外延生长来生长具有多个不同属性部分的截面的技术，对于降低成本和复杂性是有益的，需要对此进行开发和研究。
诸如所谓的选择性区域生长(Selective Area Growth，SAG)之类的现有技术涉及绝缘膜掩模，该绝缘膜掩模图案充当用于修改预定区域中的层生长速率的掩模。该技术首先在半导体衬底上形成介电绝缘膜，对其进行光刻形成掩模构图，然后使用MOCVD外延生长法(生长半导体材料。在绝缘膜掩模的顶部上不会发生半导体材料的沉积。与周边没有介绝缘膜掩模的区域相比，绝缘膜掩模之间的间隙内部的增长率得到了改善。
如图1所示，为现有技术美国专利5543353中详细概述了的现有技术方案的结构示意图，US5543353A公开了制造半导体光子集成电路的方法，半导体光子集成电路包括第一和第二光电子器件，第一和第二光电子器件在单个半导体衬底上彼此光学连接并且通过选择性区域生长工艺形成，选择性区域生长工艺包括生长构成第一和第二光电子器件的化合物半导体层 的步骤，第一光子器件使用一组绝缘膜掩模在半导体衬底上的特定区域中形成，绝缘膜掩模之间具有开放空间宽度，开放空间宽度范围为第III族物种蒸汽扩散长度的1.0到0.125倍，掩模与第一光子器件的光轴平行布置，每个掩模的宽度与光轴垂直，范围为16到800μm，第二光电子器件在不使用绝缘膜掩模的情况下形成。以美国专利5543353为例，与未通过任何掩模图案进行改性的区域相比，改性生长的区域较小。与未修改的区域相比，该技术始终导致修改后的正速率增长，即修改区域中的外延层比未修改的区域厚(图1)。当集成结构需要在关键应用中使用这些小区域时，必须仔细表征这些区域的属性，例如光致发光(Photoluminescence，PL)和晶格匹配。表征PL和晶格匹配的大多数设备都只能读取大面积的数据，读不到较小尺寸的修改区域，所以难以采用必要的精度直接表征；此外，如果采用小区域表征设备，设备成本非常昂贵。
此外，集成结构的示例是具有无源光束形成部分(Beam Forming Section BFS)的激光器。这种集成结构的关键组件是激光器，在制造中需要直接监视和表征这部分的外延层。但是，使用SAG技术，必须在未修饰的外延区域形成BFS，而必须在修饰的外延区域形成激光。因此，难以通过SAG技术监视和表征用于激光组件的材料。
发明内容
本发明的目的在于提供一种半导体制造方法，用于在单个半导体外延沉积过程中在同一平面内生长不同层厚度量子阱，发明构思在于采用选择性耗尽外延(Selective Depletion Epitaxy SDE)的方法，包括如下步骤：
步骤1，进行第一次层外延，生长基本的外延层结构，所述基本的外延层结构包括衬底(1)、一个牺牲层(2)和一个桥接层(3)，所述牺牲层(2)位于所述衬底(1)和所述桥接层(3)之间；
步骤2，通过光刻和蚀刻形成桥图案，并形成带有图案化桥头悬垂的晶片；
步骤3，将步骤2处理后的晶片进行清洗；
步骤4，将清洗后带有图案化桥头悬垂的晶片送回外延设备进行第二次层外延；
步骤5，在第二次层外延后，选择性去除高架桥结构(4)，从而形成不同区域中具有不同厚度外延层的晶片。
优选的，所述步骤1通过金属有机化学气相沉积(MOCVD)方式进行。
优选的，所述步骤1的所述衬底的材料为InP、GaAs，GaN或InAs或其他半导体单晶材料。
优选的，所述牺牲层(2)和所述桥接层(3)具有与所述衬底(1)的材料的晶格完全匹配或与晶格大致匹配的成分，当所述衬底(1)材料为InP的情况下，所述牺牲层(2)材料为InGaAs，所述桥接层(3)材料为InP。
优选的，所述步骤2采用选择性耗尽外延实施，从而在需要修改的区域上形成所述桥图案。
优选的，所述步骤2包括：
步骤21，在图案外蚀刻穿过桥接层(3)；
步骤22，使用选择性蚀刻去除牺牲层(2)，但保留了图案内的桥接层部分，从而使得桥悬置于要修改的区域上。
优选的，所述桥图案包括支撑结构(5)、高架桥结构(4)以及附着在支撑结构(5)上的侧梁(6)，其中所述支撑结构(5)大于高架桥结构(4)的宽度和侧梁(6)宽度。
优选的，所述步骤4所述第二次层外延生长期间，将层沉积在晶片上，所述高架桥结构下方的区域被修改为负增长率，形成比高架桥结构外的区域厚度更小的层。
本发明的目的还在于提供一种在单个半导体外延沉积过程中在同一平面内生长不同层厚度量子阱的激光器集成结构制造方法，在步骤1-5实施后，还包括：
步骤6，进行第三次外延生长，形成电接触后完成激光器集成器件的制备；或者为了形成分布反馈(DFB)激光器，在第三次外延生长一层光栅层，然后采用全息曝光或电子束形成光栅后，再进行第四次外延形成电接触后完成激光器集成器件的制备；
步骤7，通过标准处理形成二维光导结构，所述二维光导结构包括具有电触点的激光器(14)和波束形成部分(13)，所述激光器(14)和所述波束形成部分(13)组合形成所述激光器集成结构。
本发明的目的还在于提供一种在单个半导体外延沉积过程中在同一平面内生长不同层厚度量子阱的激光器集成结构，所述激光器集成结构包括分别形成在不同区域中的激光器(14)以及波束形成部分(13)，所述激光器(14)形成在未改性外延的高架桥结构(4)以外的区域中，所述波束形成部分(13)形成在高架桥结构(4)的下方改性外延的区域中，所述波束形成部分(13)为有源波导，所述激光器(14)上部和下部具有上部SCH(Separate Confinement Heterostructure，分离限制异质层结构)(7)和下部分离限制异质层结构(9)从而形成两层SCH(Separate Confinement Heterostructure分离限制异质层结构)层，两层SCH层之间形成多量子阱MQW(Multiple Quantum Wells)(8)，所述激光器(14)上方设置P+-InGaAs接触层(11)与InP过渡层(12)，所述P+-InGaAs接触层(11)上方设置接触金属层(10)。
本发明的有益效果：
(1)当该光学模式通过波束形成部分离开集成设备时，与没有波束形成部分的简单激光设备相比，所得的远场图案更窄。
(2)对于将设备光耦合到光纤中是有利的，当外延层足够薄以表现出量子尺寸效应时，由于形成的量子阱比激光部分窄并且因此具有更高的带隙，波束形成部分也变得不吸收激光部分所发出的光。由于波束形成部分对激光学模式具有低损耗，并且出光镜面也是非吸收性的，因此有利于器件的可靠性。
根据下文结合附图对本发明具体实施例的详细描述，本领域技术人员将会更加明了本发明的上述以及其他目的、优点和特征。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本发明的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。本发明的目标及特征考虑到如下结合附图的描述将更加明显，附图中：
附图1为根据现有技术的制造半导体光子集成电路的方法；
附图2为根据本发明实施例的通过MOCVD方式实施第一次层外延结构示意图；
附图3为根据本发明实施例的通过光刻和蚀刻形成桥图案的结构示意图；
附图4(a)为根据本发明实施例的通过光刻和蚀刻形成桥后MOCVD所长出的外延层A-A截面结构示意图；
附图4(b)为根据本发明实施例的通过光刻和蚀刻形成桥后MOCVD所长出的外延层B-B截面结构示意图；
附图4(c)为根据本发明实施例的通过光刻和蚀刻形成桥后MOCVD 所长出的外延层C-C截面结构示意图；
附图5为根据本发明实施例的具有波束形成部分波导的RWG(Ridge Waveguide)激光器。
具体实施方式
本实施例提供一种在单个半导体外延沉积过程中在同一平面内生长不同层厚度量子阱的半导体制造方法，首先在需要修改的区域上形成高架桥结构，如图3所示。由于减少了在桥结构下方的气体源扩散，桥下的外延层比桥结构外的外延层薄。因此，与未修改区域相比，此技术导致修改区域的层外延速率为负，如图4(a)-(c)所示，发明人将此项技术成为选择性耗尽外延(Selective Depletion Epitaxy SDE)。
本实施例涉及一种在单个半导体外延沉积过程中在同一平面内生长不同层厚度量子阱的晶片制造方法，包括如下步骤：
步骤1，参见图2，通过MOCVD(metal-organic chemical vapor deposition，金属有机化学气相沉积)方式实施第一次层外延，从而生长基本的外延层结构，基本的外延层结构由衬底1、一个牺牲层2和一个桥接层3组成，牺牲层2位于衬底1和桥接层3之间。其中，衬底1材料的示例可以是InP。根据应用和激光发射波长，衬底1材料可以是GaAs，GaN，InAs或其他类似材料。牺牲层2和桥接层3具有与衬底1材料的晶格完全匹配或与晶格大致匹配的成分。
作为优选实施方式，所选择牺牲层2材料和桥接层3材料使得存在选择性优于另一种的选择性化学蚀刻剂。在该示例中，衬底1材料是InP，牺牲层2材料可以是InGaAs，桥接层3材料可以是InP或满足上述条件的其他组合。
步骤2，通过光刻和蚀刻形成桥图案，并形成带有图案化桥头悬垂的晶片；其中光刻和蚀刻过程包括两个步骤：步骤21，在图案外蚀刻穿过桥接层3；步骤22，使用选择性蚀刻去除牺牲层2，但保留了图案内的桥接层3部分，从而使得桥悬置于要修改的区域上。
如图3所示，首先在需要修改的区域上形成高架桥结构4。高架桥与桥下晶圆表面最佳距离为2-6um，但其他尺寸也可以，桥结构最佳宽度为2-10um但其他尺寸也可以。桥结构的长度随设计集成结构需求而定。桥结构的宽度也可以顺着轴方向有所变化导致波导与量子阱的厚度变化。为了保持桥接层处桥梁悬空，桥梁的结构包括支撑结构5、高架桥结构4以及附着在支撑结构5上的侧梁6。侧梁6可以不止一个，也可以置于高架桥的一侧或两侧。支撑结构5大于高架桥4结构的宽度和侧梁6宽度，因此某些牺牲层2在第二次蚀刻过程中并未完全去除。参见图4，由于减少了在桥结构下方的气体源扩散，桥下的外延层比桥结构外的外延层薄。因此，与未修改区域相比，SDE技术导致修改区域的层外延速率为负。
步骤3，将步骤2处理后的晶片进行清洗；
步骤4，将清洗后带有图案化桥头悬垂的晶片送回MOCVD设备进行第二次层外延。第二次层外延生长期间，将层沉积在晶片上。高架桥结构下方的区域被修改为负增长率，因此与高架桥结构外的区域相比所形成的层更薄。
步骤5，在第二次层外延后，选择性去除部分高架桥结构4，从而形成不同区域中具有不同厚度外延层的晶片。
本实施例根据上述方法提供一种在单个半导体外延沉积过程中在同一平面内生长不同层厚度量子阱的激光器集成结构制造方法，在步骤1-5实施后，还包括：
步骤6，进行第三次外延生长，形成电接触后完成激光器集成器件的制 备；或者为了形成DFB(distributed feedback)激光器，在第三次外延生长一层光栅层，然后采用全息曝光或电子束形成光栅后，再进行第四次外延形成电接触后完成激光器集成器件的制备；
步骤7，此后，标准处理可以形成二维光导结构。进一步的处理可以形成具有电触点的激光器14和波束形成部分13。
本实施例使用步骤1-7构成的完整的制备方法制备一种在单个半导体外延沉积过程中在同一平面内生长不同层厚度量子阱的激光器集成结构，本实施例是RWG(Ridge Waveguide)结构，参见图5，激光器集成结构包括分别形成在不同区域中的激光器14以及波束形成部分13，其发明构思在于将在单个半导体外延沉积过程中在同一平面内生长不同层厚度量子阱的技术应用于具有无源波束形成部分(BFS)的激光器的集成结构的示例中，激光器14形成在未改性外延的高架桥结构4以外的区域中，波束形成部分13形成在高架桥结构4下方改性外延的区域中。由于未修饰外延的面积比修饰外延的面积大得多，因此使用本发明的技术很容易监控和表征激光切片的材料，譬如用XRD测外延层的晶格匹配，PL测外延层的光谱。波束形成部分13为无源波导。激光器14上部和下部具有上层分离限制异质层结构7和下层分离限制异质层结构9，从而形成两层分离限制异质层结构层，两层分离限制异质层结构层之间形成多量子阱8，即MQW，Multiple Quantum Wells。激光器14上方设置P+-InGaAs接触层11与InP过渡层12，P+-InGaAs接触层11上方设置接触金属层10。
在RWG的实施例中，波束形成部分13具有较薄的层，因此激光光学模式占用较大的横截面面积。这部分可作为无源波导。对本领域技术人员，即熟悉工艺的技术人员可以熟知该技术也可以实施为其他实施例，譬如BH(Buried Heterostructure).
当该光学模式通过波束形成部分离开集成设备时，与没有波束形成部 分的简单激光设备相比，所得的远场图案更窄。这对于将设备光耦合到光纤中是有利的。当外延层足够薄以表现出量子尺寸效应时，由于形成的量子阱比激光部分窄并且因此具有更高的带隙，因此波束形成部分也变得不吸收激光部分所发出的光。这很重要，因为波束形成部分对激光学模式具有低损耗。出光镜面也是非吸收性的，有利于器件的可靠性。
虽然本发明已经参考特定的说明性实施例进行了描述，但是不会受到这些实施例的限定而仅仅受到附加权利要求的限定。本领域技术人员应当理解可以在不偏离本发明的保护范围和精神的情况下对本发明的实施例能够进行改动和修改。

Claims (10)

  1. 一种半导体制造方法，其特征在于包括如下步骤：
    步骤1，进行第一次层外延，生长基本的外延层结构，所述基本的外延层结构包括衬底(1)、一个牺牲层(2)和一个桥接层(3)，所述牺牲层(2)位于衬底(1)和桥接层(3)之间；
    步骤2，通过光刻和蚀刻形成桥图案，并形成带有图案化桥头悬垂的晶片；
    步骤3，将步骤2处理后的晶片进行清洗；
    步骤4，将清洗后带有图案化桥头悬垂的晶片送回外延设备进行第二次层外延；
    步骤5，在第二次层外延后，选择性去除部分高架桥结构(4)，从而形成不同区域中具有不同厚度外延层的晶片。
  2. 根据权利要求1所述的一种半导体制造方法，其特征在于：所述步骤1外延通过金属有机化学气相沉积(MOCVD)方式进行。
  3. 根据权利要求1所述的一种半导体制造方法，其特征在于：所述步骤1的所述衬底(1)的材料为InP、GaAs，GaN或InAs。
  4. 根据权利要求3所述的一种半导体制造方法，其特征在于：所述牺牲层(2)和所述桥接层(3)具有与所述衬底(1)的材料的晶格完全匹配或与晶格大致匹配的成分，当所述衬底(1)的材料为InP的情况下，所述牺牲层(2)的材料为InGaAs，所述桥接层(3)的材料为InP。
  5. 根据权利要求1所述的一种半导体制造方法，其特征在于：所述步骤2采用选择性耗尽外延方式实施，从而在需要修改的区域上形成所述桥图案。
  6. 根据权利要求5所述的一种半导体制造方法，其特征在于：所述步骤2包括：
    步骤21，在图案外蚀刻穿过桥接层(3)；
    步骤22，使用选择性蚀刻去除牺牲层(2)，但保留了图案内的桥接层(3)的部分，从而使得桥悬置于要修改的区域上。
  7. 根据权利要求5所述的一种半导体制造方法，其特征在于：所述桥图案包括支撑结构(5)、高架桥结构(4)以及附着在支撑结构(5)上的侧梁(6)，其中所述支撑结构(5)大于高架桥结构(4)的宽度和侧梁(6)的宽度。
  8. 根据权利要求1所述的一种半导体制造方法，其特征在于：所述步骤4所述第二次层外延生长期间，将层沉积在晶片上，所述高架桥结构(4)的下方区域被修改为负增长率，形成比所述高架桥结构(4)外的区域厚度更小的层。
  9. 一种根据权利要求1-8任一所述的半导体制造方法，在步骤1-5实施后，还包括：
    步骤6，进行第三次外延生长，形成电接触后完成激光器集成器件的制备；或者为了形成分布式反馈(DFB)激光器，在第三次外延生长一层光栅层，然后采用全息曝光或电子束形成光栅后，再进行第四次外延形成电接触后完成激光器集成器件的制备；
    步骤7，通过标准处理形成二维光导结构，所述二维光导结构包括具有电触点的激光器(14)和波束形成部分(13)，所述激光器(14)和所述波束形成部分(13)组合形成所述激光器集成结构。
  10. 一种使用权利要求9所述的半导体制造方法形成的激光器集成结构，所述激光器集成结构包括分别形成在不同区域中的激光器(14)以及波束形成部分(13)，所述激光器(14)形成在未改性外延的高架桥结构以外的区域中，所述波束形成部分(13)形成在高架桥结构(4)的下方改性外延的区域中，所述波束形成部为无源波导，所述激光器(13)上部和下部分别具有上层分离限制异质层结构(7)和下层分离限制异质层结构 (9)，从而形成两层分离限制异质层结构层，两层分离限制异质层结构层之间形成多量子阱(8)，所述激光器(14)上方设置P+-InGaAs接触层(11)与InP过渡层(12)，所述P+-InGaAs接触层(11)上方设置接触金属层(10)。
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