WO2022163425A1 - チップ付き基板の製造方法、及び基板処理装置 - Google Patents

チップ付き基板の製造方法、及び基板処理装置 Download PDF

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WO2022163425A1
WO2022163425A1 PCT/JP2022/001520 JP2022001520W WO2022163425A1 WO 2022163425 A1 WO2022163425 A1 WO 2022163425A1 JP 2022001520 W JP2022001520 W JP 2022001520W WO 2022163425 A1 WO2022163425 A1 WO 2022163425A1
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Prior art keywords
substrate
chips
chip
laser beam
silicon wafer
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PCT/JP2022/001520
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English (en)
French (fr)
Japanese (ja)
Inventor
義久 松原
義弘 堤
陽平 山下
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to US18/261,898 priority Critical patent/US20240079403A1/en
Priority to JP2022578259A priority patent/JP7688054B2/ja
Priority to KR1020237027803A priority patent/KR20230135615A/ko
Priority to CN202280010534.5A priority patent/CN116783684A/zh
Publication of WO2022163425A1 publication Critical patent/WO2022163425A1/ja
Anticipated expiration legal-status Critical
Priority to JP2025085055A priority patent/JP2025114860A/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0442—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7408—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including alignment aids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7428—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/607—Located on parts of packages, e.g. on encapsulations or on package substrates

Definitions

  • the present disclosure relates to a method for manufacturing a substrate with chips and a substrate processing apparatus.
  • FIG. 20 of Patent Document 1 illustrates the chip-on-wafer manufacturing process.
  • the singulated first memory chips are bonded one by one to the base wafer on which the plurality of second memory chips are formed.
  • One aspect of the present disclosure provides a technique for reusing an alignment mark used for alignment when bonding a chip and a substrate or for measuring misalignment after bonding.
  • a method for manufacturing a substrate with a chip includes the following (A) to (B).
  • the first substrate separated from the chip includes an alignment mark used for alignment when bonding the chip and the first substrate or for measuring misalignment after bonding.
  • alignment marks can be reused.
  • FIG. 1 is a flow chart showing a method for manufacturing a chip-equipped substrate according to one embodiment.
  • FIG. 2 is a flow chart showing details of S1 in FIG.
  • FIG. 3 is a flow chart showing the details of S6 in FIG.
  • FIG. 4 is a cross-sectional view showing a state in the middle of S1 in FIG.
  • FIG. 5 is a cross-sectional view showing the state when S1 in FIG. 1 is completed.
  • FIG. 6 is a cross-sectional view showing the state when S2 in FIG. 1 is completed.
  • FIG. 7 is a cross-sectional view showing the state when S3 in FIG. 1 is completed.
  • FIG. 8 is a cross-sectional view showing a state in the middle of S4 in FIG.
  • FIG. 9 is a cross-sectional view showing the state when S4 in FIG. 1 is completed.
  • FIG. 10 is a cross-sectional view showing the state when S5 in FIG. 1 is completed.
  • FIG. 11 is a sectional view showing the state at the completion of S61 of FIG. 3 included in S6 of FIG.
  • FIG. 12 is a sectional view showing the state at the completion of S62 of FIG. 3 included in S6 of FIG.
  • FIG. 13 is a cross-sectional view showing the state at the completion of S63 of FIG. 3 included in S6 of FIG.
  • FIG. 14 is a cross-sectional view showing the state when S7 in FIG. 1 is completed.
  • FIG. 15A is a cross-sectional view showing an example of the first step of the Ge film formation method.
  • FIG. 15B is a cross-sectional view showing an example of the second step of the Ge film formation method.
  • FIG. 15C is a cross-sectional view showing an example of the third step of the Ge film formation method.
  • FIG. 15D is a cross-sectional view showing an example of the fourth step of the Ge film formation method.
  • FIG. 15E is a cross-sectional view showing an example of the fifth step of the Ge film formation method.
  • FIG. 15F is a cross-sectional view showing an example of the sixth step of the Ge film formation method.
  • FIG. 16 is a diagram showing an example of transmittance of a SiGe film.
  • FIG. 17A is a cross-sectional view showing an example of the first step of the method for forming a metal silicide film.
  • FIG. 17B is a cross-sectional view showing an example of the second step of the method for forming a metal silicide film.
  • FIG. 17C is a cross-sectional view showing an example of the third step of the method for forming a metal silicide film.
  • FIG. 17D is a cross-sectional view showing an example of the fourth step of the method for forming a metal silicide film.
  • FIG. 17E is a cross-sectional view showing an example of the fifth step of the method for forming a metal silicide film.
  • FIG. 17F is a cross-sectional view showing an example of the sixth step of the method for forming a metal silicide film.
  • FIG. 17G is a cross-sectional view showing an example of the seventh step of the method for forming a metal silicide film.
  • FIG. 18 is a diagram showing an example of absorptivity of a metal silicide film.
  • FIG. 19A is a cross-sectional view showing an example of the first step of the AlN film formation method.
  • FIG. 19B is a cross-sectional view showing an example of the second step of the AlN film formation method.
  • FIG. 19C is a cross-sectional view showing an example of the third step of the AlN film formation method.
  • FIG. 19D is a cross-sectional view showing an example of the fourth step of the AlN film formation method.
  • FIG. 19E is a cross-sectional view showing an example of the fifth step of the AlN film formation method.
  • FIG. 19F is a cross-sectional view showing an example of the sixth step of the AlN film formation method.
  • FIG. 19G is a cross-sectional view showing an example of the seventh step of the AlN film formation method.
  • FIG. 20 is a diagram showing an example of the transmittance of an AlN film.
  • FIG. 21 is a plan view showing a substrate processing apparatus according to one embodiment.
  • a method for manufacturing a substrate with a chip includes S1 to S7 shown in FIG. 1, for example.
  • S1 in FIG. 1 has S11 to S14 shown in FIG. 2, for example.
  • S6 shown in FIG. 1 has S61 to S63 shown in FIG. 3, for example.
  • the first substrate 1 has, for example, a silicon wafer 11, an absorption layer 12, and a bonding layer 13.
  • the absorption layer 12 may also serve as the bonding layer 13 as will be described later, and the first substrate 1 may have the silicon wafer 11 and the absorption layer 12 .
  • a compound semiconductor wafer may be used instead of the silicon wafer 11 .
  • Compound semiconductor wafers are not particularly limited, but are, for example, GaAs wafers, SiC wafers, GaN wafers, InP wafers, or AlN wafers.
  • the absorption layer 12 is arranged between the silicon wafer 11 and the chips 2A, 2B. Although details will be described later, as shown in FIG. 11, the laser beam LB2 passes through the silicon wafer 11 and is absorbed by the absorption layer 12 . Since the laser beam LB2 is absorbed by the absorption layer 12 and does not hit the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed.
  • the absorption layer 12 is, for example, a silicon oxide layer, and is formed by a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, or the like.
  • the absorption layer 12 may be a silicon nitride layer, a silicon carbonitride layer, or the like as long as it can absorb the laser beam LB2 to an extent that damage to the chips 2A and 2B can be suppressed.
  • the silicon nitride layer is formed by thermal nitridation, CVD, or the like.
  • the silicon carbonitride layer is formed by a CVD method or the like.
  • the bonding layer 13 is arranged between the absorbing layer 12 and the chips 2A and 2B as shown in FIG. 4 and contacts the chips 2A and 2B.
  • the bonding layer 13 is, for example, an insulating layer such as a silicon oxide layer.
  • the bonding layer 13 may be made of a material different from that of the absorbing layer 12, or may be made of the same material. In the latter case, the absorption layer 12 may also serve as the bonding layer 13 .
  • the first substrate 1 includes alignment marks 15 .
  • the alignment mark 15 is used for alignment during bonding between the first substrate 1 and the chips 2A and 2B, or for measurement of positional deviation after bonding.
  • Alignment marks 15 may be used for both alignment and misalignment measurement.
  • the measurement result of the positional deviation after bonding is used, for example, for alignment when bonding the first substrate 1 and the chip after the next time.
  • the measurement result of the positional deviation after bonding may be used for quality control such as discrimination of defective products.
  • the alignment mark 15 is formed between the silicon wafer 11 and the absorption layer 12, as shown in FIG. 12, and is formed on the side opposite to the chips 2A and 2B with respect to the dividing plane D.
  • the silicon wafer 11 can be separated from the chips 2A and 2B.
  • Alignment marks 15 are attached to the silicon wafer 11 separated from the chips 2A and 2B. Therefore, when the silicon wafer 11 is reused, the alignment mark 15 can be reused without having to re-form the alignment mark 15 .
  • the alignment mark 15 absorbs infrared rays used for imaging the alignment mark 15 .
  • the infrared camera captures an image of the alignment mark 15 by receiving infrared rays that have passed through the silicon wafer 11 .
  • the wavelength of the infrared rays used for imaging is, for example, 1000 nm to 2000 nm, different from the wavelength of the laser beam LB2.
  • the alignment mark 15 has an absorptance of infrared rays used for imaging the alignment mark 15, for example, 45% or more and 100% or less, preferably 50% or more and 100% or less, more preferably 60% or more and 100% or less. .
  • the alignment mark 15 transmits the laser beam LB2, as shown in FIG.
  • the laser beam LB2 is transmitted through the silicon wafer 11 and the alignment marks 15 and forms a modified layer M in the absorption layer 12 .
  • the modified layer M is formed by the absorption layer 12 absorbing the laser beam LB2.
  • a plurality of modified layers M are formed on the dividing surface D. As shown in FIG. Division is performed with a plurality of modified layers M as starting points.
  • the wavelength of the laser beam LB2 is, for example, 8800 nm to 11000 nm.
  • the alignment mark 15 has a transmittance of the laser beam LB2 of, for example, 45% or more and 100% or less, preferably 50% or more and 100% or less, and more preferably 60% or more and 100% or less.
  • the alignment mark 15 is made of a material that absorbs infrared rays used for imaging the alignment mark 15 and that transmits the laser beam LB2.
  • the alignment mark 15 includes, for example, a Ge film, a SiGe film, a metal silicide film, or an AlN film.
  • the Ge film or the like absorbs the infrared rays for imaging and transmits the laser beam LB2.
  • the SiO 2 film transmits infrared rays for imaging and absorbs the laser beam LB2.
  • the metal film can absorb infrared rays for imaging, it also absorbs the laser beam LB2. A method of forming the alignment mark 15 will be described later.
  • the chip 2A has a silicon wafer 21A and a device layer 22A.
  • the device layer 22A is formed on the surface of the silicon wafer 21A.
  • the device layer 22A includes semiconductor elements, circuits, terminals, or the like. After forming the device layer 22A, the silicon wafer 21A is singulated into a plurality of chips 2A.
  • the chip 2B like the chip 2A, has a silicon wafer 21B and a device layer 22B.
  • the device layer 22B has a function different from that of the device layer 22A, and has a thickness different from that of the chip 2A and chip 2B.
  • the silicon wafer 21B is singulated into a plurality of chips 2B.
  • the bonding surface 14 of the first substrate 1 is surface-modified by plasma or the like. Specifically, the SiO 2 bond on the joint surface 14 is cut to form a dangling bond of Si, thereby making the joint surface 14 hydrophilic.
  • oxygen gas which is a processing gas
  • the bonding surface 14 is irradiated with oxygen ions to modify the bonding surface 14 .
  • the processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas.
  • the bonding surface 14 of the first substrate 1 may be surface-modified. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is surface-modified.
  • the bonding surface 14 of the first substrate 1 is hydrophilized.
  • the first substrate 1 is held by a spin chuck, and pure water such as DIW (deionized water) is supplied to the bonding surface 14 of the first substrate 1 rotating together with the spin chuck.
  • An OH group is attached to a dangling bond of Si on the bonding surface 14, and the bonding surface 14 is made hydrophilic.
  • the joint surface 14 of the first substrate 1 may be made hydrophilic. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is hydrophilized.
  • the chips 2A and 2B are temporarily bonded to the bonding surface 14 of the first substrate 1 one by one. Chips 2A and 2B are bonded to first substrate 1 with device layers 22A and 22B facing first substrate 1 .
  • the chips 2A and 2B and the first substrate 1 are joined by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. After that, heat treatment may be performed in order to increase the bonding strength.
  • the heat treatment causes a dehydration reaction. Since the solids are directly attached to each other without using a liquid adhesive, it is possible to prevent misalignment due to deformation of the adhesive and inclination due to uneven thickness of the adhesive.
  • the chips 2A and 2B are permanently attached to the third substrate 6 to be described later without taking the step of temporarily bonding the chips 2A and 2B to the first substrate 1. joints effectively. Therefore, at the time of joining, it is required to simultaneously suppress entrapment of air bubbles and foreign matter and to perform position control with high accuracy.
  • the chips 2A and 2B When the chips 2A and 2B are bonded one by one to the third substrate 6 as in Patent Document 1, the chips 2A and 2B should be deformed one by one in order to suppress the entrapment of air bubbles during bonding. .
  • the bonding surfaces 24A and 24B of the chips 2A and 2B are deformed into curved surfaces convex downward, are gradually bonded to the third substrate 6 from the center toward the periphery, and finally return to flat surfaces.
  • Transforming the joint surfaces 24A, 24B of the chips 2A, 2B into curved surfaces that are convex downward includes fixing the respective peripheral edges of the chips 2A, 2B and pressing down the respective centers of the chips 2A, 2B.
  • the individual chips 2A and 2B are small in size, the distance between the fixing point and the pressed point is narrow. Therefore, it is difficult to deform chips 2A and 2B one by one.
  • the chips 2A, 2B are temporarily bonded to the first substrate 1 and separated from the first substrate 1 later. Therefore, even if the chips 2A, 2B and the first substrate 1 are joined together, even if air bubbles get into the chips, there is no problem. Therefore, in S14, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while maintaining the flat surfaces. Since the chips 2A and 2B are not deformed, the accuracy of the position control of the chips 2A and 2B can be improved, and the chips 2A and 2B can be accurately placed at the target positions.
  • the chips 2A and 2B are temporarily bonded to the first substrate 1 and separated from the first substrate 1 later. Therefore, even if particles are caught when chips 2A, 2B and first substrate 1 are joined together, no problem arises. Therefore, the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be dirty to the extent that bonding is not hindered. Requires less cleanliness.
  • the multiple chips 2A and 2B are thinned to have a uniform thickness.
  • the two-dot chain line indicates the state immediately before S2, and the solid line indicates the state upon completion of S2.
  • silicon wafers 21A, 21B are thinned, and device layers 22A, 22B are not thinned. Thinning includes grinding or laser processing.
  • a bonding layer 3 is formed on the surfaces of the chips 2A and 2B.
  • the bonding layer 3 is an insulating layer such as a silicon oxide layer, and is formed by the CVD method or the like. Since the chips 2A and 2B are spaced apart from each other and the base surface of the bonding layer 3 has unevenness, the surface of the bonding layer 3 also has unevenness.
  • the surface of the bonding layer 3 is flattened. Since the bonding layer 3 is a silicon oxide layer or the like and has high hardness, polishing such as CMP (Chemical Mechanical Polishing) takes time for flattening.
  • CMP Chemical Mechanical Polishing
  • the projections 31 of the bonding layer 3 are irradiated with a laser beam LB1.
  • the convex portion 31 absorbs the laser beam LB1, changes its state from a solid phase to a gas phase, and scatters, or scatters while remaining in the solid phase.
  • the laser beam LB ⁇ b>1 may also irradiate the concave portion 32 of the bonding layer 3 . If the irradiation intensity of the concave portions 32 is lower than the irradiation intensity of the convex portions 31, the surface of the bonding layer 3 can be planarized.
  • the irradiation point of the laser beam LB1 is moved by a galvanometer scanner or an XY ⁇ stage.
  • a galvanometer scanner moves the laser beam LB1.
  • the XY ⁇ stage moves the first substrate 1 in the horizontal direction (X-axis direction and Y-axis direction) and rotates it around the vertical axis.
  • An XYZ ⁇ stage may be used instead of the XY ⁇ stage.
  • the surface of the bonding layer 3 is further flattened by CMP or the like. Since the protrusions 31 have been selectively removed before CMP, undulations remaining on the surface of the bonding layer 3 after CMP can be reduced.
  • the chips 2A and 2B and the second substrate 5 are bonded as shown in FIG.
  • the second substrate 5 contacts the planarized surface of the bonding layer 3 and is bonded to the chips 2A and 2B via the bonding layer 3 .
  • the second substrate 5 has a silicon wafer 51 and a bonding layer 53, for example.
  • the bonding layer 53 is an insulating layer such as a silicon oxide layer, and is formed by the CVD method or the like.
  • At least one of the bonding surface 54 of the second substrate 5 and the bonding surface 34 of the bonding layer 3 may be subjected to surface modification and hydrophilization before bonding.
  • the second substrate 5 and the bonding layer 3 are bonded by van der Waals forces (intermolecular forces), hydrogen bonds between OH groups, and the like. Since the solids are directly bonded together without using a liquid adhesive, misalignment due to deformation of the adhesive can be prevented. In addition, it is possible to prevent the occurrence of inclination due to uneven thickness of the adhesive.
  • the second substrate 5 is bonded to the first substrate 1 via the bonding layer 3 with the bonding surface 54 facing downward. That is, the substrates are bonded together. At this time, the bonding surface 54 of the second substrate 5 is deformed into a downwardly convex curved surface in order to prevent air bubbles from entering, and is gradually bonded from the center toward the periphery, and finally returns to a flat surface.
  • the deformation of the second substrate 5 can be realized by fixing the periphery of the second substrate 5 and pressing down the center of the second substrate 5 .
  • the distance between the fixed portion and the depressed portion is wide, so the deformation is easy.
  • the reason why the deformation is easy is that the substrates are bonded to each other.
  • the arrangement of the second substrate 5 and the first substrate 1 may be reversed. good.
  • the bonding surface 54 of the second substrate 5 is deformed into an upwardly convex curved surface in order to prevent air bubbles from entering, and is gradually bonded from the center toward the periphery, and finally returns to a flat surface.
  • the second substrate 5 In order to bond the second substrate 5 and the first substrate 1 gradually from the center toward the periphery, the second substrate 5 is first bent and deformed, but the first substrate 1 is first bent and deformed. good too. Also in this case, the substrates are bonded together. However, from the viewpoint of protecting the chips 2A and 2B, it is preferable to hold the first substrate 1 flat and the chips 2A and 2B flat.
  • the chips 2A and 2B are separated from the first substrate 1 as shown in FIGS.
  • the modified layer M is formed in a dot shape, and is formed, for example, at a condensing point or above the condensing point.
  • the laser beam LB2 passes through the silicon wafer 11 of the first substrate 1 and forms a modified layer M in the absorption layer 12 of the first substrate 1.
  • the absorption layer 12 is arranged between the silicon wafer 11 and the chips 2A, 2B and absorbs the laser beam LB2. Since the laser beam LB2 hardly hits the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed.
  • the laser beam LB2 has a wavelength of, for example, 8800 nm to 11000 nm to pass through the silicon wafer 11 and the alignment marks 15 and be absorbed by the absorption layer 12 .
  • the light source for laser beam LB2 is, for example, a CO 2 laser.
  • the wavelength of CO2 laser is about 9300 nm.
  • the laser beam LB2 is pulse-oscillated.
  • the formation position of the modified layer M is moved by a galvanometer scanner or an XY ⁇ stage.
  • a galvanometer scanner moves the laser beam LB2.
  • the XY ⁇ stage moves the first substrate 1 in the horizontal direction (X-axis direction and Y-axis direction) and rotates it around the vertical axis.
  • An XYZ ⁇ stage may be used instead of the XY ⁇ stage.
  • a plurality of modified layers M are formed at intervals in the circumferential and radial directions of the first substrate 1 .
  • cracks CR connecting the modified layers M are also formed.
  • the first substrate 1 is divided starting from the modified layer M as shown in FIG.
  • the upper chuck 131 holds the first substrate 1 and the lower chuck 132 holds the second substrate 5 .
  • the first substrate 1 and the second substrate 5 may be arranged upside down, and the upper chuck 131 may hold the second substrate 5 and the lower chuck 132 may hold the first substrate 1 .
  • the crack CR spreads in a planar manner starting from the modified layer M, and the first substrate 1 is divided along the dividing plane D.
  • the upper chuck 131 may be rotated around the vertical axis as the upper chuck 131 is lifted.
  • the first substrate 1 can be threaded at the dividing plane D.
  • the downward movement of the lower chuck 132 may be performed.
  • rotation of the lower chuck 132 about the vertical axis may be performed.
  • Residue 16 includes a portion of absorbent layer 12 and bonding layer 13 .
  • device layers 22A, 22B of chips 2A, 2B are again exposed.
  • the device layers 22A and 22B are semiconductor memories, for example.
  • the chips 2A and 2B are bonded to one side 64 of the third substrate 6 including the device layer 62 while being bonded to the second substrate 5, as shown in FIG.
  • a third substrate 6 includes a silicon wafer 61 and a device layer 62 .
  • the device layer 62 is formed on the surface of the silicon wafer 61 .
  • the device layer 62 includes semiconductor elements, circuits, terminals, or the like, and is electrically connected to the device layers 22A, 22B of the chips 2A, 2B.
  • the device layer 62 is, for example, a semiconductor memory peripheral circuit (also called “peripheral”) or a semiconductor memory input/output circuit (also called “IO”).
  • At least one of the bonding surface 64 of the third substrate 6 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be subjected to surface modification and hydrophilization before bonding.
  • the third substrate 6 and the chips 2A and 2B are bonded by van der Waals forces (intermolecular forces), hydrogen bonds between OH groups, and the like. Since the solids are directly bonded together without using a liquid adhesive, misalignment due to deformation of the adhesive can be prevented. In addition, it is possible to prevent the occurrence of inclination due to uneven thickness of the adhesive.
  • the third substrate 6 is bonded to the second substrate 5 via the chips 2A and 2B with the bonding surface 64 facing downward. That is, the substrates are bonded together. At this time, the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface in order to prevent entrainment of air bubbles, gradually bonded from the center toward the periphery, and finally returns to a flat surface.
  • the deformation of the third substrate 6 can be realized by fixing the periphery of the third substrate 6 and pressing down the center of the third substrate 6 .
  • the distance between the fixed portion and the pressed portion is wide, so the deformation is easy.
  • the reason why the deformation is easy is that the substrates are bonded to each other.
  • the third substrate 6 and the second substrate 5 may be reversed, the third substrate 6 may be arranged below the second substrate 5, and the bonding surface 64 of the third substrate 6 may face upward. good.
  • the bonding surface 64 of the third substrate 6 is deformed into an upwardly convex curved surface in order to prevent air bubbles from entering, and is gradually bonded from the center toward the periphery, and finally returns to a flat surface. Also in this case, the substrates are bonded together.
  • the third substrate 6 is first bent and deformed, but the second substrate 5 is first bent and deformed. good too. Also in this case, the substrates are bonded together.
  • a substrate 7 with a chip is obtained by the above S7.
  • the substrate with chips 7 includes a third substrate 6 and a plurality of chips 2A and 2B.
  • the chip-equipped substrate 7 further includes a second substrate 5 .
  • the second substrate 5 may be separated from the chips 2A and 2B, and the chip-attached substrate 7 may include the third substrate 6 and the chips 2A and 2B.
  • the first substrate is first formed. Temporarily join to one side of 1. Since entrapment of air bubbles at this stage does not pose a problem, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 as flat surfaces. Since the chips 2A and 2B do not have to be forcibly deformed, the accuracy of the position control of the chips 2A and 2B can be improved, and the chips 2A and 2B can be accurately placed at the target positions.
  • the plurality of chips 2A and 2B bonded to the first substrate 1 are bonded to the surface of the second substrate 5 facing the first substrate 1. Subsequently, the plurality of chips 2A and 2B bonded to the first substrate 1 and the second substrate 5 are separated from the first substrate 1. Next, as shown in FIG. Next, the plurality of chips 2A and 2B separated from the first substrate 1 are bonded to the single side 64 including the device layer 62 of the third substrate 6 while being bonded to the second substrate 5 .
  • the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface in order to prevent air bubbles from entering, and is gradually bonded from the center toward the periphery, and finally returns to a flat surface.
  • Deforming the third substrate 6 is easier than deforming the chips 2A and 2B one by one. This is because substrates are bonded together. Therefore, compared to the case of permanently bonding the chips 2A and 2B to the third substrate 6 without going through the step of temporarily bonding the chips 2A and 2B to the first substrate 1 as in Patent Document 1, Thus, a chip-equipped substrate 7 can be obtained in which air bubbles are not trapped and the positional accuracy is good.
  • alignment marks 15 are attached to the silicon wafer 11 separated from the chips 2A and 2B. Therefore, when the silicon wafer 11 is reused, the alignment mark 15 can be reused without having to re-form the alignment mark 15 .
  • the silicon wafer 11 separated from the chips 2A, 2B is joined to a chip different from the chips 2A, 2B.
  • the forming method includes first to sixth steps.
  • a silicon wafer 11 is prepared as shown in FIG. 15A.
  • the surface of the silicon wafer 11 is etched to form trenches.
  • the depth of the trench is not particularly limited, it is, for example, 100 nm.
  • a SiO 2 film 17 is formed on the surface of the silicon wafer 11 and the trenches are filled with the SiO 2 film 17 .
  • the SiO 2 film 17 is formed by a CVD method using TEOS (tetraethoxysilane), for example.
  • TEOS tetraethoxysilane
  • the thickness of the SiO 2 film 17 is not particularly limited, it is, for example, 100 nm.
  • the SiO 2 film 17 is flattened by CMP or the like to expose part of the surface of the silicon wafer 11 .
  • the rest of the surface of silicon wafer 11 is covered with SiO 2 film 17 .
  • the thickness of the remaining SiO 2 film 17 is not particularly limited, it is, for example, 100 nm.
  • the exposed surface of the silicon wafer 11 is etched to form trenches between the SiO 2 films 17, as shown in FIG. 15E.
  • the depth of the trench is not particularly limited, it is, for example, 100 nm.
  • the SiGe film 15A is epitaxially grown on the bottom surface of the trench of the silicon wafer 11, and the Ge film 15B is epitaxially grown on the SiGe film 15A.
  • An alignment mark is formed including the SiGe film 15A and the Ge film 15B.
  • the film thickness of the SiGe film 15A is not particularly limited, it is, for example, 20 nm.
  • the film thickness of the Ge film 15B is not particularly limited, it is, for example, 80 nm.
  • Table 1 shows an example of the optical properties of a Ge film with a film thickness of 80 nm.
  • the Ge film with a film thickness of 80 nm has an infrared absorption rate of 59.0% with a wavelength of 1000 nm, and can absorb infrared rays used for imaging.
  • a Ge film with a thickness of 80 nm has a transmittance of 63.0% for a laser beam with a wavelength of 9300 nm, and can transmit the laser beam used for forming the modified layer.
  • the method of forming the SiGe film differs from the method of forming the Ge film shown in FIGS. 15A to 15F except that the Ge film 15B is not epitaxially grown after the SiGe film 15A having a thickness of 100 nm is epitaxially grown in the sixth step. , and so on.
  • An alignment mark including only the SiGe film 15A is formed. The process can be shortened compared to the case where the alignment mark includes the SiGe film 15A and the Ge film 15B. Note that the thickness of the SiGe film 15A is not limited to 100 nm.
  • FIG. 16 shows an example of optical characteristics of a SiGe film with a film thickness of 100 nm.
  • the solid line indicates the optical properties of the SiGe film
  • the dashed line indicates the optical properties of bare silicon.
  • a SiGe film with a thickness of 100 nm has a transmittance of about 48% for a laser beam with a wavelength of 9300 nm, and can transmit the laser beam used for forming the modified layer.
  • the forming method includes first to seventh steps.
  • the first to fourth steps shown in FIGS. 17A to 17D are the same as the first to fourth steps shown in FIGS. 15A to 15D, so descriptions thereof are omitted.
  • a Ni film 18 is formed on the surface of the silicon wafer 11, as shown in FIG. 17E.
  • the Ni film 18 covers not only the exposed surface of the silicon wafer 11 but also the surface of the SiO 2 film 17 .
  • the thickness of the Ni film 18 is not particularly limited, it is, for example, 20 nm.
  • the silicon wafer 11 is heated to react the silicon wafer 11 and the Ni film 18 to form a NiSi 2 film 15C.
  • the heating temperature of the silicon wafer 11 is not particularly limited, but is 500° C., for example.
  • the Ni film 18 is removed by SPM or the like to expose the NiSi 2 film 15C.
  • SPM is an aqueous solution containing sulfuric acid and hydrogen peroxide.
  • the time for etching the Ni film 18 by SPM is, for example, 15 minutes.
  • Alignment marks are formed including the NiSi 2 film 15C.
  • the metal silicide is not limited to NiSi 2 and may be TiSi 2 or CoSi, for example.
  • the film thickness of NiSi 2 is, for example, 20 nm to 40 nm.
  • the film thickness of TiSi 2 is, for example, 50 nm to 80 nm.
  • the film thickness of CoSi is, for example, 30 nm to 50 nm.
  • FIG. 18 shows an example of the absorptance of a TiSi 2 film with a thickness of 210 nm.
  • the TiSi 2 film with a thickness of 210 nm has an absorption rate of about 90% for infrared rays with a wavelength of 1000 nm to 2000 nm, and can absorb infrared rays used for imaging.
  • a TiSi 2 film with a thickness of 210 nm has an absorptance of about 15% for a laser beam with a wavelength of 9300 nm, and can transmit the laser beam used for forming the modified layer.
  • a TiSi 2 film with a thickness of 50 nm to 80 nm has an absorptance of less than about 15% for a laser beam with a wavelength of 9300 nm and can transmit the laser beam used for forming the modified layer.
  • the forming method includes first to seventh steps.
  • the first to fifth steps shown in FIGS. 19A to 19E are the same as the first to fifth steps shown in FIGS. 15A to 15E, so description thereof will be omitted.
  • an AlN film 15D is formed on the surface of the silicon wafer 11 and the trenches are filled with the AlN film 15D.
  • the AlN film 15D is formed by an ALD (Atomic Layer Depression) method using TMA (trimethylsilane), for example.
  • a plasma mixed gas (mixed gas containing Ar gas, H 2 gas, and N 2 gas), Ar gas, TMA gas, and Ar gas are repeatedly supplied in this order. , to form an AlN film.
  • NH groups are formed on the surface of the silicon wafer 11 by supplying the plasmatized mixed gas.
  • the NH groups react with the TMA gas to form an AlN film. Since the AlN film formed by this method exhibits a blue color, it is hereinafter also referred to as a blue AlN film.
  • the blue AlN film contains impurities and exhibits a blue color.
  • the film thickness of the blue AlN film is not particularly limited, it is, for example, 100 nm.
  • the AlN film 15D is planarized by CMP or the like to partially expose the surface of the silicon wafer 11.
  • the rest of the surface of the silicon wafer 11 is covered with an AlN film 15D.
  • the film thickness of the remaining AlN film 15D is not particularly limited, it is, for example, 100 nm.
  • An alignment mark including the AlN film 15D is formed.
  • FIG. 20 shows an example of the transmittance of a blue AlN film with a thickness of 100 nm.
  • a blue AlN film with a thickness of 100 nm has a transmittance of about 60% for infrared rays with a wavelength of 1000 nm, and can absorb infrared rays used for imaging.
  • a blue AlN film has a lower transmittance for infrared rays with a wavelength of 1000 nm than a normal AlN film, and is suitable as an alignment mark.
  • the substrate processing apparatus 100 that performs S61 and S62 in FIG. 3 will be described with reference to FIG. 21 and the like.
  • the X-axis direction, the Y-axis direction and the Z-axis direction are directions perpendicular to each other
  • the X-axis direction and the Y-axis direction are horizontal directions
  • the Z-axis direction is a vertical direction.
  • the substrate processing apparatus 100 has a loading/unloading section 101 , a transport section 110 , a laser processing section 120 , a dividing section 130 and a control section 140 .
  • the loading/unloading section 101 has a mounting section 102 on which the cassette C is mounted.
  • the cassette C accommodates a plurality of laminated substrates 8 shown in FIG. 10 and the like at intervals in the vertical direction.
  • the laminated substrate 8 includes a plurality of chips 2A, 2B, a first substrate 1, and a second substrate 5.
  • the laminated substrate 8 is divided along a dividing plane D into a first divided body 81 and a second divided body 82 . After that, the first divided body 81 and the second divided body 82 are accommodated in the cassette C separately.
  • the first divided body 81 includes the silicon wafer 11 and can be reused as a new first substrate 1 after being carried out of the substrate processing apparatus 100 .
  • the absorption layer 12 or the like may be re-formed on the surface of the silicon wafer 11 .
  • the second divided body 82 includes the chips 2A and 2B, and after being carried out of the substrate processing apparatus 100, is subjected to S63 in FIG. 3, S7 in FIG. 1, and the like. Note that the number of mounting units 102 and the number of cassettes C are not limited to those shown in FIG.
  • the transport unit 110 is arranged next to the carrying-in/out unit 101, the laser processing unit 120, and the dividing unit 130, and transports the laminated substrate 8 and the like to these.
  • the transport section 110 has a holding mechanism that holds the laminated substrate 8 and the like.
  • the retention mechanism is capable of horizontal (both X and Y) and vertical movement, as well as rotation about a vertical axis.
  • the laser processing unit 120 forms a plurality of modified layers M with a laser beam LB2 on the division surface D that is planned to divide the first substrate 1 in the thickness direction.
  • the modified layer M is formed in a dot shape, and is formed, for example, at a condensing point or above the condensing point.
  • the laser processing unit 120 includes, for example, a stage 121 that holds the first substrate 1 and an optical system 122 that irradiates the first substrate 1 held by the stage 121 with a laser beam LB2.
  • the stage 121 is, for example, an XY ⁇ stage or an XYZ ⁇ stage.
  • Optical system 122 includes, for example, a condenser lens. The condensing lens converges the laser beam LB2 toward the first substrate 1 .
  • Optical system 122 may further include a galvanometer scanner.
  • the dividing unit 130 divides the first substrate 1 with the modified layer M as a starting point, as shown in FIG.
  • the dividing section 130 includes, for example, an upper chuck 131 and a lower chuck 132 .
  • the upper chuck 131 holds the first substrate 1 and the lower chuck 132 holds the second substrate 5 .
  • the arrangement of the first substrate 1 and the second substrate 5 may be upside down.
  • the crack CR spreads in a planar manner starting from the modified layer M, and the first substrate 1 is divided along the dividing plane D.
  • FIG. In other words, the laminated substrate 8 is divided along the division plane D into the first divided body 81 and the second divided body 82 .
  • the upper chuck 131 may rotate around the vertical axis.
  • the first substrate 1 can be threaded at the dividing plane D. As shown in FIG.
  • the control unit 140 is, for example, a computer, and as shown in FIG. 21, includes a CPU (Central Processing Unit) 141 and a storage medium 142 such as a memory.
  • the storage medium 142 stores programs for controlling various processes executed in the substrate processing apparatus 100 .
  • the control unit 140 controls the operation of the substrate processing apparatus 100 by causing the CPU 141 to execute programs stored in the storage medium 142 .

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  • Recrystallisation Techniques (AREA)
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  • Mechanical Treatment Of Semiconductor (AREA)
PCT/JP2022/001520 2021-01-29 2022-01-18 チップ付き基板の製造方法、及び基板処理装置 Ceased WO2022163425A1 (ja)

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KR1020237027803A KR20230135615A (ko) 2021-01-29 2022-01-18 칩 포함 기판 제조 방법 및 기판 처리 장치
CN202280010534.5A CN116783684A (zh) 2021-01-29 2022-01-18 附带芯片的基板的制造方法及基板处理装置
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JP2011049210A (ja) * 2009-08-25 2011-03-10 Seiko Epson Corp 薄膜素子群の転写方法
WO2012133760A1 (ja) * 2011-03-30 2012-10-04 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
JP2017041472A (ja) * 2015-08-17 2017-02-23 株式会社ディスコ 貼り合せ基板の加工方法
JP2018125427A (ja) * 2017-02-01 2018-08-09 株式会社ディスコ 加工方法

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JP6043939B2 (ja) * 2012-08-24 2016-12-14 ボンドテック株式会社 基板上への対象物の位置決め方法及び装置
JP2015046569A (ja) 2013-07-31 2015-03-12 マイクロン テクノロジー， インク． 半導体装置の製造方法

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JP2011049210A (ja) * 2009-08-25 2011-03-10 Seiko Epson Corp 薄膜素子群の転写方法
WO2012133760A1 (ja) * 2011-03-30 2012-10-04 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
JP2017041472A (ja) * 2015-08-17 2017-02-23 株式会社ディスコ 貼り合せ基板の加工方法
JP2018125427A (ja) * 2017-02-01 2018-08-09 株式会社ディスコ 加工方法

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