WO2022156147A1 - 显示面板的驱动方法及显示面板 - Google Patents

显示面板的驱动方法及显示面板 Download PDF

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Publication number
WO2022156147A1
WO2022156147A1 PCT/CN2021/101790 CN2021101790W WO2022156147A1 WO 2022156147 A1 WO2022156147 A1 WO 2022156147A1 CN 2021101790 W CN2021101790 W CN 2021101790W WO 2022156147 A1 WO2022156147 A1 WO 2022156147A1
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WIPO (PCT)
Prior art keywords
sub
pixels
row
display panel
reach
Prior art date
Application number
PCT/CN2021/101790
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English (en)
French (fr)
Inventor
刘金风
Original Assignee
Tcl华星光电技术有限公司
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Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/599,565 priority Critical patent/US20240046843A1/en
Publication of WO2022156147A1 publication Critical patent/WO2022156147A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of display technology, and in particular, to a driving method of a display panel and a display panel.
  • a display panel generally includes a display portion for displaying an image and a gate driving module and a source driving module for driving the display portion.
  • the display part includes a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixels, and the plurality of sub-pixels are formed by intersecting the scan lines and the data lines.
  • the gate driving module scans and drives each row of sub-pixels in the display part row by row through scanning lines
  • the source driving module applies gray-scale voltages to each column of sub-pixels through data lines, so that the display panel presents images.
  • the RC load of the data line will also increase, causing a delay in the transmission of the gray-scale voltage signal.
  • the sub-pixel on the side far from the source driver module cannot be fully charged to the target voltage within the same charging time, so that the sub-pixel on the side close to the source driver module and the sub-pixel on the side far from the source driver module cannot be fully charged to the target voltage.
  • There is a deviation in the actual voltage of the pixel which causes the brightness of different areas of the display part to be different, resulting in the problem of uneven brightness of the display panel.
  • the existing display panel has the problem of uneven brightness. Therefore, it is necessary to provide a driving method of a display panel and a display panel to improve this defect.
  • Embodiments of the present application provide a driving method for a display panel and a display panel, which are used to solve the problem of uneven brightness of the existing display panel.
  • An embodiment of the present application provides a method for driving a display panel, and the method for driving a display panel includes:
  • the display panel is scanned row by row according to the scan driving signal corresponding to each row of sub-pixels.
  • the display panel is provided with at least two detection points, the detection points are used to detect the charging time required for a row of sub-pixels corresponding to the detection points to reach a target voltage, and the acquisition of the The steps of charging time required for each row of sub-pixels in the display panel to reach the target voltage include:
  • the charging time required for a row of sub-pixels respectively corresponding to any two adjacent detection points in the at least two detection points to reach the target voltage determine the time required for each row of sub-pixels between the two adjacent detection points to reach the target voltage charging time.
  • the display panel is provided with a first detection point and a second detection point
  • the first detection point is used to detect the charging required for the sub-pixels in the first row of the display panel to reach a target voltage time
  • the second detection point is used to detect the charging time required for the last row of sub-pixels in the display panel to reach the target voltage
  • the display panel is further provided with a third detection point, and the third detection point is used to detect that a row of sub-pixels located between the first row of sub-pixels and the last row of sub-pixels reaches the Charge time required for target voltage.
  • the display panel includes a plurality of scan line groups, and each scan line group includes at least two scan lines.
  • the charging time required for a corresponding row of sub-pixels to reach the target voltage, and the steps of determining the charging time required for each row of sub-pixels between the two adjacent detection points to reach the target voltage include:
  • the charging time required for a row of sub-pixels corresponding to each scan line to reach the target voltage is the same.
  • the step of adjusting the duty cycle of the scan driving signal corresponding to each row of sub-pixels according to the charging time required for each row of sub-pixels to reach the target voltage includes:
  • the duty ratio of the scan driving signal corresponding to each scan line in each scan line group is adjusted in sequence.
  • the high-level duration of the clock signal corresponding to each scan line group is the same as the high-level duration of the scan driving signals corresponding to the sub-pixels in the multiple rows connected thereto.
  • the duty cycle of the clock signal gradually increases, and the duty cycle of the clock signal corresponding to each scan line in the same scan line group than the same.
  • An embodiment of the present application further provides a display panel, the display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixels arranged in an array, and the sub-pixels in the same row of the plurality of sub-pixels are connected to the same Scan lines, sub-pixels located in the same column are connected to the same data line, and the display panel further includes:
  • a detection module configured to obtain the charging time required for each row of sub-pixels in the display panel to reach a target voltage
  • a timing control module for adjusting the duty cycle of the scan drive signal corresponding to each row of sub-pixels according to the charging time required for each row of sub-pixels to reach the target voltage
  • the gate driving module is configured to scan the plurality of sub-pixels row by row according to the scanning driving signal corresponding to each row of sub-pixels.
  • the display panel is provided with at least two detection points, the detection points are used to detect the charging time required for a row of sub-pixels corresponding to the detection points to reach a target voltage, and the detection module includes :
  • a calculation module configured to calculate the sub-pixels in each row between the two adjacent detection points according to the charging time required for a row of sub-pixels corresponding to any two adjacent detection points in the at least two detection points respectively to reach the target voltage The charging time required to reach the target voltage.
  • the display panel is provided with a first detection point and a second detection point
  • the first detection point is used to detect the charging required for the sub-pixels in the first row of the display panel to reach a target voltage time
  • the second detection point is used to detect the charging time required for the last row of sub-pixels in the display panel to reach the target voltage
  • the display panel is further provided with a third detection point, and the third detection point is used to detect that a row of sub-pixels located between the first row of sub-pixels and the last row of sub-pixels reaches the Charge time required for target voltage.
  • the display panel includes a plurality of scan line groups, each scan line group includes at least two scan lines, and each of the scan lines in the same scan line group corresponds to a row respectively
  • the charging time required for the subpixels to reach the target voltage is the same.
  • the high-level duration of the clock signal corresponding to each scan line group is the same as the high-level duration of the scan driving signals corresponding to the sub-pixels in the plurality of rows connected thereto.
  • the calculation module may be further configured to charge time required for a row of sub-pixels corresponding to any two adjacent detection points in the at least two detection points to reach the target voltage and the phase
  • the number of the scan line groups between the two adjacent detection points is obtained by linearly dividing the number of the sub-pixels corresponding to each of the scan line groups between the two adjacent detection points. Charge time required for target voltage.
  • the timing control module includes an adjustment module, and the adjustment module is configured to adjust each of the sub-pixels corresponding to each scan line group according to the charging time required for the sub-pixels to reach a target voltage.
  • the duty cycle of the clock signal corresponding to the scan line group is configured to adjust each of the sub-pixels corresponding to each scan line group according to the charging time required for the sub-pixels to reach a target voltage.
  • the duty cycle of the clock signal increases gradually, and the clocks corresponding to each of the scan lines in the same scan line group
  • the duty cycles of the signals are the same.
  • the embodiments of the present application provide a method for driving a display panel and a display panel, and the method for driving a display panel obtains the charging time required for each row of sub-pixels in the display panel to reach a target voltage, Then, according to the charging time required for each row of sub-pixels to reach the target voltage, the duty cycle of the scan drive signal corresponding to each row of sub-pixels is adjusted, and then the display panel is performed row by row according to the scan drive signal corresponding to each row of sub-pixels.
  • the sub-pixels at each position of the display panel can reach the same target voltage, thereby improving the problem of uneven brightness of the display panel.
  • FIG. 1 is a schematic flowchart of a method for driving a display panel provided by an embodiment of the present application
  • Fig. 2 is the detection schematic diagram provided by the embodiment of this application.
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a gate driving unit provided by an embodiment of the present application.
  • FIG. 6 is a first timing diagram of a method for driving a display panel provided by an embodiment of the present application.
  • FIG. 7 is a second timing diagram of a method for driving a display panel provided by an embodiment of the present application.
  • FIG. 8 is a timing diagram of a clock signal provided by an embodiment of the present application.
  • An embodiment of the present application provides a driving method for a display panel, which will be described in detail below with reference to FIG. 1 .
  • FIG. 1 is a schematic flowchart of a method for driving a display panel according to an embodiment of the present application.
  • the method for driving a display panel includes:
  • Step S10 Obtain the charging time required for each row of sub-pixels in the display panel to reach the target voltage.
  • the display panel is provided with at least two detection points, the detection points are used to detect the charging time required for a row of sub-pixels corresponding to the detection points to reach a target voltage, and the acquisition of the display
  • the steps of charging time required for each row of sub-pixels in the panel to reach the target voltage include:
  • Step S101 obtaining the charging time required for a row of sub-pixels corresponding to each of the at least two detection points to reach a target voltage
  • Step S102 According to the charging time required for a row of sub-pixels corresponding to any two adjacent detection points in the at least two detection points to reach the target voltage, determine that each row of sub-pixels between the two adjacent detection points reaches the target voltage Voltage required for charging time.
  • the charging time required to detect that a row of sub-pixels reaches the target voltage needs to be calculated from the time when the row of sub-pixels starts scanning until the voltage of the row of sub-pixels reaches the target voltage.
  • the detection point may be an actual detection point or a virtual detection point.
  • an external detection device can be used to detect the at least two detection points to obtain the charging time required for a row of sub-pixels corresponding to the detection points to reach the target voltage.
  • the detection module can also be built in the display panel, and each detection point is connected to the detection module through a signal line, so as to obtain the charging time required for a row of sub-pixels corresponding to each detection point to reach the target voltage.
  • the display panel includes a display portion 10 , a source driving module 11 located on one side of the display portion, and a source driving module 11 located on the other side of the display portion.
  • the gate driving module on the side (not shown in the figure), the display part 10 is provided with a plurality of sub-pixels arranged in an array, and the source driving module 11 is connected to the display part 10 through a plurality of data lines 111 , each data line 111 is connected to a column of sub-pixels, each row of sub-pixels is connected to a gate line, the gate driving module is connected to the display part through a plurality of scan lines, and each scan line is connected to a row of sub-pixels .
  • the display panel is provided with a first detection point a1 and a second detection point a2, and the first detection point a1 is set on the side of the display portion 10 close to the source driving module 11 , used to detect the charging time required for the first row of sub-pixels to reach the target voltage, the second detection point a2 is set on the side of the display part 10 away from the source driver module 11, used to detect the last row of sub-pixels The charging time required for the pixel to reach the target voltage.
  • the display panel is provided with a first detection point a1, a second detection point a2 and a third detection point a3, and the third detection point a3 is arranged on the first detection point a3.
  • the middle of the detection point a1 and the second detection point a2 is used to detect the charging time required for a row of sub-pixels located between the first row of sub-pixels and the last row of sub-pixels to reach a target voltage.
  • the number of detection points is not limited to 2 or 3 in the embodiments of the present application, but may also be more than 3.
  • the number of detection points and the positions of detection points set on the display panel can be limited according to the actual situation, which is not limited here.
  • FIG. 3 is a timing diagram of each detection point provided by the embodiment of the application.
  • the scanning drive signal Gate-Far of the last row of sub-pixels and the corresponding clock signal GCLK maintain the same high level time , and maintains the high level for the longest time; the scanning drive signal Gate-Mid of the middle row of sub-pixels and the corresponding clock signal GCLK maintain the high level for the same time, and the time for maintaining the high level is second; the first The scanning drive signal Gate-Near of the row sub-pixel is kept high for the same time as the corresponding clock signal GCLK, and the time of keeping the high level is the smallest.
  • the waveform below the signal GCLK is the scanning drive signal in the actual test process.
  • the time that the clock signal GCLK remains at a high level should be in an increasing state as shown on the left side of FIG. 1 . , so that the sub-pixels of each part of the display panel can reach the target voltage within the specified charging time.
  • the display panel includes a plurality of scan line groups, and each scan line group includes at least two scan lines, and according to the at least two detection points, any two adjacent detection points correspond to
  • the step of determining the charging time required for each row of sub-pixels to reach the target voltage between the two adjacent detection points includes: according to any phase of the at least two detection points
  • the charging time required for a row of sub-pixels corresponding to two adjacent detection points to reach the target voltage and the number of scanning line groups between the adjacent two detection points are obtained by linearly dividing the two adjacent detection points.
  • the charging time required for the subpixels corresponding to each scan line group to reach the target voltage; wherein, in the same scan line group, the charging time required for the subpixels in a row corresponding to each scan line to reach the target voltage is the same.
  • the m ⁇ n scan lines are divided into m scan line groups, and each scan line group includes n scan lines. line, where m and n are both positive integers and ⁇ 2.
  • the first scan line group includes n scan lines arranged at intervals in sequence, which are respectively used to transmit corresponding scan driving signals (G1, G2...Gn), and the second scan line group includes sequentially and at intervals.
  • the n scan lines are used to transmit the corresponding scan drive signals (G(n+1), G(n+2) ...G2n), and so on, the m-th scan line group includes n scan lines, which are respectively used to transmit corresponding scan drive signals (G(mn-n+1), G(mn-n+2) ... Gmn).
  • Step S20 according to the charging time required for each row of sub-pixels to reach the target voltage, adjust the duty ratio of the scan driving signal corresponding to each row of sub-pixels.
  • the step of adjusting the duty cycle of the scan driving signal corresponding to each row of sub-pixels according to the charging time required for each row of sub-pixels to reach the target voltage includes:
  • Step S201 Adjust the duty cycle of the clock signal corresponding to each scan line group according to the charging time required for the sub-pixel corresponding to each scan line group to reach the target voltage;
  • Step S202 According to the clock signal corresponding to each scan line group, sequentially adjust the duty ratio of the scan driving signal corresponding to each scan line in each scan line group.
  • the display panel includes a timing control module 13 and a level shift module 14.
  • the timing control module 13 is used to generate the first initial signal CLK1, the second initial signal CLK2 and the frame start signal. STV, and output to the level shift module 14 , the level shift module 14 is used for boosting the received signal, and outputs the generated first clock signal CK and second clock signal XCK to the gate driving module 12 .
  • the gate driving module 12 includes m ⁇ n cascaded gate driving units, each gate driving unit corresponds to a scan line, and the phases of the first clock signal CK and the second clock signal CK2 are opposite, and are used to act on odd numbers in turn.
  • the gate driving units corresponding to the scanning lines of the row or even-numbered rows are used to generate the above-mentioned scanning driving signals (G1, G2, .
  • FIG. 5 is a schematic structural diagram of a gate driving unit provided by an embodiment of the present application.
  • a pull-up control module 121 a pull-up module 122 , a pull-down module 123 , a pull-down module
  • the maintenance module 124 and the bootstrap capacitor Cgb the pull-up control module 121 is connected to the (n-1)th stage scan driving signal G(n-1), and is connected to the first node Q(n) of the nth stage gate driving unit ;
  • the pull-up module 122 is connected to the first clock signal CK or the second clock signal XCK, and is connected to the first node Q(n), and the pull-up module 122 is used to control the potential of the first node Q(n).
  • the pull-down module 123 accesses the (n+1) level scan driving signal G(n+1) and the reference low-level signal Vss, and connected to the output terminal of the nth-level scan driving signal G(n);
  • the pull-down maintaining module 124 is respectively connected to the first node Q(n) and the output terminal of the nth-level scan driving signal G(n), and is connected to the reference low Level signal Vss; one end of the bootstrap capacitor Cgb is connected to the first node, and the other end is connected to the output end of the nth-stage scan drive signal G(n).
  • the pull-up control module 121 includes a first thin film transistor T11
  • the pull-up module 122 includes a second thin film transistor T21
  • the pull-down module 123 includes a third thin film transistor T31
  • the pull-down maintaining module 124 includes a fourth thin film transistor T41.
  • FIG. 6 is the first timing diagram of the driving method of the display panel provided by the embodiment of the present application, and the left side is the timing diagram corresponding to the first scan line group.
  • the charging time required for the sub-pixels corresponding to each scan line group to reach the target voltage is T1.
  • the first clock signal CK and the second The time that the clock signal XCK is kept at a high level is T1, and the phases of the first clock signal CK and the second clock signal CK2 are opposite, and are used to act on the gate driving units corresponding to the scan lines of the odd or even rows in turn, so as to Each scan driving signal ( G1 , G2 .
  • the right side of FIG. 5 is the timing diagram corresponding to the second scan line group. According to the measured charging time required for the sub-pixels corresponding to the second scan line group to reach the target voltage, T2 is required. In the process of adjusting the duty cycle of the corresponding scan driving signal, the time that the first clock signal CK and the second clock signal XCK are kept at a high level is adjusted to T2, and the time period of the first clock signal CK and the second clock signal CK2 is adjusted to T2.
  • the phases are opposite, and are used to act on the gate driving units corresponding to the scan lines of odd or even rows in turn to generate each scan drive signal (G(n+1), G(n+2) in the second scan line group )...G2n), and the (n+1)th scan drive signal G1 to 2nth scan drive signal Gn maintains a high level for all time T2. And so on, until the duty ratio of the scan driving signal corresponding to the m th scan line group is adjusted, so that the time for which the scan drive signal corresponding to the m th scan line group remains at a high level is Tm. It can be seen that the high-level duration of the clock signal corresponding to each scan line group is the same as the high-level duration of the scan drive signals corresponding to the sub-pixels in the multiple rows connected thereto.
  • FIG. 7 is a second timing diagram of the driving method of the display panel provided by the embodiment of the application.
  • four clock signals are provided, which are the first clock signal CK1 and the second clock signal respectively.
  • Signal CK2, the third clock signal CK3, the fourth clock signal CK4, the four clock signals (CK1 ⁇ CK4) take turns to the (4b-3), (4b-2), (4b-1) and 4b stage gates respectively
  • the pole driving unit performs control to generate a corresponding scan driving signal, where (1 ⁇ b ⁇ mn/4).
  • the left side of FIG. 6 is the timing diagram corresponding to the first scan line group.
  • the first clock signal CK1 to the fourth clock signal CK4 remain high
  • the time of the high level is all T1
  • the time when the first scan driving signal G1 to the nth scan driving signal Gn maintains the high level is also T1.
  • the right side of FIG. 6 is the timing diagram corresponding to the second scan line group.
  • the first clock signal CK1 to the fourth clock signal CK4 remain high.
  • the time of the level is T2, and the time of the (n+1)th scan drive signal G(n+1) to the 2nth scan drive signal G2n is also kept at a high level of T2.
  • the number of clock signals may also be 6 or 8, which can also achieve the same technical effect as the above-mentioned embodiment, which is not repeated here.
  • the number of clock signals can be limited according to the actual situation, which is not limited here.
  • the duty ratios of the clock signals corresponding to the n scan lines in the first scan line group are all the same, and the second scan line group has the same duty cycle.
  • the duty ratios of the clock signals corresponding to the n scan lines in the scan line group are the same, and the duty cycles of the clock signals corresponding to the n scan lines in the third scan line group are also the same, and so on, the mth scan line group has the same duty cycle.
  • the duty cycles of the clock signals corresponding to the n scan lines in the group are also the same, and the duty cycles of the clock signals gradually increase from the first scan line group to the m th scan line group.
  • the duty cycles of the clock signals corresponding to the scan lines in the same scan line group are the same. From the first scan line group to the last scan line group, the duty cycle of the clock signal gradually increases to This makes the duty cycle of the gate driving signal corresponding to the scan line group gradually increase from the side of the display portion 10 close to the source driving module 11 to the side far from the source driving module 11 in each frame, m
  • the scan driving signals corresponding to the scan line groups have m duty ratios that increase gradually, so that the charging time of the sub-pixels on the side farther from the source driving module 11 is longer than the charging time of the sub-pixels on the side close to the source driving module 11 , thereby ensuring that all sub-pixels of the display panel can reach the target voltage within the same effective charging time.
  • the process of adjusting the duty cycle of the clock signal corresponding to the scan line group through the detected charging time can be completed by the timing control module 13 built into the display panel, or it can be manually
  • the detected charging time adjusts the duty cycle of the clock signal.
  • Step S30 Scan the display panel line by line according to the scan driving signal corresponding to each line of sub-pixels.
  • FIG. 4 is a schematic structural diagram of the display panel provided by the embodiment of the present application.
  • the scan driving signals (G1 ⁇ Gmn) sequentially perform scanning and driving of each scan line in each scan line group row by row, and the source driving module 11 applies gray-scale voltage to each column of sub-pixels through the data line, so that the display panel presents an image .
  • the display panel includes a display part 10, and the display part 10 includes a plurality of scan lines, a plurality of data lines and a plurality of sub-pixels (not shown in the figure). out), the sub-pixels located in the same row of the plurality of sub-pixels are connected to the same scan line, and the sub-pixels located in the same column are connected to the same data line, and the display panel further includes:
  • a detection module configured to obtain the charging time required for each row of sub-pixels in the display panel to reach a target voltage
  • the timing control module 13 is configured to adjust the duty cycle of the scan drive signal corresponding to each row of sub-pixels according to the charging time required for each row of sub-pixels to reach the target voltage;
  • the gate driving module 12 is configured to scan the plurality of sub-pixels row by row according to the scan driving signal corresponding to each row of sub-pixels.
  • the display panel is provided with at least two detection points, the detection points are used to detect the charging time required for a row of sub-pixels corresponding to the detection points to reach the target voltage, and the detection module includes:
  • a calculation module configured to calculate the sub-pixels in each row between the two adjacent detection points according to the charging time required for a row of sub-pixels corresponding to any two adjacent detection points in the at least two detection points respectively to reach the target voltage The charging time required to reach the target voltage.
  • the detection module is connected to the at least two detection points to receive signals returned by the detection points.
  • the display panel includes a first detection point a1 and a second detection point a2, the first detection point a1 is disposed on the side of the display part 10 close to the source driving module 11, In order to detect the charging time required for the sub-pixels in the first row to reach the target voltage, the second detection point a2 is set on the side of the display part 10 away from the source driving module 11 for detecting that the sub-pixels in the last row reach the target voltage. Charge time required for target voltage.
  • the display panel is provided with a first detection point a1, a second detection point a2 and a third detection point a3, and the third detection point a3 is arranged on the first detection point a3.
  • the middle of the detection point a1 and the second detection point a2 is used to detect the charging time required for a row of sub-pixels located between the first row of sub-pixels and the last row of sub-pixels to reach a target voltage.
  • the number of detection points is not limited to 2 or 3 in the embodiments of the present application, but may also be more than 3.
  • the number of detection points and the positions of detection points set on the display panel can be limited according to the actual situation, which is not limited here.
  • the display panel includes a plurality of scan line groups, each scan line group includes at least two scan lines, and the detection module can also be used to correspond to any two adjacent detection points according to the at least two detection points.
  • the charging time required for a row of sub-pixels to reach the target voltage and the number of scan line groups between the two adjacent detection points are linearly divided to obtain each scan line group between the two adjacent detection points.
  • the charging time required for the corresponding sub-pixels to reach the target voltage; wherein, in the same scan line group, the charging time required for a row of sub-pixels corresponding to each scan line to reach the target voltage is the same.
  • the timing control module 13 includes an adjustment module configured to adjust the duty cycle of the clock signal corresponding to each scan line group according to the charging time required for the sub-pixels corresponding to each scan line group to reach the target voltage.
  • the timing control module 13 outputs the adjusted clock signal to the gate driving module 12, and the gate driving module 12 can sequentially adjust the clock signals in each scan line group according to the clock signal corresponding to each scan line group.
  • the duty ratio of the scan drive signal corresponding to the scan line is adjusted, and the adjusted scan drive signal is output to the display part 10 .
  • the embodiments of the present application provide a driving method for a display panel and a display panel.
  • the driving method for the display panel obtains the charging time required for each row of sub-pixels in the display panel to reach a target voltage, and then calculates the charging time according to the The charging time required for each row of sub-pixels to reach the target voltage, adjust the duty cycle of the scan drive signal corresponding to each row of sub-pixels, and then perform line-by-line scan on the display panel according to the scan drive signal corresponding to each row of sub-pixels, Therefore, by adjusting the charging time of the sub-pixels at different positions of the display panel, the sub-pixels at each position of the display panel can reach the same target voltage, thereby improving the problem of uneven brightness of the display panel.

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Abstract

本申请提供一种显示面板的驱动方法及显示面板，该显示面板的驱动方法通过获取显示面板中每一行子像素达到目标电压所需的充电时间，再根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比，使得显示面板各个位置的子像素都能够达到相同的目标电压，从而改善显示面板亮度不均的问题。

Description

显示面板的驱动方法及显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板的驱动方法及显示面板。
 背景技术
显示面板通常包括用于显示图像的显示部分用于驱动显示部分的栅极驱动模块和源极驱动模块。显示部分包括多条扫描线、多条数据线以及多个子像素，该多个子像素由扫描线和数据线交叉限定形成。栅极驱动模块通过扫描线对显示部分的各行子像素进行逐行扫描驱动，源极驱动模块通过数据线对各列子像素施加灰阶电压，从而使显示面板呈现图像。
 技术问题
随着显示面板的尺寸逐渐增大，数据线的阻容负载也会增大，使得灰阶电压信号的传输存在延迟，具体表现为靠近源极驱动模块一侧的子像素可以在指定的充电时间内充满至目标电压，远离源极驱动模块一侧的子像素无法在相同的充电时间内充满至目标电压，从而使得靠近源极驱动模块一侧的子像素与远离源极驱动模块一侧的子像素的实际电压存在偏差，造成显示部分不同区域的亮度不同，导致显示面板出现亮度不均的问题。
综上，现有显示面板存在亮度不均的问题。故，有必要提供一种显示面板的驱动方法及显示面板来改善这一缺陷。
 技术解决方案
本申请实施例提供一种显示面板的驱动方法及显示面板，用于解决现有显示面板存在的亮度不均的问题。
本申请实施例提供一种显示面板的驱动方法，所述显示面板的驱动方法包括：
获取所述显示面板中每一行子像素达到目标电压所需的充电时间；
根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比；以及
根据每一行子像素对应的扫描驱动信号，对所述显示面板进行逐行扫描。
根据本申请一实施例，所述显示面板上设有至少两个检测点，所述检测点用于检测与该检测点对应的一行子像素达到目标电压所需的充电时间，所述获取所述显示面板中每一行子像素达到目标电压所需的充电时间的步骤包括：
获取所述至少两个检测点中各个检测点分别对应的一行子像素达到目标电压所需的充电时间；
根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间，确定该相邻两个检测点之间每一行子像素达到目标电压所需的充电时间。
根据本申请一实施例，所述显示面板上设有第一检测点和第二检测点，所述第一检测点用于检测所述显示面板中第一行子像素达到目标电压所需的充电时间，所述第二检测点用于检测所述显示面板中最后一行子像素达到目标电压所需的充电时间。
根据本申请一实施例，所述显示面板上还设有第三检测点，所述第三检测点用于检测位于所述第一行子像素和所述最后一行子像素中间的一行子像素达到目标电压所需的充电时间。
根据本申请一实施例，所述显示面板包括多个扫描线组，每一个扫描线组内包括至少两条扫描线，所述根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间，确定该相邻两个检测点之间每一行子像素达到目标电压所需的充电时间的步骤包括：
根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间以及该相邻两个检测点之间扫描线组的数量，通过线性等分的方式，得到该相邻两个检测点之间每一个扫描线组对应的子像素达到目标电压所需的充电时间；
其中，同一个扫描线组内，各条扫描线分别对应的一行子像素达到目标电压所需的充电时间相同。
根据本申请一实施例，所述根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比的步骤包括：
根据每一个扫描线组对应的子像素达到目标电压所需的充电时间，调整每一个扫描线组对应的时钟信号的占空比；
根据每一个扫描线组对应的时钟信号，依次对每个扫描线组中的各条扫描线对应的扫描驱动信号的占空比进行调整。
根据本申请一实施例，每一个扫描线组对应的时钟信号的高电平持续时间和与其连接的多行子像素对应的扫描驱动信号的高电平持续时间相同。
根据本申请一实施例，由第一个扫描线组至最后一个扫描线组，所述时钟信号的占空比渐次递增，位于同一扫描线组内的各条扫描线对应的时钟信号的占空比相同。
本申请实施例还提供一种显示面板，所述显示面板包括多条扫描线、多条数据线和阵列排布的多个子像素，所述多个子像素中位于同一行的子像素连接于同一条扫描线，位于同一列的子像素连接于同一条数据线，所述显示面板还包括：
检测模块，用于获取所述显示面板中每一行子像素达到目标电压所需的充电时间；
时序控制模块，用于根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比；
栅极驱动模块，用于根据每一行子像素对应的扫描驱动信号，对所述多个子像素进行逐行扫描。
根据本申请一实施例，所述显示面板上设有至少两个检测点，所述检测点用于检测与该检测点对应的一行子像素达到目标电压所需的充电时间，所述检测模块包括：
计算模块，用于根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间，计算该相邻两个检测点之间每一行子像素达到目标电压所需的充电时间。
根据本申请一实施例，所述显示面板上设有第一检测点和第二检测点，所述第一检测点用于检测所述显示面板中第一行子像素达到目标电压所需的充电时间，所述第二检测点用于检测所述显示面板中最后一行子像素达到目标电压所需的充电时间。
根据本申请一实施例，所述显示面板上还设有第三检测点，所述第三检测点用于检测位于所述第一行子像素和所述最后一行子像素中间的一行子像素达到目标电压所需的充电时间。
根据本申请一实施例，所述显示面板包括多个扫描线组，每一个扫描线组内包括至少两条扫描线，同一个所述扫描线组中的各条所述扫描线分别对应的一行子像素达到目标电压所需的充电时间相同。
根据本申请一实施例，每一个所述扫描线组对应的时钟信号的高电平持续时间和与其连接的多行所述子像素对应的所述扫描驱动信号的高电平持续时间相同。
根据本申请一实施例，所述计算模块还可以用于根据至少两个所述检测点中任意相邻两个所述检测点分别对应的一行子像素达到目标电压所需的充电时间以及该相邻两个所述检测点之间所述扫描线组的数量，通过线性等分的方式，得到该相邻两个所述检测点之间每一个所述扫描线组对应的所述子像素达到目标电压所需的充电时间。
根据本申请一实施例，所述时序控制模块包括调整模块，所述调整模块用于根据每一个所述扫描线组对应的所述子像素达到目标电压所需的充电时间，调整每一个所述扫描线组对应的时钟信号的占空比。
根据本申请一实施例，由第一个扫描线组至最后一个扫描线组，所述时钟信号的占空比渐次递增，位于同一所述扫描线组内的各条所述扫描线对应的时钟信号的占空比相同。
 有益效果
本揭示实施例的有益效果：本申请实施例提供一种显示面板的驱动方法及显示面板，该显示面板的驱动方法通过获取所述显示面板中每一行子像素达到目标电压所需的充电时间，再根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比，然后根据每一行子像素对应的扫描驱动信号，对所述显示面板进行逐行扫描，从而通过调整显示面板不同位置子像素的充电时间，使得显示面板各个位置的子像素都能够达到相同的目标电压，从而改善显示面板亮度不均的问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的驱动方法的流程示意图；
图2为本申请实施例提供的检测示意图；
图3为本申请实施例提供的各个检测点的时序图；
图4为本申请实施例提供的显示面板的结构示意图；
图5为本申请实施例提供的栅极驱动单元的结构示意图；
图6为本申请实施例提供的显示面板的驱动方法的第一种时序图；
图7为本申请实施例提供的显示面板的驱动方法的第二种时序图；
图8为本申请实施例提供的时钟信号的时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本申请实施例提供一种显示面板的驱动方法，下面结合图1进行详细说明。
如图1所示，图1为本申请实施例提供的显示面板的驱动方法的流程示意图，所述显示面板的驱动方法包括：
步骤S10：获取所述显示面板中每一行子像素达到目标电压所需的充电时间。
在一实施例中，所述显示面板上设有至少两个检测点，所述检测点用于检测与该检测点对应的一行子像素达到目标电压所需的充电时间，所述获取所述显示面板中每一行子像素达到目标电压所需的充电时间的步骤包括：
步骤S101：获取所述至少两个检测点中各个检测点分别对应的一行子像素达到目标电压所需的充电时间；
步骤S102：根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间，确定该相邻两个检测点之间每一行子像素达到目标电压所需的充电时间。
可以理解的是，检测一行子像素达到目标电压所需的充电时间，需要从该行子像素开启扫描的时间开始计算，直至该行子像素的电压达到目标电压。本实施例中，所述检测点可以为实际检测点，也可以为虚拟的检测点。此外，本实施例中可以使用外置的检测装置通过对所述至少两个检测点进行检测，以获得与该检测点对应的一行子像素达到目标电压所需的充电时间，在其他一些实施例中，也可以将检测模块内置于显示面板中，通过信号线将各检测点与该检测模块连接，用于获取各检测点对应的一行子像素达到目标电压所需的充电时间。
在一实施例中，如图2所示，图2为本申请实施例提供的检测示意图，所述显示面板包括显示部分10和位于显示部分一侧的源极驱动模块11和位于显示部分另一侧的栅极驱动模块（图中未示出），所述显示部分10内设有阵列排布的多个子像素，所述源极驱动模块11通过多条数据线111与所述显示部分10连接，每一条数据线111与一列子像素连接，每一行子像素与一条栅极线连接，所述栅极驱动模块通过多条扫描线与所述显示部分连接，每一条扫描线与一行子像素连接。在本实施例中，所述显示面板内设有第一检测点a1和第二检测点a2，所述第一检测点a1设置于所述显示部分10靠近所述源极驱动模块11的一侧，用于检测第一行子像素达到目标电压所需的充电时间，所述第二检测点a2设置于所述显示部分10远离所述源极驱动模块11的一侧，用于检测最后一行子像素达到目标电压所需的充电时间。
在一实施例中，如图2所示，所述显示面板上设有第一检测点a1、第二检测点a2和第三检测点a3，所述第三检测点a3设置于所述第一检测点a1和第二检测点a2的中间，用于检测位于所述第一行子像素和所述最后一行子像素中间的一行子像素达到目标电压所需的充电时间。当然，在一些实施例中，检测点的数量不仅限于本申请实施例中的2个或3个，也可以为3个以上。显示面板上设置检测点的数量以及检测点的位置可以根据实际情况进行限定，此处不做限制。
以图2所示的显示面板为例，通过对第一检测点a1、第二检测点a2和第三检测点a3分别对应的一行子像素进行检测，通过图2中左侧的波形示意图可以看出，最靠近源极驱动模块11的第一行子像素达到目标电压所需的时间t1最下，位于中间的一行子像素达到目标电压所需的时间t3次之，与所述源极驱动模块11距离最远的最后一行子像素达到目标电压所需的充电时间t2最大。如图3所示，图3为本申请实施例提供的各个检测点的时序图，检测过程中，最后一行子像素的扫描驱动信号Gate-Far与对应的时钟信号GCLK保持高电平的时间相同，且保持高电平的时间最长；位于中间的一行子像素的扫描驱动信号Gate-Mid与对应的时钟信号GCLK保持高电平的时间相同，且保持高电平的时间次之；第一行子像素的扫描驱动信号Gate-Near与对应的时钟信号GCLK保持高电平的时间相同，且保持高电平的时间最小，始终信号GCLK下方的波形曲线则为实际测试过程中的扫描驱动信号的波形，即所述显示部分10中沿靠近源极驱动模块11的一端至远离源极驱动模块11的一端，时钟信号GCLK保持高电平的时间应呈如图1左侧所示的递增状态，才能使显示面板各部分的子像素均能够在指定的充电时间内达到目标电压。
在一实施例中，所述显示面板包括多个扫描线组，每一个扫描线组内包括至少两条扫描线，所述根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间，确定该相邻两个检测点之间每一行子像素达到目标电压所需的充电时间的步骤包括：根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间以及该相邻两个检测点之间扫描线组的数量，通过线性等分的方式，得到该相邻两个检测点之间每一个扫描线组对应的子像素达到目标电压所需的充电时间；其中，同一个扫描线组内，各条扫描线分别对应的一行子像素达到目标电压所需的充电时间相同。
以图4所示的显示面板为例，所述显示面板内设有m×n条扫描线，该m×n条扫描线分为m个扫描线组，每个扫描线组内包括n条扫描线，其中m、n均为正整数，且≥2。如图4所示，第一个扫描线组包括依次间隔排列的n条扫描线，分别用于传递对应的扫描驱动信号（G1、G2……Gn），第二个扫描线组包括依次间隔排列的n条扫描线，分别用于传递对应的扫描驱动信号（G(n+1)、G(n+2) ……G2n），以此类推，第m个扫描线组包括n条扫描线，分别用于传递对应的扫描驱动信号（G(mn-n+1)、G(mn-n+2) ……Gmn）。
以m=10，n=6为例，即显示面板内设有10个扫描线组，每个扫描线组内包括6条扫描线，当检测到图2中t1=1.3s，t3=1.8s，t2=2.2s时，依据线性等分的方式，任意相邻两个扫描线组之间充电时间的差值相同，第一检测点a1与第三检测点a3之间含有6个扫描线组，第二检测点a2与第三检测点a3之间含有4个扫描线组，即第一个扫描线组至第十个扫描线组对应的充电时间T1~T10依次为：1.3s、1.4s、1.5s、1.6s、1.7s、1.8s、1.9s、2.0s、2.1s、2.2s，其中第一个扫描线组内各条扫描线对应的一行子像素达到目标电压所需的充电时间均为1.3s，第二个扫描线组内各条扫描线分别对应的一行子像素达到目标电压所需的充电时间均为1.4s，以此类推，第10个扫描线组内各条扫描线分别对应的一行子像素达到目标电压所需的充电时间均为2.2s。
步骤S20：根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比。
在一实施例中，所述根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比的步骤包括：
步骤S201：根据每一个扫描线组对应的子像素达到目标电压所需的充电时间，调整每一个扫描线组对应的时钟信号的占空比；
步骤S202：根据每一个扫描线组对应的时钟信号，依次对每个扫描线组中的各条扫描线对应的扫描驱动信号的占空比进行调整。
以图4所示的显示面板为例，显示面板包括时序控制模块13和电平转移模块14，时序控制模块13用于生成第一初始始终信号CLK1、第二初始始终信号CLK2和帧起始信号STV，并输出至电平转移模块14，电平转移模块14用于对接收到的信号进行升压操作，并将生成的第一时钟信号CK和第二时钟信号XCK输出至栅极驱动模块12。栅极驱动模块12包括m×n个级联的栅极驱动单元，每一个栅极驱动单元对应一条扫描线，第一时钟信号CK和第二时钟信号CK2的相位相反，用于轮流作用于奇数行或偶数行的扫描线对应的栅极驱动单元，以生成上述扫描驱动信号（G1、G2……Gmn），从而对显示面板进行逐行扫描驱动。
如图5所述，图5为本申请实施例提供的栅极驱动单元的结构示意图，以第n级栅极驱动单元为例，上拉控制模块121、上拉模块122、下拉模块123、下拉维持模块124和自举电容Cgb，上拉控制模块121接入第(n-1)级扫描驱动信号G(n-1)，并连接第n级栅极驱动单元的第一节点Q(n)；上拉模块122接入第一时钟信号CK或第二时钟信号XCK，并连接所述第一节点Q(n)，上拉模块122用于在所述第一节点Q(n)的电位控制下上拉栅极驱动模块12的第n级扫描驱动信号G(n)；下拉模块123接入第(n+1)级扫描驱动信号G(n+1)以及参考低电平信号Vss，并与第n级扫描驱动信号G(n)的输出端连接；下拉维持模块124分别与第一节点Q(n)和第n级扫描驱动信号G(n)的输出端连接，并接入参考低电平信号Vss；自举电容Cgb的一端与第一节点连接，另一端与第n级扫描驱动信号G(n)的输出端连接。
具体的，上拉控制模块121包括第一薄膜晶体管T11，上拉模块122包括第二薄膜晶体管T21，下拉模块123包括第三薄膜晶体管T31，下拉维持模块124包括第四薄膜晶体管T41。
进一步的，如图6所示，图6为本申请实施例提供的显示面板的驱动方法的第一种时序图，左侧为第一个扫描线组对应的时序图，依据测得的第一个扫描线组对应的子像素达到目标电压所需的充电时间为T1，在对第一个扫描线组对应的扫描驱动信号的占空比进行调整的过程中，第一时钟信号CK和第二时钟信号XCK的保持高电平的时间均为T1，第一时钟信号CK和第二时钟信号CK2的相位相反，用于轮流作用于奇数行或偶数行的扫描线对应的栅极驱动单元，以生成第一个扫描线组内的各个扫描驱动信号（G1、G2……Gn），且第一扫描驱动信号G1至第n扫描驱动信号Gn保持高电平的时间也均为T1。图5中右侧为第二个扫描线组对应的时序图，依据测得的第二个扫描线组对应的子像素达到目标电压所需的充电时间为T2，在对第二个扫描线组对应的扫描驱动信号的占空比进行调整的过程中，第一时钟信号CK和第二时钟信号XCK的保持高电平的时间均调整为T2，第一时钟信号CK和第二时钟信号CK2的相位相反，用于轮流作用于奇数行或偶数行的扫描线对应的栅极驱动单元，以生成第二个扫描线组内的各个扫描驱动信号（G(n+1)、G(n+2)……G2n），且第（n+1）扫描驱动信号G1至第2n扫描驱动信号Gn保持高电平的时间也均为T2。以此类推，直至对第m个扫描线组对应的扫描驱动信号的占空比进行调整，使得第m个扫描线组对应的扫描驱动信号保持高电平的时间为Tm。由此可见，每一个扫描线组对应的时钟信号的高电平持续时间和与其连接的多行子像素对应的扫描驱动信号的高电平持续时间相同。
当然，在一些实施例中，时钟信号的数量不仅限于上述实施例的两个。如图7所示，图7为本申请实施例提供的显示面板的驱动方法的第二种时序图，本实施例中，提供了4个时钟信号，分别为第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4，该4个时钟信号（CK1~CK4）分别轮流对第（4b-3）、（4b-2）、（4b-1）和4b级栅极驱动单元进行控制，以生成对应的扫描驱动信号，其中（1≤b≤mn/4）。图6中左侧为第一个扫描线组对应的时序图，在对第一个扫描对应的扫描驱动信号的占空比进行调整的过程中第一时钟信号CK1至第四时钟信号CK4保持高电平的时间均为T1，第一扫描驱动信号G1至第n扫描驱动信号Gn保持高电平的时间也均为T1。图6中右侧为第二个扫描线组对应的时序图，在对第二个扫描对应的扫描驱动信号的占空比进行调整的过程中第一时钟信号CK1至第四时钟信号CK4保持高电平的时间均为T2，第(n+1)扫描驱动信号G(n+1)至第2n扫描驱动信号G2n保持高电平的时间也均为T2。在其他一些实施例中，时钟信号的数量还可以为6个或者8个，其同样能够实现与上述实施例相同的技术效果，此处不做赘述。时钟信号的数量可以根据实际情况进行限定，此处不做限制。
如图8所示，图8为本申请实施例提供的时钟信号的时序图，第一组扫描线组内的n条扫描线对应的时钟信号的占空比均相同，第二组扫描线组内的n条扫描线对应的时钟信号的占空比均相同，第三组扫描线组内的n条扫描线对应的时钟信号的占空比也均相同，以此类推，第m组扫描线组内的n条扫描线对应的时钟信号的占空比也均相同，且由第一组扫描线组至第m组扫描线组，时钟信号的占空比渐次递增。由此可知，位于同一个扫描线组内的各条扫描线对应的时钟信号的占空比相同，由第一个扫描线组至最后一个扫描线组，时钟信号的占空比渐次递增，以此使得每一帧画面内，由显示部分10靠近源极驱动模块11的一侧至远离源极驱动模块11的一侧，扫描线组对应的栅极驱动信号的占空比逐渐增大，m个扫描线组对应的扫描驱动信号具有渐次递增的m种占空比，从而使得远离源极驱动模块11一侧的子像素的充电时间大于靠近源极驱动模块11一侧的子像素的充电时间，进而保证显示面板各部分子像素均能够在相同的有效充电时间达到目标电压。
需要说明的是，通过检测得到的充电时间对扫描线组对应的时钟信号的占空比进行调整的过程可以通过内置于显示面板内部的时序控制模块13完成，或者也可以人为的通过外部设备根据检测得到的充电时间对时钟信号的占空比进行调整。
步骤S30：根据每一行子像素对应的扫描驱动信号，对所述显示面板进行逐行扫描。
以图4所示的显示面板为例，图4为本申请实施例提供的显示面板的结构示意图，栅极驱动模块12在接收的第一时钟信号CK和第二时钟信号XCK的控制下，生成扫描驱动信号（G1~Gmn），依次对各个扫描线组内的各条扫描线进行逐行扫描驱动，源极驱动模块11通过数据线对各列子像素施加灰阶电压，从而使显示面板呈现图像。
本申请实施例还提供一种显示面板，如图4所示，所述显示面板包括显示部分10，所述显示部分10包括多条扫描线、多条数据线和多个子像素（图中未示出），所述多个子像素中位于同一行的子像素连接于同一条扫描线，位于同一列的子像素连接于同一条数据线，所述显示面板还包括：
检测模块，用于获取所述显示面板中每一行子像素达到目标电压所需的充电时间；
时序控制模块13，用于根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比；
栅极驱动模块12，用于根据每一行子像素对应的扫描驱动信号，对所述多个子像素进行逐行扫描。
所述显示面板上设有至少两个检测点，所述检测点用于检测与该检测点对应的一行子像素达到目标电压所需的充电时间，所述检测模块包括：
计算模块，用于根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间，计算该相邻两个检测点之间每一行子像素达到目标电压所需的充电时间。所述检测模块与所述至少两个检测点连接，以接收该检测点返回的信号。
在一实施例中，所述显示面板包括第一检测点a1和第二检测点a2，所述第一检测点a1设置于所述显示部分10靠近所述源极驱动模块11的一侧，用于检测第一行子像素达到目标电压所需的充电时间，所述第二检测点a2设置于所述显示部分10远离所述源极驱动模块11的一侧，用于检测最后一行子像素达到目标电压所需的充电时间。
在一实施例中，如图2所示，所述显示面板上设有第一检测点a1、第二检测点a2和第三检测点a3，所述第三检测点a3设置于所述第一检测点a1和第二检测点a2的中间，用于检测位于所述第一行子像素和所述最后一行子像素中间的一行子像素达到目标电压所需的充电时间。当然，在一些实施例中，检测点的数量不仅限于本申请实施例中的2个或3个，也可以为3个以上。显示面板上设置检测点的数量以及检测点的位置可以根据实际情况进行限定，此处不做限制。
所述显示面板包括多个扫描线组，每一个扫描线组内包括至少两条扫描线，所述检测模块还可以用于根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间以及该相邻两个检测点之间扫描线组的数量，通过线性等分的方式，得到该相邻两个检测点之间每一个扫描线组对应的子像素达到目标电压所需的充电时间；其中，同一个扫描线组内，各条扫描线分别对应的一行子像素达到目标电压所需的充电时间相同。
所述时序控制模块13包括调整模块，所述调整模块用于根据每一个扫描线组对应的子像素达到目标电压所需的充电时间，调整每一个扫描线组对应的时钟信号的占空比。所述时序控制模块13将所述调整后的时钟信号输出至栅极驱动模块12，栅极驱动模块12可以根据每一个扫描线组对应的时钟信号，依次对每个扫描线组中的各条扫描线对应的扫描驱动信号的占空比进行调整，并将调整后的扫描驱动信号输出至显示部分10。
综上所述，本申请实施例提供一种显示面板的驱动方法及显示面板，所述显示面板的驱动方法通过获取所述显示面板中每一行子像素达到目标电压所需的充电时间，再根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比，然后根据每一行子像素对应的扫描驱动信号，对所述显示面板进行逐行扫描，从而通过调整显示面板不同位置子像素的充电时间，使得显示面板各个位置的子像素都能够达到相同的目标电压，从而改善显示面板亮度不均的问题。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (17)

  1. 一种显示面板的驱动方法，所述显示面板的驱动方法包括：
    获取所述显示面板中每一行子像素达到目标电压所需的充电时间；
    根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比；以及
    根据每一行子像素对应的扫描驱动信号，对所述显示面板进行逐行扫描。
  2. 如权利要求1所述的显示面板的驱动方法，其中，所述显示面板上设有至少两个检测点，所述检测点用于检测与该检测点对应的一行子像素达到目标电压所需的充电时间，所述获取所述显示面板中每一行子像素达到目标电压所需的充电时间的步骤包括：
    获取所述至少两个检测点中各个检测点分别对应的一行子像素达到目标电压所需的充电时间；
    根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间，确定该相邻两个检测点之间每一行子像素达到目标电压所需的充电时间。
  3. 如权利要求2所述的显示面板的驱动方法，其中，所述显示面板上设有第一检测点和第二检测点，所述第一检测点用于检测所述显示面板中第一行子像素达到目标电压所需的充电时间，所述第二检测点用于检测所述显示面板中最后一行子像素达到目标电压所需的充电时间。
  4. 如权利要求3所述的显示面板的驱动方法，其中，所述显示面板上还设有第三检测点，所述第三检测点用于检测位于所述第一行子像素和所述最后一行子像素中间的一行子像素达到目标电压所需的充电时间。
  5. 如权利要求2所述的显示面板的驱动方法，其中，所述显示面板包括多个扫描线组，每一个扫描线组内包括至少两条扫描线，所述根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间，确定该相邻两个检测点之间每一行子像素达到目标电压所需的充电时间的步骤包括：
    根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间以及该相邻两个检测点之间扫描线组的数量，通过线性等分的方式，得到该相邻两个检测点之间每一个扫描线组对应的子像素达到目标电压所需的充电时间；
    其中，同一个扫描线组内，各条扫描线分别对应的一行子像素达到目标电压所需的充电时间相同。
  6. 如权利要求4所述的显示面板的驱动方法，其中，所述根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比的步骤包括：
    根据每一个扫描线组对应的子像素达到目标电压所需的充电时间，调整每一个扫描线组对应的时钟信号的占空比；
    根据每一个扫描线组对应的时钟信号，依次对每个扫描线组中的各条扫描线对应的扫描驱动信号的占空比进行调整。
  7. 如权利要求6所述的显示面板的驱动方法，其中，每一个扫描线组对应的时钟信号的高电平持续时间和与其连接的多行子像素对应的扫描驱动信号的高电平持续时间相同。
  8. 如权利要求6所述的显示面板的驱动方法，其中，由第一个扫描线组至最后一个扫描线组，所述时钟信号的占空比渐次递增，位于同一扫描线组内的各条扫描线对应的时钟信号的占空比相同。
  9. 一种显示面板，所述显示面板包括多条扫描线、多条数据线和阵列排布的多个子像素，所述多个子像素中位于同一行的子像素连接于同一条扫描线，位于同一列的子像素连接于同一条数据线，所述显示面板还包括：
    检测模块，用于获取所述显示面板中每一行子像素达到目标电压所需的充电时间；
    时序控制模块，用于根据每一行子像素达到目标电压所需的充电时间，调整每一行子像素对应的扫描驱动信号的占空比；
    栅极驱动模块，用于根据每一行子像素对应的扫描驱动信号，对所述多个子像素进行逐行扫描。
  10. 如权利要求9所述的显示面板，其中，所述显示面板上设有至少两个检测点，所述检测点用于检测与该检测点对应的一行子像素达到目标电压所需的充电时间，所述检测模块包括：
    计算模块，用于根据所述至少两个检测点中任意相邻两个检测点分别对应的一行子像素达到目标电压所需的充电时间，计算该相邻两个检测点之间每一行子像素达到目标电压所需的充电时间。
  11. 如权利要求10所述的显示面板，其中，所述显示面板上设有第一检测点和第二检测点，所述第一检测点用于检测所述显示面板中第一行子像素达到目标电压所需的充电时间，所述第二检测点用于检测所述显示面板中最后一行子像素达到目标电压所需的充电时间。
  12. 如权利要求11所述的显示面板，其中，所述显示面板上还设有第三检测点，所述第三检测点用于检测位于所述第一行子像素和所述最后一行子像素中间的一行子像素达到目标电压所需的充电时间。
  13. 如权利要求11所述的显示面板，其中，所述显示面板包括多个扫描线组，每一个扫描线组内包括至少两条扫描线，同一个所述扫描线组中的各条所述扫描线分别对应的一行子像素达到目标电压所需的充电时间相同。
  14. 如权利要求13所述的显示面板，其中，每一个所述扫描线组对应的时钟信号的高电平持续时间和与其连接的多行所述子像素对应的所述扫描驱动信号的高电平持续时间相同。
  15. 如权利要求13所述的显示面板，其中，所述计算模块还可以用于根据至少两个所述检测点中任意相邻两个所述检测点分别对应的一行子像素达到目标电压所需的充电时间以及该相邻两个所述检测点之间所述扫描线组的数量，通过线性等分的方式，得到该相邻两个所述检测点之间每一个所述扫描线组对应的所述子像素达到目标电压所需的充电时间。
  16. 如权利要求15所述的显示面板，其中，所述时序控制模块包括调整模块，所述调整模块用于根据每一个所述扫描线组对应的所述子像素达到目标电压所需的充电时间，调整每一个所述扫描线组对应的时钟信号的占空比。
  17. 如权利要求16所述的显示面板，其中，由第一个扫描线组至最后一个扫描线组，所述时钟信号的占空比渐次递增，位于同一所述扫描线组内的各条所述扫描线对应的时钟信号的占空比相同。
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