WO2022152032A1 - 测试电路、测试方法和包括测试电路的计算系统 - Google Patents

测试电路、测试方法和包括测试电路的计算系统 Download PDF

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WO2022152032A1
WO2022152032A1 PCT/CN2022/070473 CN2022070473W WO2022152032A1 WO 2022152032 A1 WO2022152032 A1 WO 2022152032A1 CN 2022070473 W CN2022070473 W CN 2022070473W WO 2022152032 A1 WO2022152032 A1 WO 2022152032A1
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clock
tested
paths
clock signal
test circuit
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PCT/CN2022/070473
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English (en)
French (fr)
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陈默
范志军
刘建波
许超
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深圳比特微电子科技有限公司
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Priority to US18/268,517 priority Critical patent/US20240036113A1/en
Priority to KR1020237027506A priority patent/KR20230131255A/ko
Publication of WO2022152032A1 publication Critical patent/WO2022152032A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G01R31/31726—Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/318525—Test of flip-flops or latches
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/31853—Test of registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders

Definitions

  • the present disclosure relates to test circuits, test methods, and computing systems including test circuits.
  • the design of mining machine processors usually adopts a pipeline structure.
  • the operation logic is divided into several stages of pipelines, and each stage of pipelines has similar functional design and operation structure.
  • Each stage of the pipeline needs to input a working clock, that is, a pulse clock.
  • the optimization design of flip-flops is one of the core directions to improve the performance of bitcoin chips and reduce power consumption.
  • different flip-flops will be used according to their own conditions.
  • the direction of the clock tree and the internal structure of the clock tree that connect the multi-stage pipelines at the same time depend on experience and analysis to choose.
  • the clock tree structure selected by the chip is usually conservative and not necessarily optimal.
  • test circuits including test circuits.
  • a test circuit comprising: a test sequence providing module for providing a test sequence to a sequential device to be tested; a clock driving module for providing a clock signal to the sequential device to be tested , which includes a first clock drive circuit, the first clock drive circuit includes: a plurality of first clock paths, respectively providing corresponding clock signals; and a logic unit, based on the clock signals provided by the plurality of first clock paths. At least a part of the first clock signal with pulse width adjustment is generated for the sequential device to be tested; and a verification module is used to verify the output of the sequential device to be tested.
  • the verification module includes a reference sequential device, the test sequence is provided to the reference sequential device and the sequential device to be tested synchronously, and the first clock drive circuit further provides a second a clock signal to the reference sequential device; and a comparison module that compares the output of the reference sequential device with the output of the sequential device to be tested.
  • the plurality of first clock paths receive a common clock input and respectively provide clock signals of different phases based on the clock input.
  • At least one of the first clock paths further includes: a first selector for selecting a clock signal from clock signals provided by a plurality of sub-paths of the corresponding first clock path, and providing the selected clock signal to the logic unit.
  • the clock driving module further comprises a second clock driving circuit, wherein the second clock driving circuit comprises: a plurality of second clock paths, which respectively provide clock signals of different phases, the plurality of first clock paths At least one of the two clock paths provides a clock signal based on the first clock signal; and a second selector selects a clock signal from the clock signals provided by the plurality of second clock paths for the test to be tested timing device.
  • the second clock driving circuit comprises: a plurality of second clock paths, which respectively provide clock signals of different phases, the plurality of first clock paths At least one of the two clock paths provides a clock signal based on the first clock signal; and a second selector selects a clock signal from the clock signals provided by the plurality of second clock paths for the test to be tested timing device.
  • the clock driving module further includes a third clock driving circuit, wherein the third clock driving circuit includes: a plurality of third clock paths, which respectively provide clock signals of different phases; and a third selector , for selecting a clock signal from the clock signals provided by the plurality of third clock paths for at least one of the plurality of first clock paths.
  • the plurality of first clock paths include at least a first path and a second path, the first path providing the selected clock signal to the logic unit, and the second path providing an An inverted version or an inverted and delayed version of the selected clock signal to the logic unit.
  • the second path includes: an inverter that receives the selected clock signal and generates a clock signal that is inverted to the selected clock signal; one or more sub-paths for respectively providing respective versions of the inverted clock signal to a fourth selector; and the fourth selector selecting from the different versions of the inverted clock signal and providing the selected version to the logic unit.
  • the one or more sub-paths each provide differently delayed versions of the inverted clock signal to the fourth selector.
  • the logic unit is an AND gate or an OR gate.
  • the test sequence providing module provides a test sequence with a check code to the to-be-tested sequential device
  • the test circuit further includes a check module that uses the check code for the to-be-tested device. The output of the tested sequential device is verified.
  • the sequential devices are flip-flops or latches.
  • the test circuit further includes additional sequential devices associated with the sequential device to be tested.
  • test circuit being the test circuit according to any embodiment of the present disclosure, the method comprising: providing different configurations through the clock driving module providing a test sequence to the input of the sequential device to be tested; and detecting whether the output of the sequential device to be tested meets the requirements under each configured clock signal.
  • the method further includes: determining a corresponding clock configuration or a range of clock configurations that meets the requirements; determining a predetermined range of timing parameters designed for the sequential device to be tested and the satisfying requirements determined through testing and modify the circuit design of the sequential device to be tested and/or the process parameters for preparing the sequential device to be tested according to the difference.
  • FIG. 1 shows a schematic diagram of an exemplary pipeline
  • FIG. 2A shows a schematic diagram of an exemplary circuit including a sequential device-sequential device path
  • Figure 2B shows a timing diagram for the settling time of the circuit shown in Figure 2A;
  • Figure 2C shows a timing diagram for hold times for the circuit shown in Figure 2A;
  • Figure 2D shows a schematic timing diagram of a pipelined forward clock tree
  • Figure 2E shows a schematic timing diagram of a pipelined reverse clock tree
  • FIG. 3A shows a schematic diagram of a test circuit according to one embodiment of the present disclosure
  • 3B shows a schematic diagram of a test circuit according to another embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of a test circuit according to yet another embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of a test circuit according to yet another embodiment of the present disclosure
  • FIG. 6 shows a schematic diagram of a test circuit according to another embodiment of the present disclosure.
  • FIG. 7 shows a schematic diagram of a test circuit according to yet another embodiment of the present disclosure.
  • FIG. 8 shows a schematic diagram of a test circuit according to one embodiment of the present disclosure.
  • Pipeline technology is a quasi-parallel processing implementation technology in which multiple instructions overlap and operate during program execution.
  • the pipeline stage of a processor often has one or more sequential devices, such as flip-flops. Choosing to use latches as sequential devices in the pipeline can effectively reduce power consumption and area overhead, and improve the competitiveness of mining machine products.
  • each sequential device will have a corresponding clock to control.
  • FIG. 1 shows a schematic diagram for an exemplary pipelined processor.
  • the pipeline in the processor can include multiple pipeline stages, and the working clock of each pipeline stage usually comes from the same clock source, which is passed between the various stages of the pipeline through the clock driving circuits for each stage of the pipeline, as shown in Figure 1. Show.
  • Pipelining technology can be applied to processors in the field of digital currency.
  • Bitcoin uses the hash SHA256 algorithm.
  • the SHA256 algorithm can be divided into several pipeline computing units to form an operation pipeline.
  • the usual pipeline can be divided into 32 stages, 64 stages, 128 stages and so on.
  • sampling is generally only performed on the rising or falling edge of the clock.
  • the design tool will perform static timing analysis on the synthesis results to determine whether the relative relationship between clock and data meets the requirements.
  • the following is an example of a circuit that includes a sequential device-sequential device and a path between them.
  • 2A shows a schematic diagram of an exemplary circuit including sequential device-to-sequential device paths.
  • This diagram is a common circuit diagram for digital system design.
  • it is necessary to ensure that data can be correctly transmitted between the two flip-flops, thereby determining the range of the transmission delay of the intermediate combinational logic circuit Comb.
  • FIG. 2B shows a timing diagram for the settling time for the circuit shown in Figure 2A.
  • D1 represents the input to the preceding flip-flop (referred to as a launch flip-flop) in FIG. 2A.
  • the trigger trigger in FIG. 2A collects the D1 signal, a high level is input to the trigger, and reaches the combinational logic circuit Comb after the trigger output delay Tco.
  • Tcomb of the combinational logic circuit Comb here, it is assumed that the combinational logic circuit does not change the level of the signal at this time, so it can be considered as a buffer
  • the signal on the D2 data line must satisfy the stability time > the setup time Tsu of the flip-flop,
  • the hold time is described.
  • a timing diagram for explaining the hold time of the circuit shown in FIG. 2A is shown in FIG. 2C , and each signal thereof is the same as that shown in FIG. 2B .
  • the previous trigger trigger captures the low level on D1, which is expressed on Q1 after the delay of Tco.
  • This low level reaches D2 after the combinational circuit delay Tcomb.
  • the stabilization time of the original high level on D2 after the arrival of the rising edge of the second clock needs to be greater than the holding time Th of the second flip-flop.
  • the subsequent flip-flops can stably receive the high level originally transmitted by D1. which is,
  • the premise of the normal operation of the synchronous sequential circuit is that both the setup time and the hold time of the flip-flop are satisfied.
  • the hold time is the more important indicator that must be met. If the hold time is not met, the chip may not work properly.
  • each sequential device will have a corresponding clock to control.
  • All sequential devices cannot be controlled by the same clock (the load capacity of the clock is not enough), and an inverter (inv) or a buffer (buffer, abbreviated as buf) is required to transmit the clock signal.
  • inv inverter
  • buf buffer
  • FIG. 2D shows the delay time of the clock driving circuit (Tclk delay time, which is represented by Tclklatency here).
  • Tclk can be smaller and the cycle is smaller, the frequency of the chip can be faster and achieve higher performance. But the forward clock tree has a disadvantage, the hold time is not easy to satisfy.
  • FIG. 2E shows the delay of the clock driving circuit (Tclk delay, which is represented by Tclklatency here).
  • Tclk becomes larger, the period is larger, the frequency of the chip becomes slower, and the performance decreases.
  • the advantage of the inverted clock tree is that the flip-flop hold times are easier to satisfy.
  • the clocks between adjacent pipelines need to meet certain phase requirements to meet latch-specific timing requirements, such as latch hold timing requirements and latch minimum
  • latch-specific timing requirements such as latch hold timing requirements and latch minimum
  • FIG. 3A shows a schematic diagram of a test circuit according to one embodiment of the present disclosure.
  • the test circuit 300 is used to test the sequential device 303 to be tested.
  • the sequential devices to be tested may include (but are not limited to) any device that needs to be clocked, such as registers, flip-flops, or latches.
  • the sequential device to be tested is shown as a multi-bit flip-flop (MBFF).
  • MBFF multi-bit flip-flop
  • the test circuit 300 further includes a clock driving module 307 for providing a clock signal to the sequential device to be tested.
  • the test circuit 300 further includes a verification module 305 for verifying the output of the sequential device to be tested.
  • the test circuit 300 ′ may also include other timing devices, such as the timing devices upstream and downstream of the timing device 303 to be tested.
  • Devices 309 and 311 One or more of sequential devices 309 and 311 may be included in the same pipeline stage 350 along with sequential device 303 to be tested.
  • FIG. 4 shows a schematic diagram of a test circuit according to yet another embodiment of the present disclosure.
  • the test circuit 400 includes a test sequence providing module 301 for providing a test sequence to the sequential device 303 to be tested.
  • the test sequence may include, for example, a pseudo-random bit sequence (PRBS) or a pseudo-random bit sequence including a check code.
  • PRBS pseudo-random bit sequence
  • FIG. 4 shows an additional intermediate sequential device 309, shown as MBFF (indicated by MBFF1), while the sequential device under test 303 is shown as MBFF (indicated by MBFF2).
  • the clock signal is used for the sequential device to be tested
  • the clock signal can be directly used (for example, directly provided to) the sequential device to be tested, or the clock
  • the signals may be used indirectly (eg, indirectly rather than directly provided) to the sequential device under test.
  • an intermediate module or device may exist between the clock signal and the sequential device to be tested, and the intermediate module or device may provide a clock to the sequential device to be tested based on the clock signal.
  • only two clock paths are shown here, it should be understood that more clock paths may be provided.
  • clock paths 421 and 423 may receive a common clock input and provide clock signals of various phases based on the clock input, respectively.
  • the clock path 421 in the figure has 4 phase adjustment units 425 (eg, inverters (as shown) or buffers, etc.), thereby providing a delay of 4 units relative to the incoming clock.
  • the clock path 423 provides no additional delay.
  • the delay of the passive line itself is not considered, but only the delay brought by the device or unit.
  • each clock path may or may not have a phase adjustment unit, or may have more or fewer phase adjustment units.
  • the respective phase adjustment units may be the same or different, or may be configured together or individually.
  • the reference timing device 411 may have the same circuit structure or the same circuit design as the timing device to be tested, but the reference timing device 411 may be based on the standard cell library, IP provided by the manufacturer or design manufacturer or a third party Prepared by library or craft corner.
  • the present disclosure is not limited thereto.
  • a so-called reference timing device may also be custom-made, or empirically designed or fabricated, as long as it can be used as a reference.
  • the second clock signal can be obtained from any part of any first clock path, or from a clock input or other source, as long as a subsequent comparison module can compare the output of the reference sequential device with the output of the sequential device to be tested.
  • the comparison module 413 can compare the output of the reference timing device and the output of the timing device to be tested based on certain criteria, for example, whether the output of the reference timing device and the output of the timing device to be tested are synchronized, consistent or meet timing requirements, or Whether the logical value corresponds, and so on. Thus, the result of the test is determined by the comparison module 413 .
  • the clock driving module 407 may also include an additional phase adjustment unit, such as the phase adjustment unit 429 shown in FIG. 4 .
  • the phase adjustment unit 429 is shown as an inverter 429 downstream of the logic unit 427; but it should be understood that this is only exemplary and not limiting; the type, location, number of said additional phase adjustment units All are not limited to this.
  • inverter 429 may be eliminated and additional inverters may be added in clock paths 421 and 423, respectively.
  • the intermediate device 309 may be in the same or a different pipeline stage than the sequential device 303 to be tested.
  • the reference device 411 may be in the same pipeline stage as the sequential device 303 to be tested.
  • the sequential device 303 to be tested may be located outside the pipeline stage, eg, outside the pipeline stage where the intermediate device 309 or 311 or the reference device 411 is located, eg, at a location Can be adjacent to the pipeline stage. In this case, the device under test will not participate in the actual instruction operations of the pipeline. Thus, the effects of devices and test operations on the pipeline stage can be tested, and the effects on the pipeline can be minimized while increasing the convenience of testing.
  • the selector 529 may be the multiplexer MUX0, but the present disclosure is not limited thereto.
  • the selector 529 may select from the plurality of sub-paths 525 and 527 , etc. based on the control signal Se10 to provide the clock signal on the selected path to the logic unit 427 .
  • the clock signal for the device under test can be flexibly configured, thereby providing flexibility and convenience for testing.
  • FIG. 6 shows a schematic diagram of a test circuit according to another embodiment of the present disclosure.
  • the test circuit 600 shown in FIG. 6 is basically the same as the test circuit 500 shown above except for the clock driving module 607 .
  • the same components as those shown in the previous figures are denoted by the same reference numerals; and the description of the same components will not be repeated here.
  • each second clock path may be provided with one or more phase adjustment units, such as inverters or buffers, or some paths may not be provided with a phase adjustment unit.
  • path 621 has one inverter and path 623 has three inverters.
  • the second clock driving circuit 620 may further include a selector (second selector) 625 for selecting a clock signal from the clock signals provided by the plurality of second clock paths for the sequential device to be tested.
  • the selector 625 may select a clock signal from the clock signals provided by the plurality of second clock paths based on the control signal Sel1.
  • the selector 625 is shown as the multiplexer MUX1, although the present disclosure is not limited thereto.
  • the clock signal used for the device under test can be configured more flexibly, and clock signals with different delays and phases are provided, thereby providing flexibility and convenience for testing.
  • FIG. 7 shows a schematic diagram of a test circuit according to yet another embodiment of the present disclosure.
  • the test circuit 700 shown in FIG. 7 is basically the same as the test circuit shown above except for the clock driving module 707 .
  • the same components as those shown in the previous figures are denoted by the same reference numerals; and the description of the same components will not be repeated here.
  • the clock driving module 707 used for the test circuit 700 will be described in detail below.
  • the clock driving module 707 may include a clock driving circuit (first clock driving circuit) 710 and a clock driving circuit (third clock driving circuit) 750 .
  • the clock drive circuit 710 is configured to adjust the pulse width of the clock signal and to provide the pulse width adjusted clock signal for the sequential device under test (eg, the sequential device 303 in the figure).
  • the clock driver circuit 710 may also include the clock driver circuit described in the previous embodiments, but instead use the clock output of the clock driver circuit 750 as its clock input.
  • clock path 751 has one buffer (assuming delay ⁇ ) and an inverter (for inverting), and clock path 753 has two buffers (assuming delay ⁇ respectively) and an inverter (for performing inversion) Inverted), thereby delaying the input clock differently, thereby providing an inverted and delayed version of the clock signal by ⁇ and a version of the clock signal inverted and delayed by 2 ⁇ , respectively.
  • a clock path in which the conditioning unit 755 is not provided may also be provided.
  • the selection signal (signal 0) can be used to determine which clock signal is used as the output clock to meet the timing requirements of the sequential device to be tested, such as latch hold timing and minimum clock pulse width requirements.
  • clocks with different delays on clock paths 751 and 753 arrive at the two input terminals of MUX0.
  • the selection signal 0 can be set as required to select one of the two clock paths as the clock output to transmit to the current sequential device to be tested and/or the clock drive circuit of the next stage of the pipeline.
  • the clock phases in the adjacent two-stage pipelines can be adjusted separately (each with two (or more) different delays), so as to better meet the timing requirements of the latches in the sequential devices to be tested.
  • the clock driving circuit 710 may include multiple clock paths (also referred to as fourth clock paths) 711 , 713 , etc., which respectively provide clock signals of different phases to the logic unit 715 .
  • the plurality of fourth clock paths may receive clock signals 759 from clock drive circuitry 750 and provide clock signals of different phases to logic unit 715 on the respective fourth clock paths based on the received clock signals .
  • the clock drive circuit 710 may also include a logic unit 715 .
  • the logic unit 715 may generate a pulse width adjusted clock signal for the sequential device 303 to be tested based on at least a part of the clock signals of different phases.
  • the logic unit 715 may be an AND gate or an OR gate; the present disclosure is not limited thereto.
  • the plurality of fourth clock paths may include at least a first path and a second path.
  • the first path 711 may be configured to provide the clock input 759 directly to the logic unit 715 .
  • the second path 713 may be configured to provide a further conditioned version (eg, an inverted version or an inverted and delayed version) to the logic unit 715 based on the received clock input 759 .
  • the second path 713 may include an inverter 717 .
  • Inverter 717 receives a clock input (eg, an input clock or a clock output from an intermediate circuit) 759 and generates a clock signal that is inverted from this clock input 759 .
  • the second path 713 may also include one or more sub-paths, such as the sub-paths 719 and 721 shown in the figure.
  • Sub-paths 719 and 721 provide respective versions of the inverted clock signal to selector (also referred to as a fourth selector in some cases) 723, respectively.
  • selector also referred to as a fourth selector in some cases
  • a selector MUX1 723 selects from the different versions of the inverted clock signal and provides the selected version to the logic unit.
  • MUX1 can select an appropriate clock path delay to meet the pulse width requirements of the sequential device (eg, latch) to be tested.
  • the clock provided to the sequential device under test may be clocked through a logic unit (eg, an OR gate or an AND gate) by the clock output signal of the driver circuit 750 and the inverted clock of different versions of the clock output signal. logic) generated. Since the sequential device to be tested can be located in the corresponding pipeline stage, the pulse width of the clock provided to the sequential device to be tested at this stage can be determined by the inversion of the output signal of the clock driver circuit 750 of the pipeline at this stage and its selected version The phase of the clock (ie, the delay time of this version of the inverted clock relative to the clock output signal) determines.
  • a logic unit eg, an OR gate or an AND gate
  • the selector MUX1 can select one of the two (may be more) sub-clock paths as one of the inputs of the logic unit 715 according to the selection signal 1, and the other input of the logic unit 715 is the clock output of the clock drive circuit of the pipeline of this stage Signal. In this way, the output signal of the logic unit 715 is used as a clock signal for the pipeline of this stage (especially the latch device therein), so that the duty cycle width can be adjusted.
  • the test circuit 800 includes a test sequence providing module 801 for providing a test sequence to the sequential device 303 to be tested.
  • the test sequence may include, for example, a pseudo-random bit sequence (PRBS) or a pseudo-random bit sequence including a check code.
  • PRBS pseudo-random bit sequence
  • the test circuit 800 further includes a clock driving module 807 for providing a clock signal to the timing device to be tested.
  • the test circuit 800 further includes a verification module 805, which uses the verification code to verify the output of the sequential device to be tested.
  • test circuit, processor or computing system can be used for digital currency processing or calculation.
  • digital currencies can be, for example, Bitcoin, Litecoin, Ethereum, and other digital currencies.
  • test circuit may be as described in any of the embodiments disclosed herein.
  • the method may include the following steps.
  • step S901 clock signals of different configurations are provided to the sequential device to be tested through the clock driving module.
  • step S903 the input of the test sequence to the sequential device to be tested is provided.
  • step S905 it is detected whether the output of the sequential device to be tested meets the requirements under each configured clock signal.
  • test circuits, computing systems, and test methods are provided.
  • Test circuits, computing systems and testing methods according to the present disclosure can be used for processing and computing of digital currency or virtual currency, and testing circuits or systems for digital currency or virtual currency.
  • a flexibly configured clock path is provided, and multiple clock options are provided for pipeline-level testing.
  • the more paths, the more options are provided.
  • flexibly configured clocks can be provided for the pipelines at all levels, thereby greatly improving the design and testing flexibility of the mining machine processor, and directly or indirectly improving the product yield.

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

一种测试电路(300,300',400,500,600,700,800)包括：测试序列提供模块(301)，用于提供测试序列(PRBS)到待测试的时序器件(303)；时钟驱动模块(307,407,507,607,707,807)，用于提供时钟信号(759)到待测试的时序器件(303)，其包括第一时钟驱动电路(610,710)，第一时钟驱动电路(610,710)包括：多个第一时钟路径(421,423)，分别提供对应的时钟信号(759)；以及逻辑单元(427,715)，基于多个第一时钟路径(421,423)提供的时钟信号(759)中的至少一部分，产生脉宽调节的第一时钟信号以用于待测试的时序器件(303)；以及验证模块(305,405,805)，用于对待测试的时序器件(303)的输出进行验证。

Description

测试电路、测试方法和包括测试电路的计算系统
相关申请的交叉引用
本申请要求于2021年1月14日提交的中国专利申请No.202110048109.2的优先权，并通过引用将其全部内容并入在此。
技术领域
本公开涉及测试电路、测试方法和包括测试电路的计算系统。
背景技术
近年来，数字货币受到越来越多的关注。在相关领域中，需要改进的处理器和计算系统。
矿机类处理器设计通常采用流水线的结构。根据算法，将运算逻辑分成若干级流水线，每级流水线有相似的功能设计和运算结构。每级流水线都需要输入工作时钟，即脉冲时钟。
由于比特币芯片中的运算单元由多级流水线构成，且每级流水线主要由多比特触发器构成，因此对于触发器的优化设计是使比特币芯片性能提升，功耗降低的核心方向之一。芯片内不同的流水线中，会根据其自身情况使用不同的触发器。同时连接多级流水线之间的时钟树方向和时钟树内部结构，则是依赖经验与分析来选择。由于考虑到触发器的SPICE仿真，静态时序分析和生产出的芯片之间有一定的差异，芯片所选择的时钟树结构通常是偏保守，而未必是最优的。
此外，随着矿机处理器的生产使用更加先进的制造工艺，工艺的复杂度和离散度也越来越高，导致处理器的实际工作条件和设计阶段的仿真环境偏差较大。时钟驱动电路在设计阶段即使满足仿真条件下对时钟的要求，实际的处理器也往往因为与仿真环境的差异，导致某些处理器的流水线时钟无法达到设计要求。
因此，需要改进的测试电路、测试方法和包括测试电路的处理器。
发明内容
根据本公开的一个方面，提供了一种测试电路，包括：测试序列提供模块，用于提供测试序列到待测试的时序器件；时钟驱动模块，用于提供时钟信号到所述待测试 的时序器件，其包括第一时钟驱动电路，所述第一时钟驱动电路包括：多个第一时钟路径，分别提供对应的时钟信号；以及逻辑单元，基于所述多个第一时钟路径提供的时钟信号中的至少一部分，产生脉宽调节的第一时钟信号以用于所述待测试的时序器件；以及验证模块，用于对所述待测试的时序器件的输出进行验证。
在一些实施例中，所述验证模块包括：基准时序器件，所述测试序列被同步提供到所述基准时序器件和所述待测试的时序器件，以及所述第一时钟驱动电路还提供第二时钟信号到所述基准时序器件；以及比较模块，其对所述基准时序器件的输出和所述待测试的时序器件的输出进行比较。
在一些实施例中，所述多个第一时钟路径接收共同的时钟输入，并基于所述时钟输入分别提供不同相位的时钟信号。
在一些实施例中，所述第一时钟路径中的至少一个还包括：第一选择器，用于从对应的第一时钟路径的多个子路径所提供的时钟信号中选择时钟信号，并提供所选择的时钟信号到所述逻辑单元。
在一些实施例中，所述时钟驱动模块还包括第二时钟驱动电路，其中所述第二时钟驱动电路包括：多个第二时钟路径，其分别提供不同相位的时钟信号，所述多个第二时钟路径中的至少一个基于所述第一时钟信号提供时钟信号；以及第二选择器，从所述多个第二时钟路径所提供的时钟信号中选择时钟信号以用于所述待测试的时序器件。
在一些实施例中，所述时钟驱动模块还包括第三时钟驱动电路，其中所述第三时钟驱动电路包括：多个第三时钟路径，其分别提供不同相位的时钟信号；以及第三选择器，用于从所述多个第三时钟路径所提供的时钟信号中选择时钟信号，以用于所述多个第一时钟路径中的至少一个。
在一些实施例中，所述多个第一时钟路径至少包括第一路径和第二路径，所述第一路径提供所述选择的时钟信号到所述逻辑单元，以及所述第二路径提供与所选择的时钟信号的反相版本或反相并延时的版本到所述逻辑单元。
在一些实施例中，所述第二路径包括：反相器，其接收所述选择的时钟信号，并产生与所述选择的时钟信号反相的时钟信号；一个或多个子路径，用于分别提供所述反相的时钟信号的相应版本到第四选择器；以及所述第四选择器，从所述反相的时钟信号的不同的版本中选择，并提供所选择的版本到所述逻辑单元。
在一些实施例中，所述一个或多个子路径分别提供所述反相的时钟信号的不同延 时的版本到所述第四选择器。
在一些实施例中，所述逻辑单元是与门或或门。
在一些实施例中，所述测试序列提供模块提供具有校验码的测试序列到所述待测试的时序器件，所述测试电路还包括校验模块，其利用所述校验码对所述待测试的时序器件的输出进行校验。
在一些实施例中，所述时序器件是触发器或锁存器。
在一些实施例中，所述测试电路还包括与所述待测试的时序器件关联的另外的时序器件。
根据本公开的另一方面，还提供了一种计算系统，其包括如本公开任意实施例所述的测试电路。
根据本公开的另一方面，还提供了一种测试电路的测试方法，所述测试电路是如本公开任意实施例所述的测试电路，所述方法包括：通过所述时钟驱动模块提供不同配置的时钟信号到所述待测试的时序器件；提供测试序列到所述待测试的时序器件的输入；以及检测在每种配置的时钟信号下所述待测试的时序器件的输出是否满足要求。
在一些实施例中，所述方法还包括：确定满足要求的对应的时钟配置或时钟配置范围；确定预先确定的被设计用于该待测试的时序器件的时序参数范围与通过测试确定的满足要求的对应的时钟配置之间的差异；以及根据所述差异修改所述待测试的时序器件的电路设计和/或用于制备所述待测试的时序器件的工艺参数。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1示出了一种示例性的流水线的示意图；
图2A示出了一种示例性的包括时序器件-时序器件之间的路径的电路的示意图；
图2B示出了用于图2A所示电路的建立时间的时序图；
图2C示出了用于图2A所示电路的保持时间的时序图；
图2D示出了流水线的正向时钟树的示意时序图；
图2E示出了流水线的反向时钟树的示意时序图；
图3A示出了根据本公开一个实施例的测试电路的示意图；
图3B示出了根据本公开另一实施例的测试电路的示意图；
图4示出了根据本公开又一实施例的测试电路的示意图；
图5示出了根据本公开再一实施例的测试电路的示意图；
图6示出了根据本公开另一实施例的测试电路的示意图；
图7示出了根据本公开又一实施例的测试电路的示意图；以及
图8示出了根据本公开一个实施例的测试电路的示意图。
注意，在以下说明的实施方式中，有时在不同的附图之间共同使用同一附图标记来表示相同部分或具有相同功能的部分，而省略其重复说明。在本说明书中，使用相似的标号和字母表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
为了便于理解，在附图等中所示的各结构的位置、尺寸及范围等有时不表示实际的位置、尺寸及范围等。因此，所公开的发明并不限于附图等所公开的位置、尺寸及范围等。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。应注意：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本公开的范围。另外，对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
应理解，以下对至少一个示例性实施例的描述仅仅是说明性的，并非是对本公开及其应用或使用的任何限制。还应理解，在此示例性描述的任意实现方式并不必然表示其比其它实现方式优选的或有利的。本公开不受在上述技术领域、背景技术、发明内容或具体实施方式中所给出的任何所表述的或所暗示的理论所限定。
另外，仅仅为了参考的目的，还可以在下面描述中使用某种术语，并且因而并非意图限定。例如，除非上下文明确指出，否则涉及结构或元件的词语“第一”、“第二”和其它此类数字词语并没有暗示顺序或次序。
还应理解，“包括/包含”一词在本文中使用时，说明存在所指出的特征、整体、步骤、操作、单元和/或组件，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、单元和/或组件以及/或者它们的组合。
流水线(pipeline)技术是在程序执行时多条指令重叠进行操作的一种准并行处理实现技术。处理器的流水线级中往往具有一个或多个时序器件，例如触发器。而选择使用锁存器作为流水线中的时序器件可以有效减少功耗和面积的开销，提升矿机产品的竞争力。
在同步电路设计中，每个时序器件都会有一个对应的时钟进行控制。芯片中有大量的时序器件，所有的时序器件不能由同一个时钟进行控制(时钟的负载能力不够)，需要用反相器(inv)或者缓冲器(buffer,简写为buf)来传递时钟信号。这些一级级传递的inv和buf组成了时钟树。
图1示出了一种用于示例性的流水线处理器的示意图。处理器中的流水线可以包括多个流水线级，各流水线级的工作时钟通常都来自于同一时钟源，通过用于流水线各级的各级时钟驱动电路在流水线各级之间传递，如图1所示。
以一个四级流水线处理器为例，执行一条指令需要四个周期(取指，译码，取操作数，执行)。但从第四个周期之后，每个周期均有一条指令执行完成，看起来好像一条指令只需要一个周期就可以执行完成。流水线技术可以提高执行效率，获得更高的吞吐率，提高处理器性能。
流水线技术可以应用于数字货币领域的处理器。例如，比特币使用哈希(hash)SHA256算法。可以根据对不同运算单位的切分，将SHA256算法切分成若干个流水计算单元，从而组成运算流水线。通常的流水线可以划分为32级，64级，128级等。
此外，在流水线的同步时序电路设计中，一般只在时钟的上升沿或下降沿进行采样。为了得到正确的采样结果，需要确保采样时刻数据有效，保证数据满足建立时间(setup time)和保持时间(hold time)。因此设计工具会对综合结果进行静态时序分析，以判断时钟和数据之间的相对关系是否满足要求。
下面以包含时序器件-时序器件以及二者之间的路径的电路为例来进行说明。图2A示出了一种示例性的包括时序器件-时序器件之间的路径的电路的示意图。该图是数字系统设计常见的电路图。这里需要保证数据能够正确的在两个触发器之间进行传输，由此确定中间组合逻辑电路Comb的传输延时的范围。
图2B示出了用于图2A所示电路的建立时间的时序图。D1表示到图2A中的前边的触发器(称之为发起(launch)触发器)的输入。在时钟CLK的第一个时钟上升沿，图2A中的发起触发器采集D1信号，高电平被输入到该触发器，经过触发器输出延时Tco到达组合逻辑电路Comb。又经过组合逻辑电路Comb的延时Tcomb(这里，假定组合逻辑电路此时没有改变信号的高低，从而可以把它考虑为一个缓冲器)送到了D2接口上。在第二个时钟上升沿到来之前，D2数据线上的信号要满足稳定时间>触发器的建立时间Tsu，
即，要满足时钟周期Tclk-Tco-Tcomb>Tsu。
考虑最坏情况：触发器的输出延时最大(Tco-max)，组合逻辑电路的延时(Tcomb-max)也最大，可得：
Tclk-Tco-max-Tcomb-max>Tsu
接着之前的时序图继续说明保持时间。为了图示的清晰，以图2C示出了用于说明图2A所示电路的保持时间的时序图，其各信号与图2B所示的相同。在第二个时钟上升沿，前边的发起触发器采集到D1上的低电平，经过Tco的延时在Q1上得到表达。这个低电平在经过组合电路延时Tcomb到达D2。经过Tco+Tcomb的延时，D2上原本的高电平在第二个时钟上升沿到来之后的稳定时间需要大于第二个触发器的保持时间Th。满足了这个条件，后边的触发器才能稳定的接收到最初由D1传过来的高电平。即，
Tco+Tcomb>Th
考虑到最坏的情况：触发器的输出延时最小(Tcomb-min)，组合逻辑电路的延时也最小(Tco-min)：
Tco-min+Tcomb-min>Th
同步时序电路正常工作的前提是触发器的建立时间和保持时间都得到满足。而保持时间是更重要的指标，必须满足。保持时间如果不满足，芯片可能无法正常工作。
另一方面，在同步电路设计中，每个时序器件都会有一个对应的时钟进行控制。芯片中有大量的时序器件，所有的时序器件不能由同一个时钟进行控制(时钟的负载能力不够)，需要用反相器(inv)或者缓冲器(buffer,简写为buf)来传递时钟信号。这些一级级传递的inv和buf组成了时钟树。
在流水线设计中，如果与数据流传递方向相同，则称为正向时钟树(如下图)。反之则成为反向时钟树。
对于正向时钟树，考虑图2A中所示的实例应用于前后两个流水线级的情况。这就相当于时钟连接到第一个触发器后，经过一级时钟驱动电路的延时后再到达第二个触发器。时序图如图2D所示，其中示出了时钟驱动电路的延时(Tclk延时，这里以Tclklatency表示)。
这里，对于Tsu，时序需要满足Tclk+Tclklatency-Tco-max-Tcomb-max>Tsu，
也即，Tclk>Tsu+Tco-max+Tcomb-max–Tclklatency。
如果Tclk可以更小，周期更小，芯片的频率可以更快，达到更高性能。但正向时钟树有一个缺点，保持时间不容易满足。
对于保持时间Th，需要满足：
Tco-min+Tcomb-min>Th+Tclklatency，
也即Tco-min+Tcomb-min-Tclklatency>Th。
对于反向时钟树，考虑图2A中所示的实例应用于前后两个流水线级的情况。这就相当于时钟先连接到第二个触发器后，经过一级时钟驱动电路的延时后再到达第一个触发器。时序图如图2E所示，其中示出了时钟驱动电路的延时(Tclk延时，这里以Tclklatency表示)。
对于Tsu，时序需要满足：
Tclk-Tclklatency-Tco-max-Tcomb-max>Tsu，
也即，Tclk>Tsu+Tco-max+Tcomb-max+Tclklatency
如果Tclk变大，周期更大，芯片的频率变慢，性能降低。反向时钟树的优点是触发器的保持时间更容易满足。
对于保持时间Th，时序需要满足：
Tco-min+Tcomb-min>Th–Tclklatency，
也即，Tco-min+Tcomb-min+Tclklatency>Th。
对于使用锁存器的流水线设计，相邻流水线之间的时钟需要满足一定的相位要求以满足锁存器特定的时序要求，例如，锁存器保持(hold)时序的要求和锁存器的最小脉冲宽度的要求，从而对时钟相关电路的设计和制造工艺提出了更高的要求。
然而，随着先进工艺的使用，工艺的复杂度和离散度也越来越高，导致处理器的实际工作条件和设计阶段的仿真环境偏差较大。使得时钟驱动电路在设计阶段即使满足仿真条件下对时钟的要求，实际的处理器也往往因为与仿真环境的差异，导致某些处理器的流水线时钟无法达到设计要求。这也造成了处理器的良率受限。
本申请的发明人认识到上述的一个或多个问题，并提出了在此公开的改进的测试电路和测试方法。
图3A示出了根据本公开一个实施例的测试电路的示意图。如图3A所示，测试电路300用于对待测试的时序器件303进行测试。所述待测试的时序器件可以包括(但不限于)任意需要时钟控制的器件，例如，寄存器、触发器或锁存器等。在图中，作为示例，待测试的时序器件被示出为多比特触发器(MBFF)。
在一些实施例中，待测试的时序器件303可以设置在流水线级中，例如图中所示的流水线级350中。在另一些实施例中，待测试的时序器件303可以设置在流水线级之外，以利于进行测试。
如图3A所示，测试电路300包括测试序列提供模块301，用于提供测试序列到待测试的时序器件303。所述测试序列可以包括例如伪随机比特序列(PRBS)或者包括校验码的伪随机比特序列。
测试电路300还包括时钟驱动模块307，用于提供时钟信号到所述待测试的时序器件。测试电路300还包括验证模块305，用于对所述待测试的时序器件的输出进行验证。
图3B示出了根据本公开另一实施例的测试电路的示意图。如图3B所示，测试电路300’除了包括测试序列提供模块301、时钟驱动模块307和验证模块305之外，还可以包括另外的时序器件，例如在待测试的时序器件303上游和下游的时序器件309和311。时序器件309和311中的一个或多个可以与待测试的时序器件303一起被包含在同一流水线级350中。
图4示出了根据本公开又一实施例的测试电路的示意图。如图4所示，测试电路400包括测试序列提供模块301，用于提供测试序列到待测试的时序器件303。所述测试序列可以包括例如伪随机比特序列(PRBS)或者包括校验码的伪随机比特序列。图4中还示出了另外的中间时序器件309，其被示出为MBFF(以MBFF1表示)，而待测 试的时序器件303则被示出为MBFF(以MBFF2表示)。
测试电路400还包括时钟驱动模块407，用于提供时钟信号到所述待测试的时序器件。图4示出了时钟驱动模块的一种具体实现方式。如图4中所示，时钟驱动模块407可以包括这样的时钟驱动电路(第一时钟驱动电路)，该时钟驱动电路可以包括：多个时钟路径(第一时钟路径)421和423，分别提供对应的时钟信号；以及逻辑单元427，基于所述多个时钟路径(第一时钟路径)提供的时钟信号中的至少一部分，产生脉宽调节的第一时钟信号以用于所述待测试的时序器件。在一些实施例中，逻辑单元427可以是与门或或门。
这里，需要说明的是，“时钟信号以用于所述待测试的时序器件”意图表示所述的时钟信号可以直接用于(例如，直接提供给)待测试的时序器件，或者所述的时钟信号可以间接用于(例如，间接而不是直接提供给)待测试的时序器件。换而言之，在所述的时钟信号和待测试的时序器件之间可以存在中间模块或器件，所述中间模块或器件可以基于所述的时钟信号提供时钟到所述待测试的时序器件。此外，尽管这里仅示出了两个时钟路径，但应理解，可以设置更多的时钟路径。
如图中所示，时钟路径421和423可以接收共同的时钟输入，并基于所述时钟输入分别提供多种多样的相位的时钟信号。例如，图中的时钟路径421具有4个相位调节单元425(例如，反相器(如图中所示)或缓冲器等)，从而相对于输入的时钟提供4个单元的延时。而时钟路径423则不提供额外的延时。这里，不考虑无源线路本身的延时，而仅考虑器件或单元带来的延时。
还应理解，在一些实施例中，各时钟路径对输入时钟提供彼此不同的延时和/或提供反相；在另一些实施例中，某些时钟路径也可以提供相同的延迟或反相。例如，各时钟路径可以具有或不具有相位调节单元，或者可以具有更多或更少的相位调节单元。各相位调节单元可以相同或不相同，或者可以共同或单独地配置。
测试电路400还包括验证模块405，用于对所述待测试的时序器件的输出进行验证。在图4中所示的实施例中，验证模块405可以包括基准时序器件411和比较模块413。测试序列PRBS被同步提供到基准时序器件411和待测试的时序器件303(可以经过或者不经过可选的中间器件MBFF1)。时钟驱动模块407还提供时钟信号(第二时钟信号)到基准时序器件411。比较模块413对基准时序器件的输出和待测试的时序器件的输出进行比较。
这里，作为示例，基准时序器件411可以具有与待测试时序器件相同的电路结构 或具有相同的电路设计，但是基准时序器件411可以是基于制造厂商或设计厂商或第三方提供的标准单元库、IP库或工艺角制备的。但应理解，本公开不限于此。例如，所谓基准时序器件也可以是定制的，或根据经验设计或制备的，只要其可以作为参考即可。
另外，对于第二时钟信号没有特别的限制。其可以获得自任意的第一时钟路径的任意部分，或者获得自时钟输入或其他来源，只要后续的比较模块可以对基准时序器件的输出和待测试的时序器件的输出进行比较即可。
比较模块413可以基于一定的标准来比较基准时序器件的输出和待测试的时序器件的输出，例如，基准时序器件的输出和待测试的时序器件的输出是否同步，是否一致或者满足时序要求，或者逻辑值是否对应，等等。从而，通过比较模块413确定测试的结果。
时钟驱动模块407还可以包括另外的相位调节单元，例如图4中所示的相位调节单元429。这里，相位调节单元429被示出为在逻辑单元427下游的反相器429；但应理解，这仅仅是示例性的而不是限制性的；所述另外的相位调节单元的类型、位置、数量皆不限于此。例如，作为对图4中所示的时钟驱动模块407的替代实施例，可以去除反相器429，而在时钟路径421和423中分别添加额外的反相器。
此外，在不同实施例中，中间器件309可以和待测试的时序器件303处于相同或不同的流水线级中。优选地，基准器件411可以和待测试的时序器件303处于相同的流水线级中。替代地，在另外的一些实施例中，所述待测试的时序器件303可以被设置在流水线级之外，例如在中间器件309或311或者基准器件411所处的流水线级之外，例如位置上可以与所述流水线级邻近。在这种情况下，待测试器件将不参与流水线的实际指令操作。从而，可以测试器件和测试操作对流水线级的影响，可以在增加测试的便利的同时，使得对流水线的影响最小化。
图5示出了根据本公开再一实施例的测试电路的示意图。图5所示的测试电路500除了时钟驱动模块507之外与图4所示的测试电路400基本相同。在图5中，与图4中所示相同的部件被标示以相同的附图标记；并且，对于相同的部件这里不再重复说明。
下面具体说明用于测试电路500的时钟驱动模块507。与图4中所示的驱动电路407相比，时钟驱动模块507的时钟路径(这里，以路径521作为示例)中增加了选择器(第一选择器)529，用于从对应的时钟路径(即，时钟路径521)的多个子路径 525和527所提供的时钟信号中选择时钟信号，并提供所选择的时钟信号到逻辑单元427。
此外，尽管这里仅示出了两个子路径，但应理解，可以设置更多的子路径。子路径可以接收相同的时钟信号，并提供多种多样的相位的时钟信号到选择器529。在一些实施例中，各子路径对接收的输入时钟提供彼此不同的延时和/或提供反相；在另一些实施例中，某些子路径也可以提供相同的延迟或反相。例如，子路径可以设置有一个或多个相位调节单元，例如反相器或缓冲器等，或者某些子路径也可以不设置相位调节单元。例如，在图5所示的示例中，子路径525具有一个反相器，而子路径527具有三个反相器。
选择器529可以是复用器MUX0，但本公开不限于此。选择器529可以基于控制信号Sel0来从多个子路径525和527等进行选择，来将选择的路径上的时钟信号提供到逻辑单元427。
根据本公开的实施例，可以灵活配置用于待测试器件的时钟信号，从而为测试提供了灵活性和便利性。
图6示出了根据本公开另一实施例的测试电路的示意图。图6所示的测试电路600除了时钟驱动模块607之外与前面所示的测试电路500基本相同。在图6中，与前面附图中所示相同的部件被标示以相同的附图标记；并且，对于相同的部件这里不再重复说明。
下面具体说明用于测试电路600的时钟驱动模块607。与图5中所示的驱动模块507相比，时钟驱动模块607除了可以包括前面的实施例中所描述的驱动模块例如407或507的至少一部分或全部(其可以作为第一时钟驱动电路610)之外，还包括第二时钟驱动电路620。第二时钟驱动电路620可以包括多个时钟路径(第二时钟路径)例如621和623，其分别提供不同相位的时钟信号。在一些实施例中，所述多个第二时钟路径中的至少一个基于所述第一时钟信号提供时钟信号。
尽管这里仅示出了两个第二时钟路径621和623，但应理解，可以设置更多的第二时钟路径。第二时钟路径可以接收相同的时钟信号，并提供多种多样的相位的时钟信号到选择器625。类似地，在一些实施例中，各子路径对接收的输入时钟提供彼此不同的延时和/或提供反相；在另一些实施例中，某些子路径也可以提供相同的延迟或反相。例如，各第二时钟路径可以设置有一个或多个相位调节单元，例如反相器或 缓冲器等，或者某些路径也可以不设置相位调节单元。例如，在图6所示的示例中，路径621具有一个反相器，而路径623具有三个反相器。
第二时钟驱动电路620还可以包括选择器(第二选择器)625，用于从多个第二时钟路径所提供的时钟信号中选择时钟信号以用于待测试的时序器件。选择器625可以基于控制信号Sel1，来从多个第二时钟路径所提供的时钟信号中选择时钟信号。在图6中的实施例中，选择器625被示出为复用器MUX1，然而本公开不限于此。
根据本公开的实施例，可以更加灵活配置用于待测试器件的时钟信号，提供不同延时不同相位的时钟信号，从而为测试提供了灵活性和便利性。
图7示出了根据本公开又一实施例的测试电路的示意图。图7所示的测试电路700除了时钟驱动模块707之外与前面所示的测试电路基本相同。在图7中，与前面附图中所示相同的部件被标示以相同的附图标记；并且，对于相同的部件这里不再重复说明。
下面具体说明用于测试电路700的时钟驱动模块707。参考图7，时钟驱动模块707可以包括时钟驱动电路(第一时钟驱动电路)710和时钟驱动电路(第三时钟驱动电路)750。
在一些实施例中，时钟驱动电路710被配置用于调节时钟信号的脉宽，并提供脉宽调节的时钟信号以用于待测试的时序器件(例如，图中的时序器件303)。时钟驱动电路710也可以包括前述实施例中所描述的时钟驱动电路，而代之以用时钟驱动电路750的时钟输出作为其时钟输入。
时钟驱动电路750可以包括多个时钟路径(亦可称为第三时钟路径)751和753等，分别提供对应的时钟信号到选择器MUX0(标示以757)。这里，在图7中仅示例性地示出了时钟路径751和753，然而在其他实施例中，时钟驱动电路可以包括更多个时钟路径(第三时钟路径)。
在一些实施例中，各个时钟路径(第三时钟路径)可以接收相同的输入时钟，并对该输入时钟进行不同的延时和/或反相处理，以得到不同版本的时钟信号。例如，在一些实施例中，各个时钟路径可以接收相同的输入时钟，并对该输入时钟进行多种多样的延时和/或反相处理，以得到不同版本的时钟信号。例如，在一些实施例中，各时钟路径对输入时钟提供彼此不同的延时和/或提供反相；在另一些实施例中，某些时钟路径也可以提供相同的延迟或反相。至少一部分时钟路径可以具有时钟调节单 元755，例如缓冲器或反相器等，以例如调节时钟信号的属性，例如相位。如图中所示，时钟路径751具有一个缓冲器(假设延时τ)和反相器(进行反相)，时钟路径753具有两个缓冲器(假设分别延时τ)和反相器(进行反相)，从而对输入时钟进行不同的延时，从而分别提供反相并延时τ的时钟信号版本以及反相并延时2τ的时钟信号版本。在某些情况下，也可以提供未设置调节单元755的时钟路径。
时钟驱动电路750可以包括所述选择器(亦可称为第三选择器)MUX0 757，用于从所述多个第三时钟路径所提供的时钟信号中选择时钟信号，以用于对应的待测试的时序器件。例如，选择器757可以基于选择信号(例如，选择信号0)从多个第一时钟路径中选择，以将所选择的时钟信号作为时钟输出759提供给待测试的时序器件或者传送到下一级。
在处理器的实际工作条件下，可以通过选择信号(信号0)来决定哪路时钟信号作为输出时钟，以满足待测试的时序器件的时序要求，例如锁存器的保持时序和最小时钟脉宽的要求。
如图7所示，在时钟路径751和753上经过不同延时的时钟到达MUX0的两个输入端。可以根据需求设定选择信号0来选择两路时钟通路中的一路作为时钟输出传递给当前待测试的时序器件和/或流水线的下一级的时钟驱动电路。相邻两级流水线中的时钟相位可以分别调整(各有两种(或更多种)不同的延时)，从而更好的满足各待测试的时序器件中锁存器的时序要求。
在一种具体实现中，如图7所示，时钟驱动电路710可以包括多个时钟路径(亦可称为第四时钟路径)711、713等，其分别提供不同相位的时钟信号到逻辑单元715。在一些实施例中，所述多个第四时钟路径可以接收来自时钟驱动电路750的时钟信号759，并且在各个第四时钟路径上基于所接收的时钟信号提供不同相位的时钟信号到逻辑单元715。时钟驱动电路710还可以包括逻辑单元715。逻辑单元715可以基于所述不同相位的时钟信号中的至少一部分，产生脉宽调节的时钟信号以用于待测试的时序器件303。在一些具体实施例中，逻辑单元715可以是与门或或门；本公开不限于此。
所述多个第四时钟路径可以至少包括第一路径和第二路径。在如图7所示的示例中，第一路径711可以被配置来直接提供时钟输入759到逻辑单元715。第二路径713可以被配置来基于从所接收的时钟输入759提供进行了进一步调节的版本(例如，反相版本或反相并延时的版本)到逻辑单元715。
如图所示，第二路径713可以包括反相器717。反相器717接收时钟输入(例如，输入时钟或来自中间电路的时钟输出)759，并产生与该时钟输入759反相的时钟信号。第二路径713可以还包括一个或多个子路径，例如图中所示出的子路径719和721。子路径719和721分别提供所述反相的时钟信号的相应版本到选择器(在某些情况下，亦可称为第四选择器)723。例如，在图7所示的示例中，子路径721通过缓冲器对所述反相的时钟信号进行延时，从而提供所述反相的时钟信号的延时版本，而子路径719则提供未经处理的所述反相的时钟信号。如此，反相器的输出信号经过两路不同延时的时钟传递路径到达选择器MUX1的两个输入端。
选择器MUX1 723从所述反相的时钟信号的不同的版本中选择，并提供所选择的版本到所述逻辑单元。MUX1可以选择合适的时钟路径延时，以满足待测试的时序器件(例如，锁存器)对脉冲宽度的需求。
在图7所示的示例中，提供到待测试的时序器件的时钟可以由驱动电路750的时钟输出信号和该时钟输出信号的不同版本的反相时钟通过逻辑单元(例如，或门或与门逻辑)产生。由于待测试的时序器件可以位于对应的流水线级中，因此提供到本级待测试的时序器件的时钟的脉冲宽度可由本级流水线的时钟驱动电路750的输出信号和它的选定版本的反相时钟的相位(即，该版本的反相时钟相对于时钟输出信号的延迟时间)决定。
选择器MUX1可以根据选择信号1选择两路(可以更多)子时钟路径中的一路作为逻辑单元715的输入之一，而逻辑单元715的另一个输入是本级流水线的时钟驱动电路的时钟输出信号。这样逻辑单元715的输出信号作为给本级流水线(尤其是其中的锁存器器件)的时钟信号，使得占空比宽度可调。
图8示出了根据本公开一个实施例的测试电路的示意图。如图8所示，测试电路800包括用于对待测试的时序器件303进行测试。上面就其它实施例中的相同或相似部件(例如待测试的时序器件等)所描述的内容可以同样地或适应性地应用于本实施例，因此这里省略对其重复说明。
如图8所示，测试电路800包括测试序列提供模块801，用于提供测试序列到待测试的时序器件303。所述测试序列可以包括例如伪随机比特序列(PRBS)或者包括校验码的伪随机比特序列。
测试电路800还包括时钟驱动模块807，用于提供时钟信号到所述待测试的时序 器件。测试电路800还包括验证模块805，其利用所述校验码对所述待测试的时序器件的输出进行校验。
上面就其他附图所描述的内容可以同样地或者适应性地应用于图8所示的测试电路。因此，这里不再对其细节进行重复说明。
在一些实施例中，处理器可以具有一个或多个核。前述的待测试的时序器件和时钟驱动电路等可以被设置在所述核中。
至此，还应理解，还公开了一种计算系统，其包括如这里所描述或所示出的任意实施例所述的测试电路。
根据本公开实施例的测试电路、处理器或计算系统，可以用于数字货币处理或计算。数字货币的例子可以有，例如，比特币、莱特币、以太币以及其他数字货币。
根据本公开的另一方面还构思了一种测试电路的测试方法。所述测试电路可以如在此公开的任意实施例所述的测试电路。所述方法可以包括以下步骤。
在步骤S901，通过时钟驱动模块提供不同配置的时钟信号到待测试的时序器件。在步骤S903，提供测试序列到待测试的时序器件的输入。在步骤S905，检测在每种配置的时钟信号下待测试的时序器件的输出是否满足要求。
在一些实施例中，所述方法还可以包括，在步骤S907，确定满足要求的对应的时钟配置或时钟配置范围。在步骤S911，确定预先确定的被设计用于该待测试的时序器件的时序参数范围与通过测试确定的满足要求的对应的时钟配置之间的差异。在步骤S913，根据差异修改待测试的时序器件的电路设计和/或用于制备待测试的时序器件的工艺参数。
根据本公开的实施例，提供了新颖的测试电路、计算系统和测试方法。根据本公开的测试电路、计算系统和测试方法可以用于数字货币或虚拟货币的处理和计算，以及测试用于数字货币或虚拟货币的电路或系统。根据本公开的实施例，提供了灵活配置的时钟路径，并为流水线级的测试提供了多种时钟选择。根据本公开实施例，路径越多，则提供的选择越多。根据本公开实施例，可以为各级流水线提供灵活配置的时钟，从而极大地提高了矿机处理器的设计和测试的灵活性，并直接或间接地提高了产品良品率。
本领域技术人员应当意识到，在上述实施例中描述操作(或步骤)之间的边界仅仅是说明性的。多个操作可以结合成单个操作，单个操作可以分布于附加的操作中，并且操作可以在时间上至少部分重叠地执行。而且，另选的实施例可以包括特定操作的多个实例，并且在其他各种实施例中可以改变操作顺序。但是，其它的修改、变化和替换同样是可能的。因此，本说明书和附图应当被看作是说明性的，而非限制性的。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。在此公开的各实施例可以任意组合，而不脱离本公开的精神和范围。本领域的技术人员还应理解，可以对实施例进行多种修改而不脱离本公开的范围和精神。本公开的范围由所附权利要求来限定。

Claims (16)

  1. 一种测试电路，包括：
    测试序列提供模块，用于提供测试序列到待测试的时序器件；
    时钟驱动模块，用于提供时钟信号到所述待测试的时序器件，其包括第一时钟驱动电路，所述第一时钟驱动电路包括：
    多个第一时钟路径，分别提供对应的时钟信号；以及
    逻辑单元，基于所述多个第一时钟路径提供的时钟信号中的至少一部分，产生脉宽调节的第一时钟信号以用于所述待测试的时序器件；以及
    验证模块，用于对所述待测试的时序器件的输出进行验证。
  2. 根据权利要求1所述的测试电路，其中，所述验证模块包括：
    基准时序器件，所述测试序列被同步提供到所述基准时序器件和所述待测试的时序器件，以及所述第一时钟驱动电路还提供第二时钟信号到所述基准时序器件；以及
    比较模块，其对所述基准时序器件的输出和所述待测试的时序器件的输出进行比较。
  3. 根据权利要求1所述的测试电路，其中所述多个第一时钟路径接收共同的时钟输入，并基于所述时钟输入分别提供不同相位的时钟信号。
  4. 根据权利要求1所述的测试电路，其中，所述第一时钟路径中的至少一个还包括：
    第一选择器，用于从对应的第一时钟路径的多个子路径所提供的时钟信号中选择时钟信号，并提供所选择的时钟信号到所述逻辑单元。
  5. 根据权利要求1所述的测试电路，其中，所述时钟驱动模块还包括第二时钟驱动电路，其中所述第二时钟驱动电路包括：
    多个第二时钟路径，其分别提供不同相位的时钟信号，所述多个第二时钟路径中的至少一个基于所述第一时钟信号提供时钟信号；以及
    第二选择器，从所述多个第二时钟路径所提供的时钟信号中选择时钟信号以用于 所述待测试的时序器件。
  6. 根据权利要求1所述的测试电路，其中，所述时钟驱动模块还包括第三时钟驱动电路，其中所述第三时钟驱动电路包括：
    多个第三时钟路径，其分别提供不同相位的时钟信号；以及
    第三选择器，用于从所述多个第三时钟路径所提供的时钟信号中选择时钟信号，以用于所述多个第一时钟路径中的至少一个。
  7. 根据权利要求6所述的测试电路，其中所述多个第一时钟路径至少包括第一路径和第二路径，
    所述第一路径提供所述选择的时钟信号到所述逻辑单元，以及
    所述第二路径提供与所选择的时钟信号的反相版本或反相并延时的版本到所述逻辑单元。
  8. 根据权利要求7中所述的测试电路，其中所述第二路径包括：
    反相器，其接收所述选择的时钟信号，并产生与所述选择的时钟信号反相的时钟信号；
    一个或多个子路径，用于分别提供所述反相的时钟信号的相应版本到第四选择器；以及
    所述第四选择器，从所述反相的时钟信号的不同的版本中选择，并提供所选择的版本到所述逻辑单元。
  9. 根据权利要求8所述的测试电路，其中所述一个或多个子路径分别提供所述反相的时钟信号的不同延时的版本到所述第四选择器。
  10. 根据权利要求1所述的测试电路，其中所述逻辑单元是与门或或门。
  11. 根据权利要求1所述的测试电路，其中所述测试序列提供模块提供具有校验码的测试序列到所述待测试的时序器件，
    所述测试电路还包括校验模块，其利用所述校验码对所述待测试的时序器件的输 出进行校验。
  12. 根据权利要求1所述的测试电路，其中，所述时序器件是触发器或锁存器。
  13. 根据权利要求1所述的测试电路，还包括与所述待测试的时序器件关联的另外的时序器件。
  14. 一种计算系统，其包括如权利要求1-13中任一项所述的测试电路。
  15. 一种测试电路的测试方法，其中，所述测试电路是如权利要求1-13中任一项所述的测试电路，
    所述方法包括：
    通过所述时钟驱动模块提供不同配置的时钟信号到所述待测试的时序器件；
    提供测试序列到所述待测试的时序器件的输入；以及
    检测在每种配置的时钟信号下所述待测试的时序器件的输出是否满足要求。
  16. 如权利要求15所述的方法，还包括：
    确定满足要求的对应的时钟配置或时钟配置范围；
    确定预先确定的被设计用于该待测试的时序器件的时序参数范围与通过测试确定的满足要求的对应的时钟配置之间的差异；以及
    根据所述差异修改所述待测试的时序器件的电路设计和/或用于制备所述待测试的时序器件的工艺参数。
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