WO2022142711A1 - 一种芯片叠封方法、层叠封装芯片及电子存储设备 - Google Patents

一种芯片叠封方法、层叠封装芯片及电子存储设备 Download PDF

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WO2022142711A1
WO2022142711A1 PCT/CN2021/128158 CN2021128158W WO2022142711A1 WO 2022142711 A1 WO2022142711 A1 WO 2022142711A1 CN 2021128158 W CN2021128158 W CN 2021128158W WO 2022142711 A1 WO2022142711 A1 WO 2022142711A1
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chip
stacked
package
unit
area
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PCT/CN2021/128158
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English (en)
French (fr)
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刘欢
戴强
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浙江驰拓科技有限公司
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Publication of WO2022142711A1 publication Critical patent/WO2022142711A1/zh

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Definitions

  • the invention relates to the field of chip packaging, in particular to a chip stacking and sealing method, a stacking packaging chip and an electronic storage device.
  • the chip stacking technology has emerged. As shown in Figure 1, although the technology of stacking multiple chips to multiply the storage space by using the same area is feasible, the existing chip stacking technology usually firstly cuts the overlapping wafers uniformly, and after the cutting is completed Then select qualified chips from many single-chip chips, and then stick the chips to obtain a stacked chip set, and then package it to obtain a stacked-package chip.
  • the purpose of the present invention is to provide a chip stacking method, stack packaging chip and electronic storage device, so as to solve the problems of complex chip stacking technology, low efficiency and large stacking thickness in the prior art.
  • the present invention provides a chip stacking method, including:
  • the multi-layered wafers to be processed are fixedly connected to obtain a laminated wafer group; wherein, the laminated wafer group includes multiple groups of laminated chip groups; the laminated chip group includes a plurality of unit chips, and the unit chips include a cutting area and a microcircuit area; the cutting area includes through holes, and the pads of the unit chips are arranged inside the through holes; the through holes of different unit chips in the same stacked chip group form a cavity passing through the stacked chip group ;
  • the stacked chip set is signal-connected to the package substrate by using the cavity to obtain a stacked package chip.
  • the method before stacking multiple layers of wafers to be processed, the method further includes:
  • a thinning process is performed on the to-be-processed wafer.
  • using the cavity to signally connect the stacked chip set and the package substrate to obtain the stacked package chip includes:
  • the laminated chip set and the package substrate are signally connected by using the cavity, and the laminated chip set and the package substrate are fixedly connected by bonding to obtain a laminated package chip.
  • the dicing of the stacked wafer group according to the dicing area includes:
  • the fixedly connecting the multiple layers of the wafer to be processed includes:
  • the multiple layers of the wafers to be processed are fixedly connected using DAF technology.
  • a stacked package chip comprising a package substrate and a stacked chip set
  • the stacked chip set includes a plurality of unit chips arranged in an overlapping manner; the adjacent unit chips are fixedly connected;
  • the unit chip includes a microcircuit area and a cutting area; the cutting area includes a through hole, and the pad of the unit chip is disposed inside the through hole;
  • the through holes of different unit chips are communicated with each other to form a cavity passing through the stacked package chip;
  • the stacked chip set and the package substrate are signally connected through the cavity.
  • the through hole and the pad are disposed on the first side of the unit chip
  • the through holes of the upper unit chip are arranged corresponding to the pads of the immediately lower unit chip.
  • the area of the through hole is 1 to 3 times the area of the pad, inclusive.
  • the thickness of the unit chip ranges from 50 microns to 280 microns, inclusive.
  • An electronic storage device comprising the package-on-package chip as described above.
  • the chip stacking method provided by the present invention includes stacking multiple layers of wafers to be processed; fixing and connecting the multiple layers of the wafers to be processed to obtain a stacked wafer group; wherein, the stacked wafer group includes multiple groups of stacked chips
  • the stacked chip set includes a plurality of unit chips, and the unit chips include a dicing area and a microcircuit area; the dicing area includes a through hole, and the pads of the unit chip are arranged inside the through hole; the same stack
  • the through holes of different unit chips in the chip set form a cavity passing through the laminated chip set; according to the dicing of the laminated wafer set in the dicing area, a plurality of independent laminated chip sets are obtained; using the cavity
  • the cavity signally connects the stacked chip set and the package substrate to obtain a stacked package chip.
  • an area (ie, the dicing area) of through-holes that can be externally connected to the pads of each unit chip is reserved on the to-be-processed wafer, so that the Directly after stacking and calibrating the position of the wafer to be processed, it is directly fixed and connected and then cut, so that after cutting, what is obtained is no longer a single unit chip, but a laminated chip group that has been laminated and connected, that is, the whole chip.
  • the chip set composed of all chips on the wafer only needs one position calibration, which avoids the step of needing one calibration for each packaged chip in the prior art, which greatly simplifies the chip stacking process and improves the stacking efficiency.
  • the cavity formed by the through hole can be directly connected to the pad of the unit chip, it is not necessary to set a large distance between adjacent unit chips to facilitate signal connection, thereby reducing the thickness of the stacked package chip.
  • the present invention also provides a stacked package chip and an electronic storage device with the above beneficial effects.
  • FIG. 1 is a schematic structural diagram of a package-on-package chip in the prior art
  • FIG. 2 is a schematic flowchart of a specific embodiment of the chip stacking method provided by the present invention.
  • FIG. 3 is an intermediate process flow diagram of a specific embodiment of the chip stacking method provided by the present invention.
  • FIG. 4 to FIG. 10 are schematic structural diagrams of different embodiments of the package-on-package chip provided by the present invention.
  • the core of the present invention is to provide a chip stacking method, and a schematic flowchart of a specific implementation manner is shown in FIG.
  • the method before stacking multiple layers of wafers to be processed, the method further includes:
  • a thinning process is performed on the to-be-processed wafer.
  • the wafers are thinned to the required thickness (50 ⁇ m-280 ⁇ m) for packaging, and then stacked after reaching the preset thickness. It should be noted that, after the wafer to be processed is designed to be cavitated, that is, the through hole 221 is obtained, and then the wafer to be processed is thinned, which can greatly improve the yield of finished products.
  • S102 Fixedly connecting multiple layers of the to-be-processed wafers to obtain a laminated wafer group; wherein, the laminated wafer group includes multiple groups of laminated chip groups 20; the laminated chip group 20 includes a plurality of unit chips, and the unit chips
  • the chip includes a dicing area 220 and a microcircuit area 210; the dicing area 220 includes a through hole 221, and the pads 211 of the unit chip are arranged inside the through hole 221; Holes 221 form cavities through the stacked chip set 20 .
  • the stacked chip set 20 is a group of chips that are projected and overlapped in a direction perpendicular to the surface of the stacked wafer set.
  • FIG. 3 is a schematic view of the structure of the package-on-package wafer during the preparation process.
  • the left side of FIG. 3 shows two stacked wafers to be processed, and the right side shows one of the stacked chip sets 20 , wherein wafer refers to two different wafers.
  • wafer refers to two different wafers.
  • CHIP1 and CHIP2 refer to different unit chips, and the same is true for the other figures below.
  • the multiple layers of the wafers to be processed are fixedly connected using DAF technology.
  • DAF technology DAF technology
  • other wafer bonding techniques can also be used according to the actual situation.
  • contactless dicing is performed on the stacked wafer group according to the dicing area 220 .
  • the use of non-contact dicing can reduce the poor dicing caused by stress and ensure the integrity of the chip.
  • the laminated chip set 20 and the packaging substrate 10 are fixedly connected by means of adhesive.
  • other means may also be used to connect the stacked chip set 20 and the package substrate 10 .
  • Step S104 specifically includes subsequent encapsulation processes such as filling, marking, electroplating, and rib cutting, which will not be repeated here.
  • the signal connection may be a signal connection realized by the lead 30, or the bonding pad 211 may be connected to the pad 211 by using the cavity by other means.
  • the laminated wafer group after the laminated wafer group is obtained, it can also be screened to remove the unqualified laminated wafer group, so as to avoid the waste of resources caused by the subsequent processing of the unqualified wafer group.
  • the chip stacking method provided by the present invention includes stacking multiple layers of wafers to be processed; fixing and connecting the multiple layers of the wafers to be processed to obtain a stacked wafer group; wherein, the stacked wafer group includes multiple groups of stacked chips group 20; the stacked chip group 20 includes a plurality of unit chips, the unit chips include a dicing area 220 and a microcircuit area 210; the dicing area 220 includes through holes 221, and the pads 211 of the unit chips are arranged on the the inside of the through hole 221; the through holes 221 of different unit chips in the same stacked chip set 20 form a cavity passing through the stacked chip set 20; according to the dicing area 220, the stacked wafer set is diced to obtain A plurality of independent stacked chip groups 20; the stacked chip groups 20 are signal-connected to the package substrate 10 by using the cavity to obtain a stacked package chip.
  • an area (ie, the dicing area 220 ) of the through-hole 221 that can be externally connected to the pads 211 of each unit chip is reserved on the to-be-processed wafer. , so directly after stacking and calibrating the position of the wafers to be processed, the fixed connection can be directly performed and then cut, so that the obtained after cutting is no longer a single unit chip, but a stacked chip set that has been stacked and connected. 20.
  • a chip set composed of all chips on the entire wafer only needs to be calibrated once, which avoids the step of needing one calibration for each packaged chip in the prior art, which greatly simplifies the chip stacking process and improves the stacking performance.
  • the cavity formed by the through hole 221 can be directly connected to the pad 211 of the unit chip, it is not necessary to set a large distance between the adjacent unit chips to facilitate the signal connection. The thickness of the package-on-package chip is reduced.
  • the present invention also provides a package-on-package chip, and a schematic structural diagram of a specific embodiment of the chip is shown in FIG.
  • the stacked chip set 20 includes a plurality of unit chips arranged in an overlapping manner; the adjacent unit chips are fixedly connected;
  • the unit chip includes a microcircuit area 210 and a cutting area 220; the cutting area 220 includes a through hole 221, and the pad 211 of the unit chip is disposed inside the through hole 221;
  • the through holes 221 of different unit chips are connected with each other to form a cavity passing through the stacked package chip;
  • the stacked chip set 20 is signally connected to the package substrate 10 through the cavity.
  • the through hole 221 and the pad 211 are disposed on the first side of the unit chip
  • the through holes 221 of the upper unit chip are arranged corresponding to the pads 211 of the immediately lower unit chip.
  • the stacked chip set 20 may not only include two of the unit chips, and FIG. 5 is a schematic structural diagram of the stacked chip set 20 including three of the unit chips.
  • FIG. 6 is a schematic diagram of the structure of three consecutive groups of the stacked package chips on the wafer when they are in an uncut state. It can be seen that the through holes 221 and the pads 211 in the specific embodiment in FIG. 5 are one by one. Correspondingly, the unit chip located above is translated a first distance in a direction perpendicular to the first side edge compared with the unit chip located below. In addition, the through holes 221 do not necessarily correspond to the pads 211 one-to-one, and the through holes 221 on different unit chips do not necessarily have the same shape and size. As shown in FIG. example.
  • the area of the through hole 221 is 1 to 3 times the area of the pad 211, including the endpoint value, such as 1.0 times, 2.0 times, or 3.0 times. Of course, it can also be adjusted according to the actual situation. Choose accordingly.
  • the thickness of the unit chip ranges from 50 microns to 280 microns, inclusive, such as any one of 50.0 microns, 0.0 microns or 280.0 microns.
  • the through holes 221 and the pads 211 can also be arranged on a plurality of different sides. Please refer to the figure.
  • the picture shows that the original pads 211 are etched and deposited by metal deposition through the Trench PVD process.
  • the connection between the pad 211 and the packaging substrate 10 is realized, and preparations are made for the subsequent lamination of the wafer to realize the hierarchical connection.
  • the schematic diagram of the structure on the wafer when it is not diced is shown in Figure 8. Of course, it is not necessary to carry out metal deposition, and then realize the signal connection of different unit chips in the through holes 221 through the wires 30, as shown in FIG. 9 .
  • the stacked package chip provided by the present invention includes a package substrate 10 and a stacked chip set 20; the stacked chip set 20 includes a plurality of overlapping unit chips; the adjacent unit chips are fixedly connected; the unit chips include a microcircuit area 210 and a dicing area 220; the dicing area 220 includes a through hole 221, and the pads 211 of the unit chip are arranged inside the through hole 221; the through holes 221 of different unit chips are connected to each other, forming a through-the-package chip The cavity; the stacked chip set 20 and the package substrate 10 are signally connected through the cavity.
  • an area (ie, the dicing area 220 ) of the through-hole 221 that can be externally connected to the pads 211 of each unit chip is reserved on the to-be-processed wafer. , so directly after stacking and calibrating the position of the wafers to be processed, the fixed connection can be directly performed and then cut, so that the obtained after cutting is no longer a single unit chip, but a stacked chip set that has been stacked and connected. 20.
  • a chip set composed of all chips on the entire wafer only needs to be calibrated once, which avoids the step of needing one calibration for each packaged chip in the prior art, which greatly simplifies the chip stacking process and improves the stacking performance.
  • the cavity formed by the through hole 221 can be directly connected to the pad 211 of the unit chip, there is no need to set a large distance between the adjacent unit chips to facilitate the connection of the leads 30, which realizes The thickness of the package-on-package chip is reduced.
  • the present invention provides an electronic storage device comprising the package-on-package chip as described above.
  • the chip stacking method provided by the present invention includes stacking multiple layers of wafers to be processed; fixing and connecting the multiple layers of the wafers to be processed to obtain a stacked wafer group; wherein, the stacked wafer group includes multiple groups of stacked chips group 20; the stacked chip group 20 includes a plurality of unit chips, the unit chips include a dicing area 220 and a microcircuit area 210; the dicing area 220 includes through holes 221, and the pads 211 of the unit chips are arranged on the the inside of the through hole 221; the through holes 221 of different unit chips in the same stacked chip set 20 form a cavity passing through the stacked chip set 20; according to the dicing area 220, the stacked wafer set is diced to obtain A plurality of independent stacked chip groups 20; the stacked chip groups 20 are signal-connected to the package substrate 10 by using the cavity to obtain a stacked package chip.
  • an area (ie, the dicing area 220 ) of the through-hole 221 that can be externally connected to the pads 211 of each unit chip is reserved on the to-be-processed wafer. , so directly after stacking and calibrating the position of the wafers to be processed, the fixed connection can be directly performed and then cut, so that the obtained after cutting is no longer a single unit chip, but a stacked chip set that has been stacked and connected. 20.
  • a chip set composed of all chips on the entire wafer only needs to be calibrated once, which avoids the step of needing one calibration for each packaged chip in the prior art, which greatly simplifies the chip stacking process and improves the stacking performance.
  • the cavity formed by the through hole 221 can be directly connected to the pad 211 of the unit chip, there is no need to set a large distance between the adjacent unit chips to facilitate the connection of the leads 30, which realizes The thickness of the package-on-package chip is reduced.

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Abstract

一种芯片叠封方法、层叠封装芯片及电子存储设备，通过叠放多层待处理晶圆；固定连接多层所述待处理晶圆，得到层叠晶圆组；其中，所述层叠晶圆组包括多组层叠芯片组；所述层叠芯片组包括多个单元芯片，所述单元芯片包括切割区及微电路区；所述切割区包括通孔，所述单元芯片的焊盘设置于所述通孔内侧；同一层叠芯片组中的不同单元芯片的通孔形成贯穿所述层叠芯片组的空腔；根据所述切割区的对所述层叠晶圆组划片，得到多个独立的层叠芯片组；利用所述空腔将所述层叠芯片组与封装基板信号连接，得到层叠封装芯片。本发明简化了芯片叠封流程，提高了叠封效率。

Description

一种芯片叠封方法、层叠封装芯片及电子存储设备
本申请要求于2020年12月31日提交中国专利局、申请号为202011638414.9、发明名称为“一种芯片叠封方法、层叠封装芯片及电子存储设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及芯片封装领域，特别是涉及一种芯片叠封方法、层叠封装芯片及电子存储设备。
背景技术
随着电子技术在社会各界的发展中占据的位置越来越重要，网络中的数据量也越来越大，这就对存储技术提出了越来越高的要求，而为提供存储芯片的存储容量，存储芯片的面积也就随之水涨船高。
但仅以提高存储芯片面积对存储容量的提升有限，且通过增加面积的方法增大容量也和系统小型化的发展趋势相违背，在这种背景下，芯片叠封技术出现了，其结构示意图如图1所示，将多个芯片层叠从而利用相同的面积成倍增加存储空间加的技术虽然可行，但现有的芯片叠封技术，通常为先对重叠的多张晶圆统一切割，切割完成后再在众多单片芯片中挑选合格的芯片，再粘片，得到层叠芯片组，再封装，得到层叠封装芯片，不难看出，现有技术中需要重复多次叠片，且从众多单片芯片中挑选、组装耗时很长，导致现有技术中芯片叠封效率低下，且为了保证层叠的每张芯片都能与基板信号连接，通常要设置较高的封装高度(即通过图1中的分隔层实现)，以便增加相邻芯片间距，使引线顺利插入实现信号连接。
由上可知，如何找到一种新的芯片叠封方法，避免现有技术中芯片叠封技术复杂，效率低下，叠封厚度大的问题，是本领域技术人员亟待解决的当务之急。
发明内容
本发明的目的是提供一种芯片叠封方法、层叠封装芯片及电子存储设备，以解决现有技术中芯片叠封技术复杂，效率低下，叠封厚度大的问题。
为解决上述技术问题，本发明提供一种芯片叠封方法，包括：
叠放多层待处理晶圆；
固定连接多层所述待处理晶圆，得到层叠晶圆组；其中，所述层叠晶圆组包括多组层叠芯片组；所述层叠芯片组包括多个单元芯片，所述单元芯片包括切割区及微电路区；所述切割区包括通孔，所述单元芯片的焊盘设置于所述通孔内侧；同一层叠芯片组中的不同单元芯片的通孔形成贯穿所述层叠芯片组的空腔；
根据所述切割区的对所述层叠晶圆组划片，得到多个独立的层叠芯片组；
利用所述空腔将所述层叠芯片组与封装基板信号连接，得到层叠封装芯片。
可选地，在所述的芯片叠封方法中，在叠放多层待处理晶圆之前，还包括：
对所述待处理晶圆进行减薄处理。
可选地，在所述的芯片叠封方法中，所述利用所述空腔将所述层叠芯片组与封装基板信号连接，得到层叠封装芯片包括：
利用所述空腔将所述层叠芯片组与封装基板信号连接，并通过粘接将所述层叠芯片组与所述封装基板固定连接，得到层叠封装芯片。
可选地，在所述的芯片叠封方法中，所述根据所述切割区对所述层叠晶圆组划片包括：
根据所述切割区对所述层叠晶圆组进行无接触划片。
可选地，在所述的芯片叠封方法中，所述固定连接多层所述待处理晶圆包括：
利用DAF技术固定连接多层所述待处理晶圆。
一种层叠封装芯片，包括封装基板及层叠芯片组；
所述层叠芯片组包括多个重叠设置的单元芯片；相邻的单元芯片之间固定连接；
所述单元芯片包括微电路区及切割区；所述切割区包括通孔，所述单元芯片的焊盘设置于所述通孔内侧；
不同单元芯片的通孔互相连通，形成贯穿所述层叠封装芯片的空腔；
所述层叠芯片组与所述封装基板通过所述空腔信号连接。
可选地，在所述的层叠封装芯片中，所述通孔与所述焊盘设置于所述单元芯片的第一侧边；
位于上方的单元芯片的通孔与紧邻的位于下方的单元芯片的焊盘对应设置。
可选地，在所述的层叠封装芯片中，所述通孔的面积为所述焊盘的面积的1至3倍，包括端点值。
可选地，在所述的层叠封装芯片中，所述单元芯片的厚度的范围为50微米至280微米，包括端点值。
一种电子存储设备，所述电子存储设备包括如上述任一种所述的层叠封装芯片。
本发明所提供的芯片叠封方法，通过叠放多层待处理晶圆；固定连接多层所述待处理晶圆，得到层叠晶圆组；其中，所述层叠晶圆组包括多组层叠芯片组；所述层叠芯片组包括多个单元芯片，所述单元芯片包括切割区及微电路区；所述切割区包括通孔，所述单元芯片的焊盘设置于所述通孔内侧；同一层叠芯片组中的不同单元芯片的通孔形成贯穿所述层叠芯片组的空腔；根据所述切割区的对所述层叠晶圆组划片，得到多个独立的层叠芯片组；利用所述空腔将所述层叠芯片组与封装基板信号连接，得到层叠封装芯片。
本发明通过在切割所述待处理晶圆前，就在所述待处理晶圆上预留出可从外部连接各个单元芯片的焊盘的通孔的区域(即所述切割区)，因此可直接在叠放并校准所述待处理晶圆位置后，直接进行固定连接再进行切割，这样在切割后得到的就不再是单独的单元芯片，而是已经层叠连接的层叠芯片组，即整张晶圆上的全部芯片组成的芯片组仅需一次位置校准，避免了现有技术中每叠封一个封装芯片都需要一次校准的步骤，大大简化了芯片叠封流程，提高了叠封效率，另一方面，由于所述通孔形成的空腔可直接连接至单元芯片的焊盘，因此也就没有必要在相邻的单元芯片间设置较大间距方便实现信号连接，实现了层叠封装芯片的厚度削减。本发明同时还提供了一种具有上述有益效果的层叠封装芯片及电子存储设备。
附图说明
为了更清楚的说明本发明实施例或现有技术的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的层叠封装芯片的结构示意图；
图2本发明提供的芯片叠封方法的一种具体实施方式的流程示意图；
图3本发明提供的芯片叠封方法的一种具体实施方式的中间工艺流程图；
图4至图10为本发明提供的层叠封装芯片的不同具体实施方式的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的核心是提供一种芯片叠封方法，其一种具体实施方式的流程示意图如图2所示，称其为具体实施方式一，包括：
S101：叠放多层待处理晶圆。
作为一种优选实施方式，在叠放多层待处理晶圆之前，还包括：
对所述待处理晶圆进行减薄处理。
即完成前期的全部晶圆流片及硅通孔221工艺后，将晶圆减薄至封装必须厚度(50μm～280μm)，达到预设的厚度后，再进行叠放。需要注意的是，先对所述待处理晶圆进行设计图形空腔化，即得到所述通孔221之后，再对所述待处理晶圆进行减薄，可大大提升成品的良品率。
S102：固定连接多层所述待处理晶圆，得到层叠晶圆组；其中，所述层叠晶圆组包括多组层叠芯片组20；所述层叠芯片组20包括多个单元芯片，所述单元芯片包括切割区220及微电路区210；所述切割区220包括通孔221，所述单元芯片的焊盘211设置于所述通孔221内侧；同一层叠芯片组20中的不同单元芯片的通孔221形成贯穿所述层叠芯片组20的空 腔。
所述层叠芯片组20为在垂直于所述层叠晶圆组表面的方向上投影重叠的一组芯片。
图3为所述层叠封装晶片在制备过程中的结构示意图，图3左侧为2张叠放的待处理晶圆，而右侧为其中一组层叠芯片组20，其中wafer指两张不同的待处理晶圆，CHIP1、CHIP2指不同的所述单元芯片，下面其他图同理。
作为一种优选实施方式，利用DAF技术固定连接多层所述待处理晶圆。当然，也可根据实际情况采用其他晶圆粘接技术。
S103：根据所述切割区220的对所述层叠晶圆组划片，得到多个独立的层叠芯片组20。
作为一种具体实施方式，根据所述切割区220对所述层叠晶圆组进行无接触划片。采用无接触式划片，可减轻应力造成的划片不良，保证芯片完整。
S104：利用所述空腔将所述层叠芯片组20与封装基板10信号连接，得到层叠封装芯片。
进一步地，所述层叠芯片组20与所述封装基板10通过粘接方式固定连接。当然，也可通过其他手段连接所述层叠芯片组20与所述封装基板10。
步骤S104中具体包括后续的填充、打标、电镀、切筋等封入工艺，在此不再一一赘述。
所述信号连接可以是通过引线30实现的信号连接，也可以通过其他手段利用所述空腔连接所述焊盘211。
另外，在得到所述层叠晶圆组之后，还可对其进行筛片，去除不合格的层叠晶圆组，避免后续对不合格的晶圆组继续加工造成资源浪费。
本发明所提供的芯片叠封方法，通过叠放多层待处理晶圆；固定连接多层所述待处理晶圆，得到层叠晶圆组；其中，所述层叠晶圆组包括多组层叠芯片组20；所述层叠芯片组20包括多个单元芯片，所述单元芯片包括切割区220及微电路区210；所述切割区220包括通孔221，所述单元芯片的焊盘211设置于所述通孔221内侧；同一层叠芯片组20中的不同单元 芯片的通孔221形成贯穿所述层叠芯片组20的空腔；根据所述切割区220的对所述层叠晶圆组划片，得到多个独立的层叠芯片组20；利用所述空腔将所述层叠芯片组20与封装基板10信号连接，得到层叠封装芯片。
本发明通过在切割所述待处理晶圆前，就在所述待处理晶圆上预留出可从外部连接各个单元芯片的焊盘211的通孔221的区域(即所述切割区220)，因此可直接在叠放并校准所述待处理晶圆位置后，直接进行固定连接再进行切割，这样在切割后得到的就不再是单独的单元芯片，而是已经层叠连接的层叠芯片组20，即整张晶圆上的全部芯片组成的芯片组仅需一次位置校准，避免了现有技术中每叠封一个封装芯片都需要一次校准的步骤，大大简化了芯片叠封流程，提高了叠封效率，另一方面，由于所述通孔221形成的空腔可直接连接至单元芯片的焊盘211，因此也就没有必要在相邻的单元芯片间设置较大间距方便实现信号连接，实现了层叠封装芯片的厚度削减。
本发明同时还提供了一种层叠封装芯片，其一种具体实施方式的结构示意图如图4所示，称其为具体实施方式二，包括封装基板10及层叠芯片组20；
所述层叠芯片组20包括多个重叠设置的单元芯片；相邻的单元芯片之间固定连接；
所述单元芯片包括微电路区210及切割区220；所述切割区220包括通孔221，所述单元芯片的焊盘211设置于所述通孔221内侧；
不同单元芯片的通孔221互相连通，形成贯穿所述层叠封装芯片的空腔；
所述层叠芯片组20与所述封装基板10通过所述空腔信号连接。
作为一种优选是实施方式，所述通孔221与所述焊盘211设置于所述单元芯片的第一侧边；
位于上方的单元芯片的通孔221与紧邻的位于下方的单元芯片的焊盘211对应设置。
当然，所述层叠芯片组20不仅可以包括两个所述单元芯片，如图5为包括3个所述单元芯片的层叠芯片组20的结构示意图。
图6为连续3组所述层叠封装芯片，处于未切割状态时，在晶圆上的结构示意图，可以看出，图5中的具体实施方式所述通孔221与所述焊盘211一一对应，且位于上方的单元芯片相比于位于下方的单元芯片向垂直于第一侧边的方向平移了第一距离。另外，所述通孔221不一定与所述焊盘211一一对应，不同单元芯片上的通孔221也不一定形状、大小相同，如图7所示，为通孔221大小不同的具体实施例。
具体地，所述通孔221的面积为所述焊盘211的面积的1至3倍，包括端点值，如1.0倍、2.0倍或3.0倍汇总任一种，当然，也可根据实际情况作相应选择。
作为一种优选实施方式，所述单元芯片的厚度的范围为50微米至280微米，包括端点值，如50.0微米、0.0微米或280.0微米中任一个。
需要注意的是，所述通孔221与所述焊盘211还可设置于多个不同侧边，请见图，图为通过Trench PVD工艺，在原有焊盘211基础上通过刻蚀和金属沉积实现焊盘211和封装基板10的连接，为后续叠层后晶圆实现层级连通做准备工作，其在未划片时在晶圆上的结构示意图如图8所示，当然，也可不进行金属沉积，转而通过引线30在所述通孔221中实现不同单元芯片的信号连接，如图9所示。
本发明提供的层叠封装芯片包括封装基板10及层叠芯片组20；所述层叠芯片组20包括多个重叠设置的单元芯片；相邻的单元芯片之间固定连接；所述单元芯片包括微电路区210及切割区220；所述切割区220包括通孔221，所述单元芯片的焊盘211设置于所述通孔221内侧；不同单元芯片的通孔221互相连通，形成贯穿所述层叠封装芯片的空腔；所述层叠芯片组20与所述封装基板10通过所述空腔信号连接。本发明通过在切割所述待处理晶圆前，就在所述待处理晶圆上预留出可从外部连接各个单元芯片的焊盘211的通孔221的区域(即所述切割区220)，因此可直接在叠放并校准所述待处理晶圆位置后，直接进行固定连接再进行切割，这样在切割后得到的就不再是单独的单元芯片，而是已经层叠连接的层叠芯片组20，即整张晶圆上的全部芯片组成的芯片组仅需一次位置校准，避免了现有技术中每叠封一个封装芯片都需要一次校准的步骤，大大简化了芯片叠封流程，提高了叠封效率，另一方面，由于所述通孔221形成的空腔可直 接连接至单元芯片的焊盘211，因此也就没有必要在相邻的单元芯片间设置较大间距方便引线30连接，实现了层叠封装芯片的厚度削减。
本发明提供一种电子存储设备，所述电子存储设备包括如上述任一种所述的层叠封装芯片。本发明所提供的芯片叠封方法，通过叠放多层待处理晶圆；固定连接多层所述待处理晶圆，得到层叠晶圆组；其中，所述层叠晶圆组包括多组层叠芯片组20；所述层叠芯片组20包括多个单元芯片，所述单元芯片包括切割区220及微电路区210；所述切割区220包括通孔221，所述单元芯片的焊盘211设置于所述通孔221内侧；同一层叠芯片组20中的不同单元芯片的通孔221形成贯穿所述层叠芯片组20的空腔；根据所述切割区220的对所述层叠晶圆组划片，得到多个独立的层叠芯片组20；利用所述空腔将所述层叠芯片组20与封装基板10信号连接，得到层叠封装芯片。
本发明通过在切割所述待处理晶圆前，就在所述待处理晶圆上预留出可从外部连接各个单元芯片的焊盘211的通孔221的区域(即所述切割区220)，因此可直接在叠放并校准所述待处理晶圆位置后，直接进行固定连接再进行切割，这样在切割后得到的就不再是单独的单元芯片，而是已经层叠连接的层叠芯片组20，即整张晶圆上的全部芯片组成的芯片组仅需一次位置校准，避免了现有技术中每叠封一个封装芯片都需要一次校准的步骤，大大简化了芯片叠封流程，提高了叠封效率，另一方面，由于所述通孔221形成的空腔可直接连接至单元芯片的焊盘211，因此也就没有必要在相邻的单元芯片间设置较大间距方便引线30连接，实现了层叠封装芯片的厚度削减。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求 或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上对本发明所提供的芯片叠封方法、层叠封装芯片及电子存储设备进行了详细介绍。本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本发明进行若干改进和修饰，这些改进和修饰也落入本发明权利要求的保护范围内。

Claims (10)

  1. 一种芯片叠封方法，其特征在于，包括：
    叠放多层待处理晶圆；
    固定连接多层所述待处理晶圆，得到层叠晶圆组；其中，所述层叠晶圆组包括多组层叠芯片组；所述层叠芯片组包括多个单元芯片，所述单元芯片包括切割区及微电路区；所述切割区包括通孔，所述单元芯片的焊盘设置于所述通孔内侧；同一层叠芯片组中的不同单元芯片的通孔形成贯穿所述层叠芯片组的空腔；
    根据所述切割区的对所述层叠晶圆组划片，得到多个独立的层叠芯片组；
    利用所述空腔将所述层叠芯片组与封装基板信号连接，得到层叠封装芯片。
  2. 如权利要求1所述的芯片叠封方法，其特征在于，在叠放多层待处理晶圆之前，还包括：
    对所述待处理晶圆进行减薄处理。
  3. 如权利要求1所述的芯片叠封方法，其特征在于，所述利用所述空腔将所述层叠芯片组与封装基板信号连接，得到层叠封装芯片包括：
    利用所述空腔将所述层叠芯片组与封装基板信号连接，并通过粘接将所述层叠芯片组与所述封装基板固定连接，得到层叠封装芯片。
  4. 如权利要求1所述的芯片叠封方法，其特征在于，所述根据所述切割区对所述层叠晶圆组划片包括：
    根据所述切割区对所述层叠晶圆组进行无接触划片。
  5. 如权利要求1所述的芯片叠封方法，其特征在于，所述固定连接多层所述待处理晶圆包括：
    利用DAF技术固定连接多层所述待处理晶圆。
  6. 一种层叠封装芯片，其特征在于，包括封装基板及层叠芯片组；
    所述层叠芯片组包括多个重叠设置的单元芯片；相邻的单元芯片之间固定连接；
    所述单元芯片包括微电路区及切割区；所述切割区包括通孔，所述单元芯片的焊盘设置于所述通孔内侧；
    不同单元芯片的通孔互相连通，形成贯穿所述层叠封装芯片的空腔；
    所述层叠芯片组与所述封装基板通过所述空腔信号连接。
  7. 如权利要求6所述的层叠封装芯片，其特征在于，所述通孔与所述焊盘设置于所述单元芯片的第一侧边；
    位于上方的单元芯片的通孔与紧邻的位于下方的单元芯片的焊盘对应设置。
  8. 如权利要求7所述的层叠封装芯片，其特征在于，所述通孔的面积为所述焊盘的面积的1至3倍，包括端点值。
  9. 如权利要求6所述的层叠封装芯片，其特征在于，所述单元芯片的厚度的范围为50微米至280微米，包括端点值。
  10. 一种电子存储设备，其特征在于，所述电子存储设备包括如权利要求6至9任一项所述的层叠封装芯片。
PCT/CN2021/128158 2020-12-31 2021-11-02 一种芯片叠封方法、层叠封装芯片及电子存储设备 WO2022142711A1 (zh)

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