WO2022142343A1 - 太阳能电池及其制备方法 - Google Patents

太阳能电池及其制备方法 Download PDF

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WO2022142343A1
WO2022142343A1 PCT/CN2021/110869 CN2021110869W WO2022142343A1 WO 2022142343 A1 WO2022142343 A1 WO 2022142343A1 CN 2021110869 W CN2021110869 W CN 2021110869W WO 2022142343 A1 WO2022142343 A1 WO 2022142343A1
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layer
solar cell
hydrogenated
substrate
transparent conductive
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PCT/CN2021/110869
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French (fr)
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胡玉婷
万义茂
袁声召
于元元
杨斌
庄宇峰
张文超
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东方日升新能源股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of battery technology, in particular to a solar cell and a preparation method thereof.
  • Passivated contact cell is a new type of high conversion efficiency cell, the conversion efficiency can reach more than 24%.
  • the structure of passivated contact cells is relatively simple, the feasibility of mass production is high, and the production cost has certain advantages.
  • passivation contact cells are more compatible with conventional production lines. Well, the upgrade can be completed by simply transforming the N-type conventional production line.
  • silver paste is used to achieve metallization in passivated contact cells, although silver has the advantages of good electrical conductivity, low work function, good solderability, and it is not easy to form deep level defects in silicon.
  • the price is relatively high, and the silver paste often has to corrode part of the silicon through the glass frit to form an ohmic contact.
  • the polysilicon film is required to be thicker.
  • a solar cell including:
  • the solar cell further includes an upper electrode and a lower electrode, the upper electrode is located on the upper surface of the passivation layer and penetrates the passivation layer and forms an ohmic contact with the diffusion layer, and the lower electrode is located on the passivation layer.
  • a hydrogenated transparent conductive film is used to replace the passivation layer on the surface of the doped polysilicon layer. Since the hydrogenated transparent conductive film has good electrical properties and can form a good ohmic contact with the lower electrode, the lower electrode of this application only needs to be set in The surface of the hydrogenated transparent conductive film is sufficient. It is not necessary to penetrate the hydrogenated transparent conductive film to form ohmic contact with the doped polysilicon layer. On the one hand, the thickness of the doped polysilicon layer can be reduced. On the other hand, aluminum electrodes can be used instead of silver electrodes or Silver aluminum electrodes, therefore, can effectively reduce the cost of solar cells.
  • the J0 of this region is close to or equal to that of the non-metallic contact region, which can effectively improve the conversion efficiency of the solar cell.
  • the substrate is an N-type substrate or a P-type substrate.
  • the diffusion layer is a p+ layer or an n+ layer
  • the passivation layer is at least one of a silicon oxide layer, an aluminum oxide layer or a silicon nitride stack, and the doped polysilicon layer is an n+ polysilicon layer,
  • the passivation layer is at least one of a silicon oxide layer or a silicon nitride stack, and the doped polysilicon layer is a p+ polysilicon layer.
  • the material of the hydrogenated transparent conductive film is selected from one of AZO:H, IO:H, IWO:H, and FTO:H, and the thickness of the hydrogenated transparent conductive film is 30nm-150nm.
  • the upper electrode is selected from a silver electrode or a silver-aluminum electrode.
  • the thickness of the silicon oxide layer is 0.5 nm-3 nm, and the thickness of the doped polysilicon layer is 30 nm-200 nm.
  • a method for preparing a solar cell comprising the following steps:
  • Texturing texture the substrate to form a textured structure with light trapping effect
  • Diffusion forming a diffusion layer on the upper surface of the substrate
  • Etching remove the pn junction on the lower surface of the substrate
  • Oxidation forming a silicon oxide layer on the lower surface of the substrate
  • doped amorphous silicon is formed on the lower surface of the silicon oxide layer, and then the doped amorphous silicon is crystallized under a high temperature process to activate doping atoms to form a doped polysilicon layer;
  • silicon oxide is formed by thermal oxidation or PECVD, aluminum oxide is deposited by ALD or PECVD, and silicon nitride is deposited by PECVD;
  • Deposition of hydrogenated transparent conductive film using PVD or RPD method to deposit hydrogenated transparent conductive film on the outside of the doped polysilicon layer;
  • An upper electrode and a lower electrode are formed, wherein an aluminum paste is selected when forming the lower electrode.
  • the method for forming a silicon oxide layer on the lower surface of the substrate is selected from LPCVD, thermal oxidation or wet oxidation, and the thickness of the silicon oxide layer is 0.5 nm-3 nm.
  • the method for forming doped amorphous silicon on the lower surface of the silicon oxide layer is selected from LPCVD or PECVD, and the temperature for crystallizing the doped amorphous silicon and activating the doped atoms is 600° C. -1000°C, the thickness of the doped polysilicon layer is 30nm-200nm.
  • the hydrogenated transparent conductive film is one of AZO:H, IO:H, IWO:H, and FTO:H, and the thickness is 30nm-150nm.
  • the power is 100W-12000W
  • the oxygen flow is 10sccm-50sccm
  • the hydrogen flow is 10sccm-50sccm.
  • the upper electrode and the lower electrode are formed by screen printing and sintering, aluminum paste is printed on one side of the hydrogenated transparent conductive film, and silver paste or silver-aluminum paste is printed on the passivation layer side. Sintering at 700°C-850°C forms electrode contacts.
  • FIG. 1 is a schematic structural diagram of a solar cell in the present application.
  • FIG. 1 a schematic structural diagram of a solar cell provided by the present application, the solar cell includes:
  • the diffusion layer 2 and the passivation layer 3 located on the upper surface of the substrate 1 in turn,
  • the solar cell further includes an upper electrode 7 and a lower electrode 8, the upper electrode 7 is located on the upper surface of the passivation layer 3 and penetrates the passivation layer 3 and forms ohmic contact with the diffusion layer 2, so
  • the lower electrode 8 is located on the lower surface of the hydrogenated transparent conductive film 6, wherein the lower electrode 8 is selected from aluminum electrodes.
  • the transparent conductive film (TCO film) has good optical and electrical properties, its passivation ability is poor, so it is generally only used for heterojunction cells or thin film cells, but not for crystalline silicon cells. Because the passivation performance of amorphous silicon in heterojunction cells or thin film cells is much higher than that of crystalline silicon cells, but serious light absorption leads to low current, so transparent conductive films are required to enhance optical absorption and electrical transport capabilities, thereby improving The passivation performance of the crystalline silicon cell itself is slightly worse than that of the heterojunction cell or the thin film cell, but the optical absorption is better, so good passivation performance and electrical transport capability are required.
  • the hydrogenated TCO film 6 has good electrical properties and can form a good ohmic contact with the lower electrode 8
  • the lower electrode 8 of the present application only needs to be disposed on the surface of the hydrogenated TCO film 6, and does not need to penetrate the hydrogenated TCO film 6 to form an ohmic contact with the doped polysilicon layer 5 .
  • the thickness of the doped polysilicon layer 5 can be reduced. In one or more embodiments, the thickness of the doped polysilicon layer 5 is 30 nm-200 nm.
  • the thickness of the doped polysilicon layer 5 is 30nm-80nm; on the other hand, aluminum electrodes can be used instead of silver electrodes or silver aluminum electrodes, and the cost of aluminum electrodes is much lower than that of silver electrodes or silver aluminum electrodes. Therefore, the cost of the solar cell can be effectively reduced.
  • the lower electrode 8 adopts an aluminum electrode
  • the passivation performance of the hydrogenated TCO film 6 is significantly improved, and at the same time, the open-circuit voltage and short-circuit current can be improved to a certain extent. Therefore, this area The J0 is close to or equal to the J0 of the non-metallic contact area, which can effectively improve the conversion efficiency of the solar cell.
  • the material of the hydrogenated transparent conductive film 6 is selected from one of AZO:H, IO:H, IWO:H, and FTO:H, and the thickness of the hydrogenated transparent conductive film 6 is 30nm-150nm, optionally, the thickness of the hydrogenated transparent conductive film 6 is 50nm-100nm.
  • the thickness of the silicon oxide layer 4 is 0.5 nm-3 nm.
  • the substrate 1 is an N-type substrate or a P-type substrate.
  • the diffusion layer 2 is a p+ layer or an n+ layer, wherein when the diffusion layer 2 is a p+ layer, the passivation layer 3 is a silicon oxide layer, an aluminum oxide layer or a silicon nitride layer in a stack. At least one, the doped polysilicon layer 5 is an n+ polysilicon layer, when the diffusion layer 2 is an n+ layer, the passivation layer 3 is at least one of a silicon oxide layer or a silicon nitride stack, and the doped polysilicon layer 5 is p+ polysilicon layer.
  • Choice of battery structure such as: 1) p+/p-Si/SiOx/n+poly and n+/n-Si/SiOx//p+poly structure, these two are the battery structure with pn junction on the back; 2) p+/n-Si/SiOx/n+poly and n+/p-Si/SiOx//p+poly structures, these two are cell structures with pn junction on the front side.
  • the front diffusion layer 2 is a p+ layer, a silicon oxide layer, an aluminum oxide layer or a silicon nitride stack can be selected as the passivation layer 3, and when the front diffusion layer 2 is an n+ layer, the aluminum oxide layer cannot be selected as the passivation layer 3
  • the diffusion of n+ layer generally uses 5-valent elements, while aluminum is a 3-valent element.
  • aluminum elements enter the diffusion layer due to sintering, the two will compensate each other and reduce the electron concentration, resulting in a decrease in the minority carrier lifetime, which ultimately affects battery efficiency.
  • the upper electrode 7 is selected from a silver electrode or a silver-aluminum electrode.
  • the present application also provides a method for preparing a solar cell, the preparation method comprising the following steps:
  • Texturing texture the substrate 1 to form a textured structure with light trapping effect
  • a diffusion layer 2 is formed on the upper surface of the substrate 1;
  • Etching remove the pn junction on the lower surface of the substrate 1;
  • a silicon oxide layer 4 is formed on the lower surface of the substrate 1;
  • doped polysilicon layer 5 depositing the doped polysilicon layer 5: forming doped amorphous silicon on the lower surface of the silicon oxide layer 4, and then crystallizing the doped amorphous silicon and activating the doped atoms under a high temperature process to form the doped polysilicon layer 5;
  • passivation layer 3 silicon oxide is formed by thermal oxidation or PECVD, aluminum oxide is deposited by ALD or PECVD, and silicon nitride is deposited by PECVD;
  • the upper electrode 7 and the lower electrode 8 are formed, wherein, when the lower electrode 8 is formed, aluminum paste is selected.
  • the method for forming the silicon oxide layer 4 on the lower surface of the substrate 1 is selected from LPCVD, thermal oxidation or wet oxidation, and the thickness of the silicon oxide layer 4 is 0.5 nm-3 nm.
  • the method for forming the doped amorphous silicon on the lower surface of the silicon oxide layer 4 is selected from LPCVD or PECVD, and the temperature for crystallization of the doped amorphous silicon and activation of the doped atoms The temperature is 600° C.-1000° C., and the thickness of the doped polysilicon layer 5 is 30 nm-200 nm.
  • the hydrogenated transparent conductive film 6 is one of AZO:H, IO:H, IWO:H, and FTO:H, and the thickness is 30nm-150nm.
  • the power is 100W-12000W
  • the oxygen flow is 10sccm-50sccm
  • the hydrogen flow is 10sccm-50sccm.
  • the upper electrode 7 and the lower electrode 8 are formed by screen printing and sintering, aluminum paste is printed on the hydrogenated transparent conductive film 6 side, and silver paste is printed on the passivation layer 3 side Or silver-aluminum paste, sintered at 700°C-850°C to form electrode contacts.
  • the substrate 1 is an N-type substrate
  • the diffusion layer 2 is an n+ layer
  • the passivation layer 3 is a silicon oxide/silicon nitride stack
  • the doped polysilicon layer 5 is a p+ layer Polysilicon layer
  • hydrogenated transparent conductive film 6 is selected from AZO:H
  • upper electrode 7 is selected from silver electrode
  • bottom electrode 8 is selected from aluminum electrode.
  • Diffusion In a traditional diffusion furnace tube, a phosphorus diffusion process is performed on the front side of the silicon wafer to form an n+ diffusion layer.
  • the process temperature is 790°C
  • the flow rate of POCl 3 is 1000sccm
  • the time is 900s.
  • the resulting sheet resistance is 100ohm/ ⁇ .
  • Etching The phosphorous expansion area on the back is removed by etching, and an acid solution is generally used for back etching.
  • the acid solution is prepared from HF, HNO 3 and water in a volume ratio of 1:3:6.
  • Oxidation a silicon oxide layer is formed on the upper surface of the substrate by thermal oxidation, and the thickness is controlled to be 1.5 nm.
  • doped polysilicon layer The oxidized silicon wafer is placed in the LPCVD furnace tube, and doped p+ amorphous silicon is formed on the lower surface of the silicon oxide layer by in-situ doping. The doped amorphous silicon is crystallized and the doped atoms are activated to form a doped polysilicon layer with a thickness of 180 nm.
  • passivation layer silicon oxide is formed on the upper surface of the diffusion layer by thermal oxidation, and then silicon nitride is deposited on its surface by PECVD.
  • PVD method was used to deposit a hydrogenated transparent conductive film AZO:H on the outside of the doped polysilicon layer, with a power of 4000W, an oxygen flow of 5 sccm, a hydrogen flow of 5 sccm, and a thickness of 30 nm.
  • the upper electrode and the lower electrode are formed by screen printing and sintering, and the aluminum paste is printed on one side of the hydrogenated transparent conductive film, and the silver paste is printed on the passivation layer side, and the electrodes are formed by sintering at 760 °C contact to complete the manufacture of the battery.
  • the substrate 1 is an N-type substrate
  • the diffusion layer 2 is a p+ layer
  • the passivation layer 3 is a silicon oxide/alumina/silicon nitride stack
  • a doped polysilicon layer 5 is an n+ polysilicon layer
  • the hydrogenated transparent conductive film 6 is selected from AZO:H
  • the upper electrode 7 is selected from silver-aluminum electrodes
  • the lower electrode 8 is selected from aluminum electrodes.
  • Diffusion In the traditional diffusion furnace tube, the B diffusion process is performed on the front side of the silicon wafer to form a p+ diffusion layer.
  • the process temperature is 780 ° C
  • the flow rate of BCl 3 is 250 sccm
  • the time is 600 s.
  • the resulting sheet resistance is 120 ohm/ ⁇ .
  • Etching The boron expansion region on the back is removed by etching, and an acid solution is generally used for back etching.
  • the acid solution is prepared from HF, HNO 3 and water in a volume ratio of 1:3:6.
  • Oxidation a silicon oxide layer is formed on the upper surface of the substrate by thermal oxidation, and the thickness is controlled to be 2 nm.
  • doped polysilicon layer The oxidized silicon wafer is placed in the LPCVD furnace tube, and doped n+ amorphous silicon is formed on the lower surface of the silicon oxide layer by in-situ doping. The doped amorphous silicon is crystallized and the doped atoms are activated to form a doped polysilicon layer with a thickness of 150 nm.
  • silicon oxide is formed on the upper surface of the diffusion layer by thermal oxidation, aluminum oxide is deposited on the surface by PECVD, and silicon nitride is deposited on the surface by PECVD.
  • a hydrogenated transparent conductive film AZO:H is deposited on the outside of the doped polysilicon layer 5 by PVD method, with a power of 8000W, an oxygen flow rate of 20sccm, a hydrogen flow rate of 25sccm, and a thickness of 50nm.
  • the substrate 1 is an N-type substrate
  • the diffusion layer 2 is a p+ layer
  • the passivation layer 3 is a silicon oxide/alumina/silicon nitride stack
  • a doped polysilicon layer 5 is an n+ polysilicon layer
  • the hydrogenated transparent conductive film 6 selects IO:H
  • the upper electrode 7 selects silver-aluminum electrodes
  • the lower electrode 8 selects aluminum electrodes.
  • Diffusion In a traditional diffusion furnace tube, a B diffusion process is performed on the front side of the silicon wafer to form a p+ diffusion layer.
  • the process temperature is 790°C
  • the flow rate of BCl 3 is 250sccm
  • the time is 600s.
  • the resulting sheet resistance is 120ohm/ ⁇ .
  • Etching The boron expansion region on the back is removed by etching, and an acid solution is generally used for back etching.
  • the acid solution is prepared from HF, HNO 3 and water in a volume ratio of 1:3:6.
  • Oxidation a silicon oxide layer is formed on the upper surface of the substrate by LPCVD, and the thickness is controlled to be 2 nm.
  • doped polysilicon layer The oxidized silicon wafer is placed in the LPCVD furnace tube, and doped n+ amorphous silicon is formed on the lower surface of the silicon oxide layer by in-situ doping, and then processed at a high temperature of 600-1000 °C. Next, the doped amorphous silicon is crystallized, and the doped atoms are activated to form a doped polysilicon layer with a thickness of 100 nm.
  • silicon oxide is formed on the upper surface of the diffusion layer by PECVD, aluminum oxide is deposited on the surface by ALD, and silicon nitride is deposited on the surface by PECVD.
  • the substrate 1 is a p-type substrate
  • the diffusion layer 2 is a p+ layer
  • the passivation layer 3 is a silicon oxide/alumina/silicon nitride stack
  • a doped polysilicon layer 5 is an n+ polysilicon layer
  • the hydrogenated transparent conductive film 6 is selected from IWO:H
  • the upper electrode 7 is selected from silver-aluminum electrodes
  • the lower electrode 8 is selected from aluminum electrodes.
  • Diffusion In the traditional diffusion furnace tube, the B diffusion process is performed on the front side of the silicon wafer to form a p+ diffusion layer.
  • the process temperature is 780 ° C
  • the flow rate of BCl 3 is 250 sccm
  • the time is 600 s.
  • the resulting sheet resistance is 120 ohm/ ⁇ .
  • Etching The boron expansion region on the back is removed by etching, and an acid solution is generally used for back etching.
  • the acid solution is prepared from HF, HNO 3 and water in a volume ratio of 1:3:6.
  • Oxidation a silicon oxide layer is formed on the upper surface of the substrate by LPCVD, and the thickness is controlled to be 3 nm.
  • silicon oxide is formed on the upper surface of the diffusion layer by PECVD, aluminum oxide is deposited on the surface by ALD, and silicon nitride is deposited on the surface by PECVD.
  • the hydrogenated transparent conductive film IWO:H was deposited on the outside of the doped polysilicon layer by RPD technology, and deposited by physical vapor deposition (PVD) method, power 10000W, oxygen flow rate 40sccm, hydrogen flow rate 50sccm, thickness is 120nm.
  • PVD physical vapor deposition
  • the upper electrode and the lower electrode are formed by screen printing and sintering, and the aluminum paste is printed on the hydrogenated transparent conductive film side, and the silver aluminum paste is printed on the passivation layer side, and is formed by sintering at 780 °C.
  • the electrodes come into contact, thereby completing the manufacture of the battery.
  • the substrate 1 is a p-type substrate
  • the diffusion layer 2 is a p+ layer
  • the passivation layer 3 is a silicon oxide/alumina/silicon nitride stack
  • a doped polysilicon layer 5 is an n+ polysilicon layer
  • the hydrogenated transparent conductive film 6 is selected from FTO:H
  • the upper electrode 7 is selected as a silver-aluminum electrode
  • the lower electrode 8 is selected as an aluminum electrode.
  • Diffusion In a traditional diffusion furnace tube, a B diffusion process is performed on the front side of the silicon wafer to form a p+ diffusion layer.
  • the process temperature is 800°C
  • the BCl3 flow rate is 250sccm
  • the time is 600s.
  • the resulting sheet resistance is 120ohm/ ⁇ .
  • Etching The boron expansion region on the backside is removed by etching, and an acid solution is generally used for backside etching.
  • the acid solution is prepared from HF, HNO3 and water in a volume ratio of 1:3:6.
  • Oxidation a silicon oxide layer is formed on the upper surface of the substrate by wet oxidation, and the thickness is controlled to be 3 nm.
  • doped polysilicon layer The oxidized silicon wafer is put into the PECVD furnace tube, and doped n+ amorphous silicon is formed on the lower surface of the silicon oxide layer by in-situ doping. The doped amorphous silicon is crystallized and the doped atoms are activated to form a doped polysilicon layer with a thickness of 30 nm.
  • silicon oxide is formed on the upper surface of the diffusion layer by PECVD, aluminum oxide is deposited on the surface by ALD, and silicon nitride is deposited on the surface by PECVD.
  • the hydrogenated transparent conductive film FTO:H is then deposited on the outside of the doped polysilicon layer by PVD method, deposited by physical vapor deposition (PVD) method, power 12000W, oxygen flow rate 50sccm, hydrogen flow rate 50sccm thickness 150nm.
  • PVD physical vapor deposition
  • the upper electrode and the lower electrode are formed by screen printing and sintering, and the aluminum paste is printed on the hydrogenated transparent conductive film side, and the silver aluminum paste is printed on the passivation layer side, and is formed by sintering at 780 °C.
  • the electrodes come into contact, thereby completing the manufacture of the battery.
  • the solar cell efficiency of this application can reach 23.9%-24.1%, which is slightly higher than that of the mainstream contact passivation cell. Because the application uses a transparent conductive film and an aluminum electrode to form an ohmic contact, thereby replacing the conventional passivation film and silver The ohmic contact formed by the electrodes greatly reduces the non-silicon cost of the battery.
  • Comparative Example 1 is a mainstream contact passivation cell, that is, a cell that does not use a hydrogenated TCO film to replace the passivation layer on the surface of polysilicon. The results are shown in Table 1.

Abstract

太阳能电池及其制备方法。太阳能电池包括衬底(1)，依次位于所述衬底(1)上表面的扩散层(2)和钝化层(3)，依次位于所述衬底(1)下表面的氧化硅层(4)、掺杂多晶硅层(5)和氢化透明导电薄膜(6)，以及，所述太阳能电池还包括上电极(7)和下电极(8)，所述上电极(7)位于钝化层(3)的上表面且穿透所述钝化层(3)并与所述扩散层(2)形成欧姆接触，所述下电极(8)位于所述氢化透明导电薄膜(6)的下表面，其中，所述下电极(8)选自铝电极。

Description

太阳能电池及其制备方法
相关申请
本申请要求2020年12月28日申请的，申请号为202011285647.5，发明名称为“一种低成本的高效太阳能电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电池技术领域，特别是涉及太阳能电池及其制备方法。
背景技术
钝化接触电池是新型高转化效率电池，转化效率可达到24％以上。同时，钝化接触电池与异质结电池、背结电池相比结构相对简单，推向量产可行性较高，且生产成本具有一定优势，而且，钝化接触电池与常规产线兼容性较好，对N型常规产线进行简单改造即可完成升级。
目前，钝化接触电池均采用银浆来实现金属化，虽然银具备导电性好、功函数低、可焊性好、不易在硅中形成深能级缺陷等优点。但是，由于其在地壳中含量低，价格比较高，而且，银浆往往要通过其中的玻璃料腐蚀一部分硅来形成欧姆接触，为保证多晶硅层不被烧穿，因此要求多晶硅薄膜比较厚。同时，银浆对钝化层及多晶硅的腐蚀，导致该区域的暗饱和电流密度(J0)高于非金属接触区，从而影响该区域的钝化性能，使硅片内部的一些缺陷形成“复合中心”，这些“复合中心”能捕获太阳光作用下产生的电子空穴，而电子空穴被捕获后，就无法形成有效的电流。因此，如何降低甚至消除掉金属区的复合就成为未来电池提效的关键。
发明内容
根据本申请的各种实施例，提供一种太阳能电池，包括：
衬底，
依次位于所述衬底上表面的扩散层和钝化层，
依次位于所述衬底下表面的氧化硅层、掺杂多晶硅层和氢化透明导电薄膜，
以及，所述太阳能电池还包括上电极和下电极，所述上电极位于钝化层的上表面且穿透所述钝化层并与所述扩散层形成欧姆接触，所述下电极位于所述氢化透明导电薄膜的下表面，其中，所述下电极选自铝电极。
本申请采用氢化透明导电薄膜代替掺杂多晶硅层表面的钝化层，由于氢化透明导电薄膜具有良好的电学性能，可以和下电极形成良好的欧姆接触，所以，本申请的下电极只需要设置于氢化透明导电薄膜的表面即可，不需要穿透氢化透明导电薄膜与掺杂多晶硅层形成欧姆接触，一方面，可以降低掺杂多晶硅层的厚度，另一方面，可以采用铝电极代替银电极或银铝电极，因此，可以有效降低太阳能电池的成本。
另外，下电极采用铝电极时，该区域的J0与非金属接触区的J0接近或者相等，可以有效提高太阳能电池的转化效率。
在其中一个实施例中，所述衬底为N型衬底或者P型衬底。
在其中一个实施例中，所述扩散层为p+层或n+层，
当扩散层为p+层时，钝化层为氧化硅层、氧化铝层或氮化硅叠层中的至少一种，掺杂多晶硅层为n+多晶硅层，
当扩散层为n+层时，钝化层为氧化硅层或氮化硅叠层中的至少一种，掺杂多晶硅层为p+多晶硅层。
在其中一个实施例中，所述氢化透明导电薄膜的材料选自AZO:H，IO:H，IWO:H，FTO:H中的一种，所述氢化透明导电薄膜的厚度为30nm-150nm。
在其中一个实施例中，所述上电极选自银电极或银铝电极。
在其中一个实施例中，所述氧化硅层厚度为0.5nm-3nm，所述掺杂多晶硅层的厚度为30nm-200nm。
根据本申请的各种实施例，还提供一种太阳能电池制备方法，所述制备方法包括以下步骤：
制绒：将衬底制绒，形成具有陷光作用的绒面结构；
扩散：在衬底的上表面形成扩散层；
刻蚀：去除衬底下表面的pn结；
氧化：在衬底的下表面形成氧化硅层；
沉积掺杂多晶硅层：在氧化硅层下表面形成掺杂的非晶硅，然后在高温工艺下对掺杂的非晶硅进行晶化、激活掺杂原子，形成掺杂多晶硅层；
去除BSG和PSG；
沉积钝化层：氧化硅采用热氧化或者PECVD形成，氧化铝采用ALD或者PECVD沉积，氮化硅采用PECVD沉积；
沉积氢化透明导电薄膜：采用PVD或RPD方法在掺杂多晶硅层的外侧沉积氢化透明导电薄膜；
形成上电极和下电极，其中，形成所述下电极时选用铝浆。
在其中一个实施例中，所述在衬底的下表面形成氧化硅层的方法选自LPCVD、热氧化或者湿法氧化，所述氧化硅层厚度为0.5nm-3nm。
在其中一个实施例中，所述在氧化硅层下表面形成掺杂的非晶硅的方法选自LPCVD或PECVD，对掺杂的非晶硅进行晶化、激活掺杂原子的温度为600℃-1000℃，掺杂多晶硅层的厚度为30nm-200nm。
在其中一个实施例中，所述氢化透明导电薄膜为AZO:H，IO:H，IWO:H，FTO:H中的一种，厚度为30nm-150nm。
在其中一个实施例中，所述采用PVD方法在掺杂多晶硅层的外侧沉积氢化透明导电薄膜的步骤中，功率为100W-12000W，氧气流量为10sccm-50sccm，氢气流量10sccm-50sccm。
在其中一个实施例中，所述上电极和所述下电极采用丝网印刷和烧结形成，在氢化透明导电薄膜一侧印刷铝浆，在钝化层一侧印刷银浆或银铝浆，经过700℃-850℃烧结形成电极接触。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为本申请中的太阳能电池的结构示意图。
图中：1、衬底；2、扩散层；3、钝化层；4、氧化硅层；5、掺杂多晶硅层；6、氢化透明导电薄膜；7、上电极；8、下电极。
具体实施方式
以下将对本申请提供的太阳能电池及其制备方法作进一步说明。
如图1所示，为本申请提供的太阳能电池的结构示意图，该太阳能电池包括：
衬底1，
依次位于所述衬底1上表面的扩散层2和钝化层3，
依次位于所述衬底1下表面的氧化硅层4、掺杂多晶硅层5和氢化透明导电薄膜6，
以及，所述太阳能电池还包括上电极7和下电极8，所述上电极7位于钝化层3的上表面且穿透所述钝化层3并与所述扩散层2形成欧姆接触，所述下电极8位于所述氢化透明导电薄膜6的下表面，其中，所述下电极8选自铝电极。
透明导电薄膜(TCO薄膜)虽然具有良好的光学性能和电学性能，但钝化能力较差，所以，一般只用于异质结电池或薄膜电池，而不会用于晶硅电池。因为，异质结电池或薄膜电池中非晶硅的钝化性能远远高于晶硅电池，但吸光严重，导致电流偏低，所以需要透明导电薄膜增强光学吸收和电学输运能力，从而提升电流，而晶硅电池本身钝化性能相对异质结电池或薄膜电池略微差一些，但光学吸收较好，所以需要的是良好的钝化性能和电学输运能力。
本申请人经过长期而深入的研究发现，TCO薄膜经过氢化后，可以增加TCO薄膜的钝化能力，能够满足晶硅电池对钝化的要求，因此，本申请可以采用氢化TCO薄膜6代替掺杂多晶硅层5表面的钝化层。
由于氢化TCO薄膜6具有良好的电学性能，可以和下电极8形成良好的欧姆接触，所以，本申请的下电极8只需要设置于氢化TCO薄膜6的表面即可，不需要穿透氢化TCO薄膜6与掺杂多晶硅层5形成欧姆接触。一方面， 可以降低掺杂多晶硅层5的厚度，在一个或多个实施例中，所述掺杂多晶硅层5的厚度为30nm-200nm，可选地，所述掺杂多晶硅层5的厚度为30nm-80nm；另一方面，可以采用铝电极代替银电极或银铝电极，而铝电极的成本远低于银电极或银铝电极的成本。因此，可以有效降低太阳能电池的成本。
另外，下电极8采用铝电极时，由于氢化TCO薄膜6没有被腐蚀破坏，氢化TCO薄膜6的钝化性能明显提升，同时，开路电压和短路电流均能得到一定程度的提升，所以，该区域的J0与非金属接触区的J0接近或者相等，可以有效提高太阳能电池的转化效率。
在一个或多个实施例中，所述氢化透明导电薄膜6的材料选自AZO:H，IO:H，IWO:H，FTO:H中的一种，所述氢化透明导电薄膜6的厚度为30nm-150nm，可选地，所述氢化透明导电薄膜6的厚度为50nm-100nm。
在一个或多个实施例中，所述氧化硅层4厚度为0.5nm-3nm。
在一个或多个实施例中，衬底1为N型衬底或者P型衬底。
在一个或多个实施例中，扩散层2为p+层或n+层，其中，当扩散层2为p+层时，钝化层3为氧化硅层、氧化铝层或氮化硅叠层中的至少一种，掺杂多晶硅层5为n+多晶硅层，当扩散层2为n+层时，钝化层3为氧化硅层或氮化硅叠层中的至少一种，掺杂多晶硅层5为p+多晶硅层。
电池结构上的选择：如:1)p+/p-Si/SiOx/n+poly和n+/n-Si/SiOx//p+poly结构，这两种就是pn结在背面的电池结构；2)p+/n-Si/SiOx/n+poly和n+/p-Si/SiOx//p+poly结构，这两种就是pn结在正面的电池结构。而当正面扩散层2为p+层时，可选择氧化硅层、氧化铝层或氮化硅叠层作为钝化层3，而正面扩散层2为n+层时，是不能选择氧化铝层作为钝化层3的，因为n+层 扩散一般采用5价元素，而铝是3价元素，当铝元素因为烧结进入扩散层后，两者会相互补偿，降低电子浓度，从而导致少子寿命降低，最终影响电池效率。
在一个或多个实施例中，所述上电极7选自银电极或银铝电极。
本申请还提供一种太阳能电池制备方法，所述制备方法包括以下步骤：
制绒：将衬底1制绒，形成具有陷光作用的绒面结构；
扩散：在衬底1的上表面形成扩散层2；
刻蚀：去除衬底1下表面的pn结；
氧化：在衬底1的下表面形成氧化硅层4；
沉积掺杂多晶硅层5：在氧化硅层4下表面形成掺杂的非晶硅，然后在高温工艺下对掺杂的非晶硅进行晶化、激活掺杂原子，形成掺杂多晶硅层5；
去除BSG和PSG；
沉积钝化层3：氧化硅采用热氧化或者PECVD形成，氧化铝采用ALD或者PECVD沉积，氮化硅采用PECVD沉积；
沉积氢化透明导电薄膜6：采用PVD或RPD方法在掺杂多晶硅层5的外侧沉积氢化透明导电薄膜6；
形成上电极7和下电极8，其中，形成所述下电极8时选用铝浆。
在一个或多个实施例中，所述在衬底1的下表面形成氧化硅层4的方法选自LPCVD、热氧化或者湿法氧化，所述氧化硅层4厚度为0.5nm-3nm。
在一个或多个实施例中，所述在氧化硅层4下表面形成掺杂的非晶硅的方法选自LPCVD或PECVD，对掺杂的非晶硅进行晶化、激活掺杂原子的温度为600℃-1000℃，掺杂多晶硅层5的厚度为30nm-200nm。
在一个或多个实施例中，所述氢化透明导电薄膜6为AZO:H，IO:H， IWO:H，FTO:H中的一种，厚度为30nm-150nm。
在一个或多个实施例中，所述采用PVD方法在掺杂多晶硅层的外侧沉积氢化透明导电薄膜的步骤中，功率为100W-12000W，氧气流量为10sccm-50sccm，氢气流量10sccm-50sccm。
在一个或多个实施例中，所述上电极7和所述下电极8采用丝网印刷和烧结形成，在氢化透明导电薄膜6一侧印刷铝浆，在钝化层3一侧印刷银浆或银铝浆，经过700℃-850℃烧结形成电极接触。
以下，将通过以下具体实施例对所述太阳能电池及其制备方法做进一步的说明。
实施例1
请参阅图1，该实施例的太阳能电池中，衬底1为N型衬底，扩散层2为n+层，钝化层3为氧化硅/氮化硅叠层，掺杂多晶硅层5为p+多晶硅层，氢化透明导电薄膜6选用AZO:H，上电极7选用银电极，下电极8选用铝电极。
本实施例的太阳能电池的制备方法如下：
1)制绒：以N型单晶硅片为衬底，首先采用碱制绒方式在硅片表面形成陷光的绒面，所用的溶液通常为KOH溶液，KOH溶液一般按照KOH:添加剂:H 2O＝20:3:160的体积比配制，温度为80℃。然后在5％的HF溶液中进行清洗，然后再清洗干净硅片表面。
2)扩散：在传统扩散炉管中，对硅片正面进行磷扩散工艺形成n+扩散层，工艺温度为790℃，POCl 3流量1000sccm，时间为900s，形成的方块电阻为100ohm/□。
3)刻蚀：通过刻蚀去除背面磷扩区域，一般采用酸溶液进行背面刻蚀，所述酸溶液由HF、HNO 3以及水按照体积比1:3:6配置得到。
4)氧化：通过热氧化方式在衬底的上表面形成氧化硅层，控制厚度为1.5nm。
5)沉积掺杂多晶硅层：将氧化后的硅片放入LPCVD炉管中，采用原位掺杂的方式在氧化硅层下表面形成掺杂的p+非晶硅，后在920℃高温工艺下对掺杂非晶硅进行晶化、激活掺杂原子，形成掺杂多晶硅层，厚度为180nm。
6)去除BSG和PSG：在体积浓度为2％的HF溶液中进行清洗，去除硅片上下表面的BSG和PSG。
7)沉积钝化层：通过热氧化方式在扩散层上表面形成氧化硅，后用PECVD在其表面沉积氮化硅。
8)沉积氢化透明导电薄膜：随后采用PVD方法在掺杂多晶硅层的外侧沉积氢化透明导电薄膜AZO:H，功率4000W，氧气流量5sccm，氢气流量5sccm，厚度为30nm。
9)形成上电极和下电极：最后采用丝网印刷和烧结形成上电极和下电极，在氢化透明导电薄膜一侧印刷铝浆，在钝化层一侧印刷银浆，经过760℃烧结形成电极接触，从而完成电池的制造。
实施例2
请参阅图1，该实施例的太阳能电池中，衬底1为N型衬底，扩散层2为p+层，钝化层3为氧化硅/氧化铝/氮化硅叠层，掺杂多晶硅层5为n+多晶硅层，氢化透明导电薄膜6选用AZO:H，上电极7选用银铝电极，下电极8选用铝电极。
本实施例中太阳能电池的制备方法如下：
1)制绒：以N型单晶硅片为衬底，首先采用碱制绒方式在硅片表面形成陷光的绒面，所用的溶液通常为KOH溶液，KOH溶液一般按照KOH:添加剂:H 2O＝20:3:160的体积比配制，温度为80℃。然后在5％的HF溶液中进行清洗，然后再清洗干净硅片表面。
2)扩散：在传统扩散炉管中，对硅片正面进行B扩散工艺形成p+扩散层，工艺温度为780℃，BCl 3流量250sccm，时间为600s，形成的方块电阻为120ohm/□。
3)刻蚀：通过刻蚀去除背面硼扩区域，一般采用酸溶液进行背面刻蚀，所述酸溶液由HF、HNO 3以及水按照体积比1:3:6配置得到。
4)氧化：通过热氧化方式在衬底的上表面形成氧化硅层，控制厚度为2nm。
5)沉积掺杂多晶硅层：将氧化后的硅片放入LPCVD炉管中，采用原位掺杂的方式在氧化硅层下表面形成掺杂的n+非晶硅，后在900℃高温工艺下对掺杂非晶硅进行晶化、激活掺杂原子，形成掺杂多晶硅层，厚度为150nm。
6)去除BSG和PSG：在体积浓度2％的HF溶液中进行清洗，去除硅片上下表面的BSG和PSG。
7)沉积钝化层：通过热氧化方式在扩散层上表面形成氧化硅，再采用PECVD在其表面沉积氧化铝，后用PECVD在其表面沉积氮化硅。
8)沉积氢化透明导电薄膜：随后采用PVD方法在掺杂多晶硅层5的外侧沉积氢化透明导电薄膜AZO:H，功率8000W，氧气流量20sccm，氢气流量25sccm，厚度为50nm。
9)形成上电极和下电极：最后采用丝网印刷和烧结形成上电极和下电极，在氢化透明导电薄膜一侧印刷铝浆，在钝化层一侧印刷银铝浆，经过770℃烧结形成电极接触，从而完成电池的制造。
实施例3
请参阅图1，该实施例的太阳能电池中，衬底1为N型衬底，扩散层2为p+层，钝化层3为氧化硅/氧化铝/氮化硅叠层，掺杂多晶硅层5为n+多晶硅层，氢化透明导电薄膜6选用IO:H，上电极7选用银铝电极，下电极8选用铝电极。
本实施例中太阳能电池的制备方法如下：
1)制绒：以N型单晶硅片为衬底，首先采用碱制绒方式在硅片表面形成陷光的绒面，所用的溶液通常为KOH溶液，KOH溶液一般按照KOH:添加剂:H 2O＝20:3:160的体积比配制，温度为80℃。然后在5％的HF溶液中进行清洗，然后再清洗干净硅片表面。
2)扩散：在传统扩散炉管中，对硅片正面进行B扩散工艺形成p+扩散层，工艺温度为790℃，BCl 3流量250sccm，时间为600s，形成的方块电阻为120ohm/□。
3)刻蚀：通过刻蚀去除背面硼扩区域，一般采用酸溶液进行背面刻蚀，所述酸溶液由HF、HNO 3以及水按照体积比1:3:6配置得到。
4)氧化：通过LPCVD方式在衬底的上表面形成氧化硅层，控制厚度为2nm。
5)沉积掺杂多晶硅层：将氧化后的硅片放LPCVD炉管中，采用原位掺杂的方式在氧化硅层下表面形成掺杂的n+非晶硅，后在600-1000℃高温工艺下对掺杂非晶硅进行晶化、激活掺杂原子，形成掺杂多晶硅层，厚度为100nm。
6)去除BSG和PSG：在体积浓度2％的HF溶液中进行清洗，去除硅片上下表面的BSG和PSG。
7)沉积钝化层：通过PECVD在扩散层上表面形成氧化硅，再采用ALD在其表面沉积氧化铝，后用PECVD在其表面沉积氮化硅。
8)沉积氢化透明导电薄膜：随后采用RPD方法在掺杂多晶硅层5的外侧沉积氢化透明导电薄膜IO:H，采用物理气相沉积(PVD)方式沉积，功率9000W，氧气流量30sccm，氢气流量40sccm，厚度为100nm。
9)形成上电极和下电极：最后采用丝网印刷和烧结形成上电极和下电极，在氢化透明导电薄膜一侧印刷铝浆，在钝化层一侧印刷银铝浆，经过770℃烧结形成电极接触，从而完成电池的制造。
实施例4
请参阅图1，该实施例的太阳能电池中，衬底1为P型衬底，扩散层2为p+层，钝化层3为氧化硅/氧化铝/氮化硅叠层，掺杂多晶硅层5为n+多晶硅层，氢化透明导电薄膜6选用IWO:H，上电极7选用银铝电极，下电极8选用铝电极。
本实施例中太阳能电池的制备方法如下：
1)制绒：以P型单晶硅片为衬底，首先采用碱制绒方式在硅片表面形成陷光的绒面，所用的溶液通常为KOH溶液，KOH溶液一般按照KOH:添加剂:H 2O＝20:3:160的体积比配制，温度为80℃。然后在5％的HF溶液中进行清洗，然后再清洗干净硅片表面。
2)扩散：在传统扩散炉管中，对硅片正面进行B扩散工艺形成p+扩散层，工艺温度为780℃，BCl 3流量250sccm，时间为600s，形成的方块电阻为120ohm/□。
3)刻蚀：通过刻蚀去除背面硼扩区域，一般采用酸溶液进行背面刻蚀，所述酸溶液由HF、HNO 3以及水按照体积比1:3:6配置得到。
4)氧化：通过LPCVD在衬底的上表面形成氧化硅层，控制厚度为3nm。
5)沉积掺杂多晶硅层：将氧化后的硅片放入PECVD炉管中，采用原位掺杂的方式在氧化硅层下表面形成掺杂的n+非晶硅，后在900℃高温工艺下对掺杂非晶硅进行晶化、激活掺杂原子，形成掺杂多晶硅层，厚度为50nm。
6)去除BSG和PSG：在体积浓度2％的HF溶液中进行清洗，去除硅片上下表面的BSG和PSG。
7)沉积钝化层：通过PECVD在扩散层上表面形成氧化硅，再采用ALD在其表面沉积氧化铝，后用PECVD在其表面沉积氮化硅。
8)沉积氢化透明导电薄膜：随后采用RPD技术在掺杂多晶硅层的外侧沉积氢化透明导电薄膜IWO:H，采用物理气相沉积(PVD)方式沉积，功率10000W，氧气流量40sccm，氢气流量50sccm，厚度为120nm。
9)形成上电极和下电极：最后采用丝网印刷和烧结形成上电极和下电极，在氢化透明导电薄膜一侧印刷铝浆，在钝化层一侧印刷银铝浆，经过780℃烧结形成电极接触，从而完成电池的制造。
实施例5
请参阅图1，该实施例的太阳能电池中，衬底1为P型衬底，扩散层2为p+层，钝化层3为氧化硅/氧化铝/氮化硅叠层，掺杂多晶硅层5为n+多晶硅层，氢化透明导电薄膜6选用FTO:H，上电极7选用银铝电极，下电极8选用铝电极。
本实施例中太阳能电池的制备方法如下：
1)制绒：以P型单晶硅片为衬底，首先采用碱制绒方式在硅片表面形成陷光的绒面，所用的溶液通常为KOH溶液，KOH溶液一般按照KOH:添加 剂:H 2O＝20:3:160的体积比配制，温度为80℃。然后在2-5％的HF溶液中进行清洗，然后再清洗干净硅片表面。
2)扩散：在传统扩散炉管中，对硅片正面进行B扩散工艺形成p+扩散层，工艺温度为800℃，BCl3流量250sccm，时间为600s，形成的方块电阻为120ohm/□。
3)刻蚀：通过刻蚀去除背面硼扩区域，一般采用酸溶液进行背面刻蚀，所述酸溶液由HF、HNO3以及水按照体积比1:3:6配置得到。
4)氧化：通过湿法氧化方式在衬底的上表面形成氧化硅层，控制厚度为3nm。
5)沉积掺杂多晶硅层：将氧化后的硅片放入PECVD炉管中，采用原位掺杂的方式在氧化硅层下表面形成掺杂的n+非晶硅，后在800℃高温工艺下对掺杂非晶硅进行晶化、激活掺杂原子，形成掺杂多晶硅层，厚度为30nm。
6)去除BSG和PSG：在体积浓度2％的HF溶液中进行清洗，去除硅片上下表面的BSG和PSG。
7)沉积钝化层：通过PECVD在扩散层上表面形成氧化硅，再采用ALD在其表面沉积氧化铝，后用PECVD在其表面沉积氮化硅。
8)沉积氢化透明导电薄膜：随后采用PVD方法在掺杂多晶硅层的外侧沉积氢化透明导电薄膜FTO:H，采用物理气相沉积(PVD)方式沉积，功率12000W，氧气流量50sccm，氢气流量50sccm厚度为150nm。
9)形成上电极和下电极：最后采用丝网印刷和烧结形成上电极和下电极，在氢化透明导电薄膜一侧印刷铝浆，在钝化层一侧印刷银铝浆，经过780℃烧结形成电极接触，从而完成电池的制造。
经模拟，本申请的太阳能电池效率可达到23.9％-24.1％，略高于主流接触钝化电池效率，由于本申请采用透明导电薄膜和铝电极形成欧姆接触，从而代替常规的钝化膜和银电极形成的欧姆接触，大大降低了电池的非硅成本。
对实施例1-5中太阳能电池进行性能检测，包括：开路电压(Voc)、短路电流密度(Jsc)、填充因子(FF)、转换效率(Eta)。对比例1为主流接触钝化电池，即未采用氢化TCO薄膜代替多晶硅表面的钝化层的电池。结果如表1所示。
表1
Figure PCTCN2021110869-appb-000001
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种太阳能电池，其特征在于，包括：
    衬底，
    依次位于所述衬底上表面的扩散层和钝化层，
    依次位于所述衬底下表面的氧化硅层、掺杂多晶硅层和氢化透明导电薄膜，
    以及，所述太阳能电池还包括上电极和下电极，所述上电极位于钝化层的上表面且穿透所述钝化层并与所述扩散层形成欧姆接触，所述下电极位于所述氢化透明导电薄膜的下表面，其中，所述下电极选自铝电极。
  2. 根据权利要求1所述的太阳能电池，其中，所述衬底为N型衬底或者P型衬底。
  3. 根据权利要求1所述的太阳能电池，其中，所述扩散层为p+层或n+层，
    当扩散层为p+层时，钝化层为氧化硅层、氧化铝层或氮化硅叠层中的至少一种，掺杂多晶硅层为n+多晶硅层，
    当扩散层为n+层时，钝化层为氧化硅层或氮化硅叠层中的至少一种，掺杂多晶硅层为p+多晶硅层。
  4. 根据权利要求1所述的太阳能电池，其中，所述氢化透明导电薄膜的材料选自AZO:H，IO:H，IWO:H，FTO:H中的一种，所述氢化透明导电薄膜的厚度为30nm-150nm。
  5. 根据权利要求1所述的太阳能电池，其中，所述上电极选自银电极或银铝电极。
  6. 根据权利要求1所述的太阳能电池，其中，所述氧化硅层厚度为0.5nm-3nm，所述掺杂多晶硅层的厚度为30nm-200nm。
  7. 一种太阳能电池制备方法，其特征在于，所述制备方法包括以下步骤：
    制绒：将衬底制绒，形成具有陷光作用的绒面结构；
    扩散：在衬底的上表面形成扩散层；
    刻蚀：去除衬底下表面的pn结；
    氧化：在衬底的下表面形成氧化硅层；
    沉积掺杂多晶硅层：在氧化硅层下表面形成掺杂的非晶硅，然后在高温工艺下对掺杂的非晶硅进行晶化、激活掺杂原子，形成掺杂多晶硅层；
    去除BSG和PSG；
    沉积钝化层：氧化硅采用热氧化或者PECVD形成，氧化铝采用ALD或者PECVD沉积，氮化硅采用PECVD沉积；
    沉积氢化透明导电薄膜：采用PVD或RPD方法在掺杂多晶硅层的外侧沉积氢化透明导电薄膜；
    形成上电极和下电极，其中，形成所述下电极时选用铝浆。
  8. 根据权利要求7所述的太阳能电池制备方法，其中，所述在衬底的下表面形成氧化硅层的方法选自LPCVD、热氧化或者湿法氧化，所述氧化硅层厚度为0.5nm-3nm。
  9. 根据权利要求7所述的太阳能电池制备方法，其中，所述在氧化硅层下表面形成掺杂的非晶硅的方法选自LPCVD或PECVD，对掺杂的非晶硅进行晶化、激活掺杂原子的温度为600℃-1000℃，掺杂多晶硅层的厚度为30nm-200nm。
  10. 根据权利要求7所述的太阳能电池制备方法，其中，所述氢化透明导电薄膜为AZO:H，IO:H，IWO:H，FTO:H中的一种，厚度为30nm-150nm。
  11. 根据权利要求10所述的太阳能电池制备方法，其中，所述采用PVD方法在掺杂多晶硅层的外侧沉积氢化透明导电薄膜的步骤中，功率为100W-12000W，氧气流量为10sccm-50sccm，氢气流量10sccm-50sccm。
  12. 根据权利要求7所述的太阳能电池制备方法，其中，所述上电极和所述下电极采用丝网印刷和烧结形成，在氢化透明导电薄膜一侧印刷铝浆，在钝化层一侧印刷银浆或银铝浆，经过700℃-850℃烧结形成电极接触。
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