WO2022141953A1 - 一种to封装结构 - Google Patents

一种to封装结构 Download PDF

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WO2022141953A1
WO2022141953A1 PCT/CN2021/087605 CN2021087605W WO2022141953A1 WO 2022141953 A1 WO2022141953 A1 WO 2022141953A1 CN 2021087605 W CN2021087605 W CN 2021087605W WO 2022141953 A1 WO2022141953 A1 WO 2022141953A1
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signal terminal
gold wire
carrier
ground electrode
wire lead
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PCT/CN2021/087605
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English (en)
French (fr)
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和文娟
郑庆立
汪钦
程鹏
孙甫
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武汉光迅科技股份有限公司
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Publication of WO2022141953A1 publication Critical patent/WO2022141953A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/023—Mount members, e.g. sub-mount members
    • H01S5/0232—Lead-frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/02345—Wire-bonding

Definitions

  • the present application belongs to the technical field of optoelectronic communication, and more particularly, relates to a TO packaging structure.
  • the commonly used packaging structure is shown in Figure 1, which consists of a TO base 10, a TO ground electrode 20, a signal terminal 30, a gold wire lead 50, a transmitting component and a receiving component. Since the distance between the TO base 10 and the signal terminal 30 is relatively large, and the signal terminal 30 is an inductive element, the impedance between the signal terminal 30 and the TO base 10 is relatively high, exceeding the design impedance of 25 ⁇ , so that the signal is reflected during the transmission process. Losses are great.
  • This package structure optimizes impedance matching and reduces package parasitic parameters by matching the circuit on the ceramic circuit board of the laser chip carrier on the TO base.
  • the ideal design is a single-ended impedance value. It is 25 ⁇ and the differential impedance value is 50 ⁇ , and the actual production process and raw material parameters will be limited by differences in material uniformity; accuracy errors caused during processing or assembly; impedance of connection points between components and incompletely consistent melting state of solder , so there is a certain gap between the impedance value and the ideal design value.
  • the present application provides a TO package structure, the purpose of which is to reduce the impedance between the signal terminal and the base, and reduce the gap between the actual impedance value and the ideal design value, thereby solving the problem based on the current
  • Some packaging platforms can improve the technical problems of high-frequency performance of TO packaging.
  • a TO package structure includes: a TO base 10, a TO ground electrode 20, a signal terminal 30, a signal terminal carrier 40 and a gold wire lead 50, in:
  • the TO ground electrode 20 and the signal terminal 30 are arranged on the TO base 10;
  • the signal terminal carrier 40 is disposed on the surface of the signal terminal 30, and the signal terminal carrier 40 is connected to the TO ground electrode 20 through the gold wire lead 50;
  • the structure is encapsulated in a closed cavity.
  • the present application also includes the following additional technical features.
  • the signal terminal carrier 40 is pasted on the surface of the signal terminal 30 by conductive glue. After pasting, the level of the signal terminal carrier 40 is smaller than the preset level of the TO ground electrode 20 .
  • the gold wire bonding area on the surface of the signal terminal carrier 40 is plated with a gold layer.
  • the signal terminal carrier 40 is made of alumina ceramics or aluminum nitride ceramics.
  • the signal terminal carrier 40 is a cylinder, specifically one of a square cylinder, a cylinder, a fan-shaped cylinder or a triangular cylinder.
  • the TO ground electrode 20 and the signal terminal 30 are pasted on the TO base 10 by conductive glue.
  • the signal terminal 30 is divided into a first signal terminal 31 and a second signal terminal 32, and the signal terminal carrier 40 is also divided into a first signal terminal carrier 41 and a second signal terminal carrier 42 ,in:
  • the first signal terminal 31 and the second signal terminal 32 are arranged on both sides of the TO ground electrode 20;
  • the gold wire lead 50 is divided into a first gold wire lead 51 and a second gold wire lead 52;
  • the first gold wire lead 51 is connected to the first signal terminal carrier 41 and the TO ground electrode 20;
  • the second gold wire lead 52 is connected to the second signal terminal carrier 42 and the TO ground electrode 20;
  • the signal terminal 30 and the TO ground electrode 20 are connected above the TO base 10 through the first gold wire lead 51 and the second gold wire lead 52 .
  • the first gold wire leads 51 and the second gold wire leads 52 are not in contact; the first gold wire leads 51 are not in contact with each other; the second gold wire leads 52 are not in contact with each other not in contact.
  • the number of the first gold wire leads 51 is one or more; the number of the second gold wire leads 52 is one or more.
  • the diameter of the gold wire lead 50 is 18 ⁇ m, 20 ⁇ m or 25 ⁇ m.
  • the TO ground electrode is directly connected to the signal terminal carrier on the signal terminal through the gold wire lead, avoiding the TO base and reducing the distance from the signal wire to the ground.
  • the reference ground electrode of the entire TO package structure is unified, because the signal wiring
  • the post carrier has capacitive characteristics, the signal post carrier can interact with the inductance of the signal post, reducing the impedance between the signal post and the TO base, achieving better impedance matching, reducing signal reflection, and achieving higher frequencies signal transmission.
  • the TO package structure of the present application only increases the overall material cost of the carrier, and the increase in the material cost is limited;
  • the TO package structure of the present application is used for packaging, and the overall structure of TO remains unchanged, and the materials and production lines are shared with conventional devices, no process modification is required, and it is compatible with conventional module structures.
  • 1 is a schematic diagram of a conventional TO package structure
  • FIG. 2 is a schematic diagram of the TO package structure in the first embodiment
  • Fig. 3 is a conventional TO package structure impedance simulation effect diagram
  • Fig. 4 is the TO package structure impedance simulation effect diagram in the present embodiment one;
  • Fig. 5 is a simulation effect diagram of conventional TO package structure insertion loss
  • Fig. 7 is a simulation effect diagram of conventional TO package structure insertion loss
  • Fig. 9 is the equivalent circuit model of the conventional TO package structure
  • FIG. 10 is an equivalent circuit model of the TO package structure in the first embodiment.
  • 10-TO base 20-TO ground electrode; 30-signal terminal; 31-first signal terminal; 32-second signal terminal; 40-signal terminal carrier; 41-first signal terminal carrier; 42 -The second signal terminal carrier; 50-gold wire lead; 51-first gold wire lead; 52-second gold wire lead; 60-transmitting component; 61-laser chip carrier; 62-laser chip; 70-receiving component ; 71-detector heat sink; 72-detector chip; 80-connection post.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • the single-ended impedance value is 25 ⁇
  • the differential impedance value is 50 ⁇
  • the impedance value between the signal terminal 30 and the TO base 10 is larger than the ideal design value.
  • the first embodiment provides a TO package structure, as shown in FIG. 2, the structure includes: the TO base 10, the TO ground electrode 20, the signal The terminal 30, the signal terminal carrier 40 and the gold wire lead 50, wherein:
  • the TO ground electrode 20 and the signal terminal 30 are arranged on the TO base 10;
  • the signal terminal carrier 40 is disposed on the surface of the signal terminal 30, and the signal terminal carrier 40 is connected to the TO ground electrode 20 through the gold wire lead 50;
  • the structure is encapsulated in a closed cavity.
  • the TO package structure in the first embodiment further includes: a transmitting component 60 , a receiving component 70 and a connecting column 80 , the transmitting component 60 includes a laser chip carrier 61 and a laser chip 62 , and the receiving component 70 includes a detector thermal Shen 71 and detector chip 72, of which:
  • the TO base 10 also has a detector heat sink 71 and a connection post 80;
  • the laser chip carrier 61 is pasted on the TO ground electrode 20 by conductive glue, and the laser chip 62 is arranged on the surface of the laser chip carrier 61;
  • the laser chip carrier 61 is connected with the signal terminal 30 by a gold wire;
  • the detector heat sink 71 and the connection post 80 are connected by gold wire leads;
  • the detector chip 72 is arranged on the surface of the detector heat sink 71, and the detector chip 72 and the TO base 10 are connected by gold wires;
  • the entire structure is encapsulated in a closed cavity.
  • the TO package structure in the first embodiment is applied to a coaxial package device.
  • the detector heat sink 71 is pasted on the TO base 10
  • the detector chip 72 is pasted on the detector heat sink 71
  • a gold wire lead is respectively drawn on both sides as a first gold wire lead 51 and a second gold wire lead 52, and the first gold wire lead 51 is connected to the first signal terminal carrier 41 and the TO ground electrode 20.
  • the second gold wire lead 52 is connected to the second signal terminal carrier 42 and the TO ground electrode 20, the gold wire lead 50 is fixed with gold-tin solder or directly fixed, the laser chip 62 is eutectic welded and fixed on the laser chip carrier 61, and finally The gold wire 50 connects the signal terminal carrier 40 and the TO ground electrode 20, and connects the positive and negative electrodes of the detector chip 72 to the two terminals respectively, so as to power on the detector chip 72 chip.
  • three gold wire leads are respectively set on the first signal terminal 31 and the second signal terminal 32 to be directly connected to the laser chip carrier 61 , and a gold wire is passed between the laser chip carrier 61 and the anode of the laser chip 62 .
  • the wire leads are connected, the detector heat sink 71 and the connecting post 80 are connected by a gold wire lead, and the detector chip 72 and the TO base 10 are connected by a gold wire lead. Since the pad area of the laser chip 62 is limited and the diameter is about 75 ⁇ m, at most one gold wire lead 50 is printed on the laser chip 62 .
  • the two sides of the laser chip carrier 61 are respectively connected with three gold wire leads 50 and the signal terminal 30 , but it should be noted that the more the number of gold wire leads 50 is, the faster the heat conduction is.
  • the parasitic inductance of the gold wire in the TO package structure is relatively large, which will directly affect the transmission of high frequency signals by the TO package structure.
  • the parasitic inductance value of the gold wire is represented by L, which can be estimated by the following formula:
  • ⁇ 0 is the vacuum permeability
  • ⁇ 1 is the relative permeability
  • l 1 is the length of the gold wire
  • d 1 is the diameter of the gold wire
  • ⁇ represents the skin depth
  • the parasitic inductance value of the gold wire will also decrease.
  • the circuit structure is the same as that of FIG. 1 , L1 and C1 represent the TO base 10 at the same time, and L2 and C2 represent the laser chip 72 and the TO ground electrode 20 . During the laser signal process, the receiver assembly 70 does not function.
  • the circuit structure is the same as the structure in FIG. 2 , and the extra capacitor C3 represents the gold wire lead 50 and the signal terminal carrier 40 . Due to the extra part of the capacitor C3, the resistance value of the entire circuit is reduced.
  • the signal terminal carrier 40 is pasted on the surface of the signal terminal 30 by conductive glue. After pasting, the level of the signal terminal carrier 40 is smaller than the preset level of the TO ground electrode 20 . The level of the signal terminal carrier 40 is as close as possible to the level of the TO ground electrode 20. The smaller the preset value, the shorter the length of the gold wire lead 50 and the smaller the parasitic inductance value of the gold wire.
  • the TO package structure transmits high-frequency signals the better the effect.
  • the first signal terminal 31 and the second signal terminal 32 are located on the left and right sides of the TO ground electrode 20 respectively, and the first signal terminal carrier 41 and the second signal terminal carrier 42 are located at the first Above the signal terminal 31 and the second signal terminal 32, the level of the first signal terminal carrier 41 and the second signal terminal carrier 42 is closer to the TO ground electrode 20, and the upper surface of the signal terminal carrier 40 is connected to the TO ground electrode 20. The shorter the length of the gold wires 50 therebetween, the higher the transmission signal frequency of the TO package structure.
  • the gold wire bonding on the surface of the signal terminal carrier 40 Areas are gold plated. Since the signal terminal 30 needs to power on the detector chip 72, it needs to have a conductive function. After the signal terminal carrier 40 is added, the gold wire leads 50 on the surface of the signal terminal carrier 40 also need to conduct electricity and transmit electrical signals. Therefore, the signal The upper surface of the terminal carrier 40 must be plated with a gold layer.
  • the signal terminal The carrier 40 is made of alumina ceramics or aluminum nitride ceramics. Since the signal terminal carrier 40 itself cannot conduct electricity or transmit electrical signals, there is no need to conduct electricity and transmit electrical signals between the signal terminal 30 and the TO ground electrode 20. Therefore, the signal terminal carrier 40 needs to use an insulating material, preferably alumina ceramic or Aluminum nitride ceramics.
  • the signal terminal carrier 40 is a cylinder, specifically one of a square cylinder, a cylinder, a fan-shaped cylinder or a triangular cylinder. In the first embodiment, a square cylinder is selected.
  • the TO ground electrode 20 is pasted on the TO base 10 by conductive adhesive. and the signal terminal 30 .
  • the type of conductive adhesive is H20E from epoxy-tek supplier, and there are many alternative models from other manufacturers.
  • the signal terminal 30 is divided into a first signal terminal 31 and a second signal terminal 32, and the signal terminal carrier 40 is also divided into a first signal terminal A carrier 41 and a second signal terminal carrier 42, wherein:
  • the first signal terminal 31 and the second signal terminal 32 are arranged on both sides of the TO ground electrode 20;
  • the gold wire lead 50 is divided into a first gold wire lead 51 and a second gold wire lead 52;
  • the first gold wire lead 51 is connected to the first signal terminal carrier 41 and the TO ground electrode 20;
  • the second gold wire lead 52 is connected to the second signal terminal carrier 42 and the TO ground electrode 20;
  • the signal terminal 30 and the TO ground electrode 20 are connected above the TO base 10 through the first gold wire lead 51 and the second gold wire lead 52 .
  • the current between the signal terminal 30 and the TO ground electrode 20 not only needs to pass through the TO base 10, but also can pass through the gold wire lead 50, so as to improve the transmission rate.
  • the number of the first gold wire leads 51 is one or more;
  • the number of the second gold wire leads 52 is one or more.
  • the number of the first gold wire lead 51 and the number of the second gold wire lead 52 is one, respectively.
  • the transmission rate of the entire package structure will be higher, but the heat dissipation performance will be reduced.
  • the number of gold wire leads 50 is selected according to the specific situation.
  • the gold wire leads 50 are connected between the signal terminal carrier 40 and the TO ground electrode 20 , the gold wire leads 50 are connected in parallel, the diameter of the gold wire leads 50 increases, and the gold wire parasitic inductance decreases.
  • the diameter of the gold wire lead 50 is 18 ⁇ m, 20 ⁇ m or 25 ⁇ m.
  • the diameter of the gold wire lead 50 is 25 ⁇ m, and the equivalent inductance and resistance are 1nH and 2 ⁇ /mm respectively.
  • the arc height of the gold wire lead 50 is less than or equal to 200 ⁇ m.
  • the length of the gold wire 50 also needs to consider the size of the sealing cavity of the TO package structure.
  • the wire bonding scheme of the gold wire is shown in Figure 2, and it is connected by ball welding. The ball welding is to burn a small ball at the end of the gold wire with a flame, and then weld it with the chip electrode or the gold-plated layer.
  • the photosensitive surface of the detector chip 72 is set on the The center of the TO base 10.
  • the upper surface and the lower surface of the detector chip 72 correspond to the positive electrode and the negative electrode, respectively.
  • the upper surface of the detector chip 72 or the lower surface of the detector chip 72 is selected to directly determine the positive and negative electrodes of the TO structure.
  • Fig. 3 to Fig. 8 are the conventional TO structure and the TO structure in the first embodiment for the positive and negative test simulation results of the TO structure.
  • the simulation software selects the HFSS software tool, and the time domain reflectometry (TDR) increases The edge time is set to 15ps.
  • the test uses passive test instruments, and the test board uses a PCB circuit board with SMA.
  • the simulation software first needs to establish a model.
  • the specific parameters used in the established model are: the diameter of the gold wire lead 50 is 25 ⁇ m, the arc height is 200 ⁇ m, and the lengths of the first gold wire 51 and the second gold wire 52 are respectively 2.5mm , the length of the gold wire between the laser chip 62 and the laser chip carrier 61 is 390 ⁇ m, the number of the gold wire leads of the first signal terminal carrier 41 and the second signal terminal carrier 42 respectively connected to the laser chip carrier 61 is three, The length of each gold wire lead is 1.5mm.
  • the abscissa is the transmission rate, and the ordinate is the impedance value.
  • m1 is the TO glass insulation.
  • the single-ended impedance at the same coordinate is 18 ⁇ ;
  • the impedance of the m2 and m3 signal terminals 30 is 61.2 ⁇ ;
  • m4 is the positive gold wire lead impedance of 50.5 ⁇ ;
  • m5 is the negative electrode impedance of 36.9 ⁇ ;
  • m1 represents the TO glass insulation and the single-ended impedance at the same coordinate is 18 ⁇ ;
  • m2 and m3 represent the signal wiring
  • the impedance of the column 30 is 48 ⁇ ;
  • m4 represents the positive gold wire lead impedance of 40 ⁇ ;
  • m5 represents the negative electrode impedance of 27 ⁇ .
  • the positive circuit and the negative circuit are tested together to fully display the test results. It can be seen from the test results that the results in FIG. 4 are better than those in FIG. 3.
  • the impedance of the signal terminal 30 is reduced by 13.2 ⁇ ; the impedance of the positive gold wire lead is reduced by 10.5 ⁇ ; the negative electrode impedance is reduced by 9.9 ⁇ , and the gap between the actual impedance value and the ideal design value is significantly reduced.
  • the impedance of the signal terminal 30 is reduced by 13.2 ⁇ ; the impedance of the positive gold wire lead is reduced by 10.5 ⁇ ; the negative electrode impedance is reduced by 9.9 ⁇ , and the gap between the actual impedance value and the ideal design value is significantly reduced.
  • the impedance of the signal terminal 30 is reduced by 13.2 ⁇ ; the impedance of the positive gold wire lead is reduced by 10.5 ⁇ ; the negative electrode impedance is reduced by 9.9 ⁇ , and the gap between the actual impedance value and the ideal design value is significantly reduced.
  • the impedance of the signal terminal 30 is reduced
  • the abscissa is the transmission rate, and the ordinate is the insertion loss value.
  • m1 represents the negative 3dB bandwidth of 14Ghz;
  • m2 represents the positive 3dB bandwidth of 20.2Ghz;
  • m1 represents the negative 3dB bandwidth of 19Ghz;
  • m2 represents the positive 3dB bandwidth of 21Ghz.
  • the positive circuit and the negative circuit are tested together to fully display the test results. From the test results, the results in Figure 6 are better than those in Figure 5.
  • the bandwidth results in Figure 6 are higher than those in Figure 5. It is proved that the signal response speed of the TO structure is faster.
  • the abscissa is the rate, and the ordinate is the return loss value.
  • the return loss value represents the reflection value of the signal.
  • m1 and m2 represent the signal reflection value at the 5G frequency;
  • m3 and m4 represent the signal reflection value under the 10G signal. Reflection value. It can be seen from the test results that the results in Figure 8 are better than those in Figure 7.
  • the return loss values are both 5G or 10G
  • the return loss values of m1, m2, m3 and m4 in Figure 8 all decrease, and the reflection value of the signal decreases. .

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Abstract

本申请公开了一种TO封装结构，结构包括：TO底座、TO地电极、信号接线柱、信号接线柱载体和金丝引线，其中：所述TO底座上设置所述TO地电极和所述信号接线柱；所述信号接线柱载体设置于所述信号接线柱表面上且信号接线柱载体通过所述金丝引线与TO地电极相连；所述结构被封装于封闭腔体中。通过金丝引线将TO地电极与信号接线柱上的信号接线柱载体直接连接，避免通过TO底座，减少了信号线到地的距离，整个TO封装结构的参考地电极统一，由于信号接线柱载体有容性特征，信号接线柱载体可以与信号接线柱的电感相作用，降低了信号接线柱与TO底座之间的阻抗，实现更好的阻抗匹配，降低信号反射，实现了更高频率的信号传输。

Description

一种TO封装结构
相关申请的交叉引用
本申请基于申请号为202110004837.3、申请日为2021年01月04日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请属于光电通信技术领域，更具体地，涉及一种TO封装结构。
背景技术
目前应用较广的TO封装方案技术比较成熟，普遍采用的封装结构如图1所示，由TO底座10、TO地电极20、信号接线柱30、金丝引线50、发射组件和接收组件构成，由于TO底座10与信号接线柱30间距较大，且信号接线柱30为感性元件，信号接线柱30与TO底座10之间阻抗较高，超过了25Ω的设计阻抗，使得信号在传输过程中反射损耗很大。这种封装结构通过对TO底座上激光器芯片载体的陶瓷电路板上电路进行匹配设计，优化阻抗匹配，降低了封装寄生参数，但是在高速信号传输的TO封装设计中，理想设计是单端阻抗值为25Ω，差分阻抗值为50Ω，而实际生产工艺和原材料参数都会受到材料均匀性差异的限制；在加工或装配时造成的精度误差；元件之间连接点的阻抗以及焊料不完全一致的熔融状态，因此阻抗值与理想设计值有一定差距。
为了提高封装性能，有一种思路是采取加宽激光器芯片载体的方案来解决，尽可能的让激光器芯片载体上的信号输出焊盘与TO底座上的信号接线柱相近，以缩短金丝引线的长度，减少阻抗性能。但是由于激光器芯片载体受到TO底座面积以及激光器芯片的限制，而且工艺难度较大，无法形 成量产。
随着通信频率要求不断提高，对TO封装结构的高频传输性能提出了进一步的要求，但是电极结构设计继续优化和金丝引线增加提升性能有限，因此提出了新的封装方案。
发明内容
针对现有技术的以上缺陷或改进需求，本申请提供了一种TO封装结构，其目的在于降低信号接线柱与底座之间的阻抗，缩小实际阻抗值与理想设计值差距，由此解决依据现有的封装平台就可以提升TO封装高频性能的技术问题。
为实现上述目的，按照本申请的一个方面，提供了一种TO封装结构，所述结构包括：TO底座10、TO地电极20、信号接线柱30、信号接线柱载体40和金丝引线50，其中：
所述TO底座10上设置所述TO地电极20和所述信号接线柱30；
所述信号接线柱载体40设置于所述信号接线柱30表面上且信号接线柱载体40通过所述金丝引线50与TO地电极20相连；
所述结构被封装于封闭腔体中。
作为对上述方案进一步的完善和补充，本申请还包括以下附加技术特征。
优选地，所述信号接线柱载体40通过导电胶粘贴于信号接线柱30表面上，粘贴后，所述信号接线柱载体40的水平高度小于所述TO地电极20水平高度预设值。
优选地，所述信号接线柱载体40表面的金丝键合区域镀有金层。
优选地，所述信号接线柱载体40采用氧化铝陶瓷或氮化铝陶瓷制作。
优选地，所述信号接线柱载体40为柱体，具体为方形柱体、圆柱体、扇形柱体或三角柱体中的一种。
优选地，所述TO底座10上通过导电胶粘贴所述TO地电极20和所述信号接线柱30。
优选地，所述信号接线柱30分为第一信号接线柱31和第二信号接线柱32，所述信号接线柱载体40也分为第一信号接线柱载体41和第二信号接线柱载体42，其中：
所述第一信号接线柱31和所述第二信号接线柱32设置在所述TO地电极20两侧；
所述金丝引线50分为第一金丝引线51和第二金丝引线52；
所述第一金丝引线51连接所述第一信号接线柱载体41和所述TO地电极20；
所述第二金丝引线52连接所述第二信号接线柱载体42和所述TO地电极20；
通过第一金丝引线51和第二金丝引线52将信号接线柱30与TO地电极20在所述TO底座10上方相连。
优选地，所述第一金丝引线51和所述第二金丝引线52之间不接触；所述第一金丝引线51相互之间不接触；所述第二金丝引线52相互之间不接触。
优选地，所述第一金丝引线51的数量为一根或多根；所述第二金丝引线52的数量为一根或多根。
优选地，所述金丝引线50的直径为18μm、20μm或25μm。
总体而言，通过本申请所构思的以上技术方案与现有技术相比，具有如下有益效果：
1、通过金丝引线将TO地电极与信号接线柱上的信号接线柱载体直接连接，避免通过TO底座，减少了信号线到地的距离，整个TO封装结构的参考地电极统一，由于信号接线柱载体有容性特征，信号接线柱载体可以与信号接线柱的电感相作用，降低了信号接线柱与TO底座之间的阻抗，实 现更好的阻抗匹配，降低信号反射，实现了更高频率的信号传输。
2、本申请的TO封装结构中与现有结构相比整体物料成本只增加了载体，物料成本增加有限；
3、采用本申请的TO封装结构进行封装，TO总体结构不变，与常规器件共用物料及产线，无需进行工艺改造，并与常规模块结构兼容。
附图说明
图1是常规TO封装结构示意图；
图2是本实施例一中的TO封装结构示意图；
图3是常规TO封装结构阻抗仿真效果图；
图4是本实施例一中的TO封装结构阻抗仿真效果图；
图5是常规TO封装结构插损仿真效果图；
图6是本实施例一中的TO封装结构回损仿真效果图；
图7是常规TO封装结构插损仿真效果图；
图8是本实施例一中的TO封装结构回损仿真效果图；
图9是常规TO封装结构的等效电路模型；
图10是本实施例一中的TO封装结构的等效电路模型。
在所有附图中，相同的附图标记用来表示相同的元件或结构，其中：
10-TO底座；20-TO地电极；30-信号接线柱；31-第一信号接线柱；32-第二信号接线柱；40-信号接线柱载体；41-第一信号接线柱载体；42-第二信号接线柱载体；50-金丝引线；51-第一金丝引线；52-第二金丝引线；60-发射组件；61-激光器芯片载体；62-激光器芯片；70-接收组件；71-探测器热沉；72-探测器芯片；80-连接柱。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图 及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。此外，下面所描述的本申请各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
在本申请的描述中，术语“内”、“外”、“纵向”、“横向”、“上”、“下”、“顶”、“底”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请而不是要求本申请必须以特定的方位构造和操作，因此不应当理解为对本申请的限制。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
实施例一：
TO结构的理想设计值中，单端阻抗值为25Ω，差分阻抗值为50Ω，按照常规的TO结构，信号接线柱30与TO底座10之间的阻抗值均大于理想设计值，为了降低信号接线柱30与TO底座10之间的实际阻抗值与理想设计值差距，本实施例一提供一种TO封装结构，如图2所示，所述结构包括：TO底座10、TO地电极20、信号接线柱30、信号接线柱载体40和金丝引线50，其中：
所述TO底座10上设置所述TO地电极20和所述信号接线柱30；
所述信号接线柱载体40设置于所述信号接线柱30表面上且信号接线柱载体40通过所述金丝引线50与TO地电极20相连；
所述结构被封装于封闭腔体中。
如图2所示，本实施例一中的TO封装结构还包括：发射组件60、接收组件70和连接柱80，发射组件60包括激光器芯片载体61和激光器芯片62，接收组件70包括探测器热沉71和探测器芯片72，其中：
TO底座10上除了设置TO地电极20和信号接线柱30以外还有探测器热沉71和连接柱80；
激光器芯片载体61通过导电胶粘贴于TO地电极20上，且所述激光器芯片62设置在激光器芯片载体61表面上；
激光器芯片载体61与信号接线柱30之间通过金丝引线相连；
探测器热沉71和连接柱80之间通过金丝引线相连；
探测器芯片72设置于探测器热沉71表面上，且探测器芯片72与TO底座10之间通过金丝引线相连；
整个结构被封装于封闭腔体中。
本实施例一中的TO封装结构应用于同轴封装器件上，如图2所示，将探测器热沉71粘贴在TO底座10上，再将探测器芯片72粘贴在探测器热沉71上，然后将信号接线柱载体40包含的第一信号接线柱载体41和第二信号接线柱载体42分别粘贴在第一信号接线柱31和第二信号接线柱32上，从与激光器芯片载体61连接的TO地电极20上朝两侧分别打一根金丝引线为第一金丝引线51和第二金丝引线52，第一金丝引线51连接第一信号接线柱载体41和TO地电极20，第二金丝引线52连接第二信号接线柱载体42和TO地电极20，金丝引线50采用金锡焊料固定或者直接固定，将激光器芯片62共晶焊接固定在激光器芯片载体61上，最后金丝引线50通过连接信号接线柱载体40和TO地电极20，将探测器芯片72正负极分别连接在两边接线柱上，实现对探测器芯片72芯片加电。
从图1和图2对比可以看出，由于信号接线柱30上有一根第一金丝引线51和一根第二金丝引线52分别与TO地电极20相连，组成一个新电容结构，缩短了两个信号接线柱30与TO地电极20之间的信号传输连接，而 且整个TO结构参考地电极统一。最后对本实施例一中的TO封装结构进行常规器件级封装，封装成器件后，可以应用于SFP，SFP+等系列模块。
本实施例一中，第一信号接线柱31和第二信号接线柱32上分别设置三根金丝引线与激光器芯片载体61直接相连，激光器芯片载体61与激光器芯片62的阳极之间通过一根金丝引线相连，探测器热沉71与连接柱80之间通过一根金丝引线相连，探测器芯片72与TO底座10之间通过一根金丝引线相连。由于激光器芯片62的焊盘面积受限，直径大约为75μm，因此在激光器芯片62上最多打一根金丝引线50。激光器芯片载体61两侧分别连接三根金丝引线50与信号接线柱30，但是值得注意的是，金丝引线50的数量越多，热传导越快。
本实施例一中，TO封装结构中金丝的寄生电感值较大，会直接影响TO封装结构传输高频信号。
金丝的寄生电感值用L表示，可由下式估算：
Figure PCTCN2021087605-appb-000001
(单位：H)
式中，μ 0是真空磁导率，μ 1是相对磁导率，l 1是金丝长度，d 1是金丝直径，δ表示趋肤深度。
因此，当缩短金丝长度，增大金丝直径，金丝的寄生电感值也会随之降低。
如图9所示，电路结构等同于图1的结构，L1和C1同时代表TO底座10，L2和C2代表激光器芯片72和TO地电极20。在激光器信号过程中，接收组件70不起作用。
如图10所示，电路结构等同于图2的结构，多出来的电容C3代表金丝引线50和信号接线柱载体40。由于多出电容C3的部分，整个电路的电阻值降低。
由图9至图10可以看出，图9电路感性特性比较明显，经过在信号接线柱30上增加信号接线柱载体40，经过每个信号接线柱载体40与所述TO地电极20之间增加一根金丝引线50的优化，等于在电路上增加了电容C3部分，信号接线柱载体40的容性特征与信号接线柱30的电感相作用，降低了信号接线柱30与TO底座10之间的阻抗，实现更好的阻抗匹配。
为了让信号接线柱载体40上表面与TO底座10上的TO地电极20之间的金丝引线50长度尽量缩短，结合本申请实施例，还存在一种优选的实现方案，具体的，如图2所示，所述信号接线柱载体40通过导电胶粘贴于信号接线柱30表面上，粘贴后，所述信号接线柱载体40的水平高度小于所述TO地电极20水平高度预设值。信号接线柱载体40的水平高度尽可能接近TO地电极20的水平高度，预设值越小，金丝引线50的长度越短，金丝的寄生电感值越小，TO封装结构传输高频信号的效果越好。
本实施例一中，第一信号接线柱31和第二信号接线柱32分别位于TO地电极20的左右两侧，第一信号接线柱载体41和第二信号接线柱载体42的位置在第一信号接线柱31和第二信号接线柱32上方，第一信号接线柱载体41和第二信号接线柱载体42的水平高度越靠近TO地电极20，信号接线柱载体40上表面与TO地电极20之间的金丝引线50长度越短，TO封装结构的传输信号频率越高。
为了不影响信号接线柱30传输电信号的功能，结合本申请实施例，还存在一种优选的实现方案，具体的，如图2所示，所述信号接线柱载体40表面的金丝键合区域镀有金层。由于信号接线柱30需要给探测器芯片72加电的，需要有导电功能，增加信号接线柱载体40之后，信号接线柱载体40表面上的金丝引线50也需要导电且传递电信号，因此信号接线柱载体40上表面一定要镀有金层。
为了避免信号接线柱载体40导电和传输电信号，以及降低制作难度及成本价格，结合本申请实施例，还存在一种优选的实现方案，具体的，如 图2所示，所述信号接线柱载体40采用氧化铝陶瓷或氮化铝陶瓷制作。由于信号接线柱载体40本身不能导电也不能传输电信号，信号接线柱30与TO地电极20之间不需要导电且传递电信号，因此信号接线柱载体40需要采用绝缘材料，优选氧化铝陶瓷或氮化铝陶瓷。
为了给信号接线柱载体40选择合适的位置，鉴于信号接线柱30的面积以及金丝引线50的数量有限制，可能需要对信号接线柱30进行形状改变，结合本申请实施例，还存在一种优选的实现方案，具体的，如图2所示，所述信号接线柱载体40为柱体，具体为方形柱体、圆柱体、扇形柱体或三角柱体中的一种。本实施例一中选用的是方形柱体。
为了方便导电以及传输高频信号，结合本申请实施例，还存在一种优选的实现方案，具体的，如图2所示，所述TO底座10上通过导电胶粘贴所述TO地电极20和所述信号接线柱30。导电胶的类型有epoxy-tek供应商的H20E，也有很多其他厂家替代型号。
为了方便连成电路上的回路以及提高传输速率，所述信号接线柱30分为第一信号接线柱31和第二信号接线柱32，所述信号接线柱载体40也分为第一信号接线柱载体41和第二信号接线柱载体42，其中：
所述第一信号接线柱31和所述第二信号接线柱32设置在所述TO地电极20两侧；
所述金丝引线50分为第一金丝引线51和第二金丝引线52；
所述第一金丝引线51连接所述第一信号接线柱载体41和所述TO地电极20；
所述第二金丝引线52连接所述第二信号接线柱载体42和所述TO地电极20；
通过第一金丝引线51和第二金丝引线52将信号接线柱30与TO地电极20在所述TO底座10上方相连。
本实施例一中，信号接线柱30与TO地电极20之间的电流除了需要经 过TO底座10之外，还可以通过金丝引线50，以便于提高传输速率。
为了避免出现TO地电极20表面的金丝引线短路和信号接线柱载体40表面的金丝键合线短路的情况，结合本申请实施例，还存在一种优选的实现方案，具体的，如图2所示，所述第一金丝引线51和所述第二金丝引线52之间不接触。第一金丝引线51相互之间不接触；第二金丝引线52相互之间不接触。
为了以更快的频率传输信号，结合本申请实施例，还存在一种优选的实现方案，具体的，如图2所示，所述第一金丝引线51的数量为一根或多根；所述第二金丝引线52的数量为一根或多根。
本实施例一中，第一金丝引线51和第二金丝引线52的数量分别为一根，在多根金丝引线的情况下，整个封装结构的传输速率会越高，但是散热性能会降低，在实际使用时，根据具体情况选择金丝引线50的数量。
信号接线柱载体40与所述TO地电极20之间若有多根金丝引线50连接，相当于金丝引线50并联，相当于金丝引线50的直径变大，金丝寄生电感值降低。
为了满足现实条件下的需求情况，结合本申请实施例，还存在一种优选的实现方案，具体的，如图2所示，所述金丝引线50的直径为18μm、20μm或25μm。金丝直径越大，金丝的寄生电感值越低，传输效率越好，本实施例一中，金丝引线50的直径为25μm，等效电感和电阻分别是1nH和2Ω/mm，本实施例一中，金丝引线50的弧高小于等于200μm。此外，金丝引线50长度还需要考虑TO封装结构的密封腔体尺寸。金丝的打线方案如图2，并且采用球焊方式连接，球焊是用火焰将金丝端部烧出个小球，然后与芯片电极或者镀金层进行焊接。
为了便于测试传输数据效果以及区分TO结构的正负极，结合本申请实施例，还存在一种优选的实现方案，具体的，如图2所示，所述探测器芯片72的光敏面设置在TO底座10的中心。探测器芯片72的上表面和下表 面分别对应正极和负极，TO结构封装时选用探测器芯片72的上表面或探测器芯片72的下表面直接决定了TO结构的正负极。
例如图3至图8为常规TO结构与本实施例一中的TO结构对于TO结构的正负极测试仿真效果图仿真软件选择HFSS软件工具，时域反射技术(Time domain reflectometry，简称TDR)上升沿时间设置15ps。测试选用无源测试仪器，测试板选用带有SMA的PCB电路板。仿真软件首先需要建立模型，建立的模型使用到的具体参数为：金丝引线50的直径均为25μm，弧高均为200μm，第一金丝51和第二金丝52的长度分别为2.5mm，激光器芯片62与激光器芯片载体61之间的金丝引线长度为390μm，第一信号接线柱载体41与第二信号接线柱载体42分别连接至激光器芯片载体61的金丝引线根数为三根，每根金丝引线的长度为1.5mm。
图3和图4中，横坐标为传输速率，纵坐标为阻抗值，常规TO结构的图3中m1为TO玻璃绝缘同坐标处单端阻抗为18Ω；m2和m3信号接线柱30阻抗为61.2Ω；m4为正极金丝引线阻抗50.5Ω；m5为负极阻抗36.9Ω；本实施例一TO结构的图4中，m1表征TO玻璃绝缘同坐标处单端阻抗为18Ω；m2和m3表征信号接线柱30阻抗为48Ω；m4表征正极金丝引线阻抗40Ω；m5表征负极阻抗27Ω。正极电路与负极电路共同接受测试可以全面展示测试结果，从测试结果看到，图4的结果优于图3，图4中，在每个信号接线柱载体40与所述TO地电极20之间增加一根金丝引线50，信号接线柱30阻抗减小13.2Ω；正极金丝引线阻抗减小10.5Ω；负极阻抗减小9.9Ω，实际阻抗值与理想设计值之间的差距显著缩小，效果显著。
图5和图6中，横坐标为传输速率，纵坐标为插损值，常规TO结构的图5中m1表征负极3dB带宽14Ghz；m2表征正极3dB带宽20.2Ghz；本实施例一TO结构的图6中，m1表征负极3dB带宽19Ghz；m2表征正极3dB带宽21Ghz。正极电路与负极电路共同接受测试可以全面展示测试结果，从测试结果看到，图6的结果优于图5，在插损值同为3dB时，图6 中的带宽结果比图5较高，证明TO结构的信号响应速度越快。
图7和图8中，横坐标为速率，纵坐标为回损值，回损值表征了信号的反射值，图中m1和m2表征5G频率下信号反射值；m3和m4表征10G信号下的反射值。从测试结果看到，图8的结果优于图7，在回损值同为5G或10G时，图8中m1、m2、m3和m4的回损值均有所下降，信号的反射值降低。
从图3至图8的结果可以证明，在信号接线柱30上增加信号接线柱载体40，每个信号接线柱载体40与所述TO地电极20之间增加一根金丝引线50，实际阻抗值与理想设计值之间的差距显著缩小，降低了信号接线柱30与TO底座10之间的阻抗，实现更好的阻抗匹配，带宽值增大，信号回损值降低，降低了信号传输在链路上的反射，实现了更好的信号传输。
本领域的技术人员容易理解，以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种TO封装结构，所述结构包括：TO底座(10)、TO地电极(20)、信号接线柱(30)、信号接线柱载体(40)和金丝引线(50)，其中：
    所述TO底座(10)上设置所述TO地电极(20)和所述信号接线柱(30)；
    所述信号接线柱载体(40)设置于所述信号接线柱(30)表面上且信号接线柱载体(40)通过所述金丝引线(50)与TO地电极(20)相连；
    所述结构被封装于封闭腔体中。
  2. 如权利要求1所述的TO封装结构，其中，所述信号接线柱载体(40)通过导电胶粘贴于信号接线柱(30)表面上，粘贴后，所述信号接线柱载体(40)的水平高度小于所述TO地电极(20)水平高度预设值。
  3. 如权利要求1所述的TO封装结构，其中，所述信号接线柱载体(40)表面的金丝键合区域镀有金层。
  4. 如权利要求1所述的TO封装结构，其中，所述信号接线柱载体(40)采用氧化铝陶瓷或氮化铝陶瓷制作。
  5. 如权利要求1所述的TO封装结构，其中，所述信号接线柱载体(40)为柱体，具体为方形柱体、圆柱体、扇形柱体或三角柱体中的一种。
  6. 如权利要求1所述的TO封装结构，其中，所述TO底座(10)上通过导电胶粘贴所述TO地电极(20)和所述信号接线柱(30)。
  7. 如权利要求1-6任一所述的TO封装结构，其中，所述信号接线柱(30)分为第一信号接线柱(31)和第二信号接线柱(32)，所述信号接线柱载体(40)也分为第一信号接线柱载体(41)和第二信号接线柱载体(42)，其中：
    所述第一信号接线柱(31)和所述第二信号接线柱(32)设置在所述TO地电极(20)两侧；
    所述金丝引线(50)分为第一金丝引线(51)和第二金丝引线(52)；
    所述第一金丝引线(51)连接所述第一信号接线柱载体(41)和所述TO地电极(20)；
    所述第二金丝引线(52)连接所述第二信号接线柱载体(42)和所述TO地电极(20)；
    通过第一金丝引线(51)和第二金丝引线(52)将信号接线柱(30)与TO地电极(20)在所述TO底座(10)上方相连。
  8. 如权利要求7所述的TO封装结构，其中，所述第一金丝引线(51)和所述第二金丝引线(52)之间不接触；所述第一金丝引线(51)相互之间不接触；所述第二金丝引线(52)相互之间不接触。
  9. 如权利要求7所述的TO封装结构，其中，所述第一金丝引线(51)的数量为一根或多根；所述第二金丝引线(52)的数量为一根或多根。
  10. 如权利要求7所述的TO封装结构，其中，所述金丝引线(50)的直径为18μm、20μm或25μm。
PCT/CN2021/087605 2021-01-04 2021-04-15 一种to封装结构 WO2022141953A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN113626977B (zh) * 2021-06-22 2023-10-03 南京光通光电技术有限公司 一种25g dfb激光器高频互联方法
CN113764971B (zh) * 2021-06-30 2022-11-18 武汉敏芯半导体股份有限公司 电吸收调制激光器制冷封装结构

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0496387A (ja) * 1990-08-13 1992-03-27 Nec Corp レーザ・ダイオード・パッケージ
US20050008049A1 (en) * 2003-06-03 2005-01-13 Hirotaka Oomori Optical module including a Peltier device therein and having a co-axial type package
US20050207459A1 (en) * 2004-03-19 2005-09-22 Hitachi Cable, Ltd. Photoelectric conversion module with cooling function
JP2005268362A (ja) * 2004-03-17 2005-09-29 Pioneer Electronic Corp 光ピックアップ装置
US20100008093A1 (en) * 2008-07-10 2010-01-14 Applied Optoelectronics, Inc. Fixture for Securing Optoelectronic Packages for Wire and/or Component Bonding
WO2020066821A1 (ja) * 2018-09-26 2020-04-02 ローム株式会社 半導体レーザ装置
US20200192038A1 (en) * 2018-12-17 2020-06-18 Lumentum Japan, Inc. Optical subassembly and optical module

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202423821U (zh) * 2011-11-21 2012-09-05 武汉华工正源光子技术有限公司 高速激光二极管封装结构
CN106451057A (zh) * 2016-11-30 2017-02-22 武汉光迅科技股份有限公司 一种to结构的低成本可调激光器
CN107219027A (zh) * 2017-07-17 2017-09-29 合肥皖科智能技术有限公司 一种陶瓷电容压力传感器的封装结构
CN107741618B (zh) * 2017-10-31 2019-02-12 武汉电信器件有限公司 一种高速dml发射组件
CN207965238U (zh) * 2017-11-10 2018-10-12 武汉电信器件有限公司 一种滤光片组件及采用该组件的光器件结构
CN207473158U (zh) * 2017-11-30 2018-06-08 武汉光迅科技股份有限公司 一种高速同轴光发射组件
CN108075350A (zh) * 2017-12-19 2018-05-25 深圳市东飞凌科技有限公司 同轴封装激光器
CN209151167U (zh) * 2019-01-04 2019-07-23 武汉电信器件有限公司 一种减小探测器内部跨阻放大器金丝键合地线电感的结构
CN109759973B (zh) * 2019-03-07 2021-07-02 武汉光迅科技股份有限公司 一种box封装器件夹头
CN111987076B (zh) * 2020-08-31 2023-06-16 中国电子科技集团公司第四十四研究所 一种近红外光与可见光的宽光谱光电探测器及其制作方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0496387A (ja) * 1990-08-13 1992-03-27 Nec Corp レーザ・ダイオード・パッケージ
US20050008049A1 (en) * 2003-06-03 2005-01-13 Hirotaka Oomori Optical module including a Peltier device therein and having a co-axial type package
JP2005268362A (ja) * 2004-03-17 2005-09-29 Pioneer Electronic Corp 光ピックアップ装置
US20050207459A1 (en) * 2004-03-19 2005-09-22 Hitachi Cable, Ltd. Photoelectric conversion module with cooling function
US20100008093A1 (en) * 2008-07-10 2010-01-14 Applied Optoelectronics, Inc. Fixture for Securing Optoelectronic Packages for Wire and/or Component Bonding
WO2020066821A1 (ja) * 2018-09-26 2020-04-02 ローム株式会社 半導体レーザ装置
US20200192038A1 (en) * 2018-12-17 2020-06-18 Lumentum Japan, Inc. Optical subassembly and optical module

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