WO2022141522A1 - 一种存储器和计算机 - Google Patents

一种存储器和计算机 Download PDF

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Publication number
WO2022141522A1
WO2022141522A1 PCT/CN2020/142418 CN2020142418W WO2022141522A1 WO 2022141522 A1 WO2022141522 A1 WO 2022141522A1 CN 2020142418 W CN2020142418 W CN 2020142418W WO 2022141522 A1 WO2022141522 A1 WO 2022141522A1
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Prior art keywords
circuit
carry
borrow
signal
output
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PCT/CN2020/142418
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English (en)
French (fr)
Inventor
景蔚亮
王正波
杨一波
崔靖杰
Original Assignee
华为技术有限公司
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Priority to CN202080108229.0A priority Critical patent/CN116670767A/zh
Priority to PCT/CN2020/142418 priority patent/WO2022141522A1/zh
Publication of WO2022141522A1 publication Critical patent/WO2022141522A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory

Definitions

  • the present application relates to the field of computer technology, and in particular, to a memory and a computer.
  • counters are often used a lot.
  • the counter is placed in the processor, the processor calculates the stored value in the memory each time, and the processor reads the memory through the data bus and sends it to the counter. After the counter is completed, The calculation result of the counter is rewritten into the memory via the data bus.
  • the processor needs to transmit data with the memory and the counter.
  • the data bus is seriously occupied, and there is a certain physical distance between the processor and the memory, resulting in a certain amount of data on the data bus.
  • the loss and the long data transmission time on the data bus affect the work efficiency of the counter, and the above calculation method needs to occupy the processor and the data bus for a long time, affecting the realization of other functions of the processor.
  • the present application provides a memory and a computer, which are used to provide a novel memory structure, which can implement a counting function in the memory, improve computing efficiency, and reduce the occupation of data buses and processors.
  • an embodiment of the present application provides a memory, and the memory may include: a storage unit, a carry-borrow determination circuit, and a data write-back circuit. Wherein, the storage unit stores the count start value.
  • the storage unit is respectively connected with the carry-borrow determination circuit and the data write-back circuit, and is used for outputting the count start value to the carry-borrow determination circuit;
  • the carry-borrow determination circuit is connected with the data write-back circuit, and is used for according to the processor
  • the sent first control signal for calculating the count start value and the count start value generate a second control signal;
  • the data write-back circuit is used for receiving the second control signal, and according to the second control signal, stores the data in the storage unit.
  • the count start value is updated.
  • the carry-borrow determination circuit is used to calculate the currently stored count start value, and The latest count starting value obtained after calculation is rewritten into the storage unit through the data write-back circuit, and the whole process of calculation is completed inside the memory, which reduces the data transmission delay and data transmission loss, improves the calculation efficiency, and Alleviate processor and data bus occupancy.
  • the memory may further include: a controller.
  • the controller is configured to control the carry-borrow determination circuit to generate a second control signal when receiving the first control signal, and control the data write-back circuit to update the count start value stored in the storage unit.
  • the processor when the processor needs to perform a logical operation on the initial count value stored in the memory, the processor can send a first control signal to the controller, and the controller controls the carry-borrow determination circuit when receiving the first control signal Calculate the starting count value stored in the storage unit, and use the data write-back circuit to rewrite the calculation result into the storage unit to update the starting count value. The entire calculation process is completed in the memory.
  • the count start value is an N-bit binary value
  • the carry-borrow determination circuit includes: a control circuit, a carry-borrow generating circuit corresponding to each binary value one-to-one, and a carry-borrow bit corresponding to each bit
  • the generating circuits are connected in a one-to-one correspondence with the judging circuits.
  • N can be an integer greater than or equal to 2.
  • the i-th carry-and-borrow generating circuit is used to receive the i-th binary value of the counting start value, and generate the i-th carry-borrow signal according to the first control signal and the i-th binary value, and convert the i-th carry-borrow signal.
  • the i carry-borrow signal is output to the i+1-th carry-borrow generating circuit, and the i+1-th carry-borrow generating circuit receives the i+1-th binary value of the counting start value, and the i-th
  • the +1-bit binary value is the adjacent high-order binary value of the i-th binary value
  • the i-th judgment circuit is connected to the control circuit and is used to receive the i-th carry-borrow output from the connected i-th carry-borrow generating circuit.
  • Bit signal according to the received signal, send a third control signal to the control circuit, the third control signal is used to indicate whether the i-th binary value is updated;
  • the third control signal is generated, and the second control signal is generated and output to the data write-back circuit.
  • the count start value stored in the memory is an N-bit binary value
  • the count start value stored in the memory is counted, one or more binary values in the count start value may be caused.
  • the state changes and a carry-borrow signal is generated.
  • a carry-borrow generation circuit and a judgment circuit are respectively configured for each binary value to judge the update of each binary value in the calculation process. Thereby obtaining accurate calculation results.
  • the carry-borrow generating circuit and the judging circuit can be divided into the following two cases.
  • the i-th carry-borrow generation circuit is specifically configured to receive the i-th binary value of the count start value, and generate the i-th binary value according to the first control signal and the i-th binary value. carry borrow signal, and output the i-th carry-borrow signal to the i+1-th carry-borrow generating circuit; the i-th said judging circuit is specifically used for: receiving the i-th carry-borrow signal, Based on the received signal, a third control signal is sent to the control circuit.
  • the i-th carry-borrow generation circuit is specifically configured to receive the i-th binary value of the count start value and the i-1-th carry-borrow signal, and according to the first control signal, the The i-th binary value and the i-1th carry-borrow signal generate the i-th carry-borrow signal, and the i-th carry-borrow signal is output to the i+1th carry-borrow generating circuit;
  • the i-th judgment circuit is specifically configured to: receive the i-th carry-borrow signal and the i-1-th carry-borrow signal, and send a third control signal to the control circuit according to the received signals.
  • the storage unit is provided with an output port; wherein, the output port of the storage unit is used to output the N-bit binary value and the inverse value of the N-bit binary value. If i is greater than 1, the i-th carry-borrow generating circuit includes: an amplifier circuit, a first multiplexer switch, a first switch tube, a second switch tube and a first AND gate circuit.
  • the first input end of the amplifying circuit is connected to the output port of the storage unit, the second input end of the amplifying circuit is connected to the output port of the storage unit, and the first output end of the amplifying circuit is connected to the first input of the first multiplexer switch
  • the second output end of the amplifying circuit is connected to the second input end of the first multiplexing switch; the control end of the first multiplexing switch is used to receive the first control signal, and the output end of the first multiplexing switch is used for receiving the first control signal.
  • It is connected with the second input end of the first AND gate circuit; the first end of the first switch tube is used to receive the i-1th carry-borrow signal, and the second end of the first switch tube is respectively connected with the first and gate circuit.
  • the first input end is connected with the second end of the second switch tube; the first end of the second switch tube is connected with the ground wire; the output end of the first AND gate circuit is used to output the i-th carry-borrow signal.
  • the carry-borrow generation signal can use the output port set by the storage unit to obtain the i-th binary value and the inverse value of the i-th binary value, and use the above circuit structure to accurately obtain the counting start value in the calculation process.
  • the i-th judgment circuit includes: a first delay circuit and a first XOR gate circuit.
  • the input terminal of the first delay circuit is connected to the corresponding carry-borrow generating circuit for obtaining the i-1 th carry-borrow signal, and the output terminal of the first delay circuit is connected to the first input of the first XOR circuit.
  • the second input terminal of the first XOR gate circuit is connected to the corresponding i-th carry-borrow generating circuit for receiving the i-th carry-borrow signal, and the output terminal of the first XOR gate circuit is used for outputting the third control signal.
  • the i-th judgment circuit includes: a second XOR gate circuit, a second delay circuit and a second AND gate circuit.
  • the first input terminal of the second XOR gate circuit is connected to the corresponding i-th carry-borrow generating circuit for receiving the i-th carry-borrow signal
  • the second input terminal of the second XOR gate circuit is connected to the corresponding i-th carry-borrow signal.
  • the carry-borrow generation circuit is connected to receive the i-1th carry-borrow signal
  • the output end of the second XOR gate circuit is respectively connected with the input end of the second delay circuit and the first input end of the second AND gate circuit connected
  • the output end of the second delay circuit is connected with the second input end of the second AND gate circuit
  • the output end of the second AND gate circuit is used for outputting the third control signal.
  • control circuit includes: a third switch tube, a fourth switch tube corresponding to each judgment circuit one-to-one, and a fifth switch tube corresponding to each fourth switch tube one-to-one.
  • the first end of the third switch tube is connected to the power supply, the second end of the third switch tube is connected to the first node, and the first node is used to output the second control signal; the first node of each fourth switch tube The terminals are all connected to the first node, and the control terminal of each fourth switch tube is used to receive the third control signal output by the corresponding judgment circuit; the first terminal of each fifth switch tube is connected to the corresponding fourth switch tube.
  • the second end is connected, and the second end of each fifth switch tube is connected to the ground wire.
  • the control end of the fourth switch tube receives a signal indicating whether the calculation of the one-bit binary value is completed, and when it is determined that the calculation of the multi-bit binary values in the starting value of the count is completed, the first node sends the first node.
  • Two control signals are sent to the data write-back circuit to instruct the data-write-back circuit to rewrite the calculation result into the storage unit.
  • the data write-back circuit includes: a sub-data write-back circuit connected to each carry-borrow generating circuit in a one-to-one correspondence.
  • the i-th sub-data write-back circuit is respectively connected with the control circuit and the storage unit, and is used for receiving the second control signal and the connected carry-borrow generating circuit to output the i-th carry-borrow signal, and according to the received signal to the storage unit
  • the i-th binary value in the starting value of the count is stored in the digit to be updated.
  • the i-th sub-data write-back circuit includes: a first NOT gate circuit, a third AND gate circuit, a second multiplexing switch, a third delay circuit, a second NOT gate circuit, a differential amplifier, and The third multiplexer switch.
  • the input end of the first NOT gate circuit is connected to the output end of the control circuit, the output end of the first NOT gate circuit is connected to the second input end of the third AND gate circuit; the first input end of the third AND gate circuit is used for Receiving the first enable signal, the third input terminal of the third AND gate circuit is connected to the output terminal of the corresponding carry-borrow generating circuit, and the output terminal of the third AND gate circuit is connected to the first input terminal of the second multiplexing switch connected, the first enable signal is generated by the processor by calculating the count start value; the second input end of the second multiplexer switch is connected with the first input end of the second AND gate circuit, and the second multiplexer switch The output terminals of the second delay circuit are respectively connected with the input terminal of the third delay circuit and the input terminal of the second NOT gate circuit, and the control terminal of the second multiplexing switch is used to receive the second enable signal.
  • the output terminal of the third delay circuit is connected to the storage unit; the output terminal of the second NOT gate circuit is connected to the storage unit; the first input terminal of the differential amplifier is used to receive the i-th binary value, and the differential amplifier The second input terminal of the differential amplifier is used to receive the inverse value of the i-th binary value, and the output terminal of the differential amplifier is connected to the first input terminal of the third multiplexing switch; the second input terminal of the third selection switch is connected to the data access port connection, the output end of the third multiplexing switch is respectively connected with the input end of the third delay circuit and the input end of the second NOT gate circuit, and the control end of the third multiplexing switch tube is used for receiving the second enable signal .
  • the processor accesses the memory through the data access port.
  • the controller is further configured to control the data write-back circuit to store the data sent by the processor to the storage unit; or output the data stored in the storage unit to the processor.
  • the count start value is the address of the address register.
  • embodiments of the present application provide a computer, where the computer includes a processor and a memory provided in the first aspect of the present application and any possible designs thereof.
  • the processor is connected with the memory.
  • the computer further includes a data bus through which the processor and the memory are connected.
  • the computer further includes a controller, and the controller is respectively connected with the memory and the memory.
  • FIG. 1 is a schematic structural diagram 1 of a computer according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram 1 of a memory according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a carry-borrow determination circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the correspondence between a carry-borrow generating circuit and a count start value provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of a carry-borrow generating circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a calculation process of a carry-borrow generating circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of an initialization process of a carry-borrow generation circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram 1 of a judgment circuit provided by an embodiment of the present application.
  • FIG. 9 is a second structural schematic diagram of a judgment circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of a sub-data write-back circuit according to an embodiment of the present application.
  • FIG. 12 is a second schematic structural diagram of a memory according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of an access mode of a memory provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of a computing mode of a memory provided by an embodiment of the present application.
  • FIG. 15 is a second schematic structural diagram of a computer provided by an embodiment of the present application.
  • the computer system 100 may include at least a processor 10 and a memory 20 .
  • the processor 10 is a computing core (Core) and a control core (Control Unit) of a computer system 100 .
  • the processor 10 may be a very large scale integrated circuit.
  • An operating system and other software programs are installed in the processor 10 so that the processor 10 enables access to the memory 20 of the computer system 100.
  • the processor 10 may be a central processing unit (Central Processing Unit, CPU), and may also be a processing circuit including at least one processor core 12, or other processing circuits configured to implement one or more of the embodiments of the present invention.
  • Multiple specific integrated circuits Application Specific Integrated Circuit, ASIC.
  • ASIC Application Specific Integrated Circuit
  • the multiple processor cores 12 can be interconnected through an on-chip network. It can be understood that, in practical applications, the computer system may also include multiple processors.
  • the embodiment of the present invention uses a processor as an example for illustration. In this embodiment of the present invention, the number of processors and the number of processor cores in one processor are not limited.
  • the memory 20 is a storage device of the computer system 100 .
  • the memory 20 is generally used to store various running software in the operating system, input and output data, and information exchanged with external devices. In order to improve the access speed of the processor 10, the memory 20 has the advantage of high access speed.
  • a dynamic random access memory (Dynamic Random Access Memory, DRAM) is usually used as the memory 20 .
  • Non-Volatile Memory Non-Volatile Memory
  • PCM Phase-change Random Access memory
  • RRAM resistive random access memory
  • MRAM magnetic memory
  • FRAM ferroelectric random access memory
  • the computer system 100 may also include a data bus 30.
  • the processor 10 When the processor 10 needs to access the memory 20, the processor 10 sends an access request to the memory 20 through the data bus 30, and the memory 20 writes data into the memory based on the access request sent by the processor 1. , or read data from the memory 20 and transmit the data to the processor 10 through the data bus 30 .
  • the computer 100 also includes some external devices, such as input devices, for receiving input numerical information, character information or contact touch operations/non-contact gestures, and generating signal inputs related to user settings and function control of the computer 100 .
  • input devices for receiving input numerical information, character information or contact touch operations/non-contact gestures, and generating signal inputs related to user settings and function control of the computer 100 .
  • the computer 100 may also include a power supply for powering other modules.
  • Computer 100 may also include one or more sensors, such as image sensors, brightness sensors, light sensors, GPS sensors, infrared sensors, and the like.
  • the computer 100 may further include a radio frequency (RF) circuit for performing network communication with wireless network devices, and may also include a WiFi module for performing WiFi communication with other devices, acquiring images or data transmitted by other devices, and the like.
  • RF radio frequency
  • a memory access instruction is an instruction instructing the processor 10 to access the memory 20 .
  • Memory fetch instructions may include load and store instructions.
  • the operation instruction is used to instruct the processor 10 to perform corresponding calculation on the stored value in the memory 20 .
  • the operation instructions may include addition (add) instructions, subtraction (sub) instructions, and the like.
  • the processor sends an operation instruction to the memory to calculate the stored value in the memory 20
  • the entire calculation process is in the processor 10, and each calculation needs to first pass the data bus 30.
  • the stored value to be calculated is removed from the memory. 20 is transmitted to the processor 10, and after the processor 10 completes the calculation, the calculation result is output to the memory 20 through the data bus 30 for re-storage.
  • the processor 10 affects the realization of other functions of the processor.
  • the embodiments of the present application provide a memory and a computer.
  • the memory can be applied to the aforementioned computer architecture to implement computing functions in the memory. While improving computing efficiency, it also alleviates the need for a data bus and a processor. occupancy.
  • the memory 200 may include: a storage unit 201 , a carry-borrow determination circuit 202 , and a data write-back circuit 203 .
  • the processor when the processor needs to calculate the stored value of the storage unit in the memory 200, the processor sends the first control signal to the memory 200 through the data bus.
  • the count start value may be a stored value in the storage unit 201 in the memory 200 .
  • the first control signal is used to control the carry-borrow determination circuit 202 to calculate the count start value stored in the storage unit 201 .
  • the carry-borrow determination circuit 202 calculates the count start value stored in the storage unit 201 according to the first control signal, and generates a second control signal representing the calculation result of the count start value, and The latest calculation result is rewritten into the storage unit 201 through the data write-back circuit 203, so as to update the count start value currently stored in the storage unit 201.
  • the count start value can be a multi-bit binary value.
  • a part of the logic calculation of the processor can be implemented through the memory 200, that is, the processor first sends the value to be calculated to the memory 200 through the data bus as the starting value of the count , and send the first control signal for calculating the count start value to the memory 200. After the processor completes the calculation of the count start value, the processor reads the calculation result through the data bus, and sends the calculation result to the corresponding device. , so as to reduce the occupation of the processor.
  • the count start value is the address stored in the address register.
  • the processor is internally provided with an address register, and the address register stores the address of the target program instruction to be accessed by the processor.
  • the processor obtains the target program instruction according to the address currently stored in the address register. After the execution of the target program instruction is completed, the address of the address register is automatically incremented by 1, so that the processor can automatically execute the next program instruction.
  • the address may be the segment number and/or line number of the target program instruction.
  • the processor can first output the first address of the address register to the storage unit 201 of the memory 200 through the data bus as the starting value of counting, when the target corresponding to the first address
  • the processor sends the first control signal to the memory 200.
  • the memory 200 adds 1 to the first address to obtain the second address, and the processor reads the second address through the data bus. , and output the second address to the address register.
  • the storage unit 201 is connected to the carry-borrow determination circuit 202 and the data write-back circuit 203, respectively, for outputting the stored count start value to the carry-borrow determination circuit 202; the carry-borrow determination circuit 202 is connected to the data write-back circuit 202.
  • the circuit 203 is connected to generate a second control signal according to the first control signal and the counting start value sent by the processor for calculating the starting value of counting; the data write-back circuit 203 is used for receiving the second control signal, and according to The second control signal updates the count start value stored in the storage unit 201 .
  • the carry-borrow determination circuit 202 , the storage unit 201 and the data write-back circuit 203 in the memory 200 are connected and communicated through data transmission lines.
  • the data write-back circuit 203 and the carry-borrow determination circuit 202 may be composed of switches, multiplexers, diodes, and other devices.
  • the working states of the data write-back circuit 203 and the carry-borrow determination circuit 202 can be realized by adjusting the working states of these devices (eg, switches).
  • the adjustment of the working states of the carry-borrow determination circuit 201 and the data write-back circuit 203 can be realized by a processor or a controller, that is, the memory 200 can also include a controller (not shown), which can use
  • the carry-borrow determination circuit 202 is controlled to generate a second control signal
  • the data write-back circuit 203 is controlled to update the count start value stored in the storage unit 201 .
  • the controller directly controls the carry-borrow determination circuit 202 to generate the second control signal and control data when receiving the first control signal.
  • the write-back circuit 203 updates the count start value stored in the storage unit 201 .
  • the controller controls the carry bit to determine when the storage unit 201 receives the count start value sent by the processor and receives the first control signal.
  • the circuit 202 generates the second control signal, and controls the data write-back circuit 203 to update the count start value stored in the storage unit 201 .
  • the controller can be connected to the gate of the MOS transistor, from By controlling the on-off of the MOS transistor, the carry-borrow determination circuit 202 generates a second control signal, and the data write-back circuit 203 is controlled to update the count start value stored in the storage unit 201; if the carry-borrow determination circuit in the memory 200
  • the switches in 202 and the data write-back circuit 203 are bipolar junction transistors (BJTs), and the controller can be connected to the base of the BJT, so that the carry-borrow determination circuit 202 can be determined by controlling the on-off of the BJT.
  • the second control signal is generated, and the data write-back circuit 203 is controlled to update the count start value stored in the storage unit 201 .
  • the controller may be a driver, and after receiving the first control signal sent by the processor for calculating the count start value, the driver writes the data write-back circuit 203 and the switch tube in the carry-borrow determination circuit 202 to the data write-back circuit 203 .
  • a corresponding driving signal is sent to control the state of the data write-back circuit 203 and the carry-borrow determination circuit 202 .
  • the driver may be a driving signal or a driving circuit composed of devices such as switch tubes.
  • the specific form of the controller is not limited to the above examples.
  • the storage unit 201 is respectively connected with the carry-borrow determination circuit 202 and the data write-back circuit 203, and the storage unit 201 is used to send the stored count start value to the carry-borrow determination circuit 202, and to receive the update output from the data write-back circuit 203.
  • the subsequent count start value overwrites the currently stored count start value to update the count start value.
  • the storage unit 201 may be provided with an output port and an input port.
  • the output port can be used for outputting the stored multi-bit binary value and the inverted value of the multi-bit binary value, and the input port is used for receiving the updated count start value sent by the data write-back circuit 203 .
  • the storage unit 201 may include a first input port corresponding to the multi-bit binary values in the count start value one-to-one, a second input port corresponding to the multi-bit binary values one-to-one, and a multi-bit binary value.
  • each first input port is connected to the data write-back circuit 203, and is used for receiving the binary value of the corresponding bit in the updated count start value sent by the data write-back circuit 203; each second input port is connected to the data write-back circuit 203 is connected to receive the inverse value of the binary value of the corresponding bit in the updated count start value sent by the data write-back circuit 203; each first output port is connected to the carry-borrow determination circuit 202 for outputting the stored corresponding digit binary value; each second output port is connected to the carry-borrow determination circuit 202 for outputting the inverse value of the stored corresponding digit binary value.
  • the storage unit 201 may include a third input port for receiving the updated count start value sent by the data write-back circuit 203 , and a third input port for receiving the updated count start value sent by the data write-back circuit 203 A fourth input port for the inverted value of the count start value, a third output port for outputting the multi-bit binary value, and a fourth output port for outputting the inverted value of the multi-bit binary value.
  • the storage unit may be any one of DRAM, PCM, RRAM, MRAM, and FRAM.
  • the specific form of the storage unit is not limited to the above examples.
  • the carry-borrow determination circuit 202 is respectively connected with the storage unit 201 and the data write-back circuit 203, and is used for receiving the count start value stored in the storage unit 201, and according to the first control signal sent by the processor for calculating the count start value , calculate the currently stored count start value, and send the second control signal representing the calculation result to the data write-back circuit 203 to control the data write-back circuit 203 to rewrite the calculation result into the storage unit 201 .
  • the count start value can be an N-bit binary value.
  • the carry-borrow determination circuit receives the first control signal and calculates the count start value, it may cause multiple bits in the count start value.
  • the binary value changes.
  • a carry-borrow generation circuit is configured for each binary value in the N-bit binary value. The change of each binary value.
  • N can be an integer greater than or equal to 2.
  • the carry-borrow determination circuit 202 includes a control circuit 2021 , a carry-borrow generation circuit 2022 corresponding to each binary value in the count start value one-to-one, and a carry-borrow generation circuit 2022 corresponding to each carry-borrow bit.
  • the circuits 2022 correspond to the judging circuits 2023 connected in one-to-one correspondence.
  • each i carry-borrow generating circuit 2022 is connected to the storage unit 201, and is used for receiving the i-th binary value in the count start value, and according to the first control signal sent by the processor and the i-th binary value, generate The i-th carry-borrow signal is output, and the i-th carry-borrow signal is output to the i+1-th carry-borrow generating circuit, and the i+1-th carry-borrow generating circuit receives the ith
  • the i+1-bit binary value, and the i+1-th binary value is the adjacent high-order binary value of the i-th binary value;
  • the i-th judgment circuit 2023 is connected to the control circuit 2021 for receiving and connecting the i-th binary value.
  • a carry borrow signal according to the received signal, send a third control signal to the control circuit, the third control signal is used to indicate whether the i-th binary value has been updated; the control circuit 2021 is connected to the data write-back circuit 203 for According to the third control signal output by each judgment circuit 2022 , a second control signal is generated and output to the data write-back circuit 203 .
  • the first carry-borrow generation circuit in Figure 4 receives the first binary value of the lowest bit 1, and the second carry-borrow bit generates The circuit receives the second binary value 0, the third carry-borrow generator circuit receives the first binary value 1, and the fourth carry-borrow generator circuit receives the second binary value 0.
  • each carry-borrow generating circuit 2022 is respectively connected to the first output port and the second output port in the storage unit 201 to obtain the corresponding bit binary value.
  • the first output port is used for outputting the corresponding bit binary value
  • the second output port is used for outputting the inverse value of the corresponding bit binary value.
  • each carry-borrow generation circuit 2022 is respectively connected to the third output port of the storage unit 201, and is used to obtain the corresponding bit binary value of the carry-borrow generation circuit 2022, and each carry-borrow bit
  • the generating circuits 2022 are respectively connected to the fourth output ports of the storage unit 201 , and are used to obtain the inverse value of the corresponding bit binary value of the carry-borrow generating circuit 2022 .
  • each carry-borrow generating circuit 2022 is used to confirm the calculation result of the corresponding bit binary value in the process of calculating the counting start value stored in the memory 201, and determine the borrowing
  • the bit generation circuit 2022 sends a borrow signal to the adjacent high-order binary value corresponding to the bit binary value. It should be understood that when the carry-borrow generating circuit 2022 sends a carry-borrow signal to the adjacent high-order binary value of the corresponding digit binary value, the state of the adjacent high-order binary value of the corresponding digit binary value will be directly changed. Among them, the state of the binary value includes 0 and 1.
  • 0 may be a voltage signal with a voltage value lower than a first threshold
  • 1 may be a voltage signal with a voltage value higher than a second threshold.
  • the first threshold and the second threshold may be the same, and the second threshold may also be higher than the first threshold.
  • the function of setting the judging circuit 2023 is: in the process of calculating the starting count value stored in the memory 201, detect whether the state of the corresponding bit binary value of the connected carry-borrow generating circuit 2022 has been updated, and report to the control circuit 2021.
  • a third control signal indicating whether the state of the corresponding bit binary value of the connected carry-borrow generating circuit 2022 has been updated is sent.
  • the role of the setting control circuit 2021 is: through the third control signal output by each judgment circuit 2023, to determine whether the status of all binary values in the count start value has been updated, and to determine whether the status of all binary values in the count start value has been completed.
  • a second control signal is sent to the data write-back circuit 203 to control the data write-back circuit 203 to update the count start value stored in the storage unit 201 .
  • the update of the i-th binary value is not only related to the binary value of the bit, but also related to the progress of the i-1 bit binary value. Borrow signal related.
  • the carry-borrow generation circuit 2022 corresponding to the i-th binary value can utilize the carry-borrow signal sent by the processor for the output of the first control signal, the received i-th binary value, and the output of the i-1-th binary value , generate the i-th carry-borrow signal, and send the i-th carry-borrow signal to the i+1-th carry-borrow generating circuit for the i+1-th carry-borrow generating circuit to determine the i+th binary value update status.
  • the carry-borrow generation circuit corresponding to the lowest binary value is based on the first control signal and the lowest binary value in the counting start value. , generate the first carry-borrow signal.
  • the carry-borrow generating circuit 2022 may include: an amplifier circuit U1 , a first multiplexing switch K1 , a first switch S1 , a second switch S2 and a first AND gate circuit Z1 .
  • the connection relationship between the devices in the i-th carry-borrow generation circuit 2022 shown in FIG. 5 may be: the first input terminal of U1 is connected to the third output port of the storage unit 201, and is used to obtain the first count value in the starting value.
  • the i-bit binary value the second input terminal of U1 is connected to the fourth output port of the storage unit 201 for obtaining the inverse value of the i-th binary value, the first output terminal of U1 is connected to the first input terminal of K1,
  • the second output end of U1 is connected to the second input end of K1; the control end of K1 is used to receive the first control signal, the output end of K1 is connected to the second input end of Z1;
  • the first end of S1 is used for the i-th 1 carry-borrow signal, the second end of S1 is connected to the first input end of Z1 and the second end of S2 respectively; the first end of S2 is connected to the ground wire;
  • the output end of Z1 is used to output the i-
  • the carry and borrow generation circuit may only include K1. , S1, S2, and Z1.
  • the relationship between the second carry-borrow signal, the corresponding bit binary value, the first control signal and the first carry-borrow signal in the carry-borrow generating circuit 2022 can be shown in Table 1.
  • the binary value of the corresponding bit of the i-th carry-borrow generating circuit 2022 is 1 as an example.
  • the first input terminal of U1 obtains the corresponding bit binary value 1 through the connected third output port, and the second input terminal of U1 obtains the inverse value 0 of the corresponding bit binary value through the connected fourth output port, and the obtained signal is processed Amplitude amplification, the first output terminal of U1 outputs the binary value of the corresponding bit after the amplitude amplification is 1, and the second output terminal of U1 outputs the inverse value of the binary value of the corresponding bit after the amplitude amplification.
  • K1 If the control of K1 The terminal receives the first control signal of the high-level signal, then K1 outputs the amplified 1 received by the first input terminal to the second input terminal of Z1, if the second input terminal received by the first input terminal of Z1 If the bit signal is a high-level signal 1, then the first carry borrow signal output by Z1 is a high-level signal, and the high-level signal represents a carry to the adjacent high-order binary value of the corresponding bit binary value, where the carry-in borrow is determined. Circuit 202 exhibits an addition function.
  • the binary value of the corresponding bit of the i-th carry-borrow generating circuit 2022 is 0 as an example
  • the first input terminal of U1 obtains the corresponding bit binary value 0 through the connected third output port
  • the second input of U1 The terminal obtains the inverse value 1 of the binary value of the corresponding bit through the connected fourth output port, and amplifies the amplitude of the obtained signal.
  • the first output terminal of U1 outputs the binary value of the corresponding bit after the amplitude amplification.
  • the second output terminal outputs the inverse value 1 of the corresponding bit binary value after amplitude amplification.
  • K1 If the control terminal of K1 receives the first control signal of the high-level signal, then K1 amplifies the amplitude value received by the first input terminal. The latter 0 is output to the second input terminal of Z1. If the second carry borrow signal received by the first input terminal of Z1 is a high-level signal 1, the first carry-bit borrow signal output by Z1 is a low-level signal. The low-level signal indicates that there is no need to carry out carry to the adjacent high-order binary value of the corresponding bit binary value, and here the carry-borrow determination circuit 202 exhibits an addition operation function.
  • the binary value of the corresponding bit of the i-th carry-borrow generating circuit 2022 is 1 as an example.
  • the first input terminal of U1 obtains the corresponding bit binary value 1 through the connected third output port, and the second input terminal of U1 obtains the inverse value 0 of the corresponding bit binary value through the connected fourth output port, and the obtained signal is processed Amplitude amplification, the first output terminal of U1 outputs the binary value of the corresponding bit after the amplitude amplification is 1, and the second output terminal of U1 outputs the inverse value of the binary value of the corresponding bit after the amplitude amplification.
  • K1 If the control of K1 The terminal receives the first control signal of the low-level signal, then K1 outputs the amplified 0 received by the second input terminal to the second input terminal of Z1, if the second input terminal received by the first input terminal of Z1 If the bit signal is a high-level signal 1, then Z1 outputs the first carry borrow signal as a low-level signal, and the low-level signal indicates that there is no need to borrow from the adjacent high-order binary value of the corresponding bit binary value. At this time, the carry-borrow determination circuit 202 exhibits a subtraction function.
  • the binary value of the corresponding bit of the i-th carry-borrow generating circuit 2022 is 0 as an example.
  • the first input terminal of U1 obtains the corresponding bit binary value 0 through the connected third output port, and the second input terminal of U1 obtains the inverse value 1 of the corresponding bit binary value through the connected fourth output port, and the obtained signal is processed Amplitude amplification, the first output terminal of U1 outputs the corresponding bit binary value 0 after amplitude amplification, and the second output terminal of U1 outputs the inverse value 1 of the corresponding bit binary value after amplitude amplification, if the control of K1
  • the terminal receives the first control signal of the low-level signal, then K1 outputs the amplified 1 received by the second input terminal to the second input terminal of Z1, if the second input terminal received by the first input terminal of Z1 If the bit signal is a high-level signal 1, the first carry borrow signal output by Z1 is a high-level signal, and the high-level signal represents borrowing from
  • the borrowing and borrowing of each binary value in the starting counting value is determined by the carry-borrow generating circuit 2022 corresponding to the plurality of binary values in the starting counting value. bit situation.
  • the carry-borrow generation circuit 2022 corresponding to the lowest-order binary value in the counting start value cannot receive the carry-borrow signal of the adjacent low-order binary value.
  • a high-level signal representing the carry is sent to the first end of S1 in the lowest-order binary value corresponding to the carry-borrow generating circuit 2022, and a high-level signal representing the carry is received when the count is received.
  • a low-level signal representing a borrow is sent to the first end of S1 in the carry-borrow generating circuit corresponding to the lowest-order binary value.
  • the carry-borrow generation circuit 2022 corresponding to the lowest binary value 1 performs addition operation, and at the same time adds to the first one corresponding to the lowest binary value 1
  • the carry-borrow generation circuit 2022 outputs a high-level signal 1.
  • the first carry-borrow generation circuit 2022 outputs a high-level signal 1 representing a carry, and outputs it to the second carry-borrow generation circuit 2022.
  • the carry-borrow generation circuit 2022 performs an addition operation, and outputs a high-level signal 1 that continues to carry, and the third carry-borrow generation circuit 2022 outputs a high-level signal and performs an addition operation, to the fourth carry-borrow generation circuit.
  • a high-level signal 1 for continuing carry is sent, and the fourth binary value 0 performs an addition operation.
  • the fourth carry-borrow generation circuit 0 sends a low-level signal 0 for carrying out carry and borrow. The calculation of the entire count start value is complete.
  • the carry-borrow generation circuit 2022 will only calculate the count start value stored in the memory 200 when it receives the first control signal, and avoid the signal pair received when the count start value was calculated last time. Influenced by this calculation, the controller or the processor may initialize the carry-borrow generation circuit 2022 each time the carry-borrow generation circuit 2022 calculates the carry-borrow condition of the corresponding bit binary value.
  • the clock CLK signal representing the operation of the carry-borrow generation circuit 2022 is a low-level signal, and at this time, a low-level signal is sent to the control terminal of S1 , send a high-level signal to the control terminal of S2, S1 is turned off and does not receive the i-1th carry borrow signal, and at the same time S2 is turned on to ground the first input terminal of Z1, and the first input terminal of Z1 cannot receive the signal.
  • the clock CLK signal representing the operation of the carry-borrow generation circuit 2022 is a low-level signal
  • a high-level signal is sent to the control terminal of S1
  • a low-level signal is sent to the control terminal of S2 level signal
  • S1 is turned on to receive the i-1 th carry borrow signal
  • S1 is turned off to output the i-1 th carry borrow signal transmitted by S2 to the first input terminal of Z1.
  • the i-th judgment circuit 2023 may include: a first delay circuit D1 and a first XOR circuit Z2.
  • each device in the judgment circuit 2023 shown in FIG. 8 may be: the input terminal of D1 is connected to the i-th carry-borrow generating circuit 2022 for receiving the i-1th carry-borrow signal, and the output terminal of D1 It is connected with the first input terminal of the Z2 circuit; the second input terminal of Z2 is connected with the i-th carry-borrow generating circuit 2022 for receiving the i-th carry-borrow signal, and the output terminal of Z2 is used to output the input representing the connection.
  • the borrow generation circuit 2022 corresponds to the third control signal of whether the update of the binary value state of the bit is completed.
  • the i-th carry-borrow generation circuit 2023 connected by detection receives the i-1-th carry-and-borrow signal and outputs the i-th The state of the carry borrow signal determines whether the i-th binary value is updated.
  • the i-th carry-borrow signal since the connected carry-borrow generation circuit 2022 receives the i-1th carry-borrow signal, the i-th carry-borrow signal needs to be calculated and delayed by the internal devices of the carry-borrow generation circuit 2022 to output the i-th carry-borrow signal. , therefore, there is a certain time delay between the i-1th carry-borrow signal and the i-th carry-borrow signal.
  • the first delay circuit D1 added in the judgment circuit 2023 uses D1 The i-th carry-borrow signal outputted after the delay and the i-1th carry-borrow signal received before the delay by D1 generate a third control signal indicating whether the state of the i-th binary value has been updated.
  • the relationship between the first carry borrow signal, the second carry borrow signal and the third control signal may be as shown in Table 2.
  • i-th carry-borrow signal The i-1th carry borrow signal third control signal 0 0 0 1 1 0 0 1 1
  • the judging circuit 2023 when the judging circuit 2023 receives the i-th carry-borrow signal and the i-1th carry-borrow signal are both low-level signals, it indicates that the i-th binary value does not receive a carry-borrow signal, Even the state of the i-th binary value does not need to be updated.
  • the i-th carry-borrow signal and the i-1-th carry-borrow signal connected to the connection are both high-level signals, it indicates that the i-th binary value has received adjacent low-order bits.
  • the second carry-borrow signal is sent from the binary value, and a carry or borrow is performed to the adjacent high-order binary value, the state of the i+1-th binary value will still change.
  • the second input terminal of Z2 It can be connected to the second end of the first switch tube in the i-th carry-borrow generation circuit 2022, and is used to obtain the i-1th received by the carry-borrow generation circuit 2022 connected in the calculation process of the counting start value this time.
  • a carry borrow signal to ensure the accuracy of the detection result.
  • the i-th judgment circuit 2023 includes: a second XOR gate circuit Z3 , a second delay circuit D2 and a second AND gate circuit Z4 .
  • each device in the judgment circuit 2023 shown in FIG. 8 may be as follows: the first input terminal of Z3 is connected to the output terminal of the corresponding i-th carry-borrow generating circuit 2022 for receiving the i-th carry-borrow signal , the second input terminal of Z3 is connected to the input terminal of the corresponding i-th carry-borrow generating circuit 2022 for receiving the i-1-th carry-borrow signal, and the output terminal of Z3 is respectively connected with the input terminal of D2 and the input terminal of Z4
  • the first input end of D2 is connected to the second input end of Z4; the output end of Z4 is used to output the third control signal.
  • the relationship between the i-th carry-borrow signal, the i-1-th carry-borrow signal, and the third control signal can be referred to as shown in Table 2 above, which is not repeated in this application.
  • the second end of Z3 may be connected to the second end of the first switch transistor in the i-th carry-borrow generating circuit 2022 .
  • the control circuit 2021 may include: a third switch S3 , a fourth switch S4 corresponding to each judgment circuit one-to-one, and a fourth switch S4 corresponding to each S3 one-to-one.
  • each device in the control circuit 2021 shown in FIG. 9 may be: the first end of S3 is connected to the power supply, the second end of S3 is connected to the first node, and the first node is used to output the second control signal; each The first end of one S4 is connected with the first node, and the control end of each S4 is used to receive the third control signal output by the corresponding judgment circuit; the first end of each S5 is connected with the second end of the corresponding S4 , the second end of each S5 is connected to the ground wire.
  • the power supply may be an internal power supply of the memory 200 or an external power supply connected to the memory 200 .
  • the control terminal of each S4 can receive a third control signal, and the third control signal is used to indicate the connected Whether the binary value of the corresponding bit of the carry-borrow generation circuit has completed the state update, when the third switch tube receives the third control signal of the high-level signal, the corresponding binary value of the third control signal of the high-level signal is represented. There is no carry or borrow, and the state of the entire count start value is updated.
  • S4 that receives the third control signal of the high-level signal is turned on, and the potential of the first node is pulled down to zero, and the count start value is sent.
  • the updated low-level second control signal is sent to the data write-back circuit 203 , which controls the data write-back circuit 203 to perform data write-back, and writes the latest calculation result into the storage unit 201 .
  • the control circuit 2021 receives the third control signal once every time the processor sends the first control signal to modify the count start value, and when the count start value is not modified, the control circuit 2021 receives the third control signal once.
  • a plurality of fourth control signals of 2021 may show corresponding level states. In order to avoid detection errors, a low level can be sent to the control terminal of the fifth switch tube in the control circuit 2021 when the first control signal is not received. signal, the fifth switch tube is disconnected, and all the fourth switch tubes cannot receive the third control signal.
  • a high-level signal is sent to the control terminal of the fifth switch tube, and the fifth switch tube conducts The fourth switch tube receives the third control signal, and the first node outputs the corresponding second control signal according to the third control signal.
  • the data write-back circuit 203 is respectively connected with the storage unit 201 and the carry-borrow determination circuit 202, and is used for receiving the second control signal sent by the carry-borrow determination circuit 202, and according to the second control signal, counts the stored in the storage unit 201 The starting value is updated.
  • the data write-back circuit 203 may include a sub-data write-back circuit connected to each carry-borrow generating circuit 2022 in a one-to-one correspondence.
  • the i-th sub-data write-back circuit is respectively connected with the control circuit 2021 and the storage unit 201, and is used for receiving the second control signal and the i-th carry-borrow signal output by the connected i-th carry-borrow generating circuit 2022, And according to the received signal, the i-th binary value in the count start value stored in the storage unit 201 is updated.
  • each sub-data write-back circuit is connected to the third input port and the fourth input port of the storage unit 201 .
  • the i-th sub-data write-back circuit is connected to the first input port in the storage unit 201 for receiving the i-th binary value, and each sub-data write-back circuit is connected to the storage unit 201 using a is connected to the second input port receiving the inverse value of the i-th binary value.
  • the sub-data write-back circuit includes: a first NOT gate circuit Z5, a third AND gate circuit Z6, a second multiplexing switch K2, a third delay circuit D3, a second NOT gate circuit Z7, a differential Amplifier U2 and third multiplexer K3.
  • each device in the sub-data write-back circuit shown in FIG. 10 is: the input end of Z5 is connected with the output end of the control circuit 2021, the output end of Z5 is connected with the second input end of the third AND gate circuit; An input terminal is used to receive the first enable signal, the third input terminal of Z6 is connected to the input terminal of the corresponding carry-borrow generating circuit for receiving the second carry-borrow signal, and the output terminal of Z6 is connected to the first input terminal of K2.
  • the input end is connected, and the first enable signal is generated by the processor calculating the starting value of the count; the second input end of K2 is connected with the first input end of the second AND gate circuit, and the output end of K2 is respectively connected with the input end of D3
  • the terminal is connected to the input terminal of Z7, the control terminal of K2 is used to receive the second enable signal, and the second enable signal is generated by the processor accessing the memory;
  • the output terminal of D3 is connected to the third input port in the storage unit 201 Connect;
  • the output end of Z7 is connected with the fourth input port in the storage unit 201;
  • the first input end of U2 is connected with the third output port of the storage unit 201 for receiving the i-th binary value, the second input end of U2 Connected with the fourth output port for receiving the inverse value of the i-th binary value, the output end of U2 is connected with the first input end of K3;
  • the second input end of K3 is connected with the data access port, and the output ends of K
  • the third input terminal of Z6 can be connected with the second end of the first switch tube in the carry-borrow generation circuit 2022, and is used to obtain the second carry-borrow signal received by the carry-borrow generation circuit 2022 connected during the calculation of the count start value this time, to ensure the accuracy of the test results.
  • the i-th sub-data write-back circuit shown in FIG. 11 When the i-th sub-data write-back circuit shown in FIG. 11 is used to update the i-th binary value, when the first control signal sent by the processor is received, and the received second control signal is a low-level signal, If the second enable signal is a low-level signal, the sub-data write-back circuit outputs the data sent by the processor to the storage unit 201 for storage through the data access port; if the second enable signal is a high-level signal, the sub-data The write-back circuit updates the i-th binary value stored in the storage unit.
  • the second carry-and-borrow signal received by the carry-borrow generating circuit connected by Z6 is 0, it means that the state of the corresponding bit binary value has not changed, then K2 and K3 are closed, and the i-th binary value stored in the storage unit 201 is not changed. The binary value of the bit remains unchanged. If the second carry-borrow signal received by the carry-borrow generation circuit of Z6 is 1, the state of the corresponding bit binary value changes, Z6 outputs a high-level signal, K2 is disconnected, and K3 will The inverted value of the i-th binary value stored in U2 is output to the storage unit.
  • Z7 and D3 are used to convert the signal output by K3 into two signals with opposite states and then output to the storage unit for storage.
  • the delay time of D3 is the same as the device delay time of Z7.
  • the processor when the second enable signal is a high-level signal, it means that the processor directly reads the stored value in the memory, and the processor can directly read the data stored in the storage unit through the second input terminal of K3.
  • the processor can send a second high-level enable signal through the memory, and send the updated address to the address through the data bus. register.
  • a memory provided by an embodiment of the present application may be as shown in FIG. 12 .
  • the carry-borrow determination circuit includes a plurality of amplifier circuits U1, U2, multiplexing switch tube K1, switch tubes S1, S2, S3, S4, S5, delay circuits D1, D3, first AND gate circuit Z1 and The first XOR gate circuit Z2.
  • K1, S1, S2 and Z1 constitute a carry-borrow generating circuit
  • D1 and Z2 constitute a judgment circuit
  • S3, S4, and S5 constitute a control circuit.
  • the data write-back circuit includes: a plurality of first NOT gate circuits Z5, a third AND gate circuit Z6, second multiplexing switches K2, K3, a third delay circuit D3, a second NOT gate circuit Z7 and a differential Amplifier U2.
  • Z5, Z6, K2, K3, D3, Z7, U2 and K3 constitute a sub-data write-back circuit.
  • the second enable signal sent by the processor to the multiple sub-data write-back circuits is 1. At this time, the memory works in the access mode. When the second enable signal When it is 0, the memory works in the calculation mode. Among them, 1 is a high-level signal, and 0 is a low-level signal.
  • the storage unit 201 may receive the value to be calculated sent by the processor and store it as the starting value for counting.
  • the count start value is an N-bit binary value. Taking the i-th binary value of the count start value stored in the storage unit as an example, as shown in Figure 12, when the second enable signal received by K2 and K3 in the i-th sub-data write-back circuit is 1, K3 will The data received by the data access port is output to D3 and Z7 respectively. At this time, the processor can output 1 to D3 and Z7 through the data access port. D3 delays the 1, and Z7 reverses the 1 to 0. The data transmission line between the memory cells stores 0 and 1 in the memory cells respectively.
  • the first output port will re-store the 1 output and the second output.
  • the port outputs 0, the inverse of the stored 1.
  • the i carry borrow generation circuit before receiving the first control signal, first sends a low-level signal 0 to the control terminal of S1 and a temporary pulse signal of a high-level signal 1 to S2 to borrow the i-th carry bit
  • the generation circuit is initialized, and its signal is shown in Figure 14.
  • S1 is turned off and does not receive the i-1th carry borrow signal received in the last calculation.
  • S2 is closed to pull the input of Z1 down to 0, and Z1 does not receive the signal.
  • S1 when the pulse signals received by S1 and S2 end, S1 receives the high-level signal 1, receives the i-1th carry-over signal and outputs S2, and S2 receives the low-level signal 1 and disconnects the signal received by S1.
  • the i-1th carry-borrow signal is transmitted to Z1.
  • the i-1th carry-borrow signal is a high-level signal 1
  • the i-th carry-borrow signal output by Z1 is 0 and output to one of Z2 Input terminal
  • D1 outputs the delayed i-1th carry borrow signal 1 to another input terminal of Z2
  • Z2 outputs a high-level signal 1 and transmits it to the control terminal of S4, before S4 receives the control signal sent by Z2
  • S5 is disconnected, and all S4 can not receive signals, when the pulse signal ends, S5 receives a high-level signal 1 is turned on , S4 receives the high-level signal 1 sent by Z2 and turns on, the potential of the first node is pulled down to 0, the signal is inverted to 1 by Z5 and output to one input of Z6, and the other input of Z6 receives it for control
  • the inverse value 0 of the i-bit binary value is output to D3 and Z7, D3 delays the low-level signal 0 and outputs it to the third input port of the storage unit, and Z7 inverts the low-level signal 0 to 1 and outputs it to the storage unit
  • the fourth input port of the unit after the signals output by D3 and Z7 are transmitted to the storage unit, overwrites the i-th binary value of the starting value of the count stored in the storage unit to update the i-th binary value. At this time, the third input port of the storage unit outputs 0, and the fourth output port outputs 1.
  • the over-energy protection circuit provided in the embodiment of the present application also has other structures, and the principles of other circuit structures are the same, and are not one by one in this application. Details.
  • an embodiment of the present application also provides a computer.
  • the computer 1500 includes a processor 1501 and the aforementioned memory 200 .
  • the processor 1501 is connected to the aforementioned memory 200 .
  • the computer also includes a data bus 1502 .
  • the processor 1501 is connected to the memory through the data bus 1502 .
  • the computer 1500 also includes some external devices, such as input devices, for receiving input numerical information, character information or contact touch operations/non-contact gestures, and generating signal inputs related to user settings and function control of the computer 1500.
  • input devices for receiving input numerical information, character information or contact touch operations/non-contact gestures, and generating signal inputs related to user settings and function control of the computer 1500.
  • the computer 1500 may also include a power source for powering other modules.
  • Computer 1500 may also include one or more sensors, such as image sensors, brightness sensors, light sensors, GPS sensors, infrared sensors, and the like.
  • the computer 1500 may further include a wireless radio frequency (RF) circuit for performing network communication with wireless network devices, and may also include a WiFi module for performing WiFi communication with other devices, acquiring images or data transmitted by other devices, and the like.
  • RF radio frequency
  • connection involved in this application describes the connection relationship between two objects, and can represent two connection relationships.
  • the connection between A and B can represent: A is directly connected with B, and A is connected through C and B.
  • system structure and service scenarios provided in the embodiments of the present application are mainly to explain some possible implementations of the technical solutions of the present application, and should not be construed as unique limitations on the technical solutions of the present application.
  • Those of ordinary skill in the art can know that with the evolution of the system and the emergence of newer service scenarios, the technical solutions provided in this application are still applicable to the same or similar technical problems.

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Abstract

本申请公开了一种存储器和计算机，用于在存储器内实现计算功能，提升了计算效率以及缓解计算机中数据总线和处理器的占用。该存储器包括：存储单元、进借位确定电路以及数据回写电路；其中，存储单元中存储有计数起始值；存储单元分别与进借位确定电路和数据回写电路连接，用于将计数起始值输出给进借位确定电路；进借位确定电路与数据回写电路连接，用于根据处理器发送的用于计算计数起始值的第一控制信号以及计数起始值，生成第二控制信号；数据回写电路用于接收第二控制信号，并根据第二控制信号，对存储单元中存储的计数起始值进行更新。

Description

一种存储器和计算机 技术领域
本申请涉及计算机技术领域，尤其涉及一种存储器和计算机。
背景技术
在计算机进行运算的过程中，计数器常常被大量的使用。对于传统冯诺依曼架构的计算机，计数器被放置在处理器中，处理器每一次对存储器中的存储值进行计算，处理器通过数据总线将存储器读取后发送给计数器，待计数器进行完毕，通过数据总线将计数器的计算结果重新写入存储器中。
实际应用中，处理器需要与存储器以及计数器进行数据传输，随着处理器处理数据的增多，数据总线占用严重，且处理器和存储器之间存有一定物理距离，导致数据在数据总线存在一定的损耗以及数据在数据总线上的传输时间较长，影响了计数器的工作效率，且上述计算方式需要长时间占用处理器和数据总线，影响处理器其它功能的实现。
发明内容
本申请提供一种存储器和计算机，用于提供一种新型存储器结构，可以在存储器内实现计数功能，提升了计算效率以及缓解了数据总线和处理器的占用。
第一方面，本申请实施例提供了一种存储器，该存储器可以包括：存储单元、进借位确定电路以及数据回写电路。其中，存储单元中存储有计数起始值。
其中，存储单元分别与进借位确定电路和数据回写电路连接，用于将计数起始值输出给进借位确定电路；进借位确定电路与数据回写电路连接，用于根据处理器发送的用于计算计数起始值的第一控制信号以及计数起始值，生成第二控制信号；数据回写电路用于接收第二控制信号，并根据第二控制信号，对存储单元中存储的计数起始值进行更新。
采用上述存储器结构，每次处理器对存储器内存储的存储值进行逻辑运算或对存储器内的存储的数据进行读取时，利用进借位确定电路对当前存储的计数起始值进行计算，并将计算后得到的最新的计数起始值通过数据回写电路重新写入存储单元中，计算的整个过程均在存储器内部完成，减少了数据传输时延以及数据传输损耗，提高了计算效率，且缓解了处理器和数据总线的占用。
在一种可能的设计中，存储器中还可以包括：控制器。
其中，控制器用于在接收到第一控制信号时，控制进借位确定电路生成第二控制信号，以及控制数据回写电路对存储单元中存储的计数起始值进行更新。
采用上述存储器结构，当处理器需要对存储器内存储的计数初始值进行逻辑运算时，处理器可以向控制器发送第一控制信号，控制器在接收到第一控制信号时控制进借位确定电路对存储单元内存储的计数起始值进行计算，并利用数据回写电路将计算结果重新写入存储单元内，实现对计数起始值的更新，整个计算过程均在存储器内完成。
在一种可能的设计中，计数起始值是N位二进制数值，进借位确定电路包括：控制电路、与每一位二进制数值一一对应的进借位生成电路以及与每一个进借位生成电路一一对应连接的判断电路。其中，N可以是大于或等于2的整数。
具体地，第i个进借位生成电路用于接收计数起始值的第i位二进制数值，并根据第一控制信号和第i位二进制数值，生成第i个进借位信号，并将第i个进借位信号输出给第i+1个进借位生成电路，所述第i+1个进借位生成电路接收计数起始值的第i+1位二进制数值、且所述第i+1位二进制数值为所述第i位二进制数值的相邻高位二进制数值；第i个判断电路与控制电路连接，用于接收连接的第i个进借位生成电路输出的第i个进借位信号，根据接收的信号，向控制电路发送第三控制信号，第三控制信号用于指示第i位二进制数值是否更新完毕；控制电路与数据回写电路连接，用于根据每一个判断电路输出的第三控制信号，生成第二控制信号并输出给数据回写电路。
采用上述存储器结构，由于存储器内存储的计数起始值是N位二进制数值，当对存储器内存储的计数起始值进行计数时，可能会造成计数起始值中的一位或多位二进制数值状态发生变化并产生进借位信号，为了准确的得到的计数结果，为每一位二进制数值分别配置一个进借位生成电路和判断电路，以判断计算过程中每一位二进制数值的更新情况，从而得到准确的计算结果。
在一种可能的设计中，由于最低位二进制数值无法接收到相邻低位发送的进借位信号，因此进借位生成电路和判断电路可以分别以下两种情况。
情况一i等于1：
所述第i个所述进借位生成电路具体用于接收所述计数起始值的第i位二进制数值，并根据所述第一控制信号和所述第i位二进制数值，生成第i个进借位信号，并将所述第i个进借位信号输出第i+1个进借位生成电路；第i个所述判断电路具体用于：接收所述第i个进借位信号，根据接收的信号，向所述控制电路发送第三控制信号。
情况二、i大于1：
所述第i个所述进借位生成电路具体用于接收所述计数起始值的第i位二进制数值以及第i-1个进借位信号，并根据所述第一控制信号、所述第i位二进制数值以及所述第i-1个进借位信号，生成第i个进借位信号，并将所述第i个进借位信号输出第i+1个进借位生成电路；第i个所述判断电路具体用于：接收所述第i个进借位信号以及所述第i-1个进借位信号，根据接收的信号，向所述控制电路发送第三控制信号。
在一种可能的设计中，存储单元设置有输出端口；其中，存储单元的输出端口用于输出N位二进制数值以及N位二进制数值的取反数值。若i大于1，第i个进借位生成电路包括：放大电路、第一多路选择开关、第一开关管、第二开关管和第一与门电路。
其中，放大电路的第一输入端与存储单元的输出端口连接，放大电路的第二输入端与存储单元的输出端口连接，放大电路的第一输出端与第一多路选择开关的第一输入端连接，放大电路的第二输出端与第一多路选择开关的第二输入端连接；第一多路选择开关的控制端用于接收第一控制信号，第一多路选择开关的输出端与第一与门电路的第二输入端连接；第一开关管的第一端用于接收第i-1个进借位信号，第一开关管的第二端分别与第一与门电路的第一输入端以及第二开关管的第二端连接；第二开关管的第一端与地线连接；第一与门电路的输出端用于输出第i个进借位信号。
采用上述存储器结构，进借位生成信号可以利用存储单元设置的输出端口，获取第i位二进制数值以及第i位二进制数值的取反数值，并利用上述电路结构准确得到计算过程中计数起始值中每一位二进制数值的更新情况。
在一种可能的设计中，若i大于1，第i个判断电路包括：第一延迟电路和第一异或门 电路。
其中，第一延迟电路的输入端与对应的进借位生成电路连接，用于获取第i-1个进借位信号，第一延迟电路的输出端与第一异或门电路的第一输入端连接；第一异或门电路的第二输入端与对应的第i个进借位生成电路连接，用于接收第i个进借位信号，第一异或门电路的输出端用于输出第三控制信号。
在一种可能的设计中，若i大于1，第i个判断电路包括：第二异或门电路、第二延迟电路和第二与门电路。
其中，第二异或门电路的第一输入端与对应的第i个进借位生成电路连接，用于接收第i个进借位信号，第二异或门电路的第二输入端与对应的进借位生成电路连接，用于接收第i-1个进借位信号，第二异或门电路的输出端分别与第二延迟电路的输入端以及第二与门电路的第一输入端连接；第二延迟电路的输出端与第二与门电路的第二输入端连接；第二与门电路的输出端用于输出第三控制信号。
在一种可能的设计中，控制电路包括：第三开关管、与每一个判断电路一一对应的第四开关管和与每一个第四开关管一一对应的第五开关管。
具体地，第三开关管的第一端与供电电源连接，第三开关管的第二端与第一节点连接，第一节点用于输出第二控制信号；每一个第四开关管的第一端均与第一节点连接，每一个第四开关管的控制端用于接收对应的判断电路输出的第三控制信号；每一个第五开关管的第一端均与对应的第四开关管的第二端连接，每一个第五开关管的第二端与地线连接。
采用上述存储器结构，在第四开关管的控制端分别接收一个表征一位二进制数值是否计算完毕的信号，在确定计数起始值中的多位二进制数值均计算完成时，通过第一节点发送第二控制信号给数据回写电路，指示数据回写电路将计算结果重新写入存储单元中。
在一种可能的设计中，数据回写电路包括：与每一个进借位生成电路一一对应连接的子数据回写电路。
其中，第i个子数据回写电路分别与控制电路和存储单元连接，用于接收第二控制信号和连接的进借位生成电路输出第i个进借位信号，并根据接收的信号对存储单元中存储计数起始值中的第i位二进制数值进行更新。
在一种可能的设计中，第i个子数据回写电路包括：第一非门电路、第三与门电路、第二多路选择开关、第三延迟电路、第二非门电路、差分放大器和第三多路选择开关。
具体地，第一非门电路的输入端与控制电路输出端连接，第一非门的输出端与第三与门电路的第二输入端连接；第三与门电路的第一输入端用于接收第一使能信号，第三与门电路的第三输入端与对应的进借位生成电路的输出端连接，第三与门电路的输出端与第二多路选择开关的第一输入端连接，第一使能信号是处理器对计数起始值进行计算生成的；第二多路选择开关的第二输入端与第二与门电路的第一输入端连接，第二多路选择开关的输出端分别与第三延迟电路的输入端和第二非门电路的输入端连接，第二多路选择开关的控制端用于接收第二使能信号，第二是使能信号是处理器对存储器进行访问生成的；第三延迟电路的输出端与存储单元连接；第二非门电路的输出端与存储单元连接；差分放大器的第一输入端用于接收第i位二进制数值，差分放大器的第二输入端与用于接收第i位二进制数值的取反数值，差分放大器的输出端与第三多路选择开关的第一输入端连接；第三选择开关的第二输入端与数据访问端口连接，第三多路选择开关的输出端分别与第三延迟电路的输入端和第二非门电路的输入端连接，第三多路选择开关管的控制端用于接收第二 使能信号。其中，处理器通过数据访问端口访问存储器。
在一种可能的设计中，控制器还用于控制数据回写电路将处理器发送的数据存储至存储单元；或者将存储单元存储的数据输出给处理器。
在一种可能的实现方式中，计数起始值为地址寄存器的地址。
第二方面，本申请实施例提供了一种计算机，该计算器包括处理器和本申请第一方面及其任意可能的设计中提供的存储器。
其中，处理器与存储器连接。
可选地，该计算机还包括数据总线，处理器与存储器通过数据总线连接。
可选地，该计算机还包括控制器，控制器分别与存储器和存储器连接。
附图说明
图1为本申请实施例提供的一种计算机的结构示意图一；
图2为本申请实施例提供的一种存储器的结构示意图一；
图3为本申请实施例提供的一种进借位确定电路的结构示意图；
图4为本申请实施例提供的一种进借位生成电路对计数起始值的对应关系示意图；
图5为本申请实施例提供的一种进借位生成电路的结构示意图；
图6为本申请实施例提供的一种进借位生成电路的计算过程示意图；
图7为本申请实施例提供的进借位生成电路初始化过程示意图；
图8为本申请实施例提供的一种判断电路的结构示意图一；
图9为本申请实施例提供的一种判断电路的结构示意图二；
图10为本申请实施例提供的一种控制电路的结构示意图；
图11为本申请实施例提供的一种子数据回写电路的结构示意图；
图12为本申请实施例提供的一种存储器的结构示意图二；
图13为本申请实施例提供的一种存储器的访问模式示意图；
图14为本申请实施例提供的一种存储器的计算模式示意图；
图15为本申请实施例提供的一种计算机结构示意图二。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请实施例的技术方案可以应用于计算机系统中。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
参见图1，为本发明实施例提供的一种计算机系统的结构示意图。如图1所示，计算机系统100至少可以包括处理器10和存储器20。
处理器10是一台计算机系统100的运算核心(Core)和控制核心(Control Unit)。处理器10可以是一块超大规模的集成电路。在处理器10中安装有操作系统和其他软件 程序，从而处理器10能够实现对计算机系统100的存储器20的访问。本领域技术人员可以知道，处理器10可以是中央处理单元(Central Processing Unit，CPU)，还可以是包含有至少一个处理器核12的处理电路或其他被配置成实施本发明实施例的一个或多个特定集成电路(Application Specific Integrated Circuit，ASIC)。随着集成电路工艺的发展，处理器10中可以集成越来越多的处理器核(core)。当处理器10中集成有多个处理器核12时，多个处理器核12可以通过片上网络实现互连。可以理解的是，实际应用中，计算机系统还可以包括多个处理器。本发明实施例以一个处理器为例进行示例。在本发明实施例中不对处理器的数量以及一个处理器中处理器核的数量进行限定。
存储器20是计算机系统100的存储设备。存储器20通常用来存放操作系统中各种正在运行的软件、输入和输出数据以及与外部设备交换的信息等。为了提高处理器10的访问速度，存储器20具备访问速度快的优点。在传统的计算机系统架构中，通常采用动态随机存取存储器(Dynamic Random Access Memory,DRAM)作为存储器20。随着非易失性存储器(Non-Volatile Memory,NVM)技术的发展，相变存储器(Phase-change Random Access memory，PCM)，阻变存储器(resistive random access memory，RRAM)、磁性存储器(magnetic random access memory，MRAM)或铁电式存储器(ferroelectric random access memory，FRAM)等新型NVM也逐渐被作为内存使用。在本发明实施例中不对存储器20的具体存储介质进行限定。
计算机系统100还可以包括数据总线30，当处理器10需要访问存储器20时，处理器10通过数据总线30向存储器20发送访问请求，存储器20基于处理器1发送的访问请求，将数据写入存储器，或者从存储器20中读出数据，并通过数据总线30将数据传输给处理器10。
计算机100还包括一些外接设备，例如输入设备，用于接收输入的数字信息、字符信息或接触式触摸操作/非接触式手势，以及产生与计算机100的用户设置以及功能控制有关的信号输入等。
除以上之外，计算机100还可以包括用于给其他模块供电的电源。计算机100还可以包括一个或多个传感器，例如图像传感器、亮度传感器、光线传感器、GPS传感器、红外传感器等。计算机100还可以包括无线射频(radio frequency,RF)电路，用于与无线网络设备进行网络通信，还可以包括WiFi模块，用于与其他设备进行WiFi通信，获取其他设备传输的图像或者数据等。
下面将结合图1所示的计算机系统100，对处理器10访问存储器20的过程进行详细介绍。在处理器10的指令队列中有多个待处理的计算机指令，这些指令可以包括访存指令、运算指令及其他指令。访存指令是指示处理器10访问存储器20的指令。访存指令可以包括加载(load)和存储(store)指令。运算指令用于指示处理器10对存储器20内的存储值进行相应计算。运算指令可以包括加法(add)指令、减法(sub)指令等。
处理器向存储器发送运算指令以对存储器内20内的存储值进行计算时，其整个计算过程均在处理器10内，且每次计算均需要先通过数据总线30将待计算的存储值从存储器20内传输给处理器10，待处理器10计算完毕，再将计算结果通过数据总线30输出给存储器20内重新进行存储，计算过程较长导致计算效率低，且会多次占用数据总线以及处理器10，影响处理器其它功能的实现。
基于此，本申请实施例提供了一种存储器和计算机，该存储器可以应用于前述计算机 架构中，用于在存储器内实现计算功能，在提升了计算效率的同时，缓解了数据总线和处理器的占用情况。
参见图2所示，为本申请实施例提供的一种存储器的结构示意图，如图2所示，该存储器200可以包括：存储单元201、进借位确定电路202和数据回写电路203。
其中，当处理器需要对存储器200内存储单元的存储值进行计算时，处理器通过数据总线向存储器200发送第一控制信号。计数起始值可以是存储器200中存储单元201内的存储值。所述第一控制信号用于控制进借位确定电路202对存储单元201内存储的计数起始值进行计算。存储器200接收到第一控制信号后，进借位确定电路202根据第一控制信号对存储单元201存储的计数起始值进行计算，并生成表征计数起始值计算结果的第二控制信号，并通过数据回写电路203将最新的计算结果重新写入存储单元201中，实现对存储单元201当前存储的计数起始值进行更新。其中，计数起始值可以是多位二进制数值。
在一种可实现的方式中，为了减缓处理器的占用，可以将处理器的一部分逻辑计算通过存储器200实现，即处理器先通过数据总线将待计算的数值发送给存储器200作为计数起始值，并向存储器200发送用于计算计数起始值的第一控制信号，待处理器对计数起始值计算完成后，处理器再通过数据总线读取计算结果，并将计算结果发送给对应装置，从而缓解处理器的占用。
在一种可能的实现方式中，计数起始值为地址寄存器内存储的地址。
需要说明的是，处理器内部设置有地址寄存器，该地址寄存器内存储了处理器待访问的目标程序指令的地址。处理器根据地址寄存器当前存储的地址获取目标程序指令，当目标程序指令执行完毕后，地址寄存器的地址自动加1，这样处理器可以自动执行下一条程序指令。其中，该地址可以是目标程序指令的段号和/或行号。
若采用上述存储器对地址寄存器存储的地址进行更新时，处理器可以通过数据总线先将地址寄存器的第一地址输出给存储器200的存储单元201中作为计数起始值，当第一地址对应的目标程序指令执行完毕后，处理器向存储器200发送第一控制信号，存储器200接收到第一控制信号后对第一地址进行加1计算，得到第二地址，处理器通过数据总线读取第二地址，并将第二地址输出给地址寄存器。
具体地，存储单元201分别与进借位确定电路202和数据回写电路203连接，用于将存储的计数起始值输出给进借位确定电路202；进借位确定电路202与数据回写电路203连接，用于根据处理器发送的用于计算计数起始值的第一控制信号以及计数起始值，生成第二控制信号；数据回写电路203用于接收第二控制信号，并根据第二控制信号，对存储单元201中存储的计数起始值进行更新。
实际使用时，存储器200中的进借位确定电路202、存储单元201以及数据回写电路203通过数据传输线实现连接以及通信。
具体实现时，数据回写电路203以及进借位确定电路202可以由开关管、多路选择器、二极管等器件组成。数据回写电路203以及进借位确定电路202的工作状态可以通过调节这些器件(例如开关管)的工作状态来实现。
本申请中，可以通过处理器或控制器实现上述进借位确定电路201以及数据回写电路203工作状态的调节，即，存储器200还可以包括控制器(未示出)，该控制器可以用于在接收到处理器发送的第一控制信号，控制进借位确定电路202生成第二控制信号，以及控制数据回写电路203对存储单元201中存储的计数起始值进行更新。
在一示例中，若计数起始值为存储器200中存储单元201的存储值时，控制器在接收到第一控制信号时，直接控制进借位确定电路202生成第二控制信号，以及控制数据回写电路203对存储单元201中存储的计数起始值进行更新。
在另一示例中，若计数起始值为地址寄存器的地址，则控制器在确定存储单元201接收到处理器发送的计数起始值、且接收到第一控制信号时，控制进借位确定电路202生成第二控制信号，以及控制数据回写电路203对存储单元201中存储的计数起始值进行更新。
具体地，若存储器200中进借位确定电路202以及数据回写电路203中的开关管为金属氧化物半导体(metal oxide semiconductor，MOS)管，该控制器可以与MOS管的栅极连接，从通过控制MOS管的通断使得进借位确定电路202生成第二控制信号，以及控制数据回写电路203对存储单元201中存储的计数起始值进行更新；若存储器200中进借位确定电路202以及数据回写电路203中的开关管为双极结型晶体管(bipolar junction transistor，BJT)，该控制器可以与BJT的基极连接，从通过控制BJT的通断使得进借位确定电路202生成第二控制信号，以及控制数据回写电路203对存储单元201中存储的计数起始值进行更新。
具体实现时，控制器可以是驱动器，该驱动器在接收到处理器发送的用于计算计数起始值的第一控制信号后，向数据回写电路203以及进借位确定电路202中的开关管发送对应驱动信号，来控制数据回写电路203以及进借位确定电路202的状态。
其中，驱动器可以是驱动信号，也可以是由开关管等器件组成的驱动电路，当然，控制器的具体形态不限于上述举例。
下面，对存储器200中的存储单元201、进借位确定电路202以及数据回写电路203的具体结构进行介绍。
一、存储单元201
存储单元201分别与进借位确定电路202以及数据回写电路203连接，存储单元201用于将存储的计数起始值发送给进借位确定电路202，以及接收数据回写电路203输出的更新后的计数起始值对当前存储的计数起始值进行覆盖，实现对计数起始值的更新。
其中，存储单元201可以设置有输出端口和输入端口。其中，该输出端口可以用于输出存储的多位二进制数值以及多位二进制数值的取反数值，输入端口用于接收数据回写电路203发送的更新后的计数起始值。
在一种可能的实现方式中，存储单元201可以包括与计数起始值中的多位二进制数值一一对应的第一输入端口、与多位二进制数值一一对应的第二输入端口、与多位二进制数值一一对应的第一输出端口以及与多位二进制数值一一对应的第二输出端口。
其中，每一个第一输入端口与数据回写电路203连接，用于接收数据回写电路203发送的更新后的计数起始值中对应位二进制数值；每一个第二输入端口与数据回写电路203连接，用于接收数据回写电路203发送的更新后计数起始值中对应位二进制数值的取反数值；每一个第一输出端口与进借位确定电路202连接，用于输出存储的对应位二进制数值；每一个第二输出端口与进借位确定电路202连接，用于输出存储的对应位二进制数值的取反数值。
在一种可能的实现方式中，存储单元201可以包括用于接收数据回写电路203发送的更新后的计数起始值的第三输入端口、用于接收数据回写电路203发送的更新后的计数起 始值的取反数值的第四输入端口、用于输出多位二进制数值的第三输出端口和用于输出多位二进制数值的取反数值的第四输出端口。
具体实现时，存储单元可以是DRAM、PCM、RRAM、MRAM、FRAM中的任一种，当然，存储单元的具体形态不限于上述举例。
二、进借位确定电路202
进借位确定电路202分别与存储单元201和数据回写电路203连接，用于接收存储单元201存储的计数起始值，并根据处理器发送的用于计算计数起始值的第一控制信号，对当前存储的计数起始值进行计算，并将表征计算结果的第二控制信号发送给数据回写电路203中，来控制数据回写电路203将计算结果重新写入存储单元201中。
需要说明的是，计数起始值可以为N位二进制数值，当进借位确定电路接收到第一控制信号，并对计数起始值进行计算时，可能会造成计数起始值中的多位二进制数值发生变化，为了准确的得到计算结果，为N位二进制数值中的每一位二进制数值配置用于进借位生成电路，该进借位生成电路可以确定计算过程中计数起始值中的每一位二进制数值的变化情况。其中，N可以是大于等于2的整数。
具体的，参见图3所示，进借位确定电路202包括控制电路2021、与计数起始值中的每一位二进制数值一一对应的进借位生成电路2022以及与每一个进借位生成电路2022一一对应连接的判断电路2023。
其中，每i个进借位生成电路2022与存储单元201连接，用于接收计数起始值中的第i位二进制数值，并根据处理器发送的第一控制信号和第i位二进制数值，生成第i个进借位信号，并将第i个进借位信号输出给与第i+1位进借位生成电路，所述第i+1个进借位生成电路接收计数起始值的第i+1位二进制数值、且所述第i+1位二进制数值为所述第i位二进制数值的相邻高位二进制数值；第i个判断电路2023与控制电路2021连接，用于接收连接第i个进借位信号，根据接收的信号，向控制电路发送第三控制信号，第三控制信号用于指示第i位二进制数值是否已经更新完成；控制电路2021与数据回写电路203连接，用于根据每一个判断电路2022输出的第三控制信号，生成第二控制信号并输出给数据回写电路203。
参见图4所示，假设存储单元中存储的计数起始值为0101，则图4中的第一个进借位生成电路接收最低位的第一个二进制数值1，第二个进借位生成电路接收第二个二进制数值0，第三个进借位生成电路接收第一个二进制数值1，第四个进借位生成电路接收第二个二进制数值0。
在一种可能的实现方式中，每一个进借位生成电路2022分别与存储单元201中的第一输出端口和第二输出端口连接，以获取对应位二进制数值。其中，第一输出端口用于输出对应位二进制数值，第二输出端进口用于输出对应位二进制数值的取反数值。
在另一种可能的实现方式中，每一个进借位生成电路2022分别与存储单元201的第三输出端口连接，用于获取进借位生成电路2022的对应位二进制数值，每一个进借位生成电路2022分别与存储单元201的第四出端口连接，用于获取进借位生成电路2022的对应位二进制数值的取反数值。
其中，设置进借位生成电路2022的作用是：每一个进借位生成电路2022用于确对存储器201存储的计数起始值进行计算的过程中对应位二进制数值的计算结果，以及确定进 借位生成电路2022对应位二进制数值是否向相邻高位二进制数值发送进借位信号。应理解，在进借位生成电路2022向对应位二进制数值的相邻高位二进制数值发送进借位信号时，将会直接改变与对应位二进制数值的相邻高位二进制数值的状态。其中，二进制数值的状态包括0和1。
在一示例中，0可以是电压值低于第一阈值的电压信号，1可以是电压值高于第二阈值的电压信号。其中，第一阈值和第二阈值可以相同，第二阈值也可以高于第一阈值。
设置判断电路2023的作用是；在对存储器201存储的计数起始值进行计算的过程中，检测连接的进借位生成电路2022的对应位二进制数值的状态是否已经更新完毕，并向控制电路2021发送指示连接的进借位生成电路2022的对应位二进制数值的状态是否已经更新完毕的第三控制信号。
设置控制电路2021的作用是：通过每一个判断电路2023输出的第三控制信号，确定计数起始值中的所有二进制数值的状态是否已经更新完毕，在确定计数起始值中的所有位二进制数值的状态更新完毕时，向数据回写电路203发送第二控制信号，控制数据回写电路203对存储单元201存储的计数起始值进行更新。
需要说明的是，在对存储器201内存储的计数起始值进行计算的过程中，第i位二进制数值的更新情况，不仅与该位的二进制数值有关，还与i-1位二进制数值的进借位信号有关。因此，第i位二进制数值对应的进借位生成电路2022可以利用处理器发送的用于第一控制信号、接收的第i位二进制数值以及第i-1个二进制数值的输出的进借位信号，生成第i个进借位信号，并将第i个进借位信号发送给第i+1个进借位生成电路，以供第i+1个进借位生成电路确定第i+位二进制数值的更新状态。
实际使用时，由于计数起始值中的最低位二进制数值无相邻低位二进制数值，对于最低位二进制数值对应的进借位生成电路根据第一控制信号和计数起始值中的最低位二进制数值，生成第一个进借位信号。
为了便于理解，下面分别给出进借位生成电路2022、判断电路2023以及控制电路2021的具体电路结构。
参见图5，为第i个进借位生成电路2022的结构示意图。如图5所示，该进借位生成电路2022可以包括：放大电路U1、第一多路选择开关K1、第一开关管S1、第二开关管S2和第一与门电路Z1。
图5所示的第i个进借位生成电路2022中各器件的连接关系可以是：U1的第一输入端与存储单元201的第三输出端口连接，用于获取计数起始值中的第i位二进制数值，U1的第二输入端与存储单元201的第四输出端口连接，用于获取第i位二进制数值的取反数值，U1的第一输出端与K1的第一输入端连接，U1的第二输出端与K1的第二输入端连接；K1的控制端用于接收第一控制信号，K1的输出端与Z1的第二输入端连接；S1的第一端用于第i-1个进借位信号，S1的第二端分别与Z1的第一输入端以及S2的第二端连接；S2的第一端与地线连接；Z1的输出端用于输出第i个第一进借位信号。
在一示例中，当接收的计数起始值对应位二进制数值的信号幅值满足K1和Z1的启动幅值时，为了减小进借位生成电路的体积，进借位生成电路可以只包括K1、S1、S2和Z1。
具体实现时，进借位生成电路2022中第二进借位信号、对应位二进制数值、第一控制信号与第一进借位信号的关系可以表一所示。
表一
Figure PCTCN2020142418-appb-000001
下面结合图5和表1，以处理器发送用于对计数起始值进行加法运算的第一控制信号为例，对i进借位生成电路2022生成第一进借位信号的过程进行说明。
假设计数起始值为0101为例，若i为3则第i个进借位生成电路2022的对应位二进制数值为1为例。U1的第一输入端通过连接的第三输出端口获取对应位二进制数值1，U1的第二输入端通过连接的第四输出端口获取对应位二进制数值的取反数值0，并将获取的信号进行幅值放大，U1的第一输出端输出经过幅值放大后的对应位二进制数值1，U1的第二输出端输出经过幅值放大后的对应位二进制数值的取反数值0，若K1的控制端接收高电平信号的第一控制信号，则K1将第一输入端接收的经过幅值放大后的1输出给Z1的第二输入端，若Z1的第一输入端接收的第二进借位信号为高电平信号1，则Z1输出的第一进借位信号位高电平信号，该高电平信号表征向对应位二进制数值相邻高位二进制数值进行进位，此处进借位确定电路202呈现加法运算功能。
若i为2，则第i个进借位生成电路2022的对应位二进制数值为0为例，U1的第一输入端通过连接的第三输出端口获取对应位二进制数值0，U1的第二输入端通过连接的第四输出端口获取对应位二进制数值的取反数值1，并将获取的信号进行幅值放大，U1的第一输出端输出经过幅值放大后的对应位二进制数值0，U1的第二输出端输出经过幅值放大后的对应位二进制数值的取反数值1，若K1的控制端接收高电平信号的第一控制信号，则K1将第一输入端接收的经过幅值放大后的0输出给Z1的第二输入端，若Z1的第一输入端接收的第二进借位信号为高电平信号1，则Z1输出的第一进借位信号为低电平信号，该低电平信号表征无需向对应位二进制数值相邻高位二进制数值进行进位，此处进借位确定电路202呈现加法运算功能。
下面结合图5和表1，以处理器发送用于对计数起始值进行减法运算的第一控制信号为例，对进借位生成电路2022生成第一进借位信号的过程进行说明。
假设计数起始值为0101为例，若i为3，则第i个进借位生成电路2022的对应位二进制数值为1为例。U1的第一输入端通过连接的第三输出端口获取对应位二进制数值1，U1的第二输入端通过连接的第四输出端口获取对应位二进制数值的取反数值0，并将获取的信号进行幅值放大，U1的第一输出端输出经过幅值放大后的对应位二进制数值1，U1的第二输出端输出经过幅值放大后的对应位二进制数值的取反数值0，若K1的控制端接收低电平信号的第一控制信号，则K1将第二输入端接收的经过幅值放大后的0输出给Z1的第二输入端，若Z1的第一输入端接收的第二进借位信号为高电平信号1，则Z1输出第一进 借位信号为低电平信号，该低电位信号表征无需向对应位二进制数值的相邻高位二进制数值借位。此时进借位确定电路202呈现减法运算功能。
若i为2，则第i个进借位生成电路2022的对应位二进制数值为0为例。U1的第一输入端通过连接的第三输出端口获取对应位二进制数值0，U1的第二输入端通过连接的第四输出端口获取对应位二进制数值的取反数值1，并将获取的信号进行幅值放大，U1的第一输出端输出经过幅值放大后的对应位二进制数值0，U1的第二输出端输出经过幅值放大后的对应位二进制数值的取反数值1，若K1的控制端接收低电平信号的第一控制信号，则K1将第二输入端接收的经过幅值放大后的1输出给Z1的第二输入端，若Z1的第一输入端接收的第二进借位信号为高电平信号1，则Z1输出的第一进借位信号为高电平信号，该高电平信号表征向对应位二进制数值的相邻高位二进制数值借位。此时进借位确定电路202呈现减法器功能。
以此类推，在对计数起始值进行计算过程中，通过与计数起始值中的多个二进制数值对应的进借位生成电路2022确定计数起始值中的每一位二进制数值的进借位情况。
需要说明的，与计数起始值中的最低位二进制数值对应的进借位生成电路2022无法接收到相邻低位二进制数值的进借位信号，控制器或者处存储器200在接收到用于对计数起始值进行加法运算的第一控制信号时，向最低位二进制数值对应进借位生成电路2022中的S1的第一端发送表征进位的高电平信号，以及在接收到用于对计数起始值进行减法运算的第一控制信号时，向最低位二进制数值对应进借位生成电路中的S1的第一端发送表征借位的低电平信号。
下面结合实施例，以计数起始值为000111，处理器向存储器200发送高电平信号的第一控制信号为例，采用多个进借位生成电路2022对计数起始值进行计算的过程进行说明。
如图6所示，当处理器发送高电平信号的第一控制信号时，最低位二进制数值1对应的进借位生成电路2022执行加法运算，同时向最低位二进制数值1对应的第一个进借位生成电路2022输出高电平信号1，此时第一个进借位生成电路2022输出表征进位的高电平信号1，并输出给第二个进借位生成电路2022，第二个进借位生成电路2022执行加法运算，并输出继续进位的高电平信号1，第三个进借位生成电路2022输出的高电平信号并执行加法运算，向第四个进借位生成电路2022发送继续进位的高电平信号1，第四二进制数值0执行加法运算，此时，第四个进借位生成电路0发送用于执行进借的低电平信号0。整个计数起始值的计算完成。
实际使用时，进借位生成电路2022接收在接收到第一控制信号时，才会对存储器200存储的计数起始值进行计算，而避免上一次对计数起始值进行计算时接收的信号对本次计算的影响，进借位生成电路2022在每一次计算对应位二进制数值的进借位情况时，控制器或者处理器可以对进借位生成电路2022进行初始化。
参见图7，为第i个进借位生成电路2022的初始化过程。如图7所示，控制器或存储器在未接收到第一控制信号时，表征进借位生成电路2022的工作的时钟CLK信号为低电平信号，此时向S1的控制端发送低电位信号，向S2的控制端发送高电平信号，S1断开不接收第i-1个进借位信号，同时S2导通将Z1第一输入端接地，Z1的第一输入端无法接收到信号。当控制器或者存储器接收到第一控制信号时，表征进借位生成电路2022的工作的时钟CLK信号为低电平信号，向S1的控制端发送高电平信号，向S2的控制端发送低电平信号，S1导通接收第i-1个进借位信号，S1断开实现将S2传输的第i-1个进借位信号 输出给Z1的第一输入端。
参见图8，为第i个判断电路2023的一种结构示意图。如图8所示，该第i个判断电路2023可以包括：第一延迟电路D1和第一异或门电路Z2。
图8所示的判断电路2023中各器件的连接关系可以是：D1的输入端与第i个进借位生成电路2022连接，用于接收第i-1个进借位信号，D1的输出端与Z2电路的第一输入端连接；Z2的第二输入端与第i个进借位生成电路2022连接，用于接收第i个进借位信号，Z2的输出端用于输出表征连接的进借位生成电路2022对应位二进制数值状态是否更新完成的第三控制信号。
通过图8所示的第i个判断电路2023确定第i位二进制数值状态是否更新完成时，通过检测连接的进借位生成电路2023接收到第i-1个进借位信号后输出的第i个进借位信号的状态，确定第i位二进制数值是否更新完毕。
具体实现时，由于连接的进借位生成电路2022接收到第i-1个进借位信号之后，需要经过进借位生成电路2022内部器件的计算和延时才能输出第i个进借位信号，因此，第i-1个进借位信号与第i个进借位信号之间存在一定的时延，为了保证检测结果的准确性，判断电路2023中增加的第一延迟电路D1，利用D1延时后输出的第i个进借位信号以及D1延时前接收的第i-1个进借位信号，生成指示第i位二进制数值是否状态更新完毕的第三控制信号。
具体实现时，第一进借位信号、第二进借位信号与第三控制信号的关系可以表二所示。
表二
第i个进借位信号 第i-1个进借位信号 第三控制信号
0 0 0
1 1 0
0 1 1
如表二所示，判断电路2023在接收到第i个进借位信号和第i-1个进借位信号均为低电平信号时，表征第i位二进制数值未接收进借位信号，连第i位二进制数值的状态无需更新，在连接的第i个进借位信号和第i-1个进借位信号均为高电平信号时，表征第i位二进制数值接收到相邻低位二进制数值的发送的第二进借位信号，且向相邻的高位二进制数值进行进位或者借位，则第i+1位二进制数值的状态仍然会发生变化。
应理解，当第i个判断电路2023连接的第i个进借位生成电路2023未输出第i个进借位信号时，表征第i+1位二进制数值的状态不会发生变化，整个计数起始值计算完毕。
实际使用时，为了避免连接的进借位生成电路2022上次计算时输出的第i个进借位信号以及接收的第i-1个进借位信号对检测的影响，Z2的第二输入端可以与第i个进借位生成电路2022中的第一开关管的第二端连接，用于获取本次对计数起始值计算过程中连接的进借位生成电路2022接收的第i-1个进借位信号，以保证检测结果的准确度。
参见图9，为第i个判断电路2023的另一种结构示意图。如图9所示，该第i个判断电路2023包括：第二异或门电路Z3、第二延迟电路D2和第二与门电路Z4。
图8所示的判断电路2023中各器件的连接关系可以是：Z3的第一输入端与对应的第i个进借位生成电路2022的输出端连接，用于接收第i个进借位信号，第Z3的第二输入端与对应的第i个进借位生成电路2022的输入端连接，用于接收第i-1个进借位信号，Z3的输出端分别与D2的输入端以及Z4的第一输入端连接；D2的输出端与Z4的第二输入端连 接；Z4的输出端用于输出第三控制信号。
具体实现时，第i个进借位信号、第i-1个进借位信号与第三控制信号的关系可以参见上述表二所示，本申请这里不做重复介绍。
具体实现时，Z3的第二端可以与第i个进借位生成电路2022中的第一开关管的第二端连接。
参见图10所示，为控制电路2021的一种结构示意图。如图10所示，该控制电路2021可以包括：第三开关管S3、与每一个判断电路一一对应的第四开关管S4、与每一个S3一一对应的第四开关管S4。
图9所示的控制电路2021中各器件的连接关系可以是：S3的第一端与供电电源连接，S3的第二端与第一节点连接，第一节点用于输出第二控制信号；每一个S4的第一端均与第一节点连接，每一个S4的控制端用于接收对应的判断电路输出的第三控制信号；每一个S5的第一端均与对应的S4的第二端连接，每一个S5的第二端与地线连接。其中，供电电源可以存储器200内部的供电电源，也可以是存储器200连接的外部电源。
采用图10所示的控制电路检测计数起始值中每一位二进制数值的状态是否更新完成时，每一个S4的控制端可以接收第三控制信号，所述第三控制信号用于指示连接的进借位生成电路的对应位二进制数值是否完成了状态更新，当第三开关管接收到高电平信号的第三控制信号，表征该高电平信号的第三控制信号的对应位二进制数值的并无发生进借位，整个计数起始值的状态更新完毕，此时接收高电平信号第三控制信号的S4导通，将第一节点的电位拉低至零，发送表征计数起始值更新完毕的低电平第二控制信号给数据回写电路203，控制数据回写电路203进行数据回写，将最近的计算结果写入存储单元201中。
实际使用时，控制电路2021在每一次处理器发送对计数起始值进行修改的第一控制信号，均对接收一次第三控制信号，在未对计数起始值进行修改时，控制电路2021中的多个第四控制信号可能会呈现相应的电平状态，为了避免出现检测失误，可以在未收到第一控制信号时，向控制电路2021中的第五开关管的控制端发送低电平信号，第五开关管断开，所有第四开关管均无法接收第三控制信号，当接收到第一控制信号时，向第五开关管的控制端发送高电平信号，第五开关管导通，第四开关管接收第三控制信号，并根据第三控制信号第一节点输出对应的第二控制信号。
三、数据回写电路203
数据回写电路203分别与存储单元201和进借位确定电路202连接，用于接收进借位确定电路202发送的第二控制信号，并根据第二控制信号，对存储单元201中存储的计数起始值进行更新。
其中，数据回写电路203中可以包括与每一个进借位生成电路2022一一对应连接的子数据回写电路。
具体地，第i个子数据回写电路分别与控制电路2021和存储单元201连接，用于接收第二控制信号和连接的第i个进借位生成电路2022输出的第i个进借位信号，并根据接收的信号对存储单元201中存储的计数起始值中的第i位二进制数值进行更新。
为了便于理解，下面分别给出第i个子数据回写电路的具体电路结构。
在一种可能的实现方式中，每一个子数据回写电路均与存储单元201的第三输入端口和第四输入端口连接。
在另一种可能的实现方式中，第i个子数据回写电路与存储单元201中用于接收第i 位二进制数值的第一输入端口连接，每一个子数据回写电路与存储单元201中用于接收第i位二进制数值的取反数值的第二输入端口连接。
参见图11，为子数据回写电路的结构示意图。如图11所示，该子数据回写电路包括：第一非门电路Z5、第三与门电路Z6、第二多路选择开关K2、第三延迟电路D3、第二非门电路Z7、差分放大器U2和第三多路选择开关K3。
图10所示的子数据回写电路中各器件的连接关系是：Z5的输入端与控制电路2021输出端连接，Z5的输出端与第三与门电路的第二输入端连接；Z6的第一输入端用于接收第一使能信号，Z6的第三输入端与对应的进借位生成电路的输入端连接，用于接收第二进借位信号，Z6的输出端与K2的第一输入端连接，第一使能信号是处理器对计数起始值进行计算生成的；K2的第二输入端与第二与门电路的第一输入端连接，K2的输出端分别与D3的输入端和Z7的输入端连接，K2的控制端用于接收第二使能信号，第二使能信号是处理器对存储器进行访问生成的；D3的输出端与存储单元201中的第三输入端口连接；Z7的输出端与存储单元201中的第四输入端口连接；U2的第一输入端与存储单元201的第三输出端口连接，用于接收第i位二进制数值，U2的第二输入端与第四输出端口连接，用于接收第i位二进制数值的取反数值，U2的输出端与K3的第一输入端连接；K3的第二输入端与数据访问端口连接，K3的输出端分别与D3的输入端和Z7的输入端连接，K3的控制端接收第二使能信号。其中，处理器通过上述数据访问端口访问本申请实施例提供的存储器200。具体实现时，第一使能信号和第二使能信号可以处理器发送的，也可以是控制器接收到第一控制信号后发送的。
实际使用时，为了避免连接的进借位生成电路2022上次计算时输出的第i个进借位信号以及接收的第i-1个进借位信号对检测的影响，Z6的第三输入端可以与进借位生成电路2022中的第一开关管的第二端连接，用于获取本次对计数起始值计算过程中连接的进借位生成电路2022接收的第二进借位信号，以保证检测结果的准确度。
采用图11所示的第i个子数据回写电路对与第i位二进制数值进行更新时，当接收到处理器发送的第一控制信号、且接收的第二控制信号为低电平信号时，若第二使能信号为低电平信号，子数据回写电路通过数据访问端口将处理器发送的数据输出给存储单元201中进行存储，若第二使能信号为高电平信号，子数据回写电路将存储单元内存储的第i位二进制数值进行更新。具体地，当Z6连接的进借位生成电路接收的第二进借位信号为0时，则说明对应位二进制数值的状态未发生改变，则K2和K3关闭，存储单元201内存储的第i位二进制数值保持不变，若Z6的进借位生成电路接收的第二进借位信号为1时，则对应位二进制数值的状态发生改变，Z6输出高电平信号，K2断开，K3将U2中的存储的第i位二进制数值的取反数值输出给存储单元中。
具体实现时，K3在输出更新后二进制数值后，利用Z7和D3将K3输出的信号转换为两个状态相反的信号后输出给存储单元中存储。其中，D3的延时时长与Z7的器件延时时长相同。
具体实现时，第二使能信号为高电平信号时，表征处理器对存储器内的存储值直接进行读取，处理器可以通过K3的第二输入端直接读取存储单元内存储的数据。
在一示例中，若计数起始值为地址寄存器的地址时，待地址更新完毕后，处理器可以通过存储器发送高电平的第二使能信号，并通过数据总线将更新后地址发送给地址寄存器。
结合以上描述，示例地，本申请实施例提供的一种存储器，可以如图12所示。
在进借位确定电路中，包括多个放大电路U1、U2、多路选择开关管K1、开关管S1、S2、S3、S4、S5、延时电路D1、D3、第一与门电路Z1和第一异或门电路Z2。其中，K1、S1、S2和Z1构成进借位生成电路，D1和Z2构成判断电路，S3、S4、S5构成控制电路。
在数据回写电路包括中，包括：多个第一非门电路Z5、第三与门电路Z6、第二多路选择开关K2、K3、第三延迟电路D3、第二非门电路Z7和差分放大器U2。其中，Z5、Z6、K2、K3、D3、Z7、U2和K3构成一个子数据回写电路。
下面结合图12对存储器的工作过程进行详细说明。
参见图13，处理器向图12所示的存储器发送访问指令时，处理器向多个子数据回写电路发送的第二使能信号为1，此时存储器工作访问模式，当第二使能信号为0时，存储器工作在计算模式。其中，1为高电平信号，0为低电平信号。
在一示例中，存储单元201可以接收处理器发送的待计算的数值并存储作为计数起始值。其中，计数起始值是N位二进制数值。以存储单元中存储的计数起始值的第i位二进制数值为例，如图12所示，第i个子数据回写电路中的K2和K3接收的第二使能信号为1时，K3将数据访问端口接收的数据分别输出给D3和Z7，此时处理器可以通过数据访问端口将1输出给D3和Z7，D3将1进行延时，Z7将1进行反转为0后，通过连接在存储单元之间的数据传输线，将0和1分别存储给存储单元中。
实际使用时，当接收到第二使能信号1时，经过第i个子数据回写电路的传输时延以及存储单元的存储时延后，第一输出端口将重新存储1输出，以及第二输出端口将存储的1的取反数值0输出。
以计数起始值的第i位二进制数值为0为例，当图12所示的存储器工作在计算模式时，存储单元的第三输出端口0和第四输出端口为1并输出给对应的第i进借位生成电路，在接收到第一控制信号之前，先向S1的控制端发送一个低电平信号0以及向S2发送一个高电平信号1的临时脉冲信号对第i个进借位生成电路进行初始化，其信号如图14所示，S1断开不接收上次计算时接收的第i-1个进借位信号，S2闭合将Z1的输入端拉低到0，Z1不接收信号，当S1和S2接收的脉冲信号结束时，S1接收到高电平信号1，接收第i-1个进借位信号并输出S2，S2接收到低电平信号1断开并将S1接收的第i-1个进借位信号传输给Z1，若第i-1个进借位信号为高电平信号1，则Z1输出给的第i个进借位信号为0并输出给Z2的一个输入端，D1将延后的第i-1进借位信号1输出给Z2的另一个输入端，Z2输出高电平信号1并传输给S4的控制端，S4在接收Z2发送的控制信号之前以及接收到第一控制信号之后，向S5的控制端先发送一个低电平信号的脉冲信号，S5断开，全部S4均无法接收信号，待脉冲信号结束，S5接收高电平信号1导通，S4接收Z2发送的高电平信号1导通，第一节点的电位拉低至0，该信号经过Z5反转为1输出给Z6的一个输入端，Z6的另一输入端接收用于控制计算的高电平第一使能信号1，Z6的另一端接收的第i-1进借位信号1，Z6输出高电平信号1，此时K2断开，U2将第二输入端口接收的i位二进制数值的取反数值0输出给D3和Z7，D3将低电平信号0延时后输出给存储单元的第三输入端口，Z7将低电平信号0反转为1后输出给存储单元的第四输入端口，D3和Z7输出的信号传输至存储单元后，对存储单元内存储计数起始值的第i位二进制数值进行覆盖，实现对第i位二进制数值的更新。此时，存储单元的第三输入端口输出0，第四输出端口输出1。
以此类推，对存储的计数起始值中的所有二进制数值进行更新。
需要说明的是，根据前述实施例提供的判断电路结构以及存储器中开关管的类型的不同，本申请实施例提供的过能保护电路还具有其它结构，其它电路结构原理相同，本申请不一一详细介绍。
基于同一发明构思，本申请实施例还提供一种计算机。参见图15，该计算机1500包括处理器1501和前述存储器200。
其中，处理器1501和前述存储器200连接。
可选地，该计算机还包括数据总线1502。
具体地，处理器1501通过数据总线1502与存储器连接。
计算机1500还包括一些外接设备，例如输入设备，用于接收输入的数字信息、字符信息或接触式触摸操作/非接触式手势，以及产生与计算机1500的用户设置以及功能控制有关的信号输入等。
除以上之外，计算机1500还可以包括用于给其他模块供电的电源。计算机1500还可以包括一个或多个传感器，例如图像传感器、亮度传感器、光线传感器、GPS传感器、红外传感器等。计算机1500还可以包括无线射频RF电路，用于与无线网络设备进行网络通信，还可以包括WiFi模块，用于与其他设备进行WiFi通信，获取其他设备传输的图像或者数据等。
需要说明的是，本申请中所涉及的多个，是指两个或两个以上。
本申请中所涉及的连接，描述两个对象的连接关系，可以表示两种连接关系，例如，A和B连接，可以表示：A与B直接连接，A通过C和B连接这两种情况。
另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
此外，本申请实施例中提供的系统结构和业务场景主要是为了解释本申请的技术方案的一些可能的实施方式，不应被解读为对本申请的技术方案的唯一性限定。本领域普通技术人员可以知晓，随着系统的演进，以及更新的业务场景的出现，本申请提供的技术方案对于相同或类似的技术问题仍然可以适用。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (13)

  1. 一种存储器，其特征在于，包括：存储单元、进借位确定电路以及数据回写电路；其中，所述存储单元中存储有计数起始值；
    所述存储单元用于将所述计数起始值输出给所述进借位确定电路；
    所述进借位确定电路用于根据处理器发送的用于修改所述计数起始值的第一控制信号以及所述计数起始值，生成第二控制信号；
    所述数据回写电路用于接收所述第二控制信号，并根据所述第二控制信号，对所述存储单元中存储的所述计数起始值进行更新。
  2. 如权利要求1所述的存储器，其特征在于，所述存储器还包括：控制器；
    所述控制器用于在接收到所述第一控制信号时，控制所述进借位确定电路生成所述第二控制信号，以及控制所述数据回写电路对所述存储单元中存储的所述计数起始值进行更新。
  3. 如权利要求1或2所述的存储器，其特征在于，所述计数起始值是N位二进制数值，所述进借位确定电路包括：控制电路、与每一位所述二进制数值一一对应的进借位生成电路以及与每一个所述进借位生成电路一一对应连接的判断电路；其中，N为大于等于2的整数；
    第i个所述进借位生成电路用于接收所述计数起始值的第i位二进制数值，并根据所述第一控制信号和所述第i位二进制数值，生成第i个进借位信号，并将所述第i个进借位信号输出第i+1个所述进借位生成电路；所述第i+1个进借位生成电路接收计数起始值的第i+1位二进制数值、且所述第i+1位二进制数值为所述第i位二进制数值的相邻高位二进制数值；
    第i个所述判断电路与所述控制电路连接用于接收连接的第i个所述进借位生成电路输出的所述第i个进借位信号，根据接收的信号，向所述控制电路发送第三控制信号，所述第三控制信号用于指示所述第i位二进制数值是否更新完毕；
    所述控制电路与所述数据回写电路连接，用于根据每一个所述判断电路输出的第三控制信号，生成所述第二控制信号并输出给所述数据回写电路。
  4. 如权利要求3所述的存储器，其特征在于，若i等于1，所述第i个所述进借位生成电路具体用于接收所述计数起始值的第i位二进制数值，并根据所述第一控制信号和所述第i位二进制数值，生成第i个进借位信号，并将所述第i个进借位信号输出第i+1个进借位生成电路；
    第i个所述判断电路具体用于：接收所述第i个进借位信号，根据接收的信号，向所述控制电路发送第三控制信号；
    若i大于1，所述第i个所述进借位生成电路具体用于接收所述计数起始值的第i位二进制数值以及第i-1个进借位信号，并根据所述第一控制信号、所述第i位二进制数值以及所述第i-1个进借位信号，生成第i个进借位信号，并将所述第i个进借位信号输出第i+1个进借位生成电路；
    第i个所述判断电路具体用于：接收所述第i个进借位信号以及所述第i-1个进借位信号，根据接收的信号，向所述控制电路发送第三控制信号。
  5. 如权利要求4所述的存储器，其特征在于，所述存储单元设置有输出端口；其中， 所述存储单元的输出端口用于输出所述N位二进制数值以及所述N位二进制数值的取反数值；
    若i大于1，第i个所述进借位生成电路包括：
    放大电路，所述放大电路的第一输入端与所述存储单元的输出端口连接，所述放电电路的第二输入端与所述存储单元的输出端口连接，所述放大电路的第一输出端与第一多路选择开关的第一输入端连接，所述放大电路的第二输出端与所述第一多路选择开关的第二输入端连接；
    所述第一多路选择开关，所述第一多路选择开关的控制端用于接收所述第一控制信号，所述第一多路选择开关的输出端与第一与门电路的第二输入端连接；
    第一开关管，所述第一开关管的第一端用于接收所述i-1个进借位信号，所述第一开关管的第二端分别与所述第一与门电路的第一输入端以及第二开关管的第二端连接；
    所述第二开关管，所述第二开关管的第一端与地线连接；
    所述第一与门电路，所述第一与门电路的输出端用于输出所述第i个进借位信号。
  6. 如权利要求3-5中任一项所述的存储器，其特征在于，若i大于1，第i个所述判断电路包括：
    第一延迟电路，所述第一延迟电路的输入端与对应的第i个所述进借位生成电路连接，用于接收连接所述第i-1个进借位信号，所述第一延迟电路的输出端与第一异或门电路的第一输入端连接；
    所述第一异或门电路，所述第一异或门电路的第二输入端与对应的第i个所述进借位生成电路连接，用于接收所述第i个进借位信号，所述第一异或门电路的输出端用于输出所述第三控制信号。
  7. 如权利要求3-5中任一项所述的存储器，其特征在于，若i大于1，第i个所述判断电路包括：
    第二异或门电路，所述第二异或门电路的第一输入端与对应的第i个所述进借位生成电路连接，用于接收连接所述第i个进借位信号，所述第二异或门电路的第二输入端与对应的进借位生成电路连接，用于接收所述第i-1个进借位信号，所述第二异或门电路的输出端分别与第二延迟电路的输入端以及第二与门电路的第一输入端连接；
    所述第二延迟电路，所述第二延迟电路的输出端与所述第二与门电路的第二输入端连接；
    所述第二与门电路，所述第二与门电路的输出端用于输出所述第三控制信号。
  8. 如权利要求3-7中任一项所述的存储器，其特征在于，所述控制电路包括：
    第三开关管，所述第三开关管的第一端与供电电源连接，所述第三开关管的第二端与第一节点连接，所述第一节点用于输出所述第二控制信号；
    与每一个所述判断电路一一对应的第四开关管，每一个所述第四开关管的第一端均与所述第一节点连接，每一个所述第四开关管的控制端用于接收对应的判断电路输出的第三控制信号；
    与每一个第四开关管一一对应的第五开关管，每一个所述第五开关管的第一端均与对应的第四开关管的第二端连接，每一个所述第五开关管的第二端与所述地线连接。
  9. 如权利要求5-8中任一项所述的存储器，其特征在于，所述数据回写电路包括：与每一个所述进借位生成电路一一对应连接的子数据回写电路；
    第i个所述子数据回写电路分别与所述控制电路和所述存储单元连接，用于接收所述第二控制信号和所述第i个进借位信号，并根据接收的信号对所述存储单元中存储的计数起始值中的第i位二进制数值进行更新。
  10. 如权利要求9所述的存储器，其特征在于，第i个所述子数据回写电路包括：
    第一非门电路，所述第一非门电路的输入端与所述控制电路输出端连接，所述第一非门的输出端与第三与门电路的第二输入端连接；
    所述第三与门电路，所述第三与门电路的第一输入端用于接收第一使能信号，所述第三与门电路的第三输入端与对应的进借位生成电路的输出端连接，所述第三与门电路的输出端与第二多路选择开关的第一输入端连接，所述第一使能信号是所述处理器对所述计数起始值进行计算生成的；
    所述第二多路选择开关，所述第二多路选择开关的第二输入端与所述第二与门电路的第一输入端连接，所述第二多路选择开关的输出端分别与第三延迟电路的输入端和第二非门电路的输入端连接，所述第二多路选择开关的控制端用于接收第二使能信号，所述第二使能信号是所述处理器对所述存储器进行访问生成的；
    所述第三延迟电路，所述第三延迟电路的输出端与所述存储单元连接；
    所述第二非门电路，所述第二非门电路的输出端与所述存储单元连接；
    差分放大器，所述差分放大器的第一输入端用于接收所述第i位二进制数值，所述差分放大器的第二输入端与用于接收所述第i位二进制数值的取反数值，所述差分放大器的输出端与第三多路选择开关的第一输入端连接；
    所述第三多路选择开关，所述第三选择开关的第二输入端与数据访问端口连接，所述第三多路选择开关的输出端分别与所述第三延迟电路的输入端和所述第二非门电路的输入端连接，所述第三多路选择开关的控制端用于接收所述第二使能信号，所述处理器通过所述数据访问端口访问所述存储器。
  11. 如权利要求1-10中任一项所述的存储器，其特征在于，所述控制器还用于控制所述数据回写电路将所述处理器发送的数据存储至所述存储单元；或者
    将所述存储单元存储的数据输出给所述处理器。
  12. 如权利要求1-11中任一项所述的存储器，其特征在于，所述计数起始值为地址寄存器存储的地址。
  13. 一种计算机，其特征在于，包括处理器和如权利要求1-12中任一项所述的存储器；
    所述处理器与所述存储器连接。
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