WO2022137993A1

WO2022137993A1 - Comparator and solid-state imaging element

Info

Publication number: WO2022137993A1
Application number: PCT/JP2021/043599
Authority: WO
Inventors: 大基田平; 秀樹田中; 耕治塚本
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2020-12-21
Filing date: 2021-11-29
Publication date: 2022-06-30

Abstract

A connection circuit (30) connected between a first amplifier circuit (10) and second amplifier circuit (20) includes: a first switch (31) connected between another current terminal of a third transistor (13) and the second amplifier circuit (20); and a second switch (32) connected between another current terminal of a fourth transistor (14) and the second amplifier circuit (20).

Description

Comparator and solid-state image sensor

The present disclosure relates to a comparator and a solid-state image sensor.

Some AD converters include a comparator. In the comparator, an auto zero operation for initializing the internal voltage and the like and a comparison operation (AD conversion operation) are performed. For example, Patent Document 1 discloses a method of switching the diode connection of each pair of transistors connected between a transistor constituting a differential pair and a power supply between auto zero operation and comparative operation.

Japanese Unexamined Patent Publication No. 2014-197773

Voltage fluctuation may occur due to feedthrough that occurs when switching diode connections, and the number of counts during AD conversion may increase. No specific study has been made on this point in Patent Document 1.

One aspect of the present disclosure provides a comparator and a solid-state image sensor capable of suppressing an increase in the number of counts during AD conversion.

The comparator according to one aspect of the present disclosure is a connection circuit connected between a first amplification circuit, a second amplification circuit provided after the first amplification circuit, and the first amplification circuit and the second amplification circuit. The first amplification circuit comprises a first transistor in which a reference signal is input to the control terminal, and a second transistor in which an input signal is input to the control terminal via a capacitor to form a differential pair together with the first transistor. A transistor, a third transistor in which one current terminal is connected to one of the ground and the power supply, the other current terminal is connected to one of the current terminals of the first transistor, and one current terminal is connected to one of the ground and the power supply. A fourth transistor connected and the other current terminal connected to one current terminal of the second transistor, the other current terminal of the first transistor, the other current terminal of the second transistor, and the ground and the other of the power supply. A second transistor switch connected between one of the current terminals and the control terminal of the second transistor, and a control terminal of the third transistor and the other of the third transistor. The current terminal and the control terminal of the 4th transistor are connected to each other, and the connection circuit consists of the 1st switch connected between the other current terminal of the 3rd transistor and the 2nd amplification circuit, and the other current of the 4th transistor. Includes a second switch connected between the terminal and the second amplification circuit.

The solid-state imaging device according to one aspect of the present disclosure includes a plurality of pixels and an AD converter that converts each pixel signal of each of the plurality of pixels into a digital signal, and the AD converter includes a pixel signal and a reference signal. Including a comparator to compare with, the comparator is a connection connected between the first amplification circuit, the second amplification circuit provided after the first amplification circuit, and the first amplification circuit and the second amplification circuit. The first amplification circuit includes a circuit, a first transistor in which a reference signal is input to a control terminal, and a first transistor in which an input signal is input to a control terminal via a capacitor to form a differential pair together with the first transistor. Two transistors, a third transistor in which one current terminal is connected to one of the ground and the power supply, the other current terminal is connected to one of the current terminals of the first transistor, and one current terminal is one of the ground and the power supply. A fourth transistor connected to and the other current terminal connected to one current terminal of the second transistor, the other current terminal of the first transistor and the other current terminal of the second transistor, and the ground and the other of the power supply. The control terminal of the third transistor, the control terminal of the third transistor, including the switch for the second transistor connected between the current source connected to the second transistor and one of the current terminals and the control terminal of the second transistor. The other current terminal and the control terminal of the fourth transistor are connected to each other, and the connection circuit is the first switch connected between the other current terminal of the third transistor and the second amplification circuit, and the other of the fourth transistor. Includes a second switch connected between the current terminal and the second amplification circuit.

It is a figure which shows the example of the schematic structure of the solid-state image pickup device which concerns on embodiment. It is a figure which shows the example of the schematic structure of a pixel and the like. It is a figure which shows the example of the schematic structure of a comparator. It is a figure which shows the example of the operation of a comparator schematically. It is a figure which shows the example of the schematic structure of a comparator. It is a figure which shows the example of the schematic structure of a comparator. It is a figure which shows the example of operation schematically. It is a figure which shows the example of the schematic structure of the comparator which concerns on a comparative example. It is a figure which shows the example of the schematic structure of the comparator which concerns on a comparative example. It is a figure which shows typically the example of the operation of the comparator which concerns on a comparative example. It is a figure which shows the example of the operation of a comparator schematically. It is a figure which shows the example of the schematic structure of the comparator which concerns on the modification. It is a figure which shows the example of the operation of a comparator schematically. It is a block diagram which shows an example of the schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of the vehicle exterior information detection unit and the image pickup unit.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the following embodiments, the same elements are designated by the same reference numerals, so that duplicate description will be omitted.
The present disclosure will be described according to the order of items shown below.
1. 1. Embodiment 2. Modification example 3. Application example to mobile body 4. Effect 1. Embodiment

FIG. 1 is a diagram showing an example of a schematic configuration of a solid-state image sensor according to an embodiment. The solid-state image sensor 111 includes a pixel array unit 112, a timing control unit 113, a reference signal generation circuit 114, a row scanning unit 115, a column scanning unit 116, and a column processing unit 117. The solid-state image sensor 111 is, for example, a CMOS image sensor.

The pixel array unit 112 includes a plurality of pixels 121 arranged in a matrix (m rows and n columns). In order to distinguish each pixel 121, it is referred to as a pixel 121 _mn or the like and is shown. The pixels 121 in each row are connected to the row scanning unit 115 via the horizontal signal line 122. The horizontal signal line 122 corresponding to each line is referred to as a horizontal signal line 122 _m or the like and is illustrated. The pixels 121 in each row are connected to the column processing unit 117 via the vertical signal line 123. Each vertical signal line 123 corresponding to each line is referred to as a vertical signal line 123 _n or the like and is illustrated. Each pixel 121 is driven line by line according to a control signal supplied via the horizontal signal line 122, and outputs a pixel signal VSL at a level corresponding to the amount of received light to the vertical signal line 123.

The timing control unit 113 controls the operation timing of the reference signal generation circuit 114, the row scanning unit 115, the column scanning unit 116, and the column processing unit 117 by generating and supplying various signals. Examples of the signal generated by the timing control unit 113 include a clock signal CLK, a control signal CS1, a control signal CS2, and a control signal CS3. The clock signal CLK serves as an operating reference for the reference signal generation circuit 114 and the column processing unit 117. The control signal CS1 controls the operation of the reference signal generation circuit 114. The control signal CS2 and the control signal CS3 control the operation of the column processing unit 117.

The reference signal generation circuit 114 generates a reference signal Vramp and supplies it to the column processing unit 117. The reference signal Vramp is a lamp signal whose voltage value changes (rises or falls) with a constant gradient according to the clock signal CLK.

The row scanning unit 115 drives the pixel 121 row by row. For example, the row scanning unit 115 supplies the pixel 121 with a control signal (transfer signal, selection signal, reset signal, etc.) for driving the pixel 121 row by row.

The column scanning unit 116 supplies a control signal to the column processing unit 117, and outputs the pixel signal VSL AD-converted by the column processing unit 117, which will be described later, to the horizontal output line in order for each column.

The column processing unit 117 is provided for each column and processes the pixel signal from the pixel 121. An example of processing is AD conversion, and the column processing unit 117 includes an AD conversion circuit 130 provided for each column. The AD conversion circuit 130 corresponding to each column is referred to as an AD conversion circuit 130 _n or the like and is illustrated. The AD conversion circuit 130 AD-converts the pixel signal VSL from the pixel 121 input via the vertical signal line 123.

The AD conversion circuit 130 includes a comparator 131, a counter 132, a switch 133, and a memory 134. The comparator 131, the counter 132, and the switch 133 corresponding to each column are referred to as a comparator 131 _n , a counter 132 _n , a switch 133 _n , and the like, and are illustrated.

The reference signal Vramp is input to one input terminal of the comparator 131. A pixel signal VSL is input to the other input terminal of the comparator 131. The output terminal of the comparator 131 is connected to the counter 132. Comparator 131 compares the reference signal Vram with the pixel signal VSL. For example, the comparator 131 outputs a high-level signal when the voltage of the reference signal Vram is larger than the voltage of the pixel signal VSL, and outputs a low-level signal when the voltage of the reference signal Vram is equal to or lower than the voltage of the pixel signal VSL. Output. Alternatively, the comparator 131 outputs a high-level signal when the voltage of the reference signal Vram is equal to or lower than the voltage of the pixel signal VSL, and outputs a low-level signal when the voltage of the reference signal Vram is larger than the voltage of the pixel signal VLS. Output. The output voltage of the comparator 131 is referred to as a voltage VOUT2 and is shown in the figure.

The counter 132 performs a down count or an up count in synchronization with the clock signal CLK according to the control signal CS2. The count value (count result) corresponds to the comparison period between the reference signal Vram and the pixel signal VSL in the comparator 131.

The switch 133 is turned on (conducting state) when the counting operation of the counter 132 for the pixel 121 in the predetermined row is completed according to the control signal CS3. Then, the switch 33 transfers the count value of the counter 132 to the memory 134.

The memory 134 outputs the retained pixel signal VSL after AD conversion to the horizontal output line according to the control signal supplied from the column scanning unit 116.

FIG. 2 is a diagram showing an example of a schematic configuration of pixels and the like. The pixel 121 includes a PD 141, a transfer transistor 142, a charge storage unit 143, an FD (floating diffusion) unit 144, an amplification transistor 145, a selection transistor 146, and a reset transistor 147.

PD141 is a photodiode (photoelectric conversion unit) that generates and stores electric charges according to the amount of received light. The anode of the PD 141 is connected to the ground GND and the cathode is connected to the gate of the amplification transistor 145 via the transfer transistor 142.

The transfer transistor 142 is connected between the PD 141 and the charge storage unit 143, and transfers the charge stored in the PD 141 to the charge storage unit 143. The charge transfer is controlled by the transfer signal Tx supplied to the gate of the transfer transistor 142. The transfer signal Tx is supplied from the row scanning unit 115 (FIG. 1).

The charge storage unit 143 is a capacitance provided between the ground GND and the FD unit 144, and stores the charge transferred from the PD 141 via the transfer transistor 142.

The FD unit 144 is a charge detection unit that converts an electric charge into a voltage, and the electric charge held in the FD unit 144 is converted into a voltage in the amplification transistor 145.

The amplification transistor 145 outputs a voltage at a level corresponding to the electric charge stored in the FD unit 144 to the source. The source of the amplification transistor 145 is connected to the vertical signal line 123 via the selection transistor 146. The amplification transistor 145 constitutes a source follower together with a current source (not shown). The source follower is a read-out circuit that reads out a signal obtained by photoelectric conversion in PD141.

The selection transistor 146 is connected between the amplification transistor 145 and the vertical signal line 123, and the output voltage of the amplification transistor 145 appears on the vertical signal line 123 as a pixel signal VSL. This appearance is controlled by the selection signal SEL supplied to the gate of the selection transistor 146. The selection signal SEL is supplied from the row scanning unit 115 (FIG. 1).

The reset transistor 147 is connected between the FD unit 144 and the power supply VDD to reset the FD unit 144. The reset of the FD unit 144 is controlled by the reset signal RST supplied to the gate of the reset transistor 147. The reset signal RST is supplied from the row scanning unit 115 (FIG. 1).

The pixel signal VSL of the pixel 121 is input to the comparator 131 via the vertical signal line 123. Although not essential, the reference signal Vram is input to one input terminal of the comparator 131 via the capacitor C1 in this example. The pixel signal VSL is input to the other input terminal of the comparator 131 via the capacitor C2.

For example, in the solid-state image sensor 111 having the configuration described above, the charges accumulated in the PD 141 are collectively transferred to the FD unit 144, and the shutter closing simultaneity is maintained by sequentially reading out each column.

In the solid-state image sensor 111, the signal (D phase) when the FD unit 144 is reset by the reset transistor 147 and the signal (P phase) when the FD unit 144 stores the electric charge generated by the PD 141 are read. It is issued and AD converted.

FIG. 3 is a diagram showing an example of a schematic configuration of a comparator. The comparator 131 includes an amplifier circuit 10 (first amplifier circuit), an amplifier circuit 20 (second amplifier circuit), and a connection circuit 30. As the control signals supplied to some transistors, control signals φ1 to control signals φ3 and control signals Xφ1 to control signals Xφ3 obtained by inverting these are exemplified. Each control signal is supplied from, for example, the row scanning unit 115.

In the following description, "connection" may mean that the two elements are directly connected to each other, or that the two elements are electrically connected to each other via another element. You may.

The amplifier circuit 10 is a differential amplifier circuit provided in the previous stage (input stage), and outputs a voltage corresponding to the difference between the pixel signal VSL (input signal) and the reference signal Vram. The amplifier circuit 10 includes transistors 11 to 18, a current source Is, a capacitor C1, and a capacitor C2. Of the transistors 11 to 18, in this example, the transistor 11, the transistor 12, and the transistor 17 are n-type transistors (more specifically, n-type MOSFETs). The transistors 13 to 16 and the transistor 18 are p-type transistors (more specifically, p-type MOSFETs). The gate (or the base) of the transistor may be referred to as a "control terminal". The drain and source (may be collector or emitter) of a transistor may be referred to as a "current terminal".

The transistor 11 is a first transistor that constitutes a differential pair together with the transistor 12. In this example, the reference signal Vram is input to the gate (control terminal) of the transistor 11 via the capacitor C1. The reference signal Vram of the pixel 121 in the i-th column is referred to as a reference signal Vram_i and is illustrated. The drain of the transistor 11 (one current terminal) is connected to the source of the transistor 13 (the other current terminal). The voltage of the drain of the transistor 11 is referred to as a voltage VOUT1_AZ and is shown in the figure. The source of the transistor 11 (the other current terminal) is connected to the ground GND via the current source Is.

The transistor 12 is a second transistor that constitutes a differential pair together with the transistor 11. A pixel signal VSL is input to the gate (control terminal) of the transistor 12 via the capacitor C2. The pixel signal VSL of the pixel 121 in the i-th column is referred to as a pixel signal VSL_i and is shown. The drain of the transistor 12 (one current terminal) is connected to the source of the transistor 14 (the other current terminal). The source of the transistor 12 (the other current terminal) is connected to the ground GND via the current source Is.

The transistor 13 is connected between the transistor 11 and the power supply VDD. The gate (control terminal) of the transistor 13 is connected to the source of the transistor 13. The drain (one current terminal) of the transistor 13 is connected to the power supply VDD. The source of the transistor 13 is connected to the drain of the transistor 11. The voltage of the source of the transistor 13 is referred to as a voltage VOUT1 and is shown in the figure.

The transistor 14 is connected between the transistor 12 and the power supply VDD. The gate (control terminal) of the 14 is connected to the gate of the transistor 13. That is, the gate of the transistor 13, the source of the transistor 13, and the gate of the transistor 14 are connected to each other. The drain (one current terminal) of the transistor 14 is connected to the power supply VDD. The source of the transistor 14 is connected to the drain of the transistor 12.

The current source Is is connected between the transistor 11 and the transistor 12 and the ground GND. Specifically, the current source Is is connected between the source of the transistor 11 and the source of the transistor 12 and the ground GND so that the current flows from the transistor 11 and the transistor 12 toward the ground GND.

The transistor 15 is a switch transistor (second transistor switch) connected between the drain and the gate of the transistor 12. A control signal Xφ1 is supplied to the gate (control terminal) of the transistor 15. One of the drain and the source (current terminal) of the transistor 15 is connected to the drain of the transistor 12, and the other is connected to the gate of the transistor 12.

The transistor 16 is a switch transistor (switch for the first transistor) connected between the drain and the gate of the transistor 11. A control signal Xφ1 is supplied to the gate (control terminal) of the transistor 16. One of the drain and the source (current terminal) of the transistor 16 is connected to the drain of the transistor 11, and the other is connected to the gate of the transistor 11.

The transistor 17 is an example of a level shift circuit LSC connected between the transistor 11 and the transistor 13. In this example, the transistor 17 is a diode connected diode. The gate (control terminal) of the transistor 17 is connected to the drain (one current terminal). The drain of the transistor 17 is connected to the source of the transistor 13. The source of the transistor 17 (the other current terminal) is connected to the drain of the transistor 11.

The configuration of the level shift circuit LSC is not limited to the example shown in FIG. The level shift circuit LSC may be configured to include other circuit elements such as resistors in place of or with a diode such as a transistor 17.

The transistor 18 is a bypass switch connected in parallel to the level shift circuit LSC between the source of the transistor 13 and the drain of the transistor 11. The control signal Xφ2 is supplied to the gate (control terminal) of the transistor 18. One of the drain and the source (current terminal) of the transistor 18 is connected to the source of the transistor 13, and the other is connected to the drain of the transistor 11.

The amplifier circuit 20 is provided in the subsequent stage (output stage) of the amplifier circuit 10. The amplifier circuit 20 includes transistors 21 to 23 and a capacitor C3. Of the transistors 21 to 23, in this example, the transistor 23 is an n-type transistor, and the transistor 21 and the transistor 22 are p-type transistors.

The transistor 21 is an input transistor of the amplifier circuit 20. The gate (control terminal) of the transistor 21 is connected to the amplifier circuit 10 via the connection circuit 30. The voltage input to the gate of the transistor 21 is referred to as a voltage VOUT0 and is shown in the figure. The drain (one current terminal) of the transistor 21 is connected to the power supply VDD. The source of the transistor 21 (the other current terminal) is connected to the drain of the transistor 22 (the other current terminal).

The transistor 22 is connected between the transistor 21 and the ground GND. The gate (control terminal) of the transistor 22 is connected to the drain of the transistor 22 via the transistor 23 and is connected to the ground GND via the capacitor C3. The drain of the transistor 22 (one of the current terminals) is connected to the source of the transistor 21. The source of transistor 22 (the other current terminal) is connected to ground GND.

The transistor 21 and the transistor 22 form a source grounded amplifier circuit. The voltage at the connection point between the source of the transistor 21 and the drain of the transistor 22 is referred to as a voltage VOUT2 and is shown in the figure. The voltage VOUT2 is the output voltage of the comparator 131, that is, the result of comparison between the reference signal Vram and the pixel signal VSL.

The transistor 23 is a switch transistor connected between the drain and the gate of the transistor 22. A control signal φ1 is supplied to the gate (control terminal) of the transistor 23. One of the drain and the source (current terminal) of the transistor 23 is connected to the drain of the transistor 22, and the other is connected to the gate of the transistor 22.

The capacitor C3 is connected between the gate of the transistor 22 and the ground GND.

The connection circuit 30 is connected between the amplifier circuit 10 and the amplifier circuit 20. The connection circuit 30 includes a transistor 31 and a transistor 32. In this example, the transistor 31 and the transistor 32 are p-type transistors.

The transistor 31 is a switch transistor (first switch) connected between the source of the transistor 13 of the amplifier circuit 10 and the gate of the transistor 21 of the amplifier circuit 20. A control signal Xφ3 is supplied to the gate (control terminal) of the transistor 31. One of the drain and the source (current terminal) of the transistor 31 is connected to the source of the transistor 13, and the other is connected to the gate of the transistor 21.

The transistor 32 is a switch transistor (second switch) connected between the source of the transistor 14 of the amplifier circuit 10 and the gate of the transistor 21 of the amplifier circuit 20. A control signal φ3 is supplied to the gate (control terminal) of the transistor 32. One of the drain and the source (current terminal) of the transistor 32 is connected to the source of the transistor 14, and the other is connected to the gate of the transistor 21.

An example of the operation of the comparator 131 having the configuration described above will be described. The operation of the comparator 131 includes an auto zero operation (AZ operation) and a comparison operation (AD conversion operation) after the auto zero operation is canceled (after completion). Each operation will be described in association with some control signals.

During auto zero operation, the control signal Xφ1 is set to the low level. The transistor 15, the transistor 16 and the transistor 23 are turned on (conducting state). The control signal Xφ2 is set to a high level. The transistor 18 is turned off (non-conducting state). The control signal Xφ3 is set to a low level. The transistor 31 is turned on. The transistor 32 is turned off.

In the amplifier circuit 10, a voltage obtained by lowering (shifting) the source voltage of the transistor 13 by the voltage of the level shift circuit LSC is supplied to the gate of the transistor 11, and is held by the capacitor C1. As a result, the voltage at the gate of the transistor 11 is initialized. The voltage at the gate of the transistor 11 is copied to the gate of the transistor 12 by the voltage follower and held by the capacitor C2. As a result, the voltage at the gate of the transistor 12 is initialized.

In the amplifier circuit 20, the voltage VOUT1 of the amplifier circuit 10 in the above-mentioned state is supplied to the gate of the transistor 21 via the transistor 31. The voltage value corresponding to the amount of current flowing through the transistor 21 and the transistor 22 is held by the capacitor C3. As a result, the gate voltage of the transistor 22, and thus the current flowing through the transistor 21 and the transistor 22 are initialized.

After that, the auto zero operation is canceled. The control signal Xφ1 switches from low level to high level. The transistor 15, the transistor 16 and the transistor 23 are turned off. The control signal Xφ2 switches from high level to low level. Transistor 18 is turned on. Then, the control signal Xφ3 is switched from the high level to the low level. The transistor 31 is turned off. The transistor 32 is turned on.

After the auto zero operation is canceled, that is, during the comparison operation, the voltage corresponding to the difference between the reference signal Vramp_i input to the gate of the transistor 11 and the pixel signal VSL_i input to the gate of the transistor 12 is set as the voltage VOUT0 and eventually the voltage VOUT2. It is output. The voltage VOUT2 is counted by the counter 132 (FIG. 3), and AD conversion is performed.

FIG. 4 is a diagram schematically showing an example of the operation of the comparator. During the auto zero operation (AZ period) before the time t1, the control signal Xφ1, the control signal Xφ2, and the control signal Xφ3 are controlled to low level, high level, and low level (control signal φ3 is high level). A voltage VOUT1_AZ obtained by shifting the voltage VOUT1 by the voltage of the level shift circuit LSC is supplied to the gate of the transistor 11, and the gate voltage of the transistor 11 and the gate voltage of the transistor 12 are initialized.

The comparison operation (AD conversion operation) is performed after the auto zero operation is canceled (after the AZ is canceled) after the time t1. At time t1, the control signal Xφ1 and the control signal Xφ2 are controlled to high level and low level. At time t2, the control signal Xφ3 is controlled to a high level. The voltage corresponding to the difference between the reference voltage Vramp_i and the pixel signal VSL_i is output as the voltage VOUT0 and thus the voltage VOUT2.

The D phase is AD converted from time t3 to time t4. That is, at time t3, the voltage of the reference signal Vram_i begins to change, and at time t4, it becomes equal to the voltage of the pixel signal VSL_i. This period is counted as the AD conversion value of the D phase.

The P phase is AD converted from time t5 to time t6. That is, at time t5, the voltage of the reference signal Vram_i begins to change, and at time t6, it becomes equal to the voltage of the pixel signal VSL_i. This period is counted as the AD conversion value of the P phase.

For example, the comparator 131 operates as described above. The order of AD conversion of the D phase and the P phase may be reversed.

One of the features of the comparator according to the embodiment described above is that it includes a connection circuit 30. This will be described with reference to FIGS. 5 to 7. In order to facilitate understanding, some configurations of the illustrated comparator are omitted or simplified.

The comparator 131A exemplified in FIGS. 5 and 6 is also one of the comparators according to the embodiment. The comparator 131A is different from the comparator 131 (FIG. 3) described so far in that it does not include the capacitor C1, the transistor 16, the level shift circuit LSC (transistor 17), and the transistor 18. The current source Is is illustrated as a transistor to which a control voltage VGCM is supplied to the gate. The transistor 15, transistor 23, transistor 31 and transistor 32 are illustrated as switches.

During the auto zero operation, as shown in FIG. 5, the transistor 17, the transistor 23, and the transistor 31 are controlled to be on, and the transistor 32 is controlled to be turned off. Since there is no capacitor C1, the reference signal Vramp is directly input to the gate of the transistor 11, and the voltage of the gate of the transistor 11 and the voltage of the gate of the transistor 12 are initialized. The current flowing through the transistor 21 and the transistor 22 is also initialized.

During the comparative operation, as shown in FIG. 6, the transistor 17, the transistor 23, and the transistor 31 are controlled to be off, and the transistor 32 is controlled to be on. The voltage corresponding to the difference between the reference signal Vram and the pixel signal VSL_i is output as the voltage VOUT0 and thus the voltage VOUT2.

FIG. 7 is a diagram schematically showing an example of the operation of the comparator. During the auto zero operation before the time t11, the control signal Xφ1 and the control signal φ3 are set to low level and high level. A reference signal Vram is input to the gate of the transistor 11, and the voltage of the gate of the transistor 11 and the voltage of the gate of the transistor 12 are initialized.

After canceling the auto zero operation after time t11, a comparison operation (AD conversion operation) is performed. At time t11, the control signal Xφ1 is controlled to a high level. At time t12, the control signal φ3 is controlled to a low level. At this time, since the operating point of the voltage VOUT0 does not change, the feedthrough as in the comparative examples (FIGS. 8 to 10) described later does not occur, and the fluctuation of the pixel signal VSL_i is suppressed.

The D phase is AD converted from time t13 to time t14. That is, at time t13, the voltage of the reference signal Vram begins to change, and at time t14, it becomes equal to the voltage of the pixel signal VSL_i. This comparison period is counted.

The P phase is AD converted from time t15 to time t16. That is, at time t5, the voltage of the reference signal Vram begins to change, and at time t6, it becomes equal to the voltage of the pixel signal VSL_i. This comparison period is counted.

A comparative example will be described with reference to FIGS. 8 to 10. The comparator 131E according to the comparative example shown in FIGS. 8 and 9 has the same configuration as that of Patent Document 1. The components of the comparator 131E are obtained by adding "E" to the codes of the corresponding components of the comparator 131 (FIG. 3) and the comparator 131A (FIGS. 6 and 7) described above (referred to as transistors 11E and the like). Illustrated.

The comparator 131E does not have a configuration corresponding to the capacitor C2 (FIG. 3). In the comparator 131E, the diode connection is switched by the transistor 31E connected between the gate and the source of the transistor 13E and the transistor 32E connected between the gate and the source of the transistor 14E.

During the auto zero operation, as shown in FIG. 8, the transistor 16E, the transistor 23E, and the transistor 32E are controlled to be on, and the transistor 31E is controlled to be turned off. During the comparative operation, as shown in FIG. 9, the transistor 16E, the transistor 23E, and the transistor 32E are controlled to be off, and the transistor 31E is controlled to be on.

FIG. 10 is a diagram schematically showing an example of the operation of the comparator according to the comparative example. During the auto zero operation before the time t21, the control signal Xφ1 and the control signal φ3 are set to low level and high level. The pixel signal VSL is input to the gate of the transistor 12E, and the voltage of the gate of the transistor 11E and the voltage of the gate of the transistor 12 are initialized.

After canceling the auto zero operation after time t21, a comparison operation (AD conversion operation) is performed. At time t21, the control signal Xφ1 is controlled to a high level. At time t22, the control signal φ3 is controlled to a low level. At this time, it should be noted that the voltage VOUT1 rises and the reference voltage Vramp_i also rises via the coupling. The amount of this rise varies, and some examples of the reference voltage Vramp_i after the rise are illustrated by the alternate long and short dash line. When the reference voltage Vramp_i rises due to feedthrough in this way, the count value in the subsequent AD conversion increases, and the AD conversion time becomes longer by that amount.

The D phase is AD converted from time t23 to time t24. That is, at time t23, the voltage of the reference signal Vramp_i begins to change, and at time t24, it becomes equal to the voltage of the pixel signal VSL. This period is counted as the AD conversion value of the D phase. The count period (time t23 to time t24) becomes longer due to the occurrence of the feedthrough described above, and the count value increases.

The P phase is AD converted from time t25 to time t26. That is, at time t25, the voltage of the reference signal Vramp_i begins to change, and at time t26, it becomes equal to the voltage of the pixel signal VSL. This comparison period is counted. The comparison period (time t25 to time t26) becomes longer and the count value increases by the amount of the above-mentioned feedthrough.

On the other hand, according to the comparator 131A (FIGS. 5 to 7) described above, feedthrough does not occur, so that the increase in the count value is suppressed. Specifically, the comparison period of the D phase of the comparator 131A (time t13 to time t14 in FIG. 7) is shorter than the comparison period of the D phase of the comparator 131E (time t23 to time t24 in FIG. 10). The comparison period of the P phase of the comparator 131A (time t15 to time t16 in FIG. 7) is shorter than the comparison period of the P phase of the comparator 131E (time t25 to time t26 in FIG. 10). The AD conversion can be speeded up by that amount.

As described above, according to the comparator 131A, the feedthrough at the time of switching the diode connection unlike the comparator 131E does not occur, so that the increase in the count number at the time of AD change can be suppressed by that amount.

One of the other features of the comparator according to the embodiment is that it includes a level shift circuit LSC. This will be described with reference to FIG. 11 in addition to FIG. 3 described so far. FIG. 11 is a diagram schematically showing an example of the operation of the comparator. The upper limit UL and the lower limit LL of the operating voltage range of the comparator are shown. The upper limit UL and the lower limit LL are located between the power supply VDD and the voltage VSS (corresponding to the ground GND).

During the auto zero operation, the voltage VOUT1_AZ is supplied to the gate of the transistor 11, and the voltage of the gate of the transistor 11 and the voltage of the gate of the transistor 12 are initialized. The voltage VOUT1_AZ is a voltage obtained by shifting the voltage VOUT1 at the source of the transistor 13 by the level shift circuit LSC, and is a voltage closer to the lower limit value LL than the voltage VOUT1.

At the time of comparison operation (AD conversion) after the auto zero is released, the voltage of the reference voltage Vramp_i is changed, the voltage is compared with the voltage of the pixel signal VSL_i, and AD conversion is performed. In this example, the operating voltage is within the range of the upper limit value UL and the lower limit value LL in any AD conversion of the D phase and the P phase.

In FIG. 11, an example of voltage fluctuation in the absence of the level shift circuit LSC is shown by an alternate long and short dash line. During the comparative operation (AD conversion), the voltage VOUT1 is supplied to the gate of the transistor 11, and the voltage of the gate of the transistor 11 and the voltage of the gate of the transistor 12 are initialized. This voltage is farther from the lower limit value LL than the voltage VOUT1 described above. As a result, in this example, the operating voltage exceeds the upper limit UL in the P-phase AD conversion after the D-phase AD conversion, and the AD conversion is not properly performed.

As described above, according to the comparator 131, by providing the level shift circuit LSC, the voltage of the gate of the transistor 11 and the voltage of the gate of the transistor 12 can be initialized with a more appropriate voltage. Therefore, the operating voltage at the time of AD conversion can be kept within the upper limit value UL and the lower limit value LL, and AD conversion can be appropriately performed. Further, by using the level shift circuit LSC, the circuit area can be reduced as compared with the case where a circuit for separately generating and supplying a voltage is provided, for example.

2. 2. Modification example There are various combinations of n-type transistors and p-type transistors in the comparator. FIG. 12 is a diagram showing an example of a schematic configuration of a comparator according to a modified example. It is illustrated by adding "B" to the code of the component corresponding to the comparator 131 (FIG. 3) (referred to as transistor 11B or the like).

In the comparator 131B, the transistor 13B, the transistor 14B, the transistor 15B, the transistor 16B, the transistor 17B, the transistor 18B, the transistor 21B, the transistor 31B and the transistor 32B are n-type transistors. The transistor 11B, the transistor 12B, the transistor 22B and the transistor 23B are p-type transistors.

The connection relationship of each element is appropriately changed from the comparator 131. For example, in FIG. 3 and the like, one current terminal and the other current terminal of the transistors 11 to 14 are described as drains and sources, but in FIG. 12, one current terminal of the transistors 11B to 14B and the other current terminal are described. Is described as source and drain. The source of transistor 13B (one current terminal) and the source of transistor 14B (one current terminal) are connected to ground GND. The current source Is is located between the power supply VDD and the drain of the transistor 11B (the other current terminal) and the drain of the transistor 12B (the other current terminal) so that the current flows from the power supply VDD toward the transistor 11B and the transistor 12B. Be connected. As for the control signal, for example, the low level and the high level of the control signal φ1 and the control signal Xφ1 are appropriately changed so as to be opposite to those of the comparator 131. The same applies to the control signal φ2, the control signal φ3, and the like. A control signal φ1 is supplied to the gate of the transistor 15B and the gate of the transistor 16B. A control signal φ2 is supplied to the gate of the transistor 18B. A control signal Xφ1 is supplied to the gate of the transistor 23B. A control signal φ3 is supplied to the gate of the transistor 31B. The control signal Xφ3 is supplied to the gate of the transistor 32B.

FIG. 13 is a diagram schematically showing an example of the operation of the comparator. During the auto zero operation, the control signal φ1, the control signal φ2, and the control signal φ3 are controlled to low level, high level, and high level (control signal X φ3 is low level). During the comparison operation (AD conversion operation), the control signal φ1, the control signal φ2, and the control signal φ3 are controlled to high level, low level, and low level. Since the specific operation is the same as that of the comparator 131 (FIG. 4, etc.), the description will not be repeated.

3. 3. Examples of application to mobile objects The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.

FIG. 14 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 14, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (Interface) 12053 are shown.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 has a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, turn signals or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.

The outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle outside information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The out-of-vehicle information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.

The image pickup unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the image pickup unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects the in-vehicle information. For example, a driver state detection unit 12041 that detects a driver's state is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether or not the driver has fallen asleep.

The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.

Further, the microcomputer 12051 controls the driving force generating device, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, so that the driver can control the driver. It is possible to perform coordinated control for the purpose of automatic driving that runs autonomously without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.

The audio image output unit 12052 transmits an output signal of at least one of audio and image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle. In the example of FIG. 16, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

FIG. 15 is a diagram showing an example of the installation position of the image pickup unit 12031.

In FIG. 15, the image pickup unit 12031 has

image pickup units

12101, 12102, 12103, 12104, and 12105.

The

image pickup units

12101, 12102, 12103, 12104, 12105 are provided at positions such as, for example, the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The image pickup unit 12101 provided in the front nose and the image pickup section 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The

image pickup units

12102 and 12103 provided in the side mirror mainly acquire images of the side of the vehicle 12100. The image pickup unit 12104 provided in the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The image pickup unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 15 shows an example of the shooting range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging range of the

imaging units

12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 can be obtained.

At least one of the image pickup units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera including a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 has a distance to each three-dimensional object in the image pickup range 12111 to 12114 based on the distance information obtained from the image pickup unit 12101 to 12104, and a temporal change of this distance (relative speed with respect to the vehicle 12100). By obtaining, it is possible to extract a three-dimensional object that is the closest three-dimensional object on the traveling path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more) as a preceding vehicle. can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like that autonomously travels without relying on the driver's operation.

For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles, and other three-dimensional objects based on the distance information obtained from the image pickup units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.

At least one of the image pickup units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging unit 12101 to 12104. Such recognition of a pedestrian is, for example, a procedure for extracting feature points in an image captured by an image pickup unit 12101 to 12104 as an infrared camera, and pattern matching processing is performed on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured image of the image pickup unit 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 determines the square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

The above is an example of a vehicle control system to which the technique according to the present disclosure can be applied. The technique according to the present disclosure can be applied to, for example, the image pickup unit 12031 among the configurations described above. Specifically, the solid-state image sensor 111 described with reference to FIG. 1 can be applied to the image pickup unit 12031. By applying the technique according to the present disclosure to the image pickup unit 12031, it is possible to suppress an increase in the number of counts at the time of AD conversion, so that higher speed imaging becomes possible.

4. Effects The techniques described above are specified, for example, as follows. As described with reference to FIGS. 3, 5, 6, 6 and the like, the comparator 131 includes an amplifier circuit 10, an amplifier circuit 20, and a connection circuit 30. The amplifier circuit 10 is a first amplifier circuit. The amplifier circuit 20 is a second amplifier circuit provided after the amplifier circuit 10. The connection circuit 30 is connected between the amplifier circuit 10 and the amplifier circuit 20. The amplifier circuit 10 includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, a current source Is, and a transistor 15. The transistor 11 is a first transistor to which a reference signal Vram is input to the gate. The transistor 12 is a second transistor in which a pixel signal VSL (input signal) is input to the gate via the capacitor C2 and forms a differential pair together with the transistor 11. The transistor 13 is a third transistor whose drain is connected to the power supply VDD and whose source is connected to the drain of the transistor 11. The transistor 14 is a fourth transistor whose drain is connected to the power supply VDD and whose source is connected to the drain of the transistor 12. The current source Is is connected between the source of the transistor 11 and the source of the transistor 12 and the ground GND so that the current flows from the transistor 11 and the transistor 12 toward the ground GND. The transistor 15 is a switch for a second transistor connected between the drain and the gate of the transistor 12. The gate of transistor 13, the source of transistor 13 and the source of transistor 14 are connected to each other. The connection circuit 30 includes a transistor 31 and a transistor 32. The transistor 31 is a first switch connected between the source of the transistor 13 and the amplifier circuit 20. The transistor 32 is a second switch connected between the source of the transistor 13 and the amplifier circuit 20.

According to the above-mentioned comparator 131, for example, if each switch is controlled to perform an auto zero operation and a comparison operation as described above with reference to FIGS. 4 to 7, feedthrough as in Patent Document 1 does not occur. Therefore, it is possible to suppress an increase in the number of counts at the time of AD conversion by that amount. As a result, AD conversion can be speeded up.

As described with reference to FIGS. 4 and 7, the transistor 31 is controlled to be in the conductive state, the transistor 32 is controlled to be in the non-conducting state, and the transistor 15 is controlled to be in the conductive state during the auto zero operation. At the time of the comparative operation, the transistor 31 may be controlled in the non-conducting state, the transistor 32 may be controlled in the non-conducting state, and the transistor 15 may be controlled in the non-conducting state. For example, by such switch control, auto zero operation and comparison operation can be performed.

As described with reference to FIG. 3 and the like, the reference signal Vramp is input to the gate of the transistor 11 via the capacitor C1, and the amplifier circuit 10 is a transistor connected between the drain and the gate of the transistor 11. 16 (switch for the first transistor) may be included. As described with reference to FIG. 4 and the like, the transistor 16 may be controlled to be in a conductive state during the auto zero operation, and the transistor 16 may be controlled to be in a non-conducting state during the comparative operation. As a result, during the Ozero operation, a voltage can be supplied to the gate of the transistor 11 via the transistor 13 or the like to perform initialization.

As described with reference to FIG. 3 and the like, the amplifier circuit 10 includes a level shift circuit LSC connected between the source of the transistor 13 and the drain of the transistor 11, and the source of the transistor 13 and the drain of the transistor 11. A transistor 18 (bypass switch) connected in parallel to the level shift circuit LSC may be included between the two. An example of a level shift circuit LSC is a diode (diode-connected transistor 17). As described with reference to FIG. 4 and the like, the transistor 18 may be set to the non-conducting state during the auto zero operation, and the transistor 18 may be set to the conducting state during the comparative operation. As a result, as described with reference to FIG. 11 and the like, the operating voltage during the comparative operation (during AD conversion) can be kept within an appropriate range. Further, the circuit area can be made smaller than, for example, as compared with the case where a circuit for separately generating and supplying a voltage is provided.

As described with reference to FIG. 12 and the like, the transistor 11B (first transistor) and the transistor 12B (second transistor) are p-type transistors, and the transistor 13B (third transistor) and the transistor 14B (fourth transistor) are. It may be an n-type transistor. In this case, the source of the transistor 13B and the source of the transistor 14B may be connected to the ground GND. The current source Is may be connected between the power supply VDD and the drain of the transistor 11B and the drain of the transistor 12B so that a current flows from the power supply VDD toward the transistor 11B and the transistor 12B. Even with such a configuration, it is possible to realize a comparator capable of suppressing an increase in the number of counts at the time of AD conversion as described above.

The solid-state image sensor 111 described with reference to FIG. 1 and the like is also an aspect of the present disclosure. The solid-state image sensor 111 includes a plurality of pixels 121 and an AD conversion circuit 130 that converts a pixel signal VSL of each of the plurality of pixels 121 into a digital signal. The AD conversion circuit 130 includes a comparator (such as the above-mentioned comparator 131) that compares the pixel signal VSL and the reference signal Vram. As a result, as described above, the solid-state image sensor 111 capable of suppressing an increase in the number of counts at the time of AD conversion can be obtained.

Note that the effects described in this disclosure are merely examples and are not limited to the disclosed contents. There may be other effects.

Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments as they are, and various changes can be made without departing from the gist of the present disclosure. In addition, components over different embodiments and modifications may be combined as appropriate.

The disclosed technology can also have the following configurations.
(1)
The first amplifier circuit and
The second amplifier circuit provided after the first amplifier circuit and
A connection circuit connected between the first amplifier circuit and the second amplifier circuit,
Equipped with
The first amplifier circuit is
The first transistor to which the reference signal is input to the control terminal,
An input signal is input to the control terminal via a capacitor, and the second transistor forming a differential pair together with the first transistor
A third transistor in which one current terminal is connected to one of the ground and the power supply and the other current terminal is connected to one of the current terminals of the first transistor.
A fourth transistor in which one current terminal is connected to one of the ground and the power supply and the other current terminal is connected to one of the current terminals of the second transistor.
A current source connected between the other current terminal of the first transistor, the other current terminal of the second transistor, and the other of the ground and the power supply.
A switch for the second transistor connected between one of the current terminals and the control terminal of the second transistor,
Including
The control terminal of the third transistor, the other current terminal of the third transistor, and the control terminal of the fourth transistor are connected to each other.
The connection circuit is
A first switch connected between the other current terminal of the third transistor and the second amplifier circuit,
A second switch connected between the other current terminal of the fourth transistor and the second amplifier circuit,
including,
comparator.
(2)
During auto zero operation
The first switch is controlled to be in a conductive state and is controlled to a conduction state.
The second switch is controlled to be in a non-conducting state.
The switch for the second transistor is controlled to be in a conductive state, and is controlled.
During comparison operation
The first switch is controlled to be in a non-conducting state.
The second switch is controlled to be in a conductive state and is controlled to a conduction state.
The second transistor switch is controlled to be in a non-conducting state.
The comparator according to (1).
(3)
The reference signal is input to the control terminal of the first transistor via a capacitor.
The first amplifier circuit includes a switch for the first transistor connected between one of the current terminals and the control terminal of the first transistor.
The comparator according to (1) or (2).
(4)
At the time of auto zero operation, the switch for the first transistor is controlled to be in a conductive state.
During the comparative operation, the switch for the first transistor is controlled to be in a non-conducting state.
The comparator according to (3).
(5)
The first amplifier circuit is
A level shift circuit connected between the other current terminal of the third transistor and one current terminal of the first transistor.
A bypass switch connected in parallel to the level shift circuit between the other current terminal of the third transistor and one current terminal of the first transistor.
including,
The comparator according to (3) or (4).
(6)
During auto zero operation, the bypass switch is set to the non-conducting state.
During the comparison operation, the bypass switch is set to the conductive state.
The comparator according to (5).
(7)
The level shift circuit includes a diode.
The comparator according to (5) or (6).
(8)
The first transistor and the second transistor are n-type transistors and are n-type transistors.
The third transistor and the fourth transistor are p-type transistors and are p-type transistors.
The one current terminal and the other current terminal of each of the first transistor to the fourth transistor are a drain and a source.
The drain of the third transistor and the drain of the fourth transistor are connected to the power supply.
The current source is connected between the source of the first transistor and the source of the second transistor and the ground so that a current flows from the first transistor and the second transistor toward the ground. ,
The comparator according to any one of (1) to (7).
(9)
The first transistor and the second transistor are p-type transistors and are p-type transistors.
The third transistor and the fourth transistor are n-type transistors and are n-type transistors.
The one current terminal and the other current terminal of each of the first transistor to the fourth transistor are a source and a drain.
The source of the third transistor and the source of the fourth transistor are connected to the ground.
The current source is connected between the power supply and the drain of the first transistor and the drain of the second transistor so that a current flows from the power supply toward the first transistor and the second transistor.
The comparator according to any one of (1) to (7).
(10)
With multiple pixels,
An AD converter that converts each pixel signal of each of the plurality of pixels into a digital signal,
Equipped with
The AD converter includes a comparator that compares the pixel signal with the reference signal.
The comparator is
The first amplifier circuit and
The second amplifier circuit provided after the first amplifier circuit and
A connection circuit connected between the first amplifier circuit and the second amplifier circuit,
Equipped with
The first amplifier circuit is
The first transistor to which the reference signal is input to the control terminal,
An input signal is input to the control terminal via a capacitor, and the second transistor forming a differential pair together with the first transistor
A third transistor in which one current terminal is connected to one of the ground and the power supply and the other current terminal is connected to one of the current terminals of the first transistor.
A fourth transistor in which one current terminal is connected to one of the ground and the power supply and the other current terminal is connected to one of the current terminals of the second transistor.
A current source connected between the other current terminal of the first transistor, the other current terminal of the second transistor, and the other of the ground and the power supply.
A switch for the second transistor connected between one of the current terminals and the control terminal of the second transistor,
Including
The control terminal of the third transistor, the other current terminal of the third transistor, and the control terminal of the fourth transistor are connected to each other.
The connection circuit is
A first switch connected between the other current terminal of the third transistor and the second amplifier circuit,
A second switch connected between the other current terminal of the fourth transistor and the second amplifier circuit,
including,
Solid-state image sensor.

10 Amplifier circuit (first amplifier circuit)
11 Transistor (1st transistor)
12 Transistor (2nd transistor)
13 Transistor (3rd transistor)
14 Transistor (4th transistor)
15 Transistor (Switch for 2nd transistor)
16 Transistor (Switch for 1st transistor)
17 Transistor 18 Transistor (Bypass switch)
20 Amplifier circuit (second amplifier circuit)
21 Transistor 22 Transistor 23 Transistor 30 Connection circuit 31 Transistor (1st switch)
32 Transistor (2nd switch)
111 Solid-state image sensor 121 pixel 130 AD conversion circuit 131 comparator 132 counter C1 capacitor C2 capacitor Is current source LSC level shift circuit

Claims

The first amplifier circuit and
The second amplifier circuit provided after the first amplifier circuit and
A connection circuit connected between the first amplifier circuit and the second amplifier circuit,
Equipped with
The first amplifier circuit is
The first transistor to which the reference signal is input to the control terminal,
An input signal is input to the control terminal via a capacitor, and the second transistor forming a differential pair together with the first transistor
A third transistor in which one current terminal is connected to one of the ground and the power supply and the other current terminal is connected to one of the current terminals of the first transistor.
A fourth transistor in which one current terminal is connected to one of the ground and the power supply and the other current terminal is connected to one of the current terminals of the second transistor.
A current source connected between the other current terminal of the first transistor, the other current terminal of the second transistor, and the other of the ground and the power supply.
A switch for the second transistor connected between one of the current terminals and the control terminal of the second transistor,
Including
The control terminal of the third transistor, the other current terminal of the third transistor, and the control terminal of the fourth transistor are connected to each other.
The connection circuit is
A first switch connected between the other current terminal of the third transistor and the second amplifier circuit,
A second switch connected between the other current terminal of the fourth transistor and the second amplifier circuit,
including,
comparator.
During auto zero operation
The first switch is controlled to be in a conductive state and is controlled to a conduction state.
The second switch is controlled to be in a non-conducting state.
The switch for the second transistor is controlled to be in a conductive state, and is controlled.
During comparison operation
The first switch is controlled to be in a non-conducting state.
The second switch is controlled to be in a conductive state and is controlled to a conduction state.
The second transistor switch is controlled to be in a non-conducting state.
The comparator according to claim 1.
The reference signal is input to the control terminal of the first transistor via a capacitor.
The first amplifier circuit includes a switch for the first transistor connected between one of the current terminals and the control terminal of the first transistor.
The comparator according to claim 1.
At the time of auto zero operation, the switch for the first transistor is controlled to be in a conductive state.
During the comparative operation, the switch for the first transistor is controlled to be in a non-conducting state.
The comparator according to claim 3.
The first amplifier circuit is
A level shift circuit connected between the other current terminal of the third transistor and one current terminal of the first transistor.
A bypass switch connected in parallel to the level shift circuit between the other current terminal of the third transistor and one current terminal of the first transistor.
including,
The comparator according to claim 3.
During auto zero operation, the bypass switch is set to the non-conducting state.
During the comparison operation, the bypass switch is set to the conductive state.
The comparator according to claim 5.
The level shift circuit includes a diode.
The comparator according to claim 5.
The first transistor and the second transistor are n-type transistors and are n-type transistors.
The third transistor and the fourth transistor are p-type transistors and are p-type transistors.
The one current terminal and the other current terminal of each of the first transistor to the fourth transistor are a drain and a source.
The drain of the third transistor and the drain of the fourth transistor are connected to the power supply.
The current source is connected between the source of the first transistor and the source of the second transistor and the ground so that a current flows from the first transistor and the second transistor toward the ground. ,
The comparator according to claim 1.
The first transistor and the second transistor are p-type transistors and are p-type transistors.
The third transistor and the fourth transistor are n-type transistors and are n-type transistors.
The one current terminal and the other current terminal of each of the first transistor to the fourth transistor are a source and a drain.
The source of the third transistor and the source of the fourth transistor are connected to the ground.
The current source is connected between the power supply and the drain of the first transistor and the drain of the second transistor so that a current flows from the power supply toward the first transistor and the second transistor.
The comparator according to claim 1.
With multiple pixels,
An AD converter that converts each pixel signal of each of the plurality of pixels into a digital signal,
Equipped with
The AD converter includes a comparator that compares the pixel signal with the reference signal.
The comparator is
The first amplifier circuit and
The second amplifier circuit provided after the first amplifier circuit and
A connection circuit connected between the first amplifier circuit and the second amplifier circuit,
Equipped with
The first amplifier circuit is
The first transistor to which the reference signal is input to the control terminal,
An input signal is input to the control terminal via a capacitor, and the second transistor forming a differential pair together with the first transistor
A third transistor in which one current terminal is connected to one of the ground and the power supply and the other current terminal is connected to one of the current terminals of the first transistor.
A fourth transistor in which one current terminal is connected to one of the ground and the power supply and the other current terminal is connected to one of the current terminals of the second transistor.
A current source connected between the other current terminal of the first transistor, the other current terminal of the second transistor, and the other of the ground and the power supply.
A switch for the second transistor connected between one of the current terminals and the control terminal of the second transistor,
Including
The control terminal of the third transistor, the other current terminal of the third transistor, and the control terminal of the fourth transistor are connected to each other.
The connection circuit is
A first switch connected between the other current terminal of the third transistor and the second amplifier circuit,
A second switch connected between the other current terminal of the fourth transistor and the second amplifier circuit,
including,
Solid-state image sensor.