WO2021095560A1 - Event detection device - Google Patents

Abstract

The present technology pertains to an event detection device that makes it possible to achieve miniaturization of a device which detects occurrence of an event. The present invention is provided with: a first photoelectric conversion element; a second photoelectric conversion element; and a differential amplifier circuit as a circuit that generates a difference signal corresponding to a difference in voltage between the first photoelectric conversion element and the second photoelectric conversion element, wherein occurrence of an event that is a change in a signal is detected by the signal from the differential amplifier circuit. Transistors constituting the differential amplifier circuit are dispersedly disposed in a first pixel including the first photoelectric conversion element and a second pixel including the second photoelectric conversion element. The present technology can be applied, for example, to a sensor for detecting an event that is a change in the electrical signal of a pixel, or the like.

Description

Event detector

The present technology relates to an event detection device, for example, an event detection device in which a device that detects a change in pixel brightness as an event is made smaller.

An image sensor has been proposed that outputs event data indicating the occurrence of an event when an event occurs, using a change in pixel brightness as an event (see, for example, Patent Document 1).

Here, an image sensor that performs imaging in synchronization with a vertical synchronization signal and outputs frame data in a raster scan format can be said to be a synchronous image sensor. On the other hand, the image sensor that outputs the event data can be said to be an asynchronous image sensor because the pixel in which the event data is generated is read out at any time. The asynchronous image sensor is called, for example, DVS (Dynamic Vision Sensor).

Special Table 2017-535999 Gazette

It is desired to reduce the size of the device that detects the occurrence of an event using an asynchronous image sensor.

This technology was made in view of such a situation, and makes it possible to miniaturize a device that detects the occurrence of an event by using an asynchronous image sensor.

The event detection device of one aspect of the present technology is a difference corresponding to the difference in voltage between the first photoelectric conversion element, the second photoelectric conversion element, the first photoelectric conversion element, and the second photoelectric conversion element. It is an event detection device including a differential amplifier circuit as a circuit for generating a signal, and detecting the occurrence of an event which is a change in the signal by the signal from the differential amplifier circuit.

In the event detection device of one aspect of the present technology, the difference signal corresponding to the voltage difference between the first photoelectric conversion element, the second photoelectric conversion element, and the first photoelectric conversion element and the second photoelectric conversion element. A differential amplifier circuit is provided as a circuit for generating the above, and the occurrence of an event, which is a change in the signal, is detected by the signal from the differential amplifier circuit.

The event detection device may be an independent device or a module incorporated in another device.

It is a figure which shows the structure of one Embodiment of the event detection apparatus to which this technique is applied. It is a figure which shows the structural example of a DVS chip. It is a figure which shows the structural example of a pixel array part. It is a figure which shows the structural example of a pixel block. It is a figure which shows the configuration example of the event detection part. It is a figure which shows the structural example of the current-voltage conversion part. It is a figure which shows the structural example of the subtraction part and the quantization part. It is a figure which shows the other structural example of the quantization part. It is a figure which shows the structural example of the pixel array part in 1st Embodiment. It is a figure for demonstrating the arrangement of a read pixel and a reference pixel. It is a figure for demonstrating the operation of the pixel array part in 1st Embodiment. It is a figure which shows the structural example of the pixel array part in 2nd Embodiment. It is a figure for demonstrating the operation of the pixel array part in 2nd Embodiment. It is a figure which shows the structural example of the pixel array part in 3rd Embodiment. It is a figure which shows the structural example of the pixel array part in 4th Embodiment. It is a figure for demonstrating the arrangement of a read pixel and a reference pixel. It is a figure for demonstrating the arrangement of a read pixel and a reference pixel. It is a figure for demonstrating the arrangement of a read pixel and a reference pixel. It is a figure for demonstrating the arrangement of a read pixel and a reference pixel. It is a figure which shows the other structural example of the pixel array part in 4th Embodiment. It is a figure which shows the structural example of the pixel array part in 5th Embodiment. It is a figure which shows the other structural example of the pixel array part in 5th Embodiment. It is a figure which shows the structural example of the pixel array part in 6th Embodiment. It is a figure which shows the other structural example of the pixel array part in 6th Embodiment. It is a figure which shows the structural example of the pixel array part in 7th Embodiment. It is a figure which shows the other structural example of the pixel array part in 7th Embodiment. It is a figure which shows the structural example of the pixel array part in 8th Embodiment. It is a figure which shows the other structural example of the pixel array part in 8th Embodiment. It is a figure which shows the structural example of the pixel array part in 9th Embodiment. It is a figure which shows the other structural example of the pixel array part in 9th Embodiment. It is a figure which shows the structural example of the pixel array part in 10th Embodiment. It is a figure which shows the other structural example of the pixel array part in 10th Embodiment. It is a figure which shows the structural example of the pixel array part in 11th Embodiment. It is a figure which shows the structural example of the pixel array part in the twelfth embodiment. It is a figure which shows the structural example of the pixel array part in 13th Embodiment. It is a figure which shows the structural example of the pixel array part in 14th Embodiment. It is a figure for demonstrating the operation of the pixel array part in 14th Embodiment. It is a figure which shows the structural example of the pixel array part in 15th Embodiment. It is a figure for demonstrating the operation of the pixel array part in the fifteenth embodiment. It is a block diagram which shows an example of the schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of the vehicle exterior information detection unit and the image pickup unit.

The embodiment for implementing the present technology (hereinafter referred to as the embodiment) will be described below.

<One embodiment of a data processing chip to which this technology is applied>

FIG. 1 is a diagram showing a configuration example of an embodiment of a data processing chip to which the present technology is applied.

The data processing chip is a one-chip semiconductor chip, and is configured by stacking a sensor die (board) 11 as a plurality of dies (boards) and a logic die 12. The data processing chip may be configured by one die, or may be configured by stacking three or more dies.

In the data processing chip of FIG. 1, the sensor die 11 is configured with an event generation unit 21 (as a circuit), and the logic die 12 is configured with a data processing unit 22. A part of the event generation unit 21 can be configured in the logic die 12. Further, a part of the data processing unit 22 can be configured in the sensor die 11.

The event generation unit 21 has pixels that generate an electric signal by performing photoelectric conversion of incident light, and generates event data indicating the occurrence of an event that is a change in the electric signal of the pixels. The event generation unit 21 supplies the event data to the data processing unit 22. That is, for example, the event generation unit 21 performs imaging to generate an electric signal by performing photoelectric conversion of incident light in pixels, as in the case of a synchronous image sensor, but may generate image data in frame format. It generates image data in the form of no or in a frame format, and also generates event data indicating the occurrence of an event that is a change in an electrical signal of a pixel.

The data processing unit 22 performs data processing according to the event data from the event generation unit 21, and outputs the data processing result which is the result of the data processing.

Since the event generation unit 21 does not output the event data in synchronization with the vertical synchronization signal, it can be said to be an asynchronous image sensor. Asynchronous image sensors are also called DVS (Dynamic Vision Sensor), for example. In the following, the sensor die 11 in which the event generation unit 21 is configured will be referred to as a DVS chip 11 in order to facilitate the distinction.

<DVS chip configuration example>
FIG. 2 is a block diagram showing a configuration example of the DVS chip 11.

The DVS chip 11 includes a pixel array unit 31, a drive unit 32, an arbiter 33, and an output unit 34.

A plurality of pixels are arranged in a two-dimensional grid pattern in the pixel array unit 31. Further, the pixel array unit 31 is divided into a plurality of pixel blocks, each of which is composed of a predetermined number of pixels. Hereinafter, a set of pixels or pixel blocks arranged in the horizontal direction is referred to as a "row", and a set of pixels or pixel blocks arranged in a direction perpendicular to the row is referred to as a "column".

The pixel block detects a change in the photocurrent as an event when a change exceeding a predetermined threshold value occurs in the photocurrent as an electric signal generated by the photoelectric conversion of the pixel. When an event is detected, the pixel block outputs a request to the arbiter 33 requesting the output of event data indicating the occurrence of the event.

The drive unit 32 drives the pixel array unit 31 by supplying a control signal to the pixel array unit 31.

The arbiter 33 arbitrates the request from the pixel block constituting the pixel array unit 31, and returns a response indicating permission or disapproval of output of event data to the pixel block. The pixel block that has received the response indicating the permission to output the event data outputs the event data to the output unit 34.

The output unit 34 performs necessary processing on the event data output by the pixel blocks constituting the pixel array unit 31 and supplies the event data to the data processing unit 22 (FIG. 1).

Here, since the change in the light current as the electric signal of the pixel can be regarded as the change in the brightness of the pixel, the event can also be said to be the change in the brightness of the pixel (the change in brightness exceeding the threshold value).

The event data representing the occurrence of an event includes at least position information (coordinates, etc.) representing the position of the pixel block in which the brightness change as an event has occurred. In addition, the event data can include the polarity (positive or negative) of the brightness change.

<Structure example of pixel array unit 31>
FIG. 3 is a block diagram showing a configuration example of the pixel array unit 31 of FIG.

The pixel array unit 31 has a plurality of pixel blocks 41. The pixel block 41 includes 1 or more I × J pixels 51 arranged in I rows × J columns (I and J are integers), and an event detection unit 52. One or more pixels 51 in the pixel block 41 share an event detection unit 52.

The pixel 51 receives the incident light from the subject and performs photoelectric conversion to generate a photocurrent as an electric signal. The pixel 51 supplies the generated photocurrent to the event detection unit 52.

The event detection unit 52 detects as an event a change in which the photocurrent from each of the pixels 51 exceeds a predetermined threshold value after being reset by the reset signal from the arbiter 33. When the event detection unit 52 detects an event, the event detection unit 52 supplies the arbiter 33 (FIG. 2) with a request for outputting event data indicating the occurrence of the event. Then, when the event detection unit 52 receives a response from the arbiter 33 to the effect that the output of the event data is permitted in response to the request, the event detection unit 52 outputs the event data to the output unit 34.

Here, detecting a change exceeding a predetermined threshold value of the photocurrent as an event can be regarded as detecting that there is no change exceeding a predetermined threshold value of the photocurrent as an event at the same time.

<Structure example of pixel block 41>
FIG. 4 is a circuit diagram showing a configuration example of the pixel block 41 of FIG.

As described with reference to FIG. 3, the pixel block 41 includes one or more pixels 51 and an event detection unit 52.

The pixel 51 includes a photoelectric conversion element 61. The photoelectric conversion element 61 is composed of, for example, a PD (Photodiode), receives incident light, and performs photoelectric conversion to generate an electric charge.

The I × J pixels 51 constituting the pixel block 41 are connected to the event detection unit 52 constituting the pixel block 41 via the node 60. Therefore, the photocurrent generated by the pixel 51 (photoelectric conversion element 61) is supplied to the event detection unit 52 via the node 60. As a result, the event detection unit 52 is supplied with the sum of the photocurrents of all the pixels 51 in the pixel block 41. Therefore, the event detection unit 52 detects a change in the sum of the photocurrents supplied from the I × J pixels 51 constituting the pixel block 41 as an event.

In the pixel array unit 31 of FIG. 3, the pixel block 41 is composed of one or more pixels 51, and the event detection unit 52 is shared by the one or more pixels 51. Therefore, when the pixel block 41 is composed of a plurality of pixels 51, the number of event detection units 52 is increased as compared with the case where one event detection unit 52 is provided for one pixel 51. The number can be reduced, and the scale of the pixel array unit 31 can be suppressed.

When the pixel block 41 is composed of a plurality of pixels 51, an event detection unit 52 can be provided for each pixel 51. When the event detection unit 52 is shared by a plurality of pixels 51 of the pixel block 41, an event is detected in units of the pixel block 41, but when the event detection unit 52 is provided for each pixel 51, the pixels. Events can be detected in units of 51.

<Configuration example of event detection unit 52>
FIG. 5 is a block diagram showing a configuration example of the event detection unit 52 of FIG.

The event detection unit 52 includes a current / voltage conversion unit 81, a buffer 82, a subtraction unit 83, a quantization unit 84, and a transfer unit 85.

The current-voltage conversion unit 81 converts (the sum) of the optical current from the pixel 51 into a voltage corresponding to the logarithm of the optical current (hereinafter, also referred to as an optical voltage) and supplies it to the buffer 82.

The buffer 82 buffers the optical voltage from the current-voltage conversion unit 81 and supplies it to the subtraction unit 83.

The subtraction unit 83 calculates the difference between the current optical voltage and the optical voltage at a timing different from the current one by a minute time at the timing according to the reset signal from the arbiter 33, and quantizes the difference signal corresponding to the difference. It is supplied to the conversion unit 84.

The quantization unit 84 quantizes the difference signal from the subtraction unit 83 into a digital signal, and supplies the quantization value of the difference signal to the transfer unit 85 as event data.

The transfer unit 85 transfers (outputs) the event data to the output unit 34 in response to the event data from the quantization unit 84. That is, the transfer unit 85 supplies the arbiter 33 with a request for outputting event data. Then, when the transfer unit 85 receives a response from the arbiter 33 to the effect that the output of the event data is permitted in response to the request, the transfer unit 85 outputs the event data to the output unit 34.

<Configuration example of current-voltage converter 81>
FIG. 6 is a circuit diagram showing a configuration example of the current-voltage conversion unit 81 of FIG.

The current-voltage conversion unit 81 is composed of transistors 91 to 93. As the transistors 91 and 93, for example, an N-type MOS FET can be adopted, and as the transistor 92, for example, a P-type MOS FET can be adopted.

The source of the transistor 91 is connected to the gate of the transistor 93, and the photocurrent from the pixel 51 is supplied to the connection point between the source of the transistor 91 and the gate of the transistor 93. The drain of the transistor 91 is connected to the power supply VDD, and its gate is connected to the drain of the transistor 93.

The source of the transistor 92 is connected to the power supply VDD, and its drain is connected to the connection point between the gate of the transistor 91 and the drain of the transistor 93. A predetermined bias voltage Vbias is applied to the gate of the transistor 92. The transistor 92 is turned on / off by the bias voltage Vbias, and the operation of the current-voltage converter 81 is also turned on / off by turning the transistor 92 on / off.

The source of transistor 93 is grounded.

In the current-voltage conversion unit 81, the drain of the transistor 91 is connected to the power supply VDD side and serves as a source follower. A pixel 51 (FIG. 4) is connected to the source of the transistor 91 which is a source follower, whereby the electric charge generated by the photoelectric conversion element 61 of the pixel 51 is applied to the transistor 91 (from the drain to the source). Photocurrent flows. The transistor 91 operates in the subthreshold region, and an optical voltage corresponding to the logarithm of the photocurrent flowing through the transistor 91 appears at the gate of the transistor 91. As described above, in the current-voltage conversion unit 81, the transistor 91 converts the optical current from the pixel 51 into an optical voltage corresponding to the logarithm of the optical current.

In the current-voltage conversion unit 81, the gate of the transistor 91 is connected to the connection point between the drain of the transistor 92 and the drain of the transistor 93, and the optical voltage is output from the connection point.

<Structure example of subtraction unit 83 and quantization unit 84>
FIG. 7 is a circuit diagram showing a configuration example of the subtraction unit 83 and the quantization unit 84 of FIG. As will be described later, the reading from the pixel 51 (PD61) will be described by taking as an example a case where the reading is performed using a differential amplifier circuit and the difference between the signals of the two pixels is output. Further, a case where a differential amplifier circuit is applied to the subtraction unit 83 and the quantization unit 84 will be described as an example.

In order to facilitate the explanation of the subtraction unit 83 and the quantization unit 84 to which such a differential amplifier circuit is applied, the conventional subtraction unit 83 and the quantization unit 84 to which such a differential amplifier circuit is not applied are shown in FIG. 7 will be described, and the configuration of the event detection unit 52 included in the DVS chip 11 will be described.

The subtraction unit 83 includes a capacitor 101, an operational amplifier 102, a capacitor 103, and a switch 104. The quantization unit 84 includes a comparator 111.

One end of the capacitor 101 is connected to the output terminal of the buffer 82 (FIG. 5), and the other end is connected to the input terminal (inverting input terminal) of the operational amplifier 102. Therefore, the optical voltage is input to the input terminal of the operational amplifier 102 via the capacitor 101.

The output terminal of the operational amplifier 102 is connected to the non-inverting input terminal (+) of the comparator 111. One end of the capacitor 103 is connected to the input terminal of the operational amplifier 102, and the other end is connected to the output terminal of the operational amplifier 102.

The switch 104 is connected to the capacitor 103 so as to turn on / off the connection at both ends of the capacitor 103. The switch 104 turns on / off the connection at both ends of the capacitor 103 by turning it on / off according to the reset signal.

The optical voltage on the buffer 82 (FIG. 5) side of the capacitor 101 when the switch 104 is turned on is represented by Vinit, and the capacitance (capacitance) of the capacitor 101 is represented by C1. The input terminal of the operational amplifier 102 is virtually grounded, and the charge Qinit accumulated in the capacitor 101 when the switch 104 is on is represented by the equation (1).
Qinit = C1 × Vinit ・ ・ ・ (1)

Further, when the switch 104 is on, the connections at both ends of the capacitor 103 are turned off (short-circuited), so that the electric charge accumulated in the capacitor 103 becomes zero.

After that, if the optical voltage on the buffer 82 (FIG. 5) side of the capacitor 101 when the switch 104 is turned off is expressed as Vafter, the electric charge stored in the capacitor 101 when the switch 104 is turned off is expressed as Vafter. Qafter is expressed by equation (2).
Qafter = C1 × Vafter ・ ・ ・ (2)

Assuming that the capacitance of the capacitor 103 is represented by C2 and the output voltage of the operational amplifier 102 is represented by Vout, the charge Q2 stored in the capacitor 103 is represented by the equation (3).
Q2 = -C2 × Vout ・ ・ ・ (3)

Since the total amount of electric charges including the electric charges of the capacitor 101 and the electric charges of the capacitor 103 does not change before and after the switch 104 is turned off, the equation (4) is established.
Qinit = Qafter + Q2 ・ ・ ・ (4)

By substituting the equations (1) and (3) into the equation (4), the equation (5) is obtained.
Vout =-(C1 / C2) × (Vafter --Vinit) ・ ・ ・ (5)

According to the equation (5), the subtraction unit 83 subtracts the optical voltages Vafter and Vinit, that is, calculates the difference signal (Vout) corresponding to the difference Vafter-Vinit between the optical voltages Vafter and Vinit. According to the equation (5), the subtraction gain of the subtraction unit 83 is C1 / C2. Since it is usually desired to maximize the gain, it is preferable to design C1 to be large and C2 to be small. On the other hand, if C2 is too small, kTC noise may increase and noise characteristics may deteriorate. Therefore, the capacity reduction of C2 is limited to the range in which noise can be tolerated. Further, since the event detection unit 52 including the subtraction unit 83 is mounted on each pixel block 41, the capacitances C1 and C2 have restrictions on the area. In consideration of these, the values of the capacities C1 and C2 are determined.

The comparator 111 quantizes the difference signal by comparing the difference signal from the subtraction unit 83 with a predetermined threshold (voltage) Vth (> 0) applied to the inverting input terminal (-), and quantizes the difference signal. The quantization value obtained by the above is output to the transfer unit 85 as event data.

For example, the comparator 111 outputs an H (High) level representing 1 when the difference signal exceeds the threshold value Vth as event data indicating the occurrence of an event, and 0 when the difference signal does not exceed the threshold value Vth. The L (Low) level representing is output as event data indicating that no event has occurred.

The transfer unit 85 makes a request when it is recognized that a change in the amount of light as an event has occurred according to the event data from the quantization unit 84, that is, when the difference signal (Vout) is larger than the threshold value Vth. After supplying to 33 and receiving a response indicating permission to output event data, event data (for example, H level) indicating the occurrence of an event is output to the output unit 34.

<Other configuration examples of the quantization unit 84>
FIG. 8 is a block diagram showing another configuration example of the quantization unit 84 of FIG. In the drawings, the parts corresponding to the case of FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted as appropriate below.

In FIG. 8, the quantization unit 84 includes comparators 111 and 112, and an output unit 113.

Therefore, the quantization unit 84 of FIG. 8 is common to the case of FIG. 7 in that it has a comparator 111. However, the quantization unit 84 of FIG. 8 is different from the case of FIG. 7 in that the comparator 112 and the output unit 113 are newly provided.

In the event detection unit 52 (FIG. 5) having the quantization unit 84 of FIG. 8, in addition to the event, the polarity of the change in the amount of light as an event is also detected.

In the quantization unit 84 of FIG. 8, when the difference signal exceeds the threshold value Vth, the comparator 111 outputs the H level representing 1 as event data indicating the occurrence of a positive event, and the difference signal is the threshold value Vth. If it does not exceed, the L level representing 0 is output as event data indicating that no positive event has occurred.

Further, in the quantization unit 84 of FIG. 8, the threshold value Vth'(<Vth) is supplied to the non-inverting input terminal (+) of the comparator 112, and the subtraction unit 83 is supplied to the inverting input terminal (-) of the comparator 112. The difference signal from is supplied. Now, for the sake of simplicity, it is assumed that the threshold value Vth'is equal to, for example, -Vth.

The comparator 112 quantizes the difference signal by comparing the difference signal from the subtraction unit 83 with the threshold value Vth'applied to the inverting input terminal (-), and obtains the quantization value obtained by the quantization. Output as event data.

For example, when the difference signal is smaller than the threshold value Vth'(when the absolute value of the negative value difference signal exceeds the threshold value Vth), the comparator 112 sets the H level representing 1 to indicate the occurrence of a negative event. Output as event data. Further, in the comparator 112, when the difference signal is not smaller than the threshold value Vth'(when the absolute value of the negative value difference signal does not exceed the threshold value Vth), a negative event occurs at the L level representing 0. It is output as event data indicating that it has not been done.

The output unit 113 indicates that the event data indicating the occurrence of a positive event, the event data indicating the occurrence of a negative event, or the event has not occurred, depending on the event data output by the comparators 111 and 112. The event data to be represented is output to the transfer unit 85.

The transfer unit 85 supplies a request to the arbiter 33 when it is recognized that a change in the amount of light as a positive or negative event has occurred according to the event data from the output unit 113 of the quantization unit 84, and the event data. After receiving the response indicating the permission of the output of, the event data (H pulse representing 1 or L pulse representing -1) indicating the occurrence of the positive or negative event is output to the output unit 34.

When the quantization unit 84 has the configuration shown in FIG. 7, the occurrence of the event is output with 1 bit (0 or 1) having only positive electrode properties, and when the configuration shown in FIG. 8 is used, the occurrence of the event is 1. It is output in 5 bits (1, 0, or -1).

<About differential amplification reading>
The above-mentioned DVS chip 11 includes a pixel array unit 31, and PD 61 is two-dimensionally arranged in a matrix in the pixel array unit 31. As a sensor including PD61, there is a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

In a CMOS image sensor, a photodiode (PD) as a photoelectric conversion unit and a floating diffusion region (FD:) that voltage-converts electrons photoelectrically converted by the photodiode into pixels arranged in a matrix in a pixel array. Floating Diffusion) and an amplification transistor whose gate input is the voltage obtained in the floating diffusion region (FD), and reading by a source follower circuit using this amplification transistor (hereinafter referred to as source follower type reading) is performed. Is common.

On the other hand, although the pixels have the same configuration, there are a configuration in which reading is performed by a grounded-source circuit and a configuration in which reading is performed by a differential amplifier circuit (hereinafter referred to as differential type amplification reading). In the case of differential amplification reading, there is an advantage that the signal can be read with high conversion efficiency.

By applying the differential type amplification reading that can obtain such an advantage to the DVS chip 11, the signal can be read with high conversion efficiency. The case where the differential type amplification reading is applied to the DVS chip 11 will be described below.

<First Embodiment>
FIG. 9 is a diagram showing the configuration of the DVS chip 11 in the first embodiment. FIG. 9 shows the configuration of the pixel array unit 31 of the DVS chip 11. Further, in order to show that it is the pixel array unit 31 in the first embodiment, it is described as the pixel array unit 31a.

FIG. 9 shows two pixels arranged in the column direction included in the pixel array unit 31a. In FIG. 9, the upper pixel 51S is a read pixel, and the lower pixel 51R is a reference pixel. The present embodiment described below is a pixel array unit 31 that performs differential type reading, and is configured to read and output the difference between the read pixel and the reference pixel.

In the case of the differential type reading described below, the transistor of the reading pixel and the transistor of the reference pixel form a differential amplifier circuit, and the voltage signal corresponding to the signal charge detected by the PD of the reading pixel is generated. It is output.

In addition to storing and reading signals, the read pixels can be switched to reference pixels. For example, the pixel drive line changeover switch scans the address while exchanging the pixel pairs of the read pixels and the reference pixels, and the pixel array. It is possible to read out all the effective pixels arranged two-dimensionally in the unit 31.

In the example shown in FIG. 9, one of the two pixels arranged in the column direction (vertical direction in the figure) is the read pixel 51S, and the other is the reference pixel 51R. Further, in the following description, as shown in FIG. 9, the case where the two pixels arranged in the column direction are set as the read pixel 51S and the reference pixel 51R will be described as an example, but the description will be continued with reference to the read pixel 51S. The pixel 51R is not limited to the two pixels arranged in the column direction.

Although not shown, this technique can be applied even when one of the two pixels arranged in the row direction (horizontal direction) is the read pixel 51S and the other is the reference pixel 51R. Further, the read pixel 51S and the reference pixel 51R do not have to be adjacent to each other, and may be, for example, one pixel or two pixels located two pixels apart.

Further, the reference pixel 51R may be a pixel provided exclusively as a reference pixel commonly used for pixels arranged in the column direction or the row direction.

Further, as shown in FIG. 10, the present technology can be applied even when reading is performed in which the idle pixel 51I is set. The idle pixel 51I is a pixel that is not set in either the read pixel 51S or the reference pixel 51R, and is set as a pixel that does not form a differential amplifier circuit described later.

The idle pixel 51I is also set to the read pixel 51S and the reference pixel 51R, and is configured to be able to read out all the effective pixels arranged two-dimensionally in the pixel array unit 31.

With reference to FIG. 10, the read pixel 51S is arranged in the upper row in the figure, and the reference pixel 51R is arranged in the lower row in the figure.

Focusing on the upper row, the idle pixel 51I-1, the read pixel 51S-1, the idle pixel 51I-2, the read pixel 51S-2, and the idle pixel 51I-3 are arranged in this order. A signal is read out from the read pixel 51S-1 and the read pixel 51S-2 at the same time.

Focusing on the lower row, the reference pixel 51R-1, the idle pixel 51I-4, the reference pixel 51R-2, the idle pixel 51I-5, and the reference pixel 51R-3 are arranged in this order.

In the case shown in FIG. 10, for example, the read pixel 51S-1 and the reference pixel 51R-1 are paired, and as will be described later, the read pixel 51S-1 and the reference pixel 51R-1 form a differential amplifier circuit. Differential reading is done.

Similarly, for example, the read pixel 51S-2 and the reference pixel 51R-2 are paired, and as will be described later, a differential amplifier circuit is formed by the read pixel 51S-2 and the reference pixel 51R-2, and is a differential type. Is read out.

In this case, the pixel arranged on the lower left side of the read pixel 51S is an example in which the reference pixel 51R is set. As described above, the read pixel 51S and the reference pixel 51R are in different rows, and it is possible to arrange them in different examples.

Here, as shown in FIG. 9, the description will be continued by taking as an example the case where the read pixel 51S and the reference pixel 51R are arranged in a row (vertical direction).

Return to the explanation with reference to FIG. The pixel 51S shown in FIG. 9 includes a PD61S, a PRC (signal processing circuit) 311S, a capacitor 312S, a switch 313S, an MIMO transistor 314S, a MOSFET transistor 315S, an OR circuit 316S, and a switch 317S.

Similarly, the pixel 51R includes a PD61R, a PRC311R, a capacitor 312R, a switch 313R, an MIMO transistor 314R, a MOSFET transistor 315R, an OR circuit 316R, and a switch 317R.

Since the pixel 51S and the pixel 51R have the same configuration, the pixel 51S will be described as an example. The PD61S is connected to the PRC311S. As described with reference to FIG. 4, the signal from the PD 61 is supplied to the event detection unit 52. The configuration of the event detection unit 52 has a configuration as described with reference to FIG. 5, and the signal from the PD 61 is supplied to the current-voltage conversion unit 81.

The PRC311S is provided as a processing circuit for processing a signal from the PD61S. The PRC311S corresponds to the current-voltage conversion unit 81 of the event detection unit 52, and executes, for example, a process of converting a signal from the PD61S into a voltage signal. The PRC311 is connected to the capacitor 312S.

The capacitor 312S is connected to one end of the switch 313S and the gate of the NMOS transistor 314S. The source of the NMOS transistor 314S is connected to the current supply line 319. The current supply line 319 is connected to the load MOS circuit 320, which is a constant current source. The drain of the NMOS transistor 314S is connected to the drain of the MOSFET transistor 315S.

As shown in FIG. 9, the load MOS circuit 320, which is a constant current source, may be provided shared by two pixels, or may be provided for each pixel. Further, the configuration may be shared by a plurality of pixels 51 (two or more pixels 51) arranged in the column direction.

The gate of the PMOS transistor 315S is connected to the gate of the PMOS transistor 315R in the pixel 51R which is a reference pixel. The source of the epitaxial transistor 315S is connected to the power supply VDD (not shown).

The drain of the MIMO transistor 315S in the pixel 51S, which is the read pixel, is connected to one end of the switch 318S. The other end of the switch 318S is connected to the vertical signal line 321. The switch 318S is configured to be closed when the pixel 51S is set to the pixel to be read.

One end of the switch 317S is connected to the ACK signal line 322, and the other end is connected to one of the two inputs of the OR circuit 316S. The ACK signal line 322 is connected to the arbiter 33 (FIG. 2). Although the details will be described later, the switch 317S is closed when the signal ACKen is supplied via the ACK signal line.

In the configuration shown in FIG. 9, the MIMO transistor 315S and the MIMO transistor 315R form a current mirror circuit. Further, a portion including the NMOS transistor 315S and the MOSFET transistor 315R constituting the current mirror circuit and adding the NMOS transistor 314S and the NMOS transistor 314R constitutes a differential amplifier circuit.

In this case, the MOSFETs 315S and 315R function as MOS transistors on the side of reading the signal, and the NMOS transistors 314S and 314R function as MOS transistors on the side of inputting the signal.

The MOS transistor on the read side may be an NMOS transistor, and the MOS transistor on the input side may be a MOSFET transistor.

Further, the portion including the MIMO transistor 315S, the MOSFET transistor 315R, the NMOS transistor 314S, and the NMOS transistor 314R constituting this differential amplifier circuit corresponds to the quantization unit 84 (FIGS. 5 and 7) of the event detection unit 52. ..

As described with reference to FIG. 7, the quantization unit 84 compares the signal from the subtraction unit 83, in other words, the signal from the PD61, with a predetermined threshold (voltage) Vth (> 0). The difference signal is quantized by the above method, and the quantized value obtained by the quantization is output to the transfer unit 85 as event data. In the configuration shown in FIG. 9, the predetermined threshold value is a signal supplied from the pixel 51R, which is a reference pixel.

In the pixel array unit 31a shown in FIG. 9, the voltage value VdiffS supplied to the gate side of the NMOS transistor 314S of the pixel 51S which is the read pixel and the voltage value VdiffS supplied to the gate side of the NMOS transistor 314R of the pixel 51R which is the reference pixel are supplied. A difference value indicating which of the voltage values VdiffR is larger is supplied to the switch 318S, and is supplied to the transfer unit 85 (FIG. 5) via the vertical signal line 321.

The voltage value VdiffS represents the amount of time change in the amount of light in the read pixel, and the voltage value VdiffS represents the amount of time change in the amount of light in the reference pixel. As shown in FIG. 9, the pixel 51S and the pixel 51R are pixels arranged at different positions. Therefore, it can be said that the configuration shown in FIG. 9 has a configuration in which the amount of time change in the amount of light of the read pixel and the reference pixel is read out by a spatial difference.

The reading operation in the pixel array unit 31a shown in FIG. 9 will be described with reference to the timing chart of FIG. At time t11, the signal SELa that gives an instruction to close the switch 318S is regarded as an H level signal. When the signal SELa is converted to an H level signal, the switch 318S is closed, and a signal is output from the pixel 51S, which is a read pixel, to the vertical signal line 321.

The signal applied to the vertical signal line 321 (the signal described as VSL in FIG. 11) gradually increases from time t11 and reaches a certain value. The signal ACK is a signal that is set to H level when the column circuit (not shown) receives the signal. At time t12, the signal ACK is set to H level. Then, at time t13, the signal ACKen is set to H level. This signal ACKen is a signal indicating the start of reset.

When the signal ACKen is set to H level, the switch 313S is closed and the OR circuit 316S and the capacitor 312S are connected. The switch 313S has the same role as the switch 104 (FIG. 7), and when it is turned on, the capacitor 312S is reset. The reset signal for resetting the capacitor 312S is generated by the OR relationship between the global reset signal RST G and the reset signal RST Pa by the signal ACKEN.

When the signal applied to the vertical signal line 321 reaches the 0 level, the signal ACKen is switched to the L level signal (time t14). When the signal ACKen becomes an L level signal, the switch 313S is opened. At time t15, the switch 318S is opened by switching the signal SELa to the L level. Further, at time t15, the signal ACK is also switched to the L level, so that the switch 317S is opened.

In the configuration shown in FIG. 9, when the process based on the timing chart shown in FIG. 11 is executed, the reset is performed synchronously in the pixel 51S and the pixel 51R.

According to the configuration shown in FIG. 9, the circuit configuration can be reduced. Here, for comparison, reference is made to FIG. 7 again. FIG. 7 is a diagram showing a configuration example of a subtraction unit 83 and a quantization unit 84 constituting the event detection unit 52. The configuration shown in FIG. 7 is provided for each pixel 51 (pixel block 41, FIG. 4). Therefore, the comparator 111 is provided for each pixel 51. When the comparator 111 is provided for each pixel 51, the area for arranging the comparator 111 becomes large, which may be one of the factors that hinder the miniaturization of the pixel array unit 31.

According to the configuration shown in FIG. 9, the configuration does not have the comparator 111. The pixel array unit 31a shown in FIG. 9 has a portion corresponding to the comparator 111 (quantization unit 84), but the portion is configured over two pixels. Further, in the pixel array unit 31a shown in FIG. 9, the portion corresponding to the subtraction unit 83 is included in the portion corresponding to the comparator 111. Therefore, the pixel array unit 31a shown in FIG. 9 has a configuration that can be miniaturized.

Also, the read pixel and the reference pixel are adjacent pixels. That is, since the reference pixel that supplies the threshold voltage is near the read pixel, the threshold voltage can be generated near the pixel. Therefore, high-speed reading can be realized. Further, since adjacent pixels are used, the temperature characteristics can be canceled and the influence of flicker can be suppressed.

<Second embodiment>
FIG. 12 is a diagram showing the configuration of the pixel array portion 31b of the DVS chip 11 in the second embodiment. The same parts as those of the pixel array part 31a (FIG. 9) in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31b in the second embodiment has a configuration in which capacitors 341S, 341R, switches 342S, 342R, and switches 343S, 343R are added as compared with the pixel array unit 31a in the first embodiment. It is the same except that it is.

The capacitor 341S is arranged at a position where the gate and drain of the NMOS transistor 314S are connected. Similarly, the capacitor 341R is arranged at a position connecting the gate and drain of the NMOS transistor 314R.

Also in the pixel array unit 31b shown in FIG. 12, the upper pixel 51S is used as a read pixel and the lower pixel 51R is used as a reference pixel. However, in the configuration shown in FIG. 12, the read pixel and the reference pixel can be exchanged. It is said that it can be configured.

A switch 342S and a switch 343S are arranged in the pixel 51S. The switch 342S is a switch that is closed when the pixel 51S functions as a read pixel. The switch 343S is a switch that is closed when the pixel 51S does not function as a read pixel, and is a switch that is closed when the pixel 51R functions as a reference pixel.

Switch 342S and switch 343S are controlled so that when one is closed, the other is open. When the switch 342S is closed, the difference between the pixel 51S as the read pixel and the pixel 51R as the reference pixel is supplied to the vertical signal line 321. When the switch 343S is closed, the voltage applied to the drain side of the MIMO transistor 315S is supplied to the 1 input side of the OR circuit 316S.

A switch 342R and a switch 343R are arranged in the pixel 51R. The switch 342R is a switch that is closed when the pixel 51R functions as a read pixel. The switch 343R is a switch that is closed when the pixel 51R is not functioned as a read pixel, and is a switch that is closed when the pixel 51S is functioned as a reference pixel.

Switch 342R and switch 343R are controlled so that when one is closed, the other is open. When the switch 342R is closed, the difference between the pixel 51R as the read pixel and the pixel 51S as the reference pixel is supplied to the vertical signal line 321. When the switch 343R is closed, the voltage applied to the drain side of the MIMO transistor 315R is supplied to one input side of the OR circuit 316R.

The switch 342S and the switch 342R are switches that are closed when they function as read pixels, and are controlled so that when one is closed, the other is open. The switch 343S and the switch 343R are switches that are closed when functioning as a reference pixel, and are controlled so that when one is closed, the other is open.

In FIG. 12, one of the two pixels arranged in the column direction is used as a read pixel and the other is used as a reference pixel as an example. Therefore, the switch is controlled as described above. It is also possible to use one of a plurality of pixels arranged in the column direction as a read pixel and a pixel adjacent to the read pixel as a reference pixel to perform reading while sequentially switching the read pixels (reference pixels).

When a plurality of pixels are sequentially set as read pixels and read, the switch 342 in the pixel 51 set as the read pixel is closed and connected to the vertical signal line 321. Further, the switch 343 in the pixel 51 set as the reference pixel is closed, and the voltage applied to the drain side of the MIMO transistor 315 is applied to one input of the OR circuit 316. The switch 342 and the switch 343 of the pixel 51 other than the pixel 51 set as the read pixel or the reference pixel are in an open state.

The state shown in FIG. 12 indicates a state in which the pixel 51S shown on the upper side in the figure is set as the read pixel and the pixel 51S shown on the lower side in the figure is set as the reference pixel. In such a setting, the switch 342S in the pixel 51S is closed and the switch 343S is open. Further, the switch 342R in the pixel 51R is open, and the switch 343R is closed.

In the case of the switch state shown in FIG. 12, the state is the same as that of the pixel array unit 31a shown in FIG. 9, and the drain and gate of the MIMO transistor 315R of the reference pixel 51R and the gate of the MIMO transistor 315S of the read pixel 51S are connected. It will be in the state of being. Therefore, as in the first embodiment, the difference between the read pixel and the reference pixel is supplied to the vertical signal line 321.

Further, as in the first embodiment, the portion including the MOSFET transistor 315S, the MOSFET transistor 315R, the NMOS transistor 314S, and the NMOS transistor 314R constituting the differential amplifier circuit, and the switches 342S, 342R and the switches 343S, 343R are further included. The portion corresponds to the quantization unit 84 (FIGS. 5 and 7) of the event detection unit 52.

In the pixel array unit 31b in the second embodiment shown in FIG. 12, as in the first embodiment, the voltage value VdiffS supplied to the gate side of the NMOS transistor 314S of the pixel 51S which is the read pixel and A difference value indicating which of the voltage value VdiffR supplied to the gate side of the NMOS transistor 314R of the pixel 51R, which is the reference pixel, is larger is supplied to the switch 342S and is supplied to the switch 342S via the vertical signal line 321 to the transfer unit 85 (FIG. 5). Is supplied to.

The voltage value VdiffS represents the amount of time change in the amount of light in the read pixel, and the voltage value VdiffR represents the amount of time change in the amount of light in the reference pixel. As shown in FIG. 12, the pixel 51S and the pixel 51R are pixels arranged at different positions. Therefore, it can be said that the configuration shown in FIG. 12 also has a configuration in which the amount of time change in the amount of light of the read pixel and the reference pixel is read out by a spatial difference, as in the first embodiment.

Further, according to the configuration shown in FIG. 12, since the configuration does not have the comparator 111, the pixel array unit 31b can be miniaturized.

The reading operation in the pixel array unit 31b shown in FIG. 12 will be described with reference to the timing chart of FIG. The pixel array unit 31b shown in FIG. 12 corresponds to a case where a plurality of pixels 51 are synchronously reset and a case where a plurality of pixels 51 are reset asynchronously. First, a description will be added to the reading operation when the plurality of pixels 51 are synchronously reset.

The signal SELa and the signal ACKen are synchronized signals for each line. Further, the signal SELa and the signal ACKen are control signals supplied from outside the pixel 51. Although not shown in FIG. 12, for example, other pixels 51S are arranged in the row direction on the left side or the right side of the pixel 51S. The signal SELa and the signal ACKen are signals supplied at the same timing to the pixels 51 arranged in the row direction.

The signal SELa is a read valid signal, and when it is set to H level, the switch 342 is turned on and a signal is output to the vertical signal line 321. This signal SELa is set to H level from time t21 to time t24, during which the switch 342, for example, the switch 342S in FIG. 12 is closed.

When the signal ACKen is set to H level at time t22, the signal previously supplied to the vertical signal line 321 (hereinafter referred to as VSL signal) is propagated to one input of the OR circuit 316S. When the VSL signal is propagated to the OR circuit 316S, a reset signal is generated and output by the OR circuit 316S in relation to the global reset signal RST G and OR. By enabling this reset signal, that is, in this case, by connecting the switch 313S to the output side of the OR circuit 316S, the Vdiffs of the pixel 51S are reset.

By repeating such a reading operation, a signal is read from each pixel 51.

Next, a description will be added to the reading operation when resetting asynchronously in a plurality of pixels 51. Even when resetting asynchronously, the timing chart is the timing chart shown in FIG.

The signal SELa is a synchronization signal for each line. Further, the signal SELa is a control signal supplied from outside the pixel 51. In the case of asynchronous reset, the signal ACKen is a control signal supplied from within the pixel 51.

The signal SELa is set to the H level from the time t21 to the time t24 as in the above case, and the switch 342, for example, the switch 342S in FIG. 12 is closed during that time. When the switch 342S is closed, the VSL signal is supplied to the vertical signal line 321.

A column circuit (not shown) provided outside the pixel array unit 31b generates a signal ACKen when a VSL signal is supplied. Specifically, the signal ACKen is set to H level only for the column in which the VSL signal is read as High. For columns where the VSL signal is not read as High, the signal ACKen remains at L level.

By controlling the signal ACKen in this way, only the pixel 51 whose VSL signal is High, in other words, the pixel 51 whose brightness has changed, can be controlled by the signal ACKen. In the pixel 51S supplied with the H-level signal ACKen, the VSL signal is propagated as the reset signal RSTPa of the OR circuit 316S.

The operation after this is the same as the above case. In this way, by making the signal ACKen supplied only to the pixel 51 in which the VSL signal is high, it is possible to reset only the pixel 51 in which the brightness has changed.

Note that, in the above and the embodiments described below, the global reset signal RST G is an example and is not an essential configuration.

The pixel array unit 31b in the second embodiment can also be miniaturized. Further, as in the first embodiment, since the reference pixel that supplies the threshold voltage is in the vicinity of the read pixel, the threshold voltage can be generated in the vicinity of the pixel. Therefore, high-speed reading can be realized. Further, since adjacent pixels are used, the temperature characteristics can be canceled and the influence of flicker can be suppressed. Such an effect is also an effect that can be expected in the third to fifteenth embodiments described below.

<Third embodiment>
FIG. 14 is a diagram showing the configuration of the pixel array unit 31c of the DVS chip 11 according to the third embodiment. Of the configurations of the pixel array unit 31c in the third embodiment, the same parts as the pixel array unit 31b (FIG. 12) in the second embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate. To do.

The pixel array unit 31c in the third embodiment is different from the pixel array unit 31b in the second embodiment in that the shared quantization unit 361 is added, and the other points are different. The same is true.

The shared quantization unit 361 is provided between the pixel 51 and the vertical signal line 321c. That is, the pixel array unit 31c in the third embodiment has a structure in which the signal read from the pixel 51 is supplied to the vertical signal line 321c via the shared quantization unit 361.

The shared quantization unit 361 is configured to include a MOSFET transistor 371, an MIMO transistor 372, and a switch 373. The signal read from the pixel 51 is supplied to the gate of the MIMO transistor 371 of the shared quantization unit 361. The drain of the epitaxial transistor 371 is connected to one end of the switch 373 and the drain of the NMOS transistor 372.

The switch 373 is closed and connected to the vertical signal line 321C when the pixel 51S is set as the read pixel and when the pixel 51R is set as the read pixel.

The signal Von and the signal Voff are time-division-switched and supplied to the gate of the NMOS transistor 372. The signal Von and the signal Voff correspond to the threshold value Vth and the threshold value Vth'in the description with reference to FIG. Here, the description will be continued assuming that the signal Von corresponds to the threshold value Vth and the signal Voff corresponds to the threshold value Vth'.

By providing the shared quantization unit 361, it is possible to detect not only the event but also the polarity of the change in the amount of light as an event.

Similar to the quantization unit 84 of FIG. 8, the shared quantization unit 361 sets the H level to the positive event when the difference signal supplied from the pixel 51 side is larger than the signal Von supplied in the time division. It is output as event data indicating occurrence, and when the difference signal is not larger than the signal Von, the L level representing 0 is output as event data indicating that a positive event has not occurred.

Further, the shared quantization unit 361 sets the H level representing 1 when the difference signal is smaller than the signal Voff (when the absolute value of the negative value difference signal is larger than the signal Voff), and sets the event indicating the occurrence of a negative event. Output as data. Further, when the difference signal is not smaller than the signal Voff (when the absolute value of the negative value difference signal is not larger than the signal Voff), the shared quantization unit 361 generates a negative event at the L level representing 0. Output as event data indicating that it has not been done.

By providing the shared quantization unit 361 in this way, event data indicating the occurrence of a positive event, event data indicating the occurrence of a negative event, or event data indicating that no event has occurred can be obtained. , It can be configured to output to the transfer unit 85.

In the pixel array unit 31c shown in FIG. 14, a portion including a MOSFET transistor 315S, a MOSFET transistor 315R, an NMOS transistor 314S, and an NMOS transistor 314R constituting a differential amplifier circuit, switches 342S, 342R, and switches 343S, 343R are included. The portion further included corresponds to the subtraction unit 83 (FIGS. 5 and 8) of the event detection unit 52, and the shared quantization unit 361 corresponds to the quantization unit 84 (FIGS. 5 and 8).

Although the shared quantization unit 361 shown in FIG. 14 is described as a quantization unit shared by two pixels of the pixel 51S and the pixel 51R, it can also be provided as a quantization unit shared by two or more pixels. Is. When the shared quantization unit 361 is provided as a quantization unit shared by a plurality of (n) pixels 51, the switch 373 is closed when the n pixels 51 are set as the read pixels. It is controlled to be.

Also in the third embodiment, the pixel array unit 31c can be miniaturized. The pixel array unit 31c in the third embodiment includes the shared quantization unit 361, but since it is provided in common for pixels of two or more pixels, the number is smaller than that in the case where it is provided for each pixel. Therefore, even in the case of the configuration including the shared quantization unit 361, the pixel array unit 31c can be miniaturized.

<Fourth Embodiment>
FIG. 15 is a diagram showing the configuration of the pixel array unit 31d of the DVS chip 11 according to the fourth embodiment. The same parts as those of the pixel array part 31b (FIG. 12) in the second embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

In the first to third embodiments, the configuration focuses on the two pixels arranged in the column direction, but in the fourth embodiment, the pixels further arranged in the row direction are also focused on. It is a composition.

FIG. 15 illustrates 2 × 2 4 pixels arranged in the pixel array unit 31d. In the figure, the pixel 51S-1 and the pixel 51R-1 shown on the left side correspond to the pixel 51S and the pixel 51R shown in FIG. The pixel on the right side of the pixel 51S-1 in the figure is referred to as 51S-2, and the pixel on the right side of the pixel 51R-1 in the figure is referred to as 51R-2. In this case, the pixel 51S-1 and the pixel 51S-2 are set as read pixels, and the pixel 51R-1 and the pixel 51R-2 are set as reference pixels.

In FIG. 15, for convenience of explanation, the pixels 51S-2 and 51R-2 shown on the right side of the figure are described with some configurations omitted, but are described as the pixels 51S-1 shown on the left side of the figure. It has the same configuration as the pixel 51R-1. Although some of them are omitted in the following description, the pixels 51 in the pixel array unit 31 have basically the same configuration.

The pixel 51 of the pixel array unit 31d in the fourth embodiment has the same configuration as the pixel 51 of the pixel array unit 31b in the second embodiment, except that it is connected to adjacent pixels. In the example shown in FIG. 15, the reference pixels are connected to each other. Hereinafter, a configuration in which reference pixels arranged in the horizontal direction are connected to each other will be appropriately described as a horizontal connection configuration.

Similar to the first to third embodiments, the read pixel and the reference pixel are connected in the fourth embodiment. Specifically, the gate of the PMOS transistor 315S-1 of the pixel 51S-1 and the gate of the PMOS transistor 315R-1 of the pixel 51R-1 are connected. Further, the gate of the PMOS transistor 315S-2 of the pixel 51S-2 and the gate of the PMOS transistor 315R-2 of the pixel 51R-2 are also connected.

Further, the gate of the PMOS transistor 315R-1 of the pixel 51R-1 set as the reference pixel and the gate of the PMOS transistor 315R-2 of the pixel 51R-2 are also connected. Therefore, the pixel 51S-1, the pixel 51R-1, the pixel 51R-2, and the pixel 51S-2 shown in FIG. 15 are in a state in which the gate of the MIMO transistor 315 included in each is connected.

Such a connection can be said to be a configuration in which the current mirror circuit is connected horizontally. That is, the current mirror circuit is configured by connecting the PMOS transistor 315S-1 of the pixel 51S-1 and the PMOS transistor 315R-1 of the pixel 51R-1. Further, the current mirror circuit is configured by connecting the PMOS transistor 315S-2 of the pixel 51S-2 and the PMOS transistor 315R-2 of the pixel 51R-2. The two current mirror circuits are connected horizontally.

By connecting the reference pixels in this way, the reference voltage can be generated by the same circuit as the signal voltage, and the temperature characteristic can be canceled. Further, the influence of the flicker can be canceled in the pixel circuit. Therefore, it is possible to perform reading with reduced noise.

When the reference pixels are sequentially set to the reading pixels so that the reading is performed, as shown in FIG. 15, the switch 391 is set between the pixels 51 provided in the row direction (horizontal direction in the drawing). It may be provided as a configuration. For example, in the configuration shown in FIG. 15, a switch 391 is provided between the pixel 51R-1 and the pixel 51R-2. The switch 391 is provided as a switch for connecting the pixels 51 set as the reference pixels. In other words, it is provided as a switch that is opened when it is set to a pixel other than the reference pixel.

When a horizontally connected configuration in which reference pixels 51R arranged in the horizontal direction are connected is applied, there is a relationship as shown in FIG. 16 as an example of the relationship between the read pixel 51S and the reference pixel 51R. FIG. 16 shows a case where a plurality of reference pixels 51R are associated with one read pixel 51S-1.

In the upper row in the figure set as the read row, the pixels other than the read pixel 51S-1 are set to the idle pixel 51I. The lower row in the figure set as the reference row is in a state where the reference pixels 51R-1 to 51R-5 are connected because of the horizontally connected configuration.

The idle pixel 51I located in the row set in the read row is sequentially set in the read pixel 51S, and the difference from the signals from the horizontally connected reference pixels 51R-1 to 51R-5 is calculated.

Note that FIG. 16 shows a case where one read pixel 51S is set in the line set as the read line, but as shown in FIG. 17, a plurality of pixels are set in the read pixel 51S and simultaneously. It can also be configured so that the signal is read out.

FIG. 17 is a diagram showing an example of another relationship between the read pixel 51S and the reference pixel 51R in the case of the horizontally connected configuration. Further, the example shown in FIG. 17 is an example in which a plurality of read pixels 51S are set in the line set in the read line.

The example shown in FIG. 17 shows a case where all the pixels in the row set in the read row are set as the read pixels. In FIG. 17, read pixels 51S-1 to 51S-5 are set as read pixels.

In the example shown in FIG. 17, the reference pixel shows a case where all the pixels in the row set as the row of the reference pixel are connected in a horizontally connected configuration, as in the example shown in FIG.

In this way, a plurality of read pixels 51S can be set, and the difference from the horizontally connected reference image 51R can be simultaneously calculated and output by each read pixel 51S.

Further, as shown in FIG. 18, the reference pixel 51R does not connect all the pixels in the row set in the row of the reference pixels, but connects the reference pixels located at positions separated by a predetermined number of pixels. It can also be configured.

In the example shown in FIG. 18, among the rows set in the row of the reference pixel shown on the lower side in the figure, the reference pixel 51R-1, the reference pixel 51R-2, and the reference pixel 51R-3 are set, and the reference pixel 51R-3 is set between them. Pixels are set to idle pixels 51I-4 and idle pixels 51I-5.

In the example shown in FIG. 18, the reference pixels 51R-1 to 51R-3 are connected horizontally. At the next timing, the idle pixel 51I-4 and the idle pixel 51I-5 are set to the reference pixel 51R and are connected horizontally.

In FIG. 18, among the rows set in the row of the read pixels, the read pixels 51S-1 and the read pixels 51S-2 are set, and the pixels in between are set to the idle pixels 51I-1 to 51I-3. ..

The read pixel 51S-1 and the read pixel 51S-2 calculate the difference using the signals from the reference pixels 51R-1 to 51R-3 connected horizontally as reference signals, and output them at the same time.

In this way, when the reference pixel 51R is horizontally connected, the read pixel 51S and the reference pixel 51R are read in a one-to-many relationship.

Further, as shown in FIG. 19, the reference pixels 51R may be arranged in a plurality of rows.

In FIG. 19, among the rows set in the read row, the read pixel 51S-1, the read pixel 51S-2, the read pixel 51S-3, and the read pixel 51S-4 are set, and the pixels in between are the idle pixels 51I. It is set to -1 to 51I-4.

The line next to the read line (middle in the figure) is set to the line of the reference pixel, and the reference pixel 51R-1 and the reference pixel 51R-2 are set in the line, and the pixel in between is the idle pixel 51I-. It is set to 5 to 51I-10.

Further, the line next to the line of the reference pixel (lower row in the figure) is also set to the line of the reference pixel, and the reference pixel 51R-3 and the reference pixel 51R-4 are set in the line, and the pixels in between are set. It is set to idle pixels 51I-11 to 51I-16.

Reference pixels 51R-1 to 51R-4 arranged over a plurality of lines (two lines in this case) are connected by a horizontally connected configuration. Here, although it is described as a horizontally connected configuration, it is possible to connect not only the pixels arranged in the row direction (horizontal direction) but also the pixels arranged in the column direction (vertical direction). it can.

Here, as shown in FIG. 19, the case where the reference pixels 51R-1 to 51R-4 arranged over two rows are connected is described as an example, but the reference pixels 51R-1 to 51R-4 are arranged over two or more rows. It is also possible to configure the reference pixel 51R to be connected.

The read pixel 51S-1 and the read pixel 51S-2 calculate the difference using the signals from the connected reference pixels 51R-1 to 51R-4 as reference signals, and output them at the same time.

Also in the fourth embodiment, the configuration of the pixel array unit 31d can be miniaturized. In addition, it is possible to perform high-efficiency reading with reduced noise.

The pixel array unit 31d in the fourth embodiment shown in FIG. 15 had a configuration in which a current mirror circuit was horizontally connected. Further, as shown in FIG. 20, a configuration in which current sources are connected horizontally may be used.

The pixel array unit 31d shown in FIG. 20 is connected to the current sources of adjacent pixels. Specifically, the current source (load MOS circuit 320) of the pixels 51S-1 and the pixels 51R-1 arranged in the row direction, and the pixels 51S-2 and the pixels arranged in the row direction next to the current source (load MOS circuit 320). The current source (load MOS circuit 320) of 51R-2 is connected in a horizontal connection configuration. A switch 392 may be provided on the wiring for connecting the current source (load MOS circuit 320).

In other words, the current supply line 319 wired to the pixel 51S-1 and the pixel 51R-1 and the current supply line 319 wired to the pixel 51S-2 and the pixel 51R-2 may be connected. .. Further, a switch 392 may be provided between the current supply lines 319.

Switch 392 is turned on or off at the same time as switch 392. Therefore, as shown in FIGS. 16 to 19, when the reference pixel 51R is set, the switch 391 and the switch 392 connecting the reference pixels 51R are turned on (closed). In this way, the current sources can also be connected horizontally.

<Fifth Embodiment>
FIG. 21 is a diagram showing the configuration of the pixel array unit 31e of the DVS chip 11 according to the fifth embodiment. The same parts as those of the pixel array part 31c (FIG. 14) in the third embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31d in the fourth embodiment described with reference to FIG. 21 is arranged in the lateral direction (row direction) with respect to the pixel array unit 31b (FIG. 12) in the second embodiment. It was a configuration in which reference pixels were connected (horizontal connection configuration). Such a horizontal connection configuration can also be applied to the pixel array unit 31c in the third embodiment.

The pixel array unit 31e in the fifth embodiment shown in FIG. 21 has a configuration in which a horizontally connected configuration is applied to the pixel array unit 31c in the third embodiment. That is, the shared quantization unit 361e is provided between the read pixels and the reference pixels.

The shared quantization unit 361e has the same configuration as the shared quantization unit 361 shown in FIG. 14, and is a result of comparing the signal output as the difference between the read pixel and the reference pixel with the threshold signal Von or the threshold signal VOFF. Is output to the vertical signal line 321c. Further, similarly to the pixel array unit 31d of the fourth embodiment, the gate of the PMOS transistor 315 included in each of the pixel 51S-1, the pixel 51R-1, the pixel 51R-2, and the pixel 51S-2 is connected to the pixel array unit 31d. It is said that it is in a state of being.

In this way, the configuration can be configured to include the shared quantization unit 361e. Also in the fifth embodiment, the configuration of the pixel array unit 31e can be miniaturized. In addition, it is possible to perform high-efficiency reading with reduced noise.

The pixel array unit 31e in the fifth embodiment shown in FIG. 21 had a configuration in which a current mirror circuit was horizontally connected. Further, as shown in FIG. 22, the current sources may be connected horizontally.

The pixel array unit 31e shown in FIG. 22 is connected to the current sources of adjacent pixels. Specifically, the current source (load MOS circuit 320) of the pixels 51S-1 and the pixels 51R-1 arranged in the row direction, and the pixels 51S-2 and the pixels arranged in the row direction next to the current source (load MOS circuit 320). The current source (load MOS circuit 320) of 51R-2 is connected in a horizontal connection configuration. A switch 392 may be provided on the wiring for connecting the current source (load MOS circuit 320).

In other words, the current supply line 319 wired to the pixel 51S-1 and the pixel 51R-1 and the current supply line 319 wired to the pixel 51S-2 and the pixel 51R-2 may be connected. .. Further, a switch 392 may be provided between the current supply lines 319.

Switch 392 is turned on or off at the same time as switch 392. Therefore, as shown in FIGS. 16 to 19, when the reference pixel 51R is set, the switch 391 and the switch 392 connecting the reference pixels 51R are turned on (closed). In this way, the current sources can also be connected horizontally.

<Sixth Embodiment>
FIG. 23 is a diagram showing the configuration of the pixel array unit 31f of the DVS chip 11 according to the sixth embodiment. In the pixel array unit 31f according to the sixth embodiment, the same parts as those of the pixel array unit 31e (FIG. 21) according to the fifth embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31f in the sixth embodiment shown in FIG. 23 is different in that the memory unit 411 is added to the pixel array unit 31e in the fifth embodiment.

The memory unit 411 is configured to include the memory 412. The memory unit 411 is provided between the shared quantization unit 361f and the vertical signal line 321f. The switch 373 provided in the shared quantization unit 361e (FIG. 21) is not provided in the shared quantization unit 361f when the memory unit 411 is provided, and is between the memory unit 411 and the vertical signal line 321f. It is configured to be provided in.

That is, the output of the shared quantization unit 361f is configured to be directly input to the memory 412 of the memory unit 411, and the signal stored in the memory 412 is output to the vertical signal line 321f via the switch 373f. It is said that the configuration is as follows.

The switch 373f provided at the set of the selected read pixel and the reference pixel is closed, and the switch 373f provided at the set of the unselected read pixel and the reference pixel is open. The switch 373f is controlled so as to be.

The memory 412 is configured to temporarily store the output result from the shared quantization unit 361f and output the stored signal to the vertical signal line 321f when the switch 373f is closed. The memory 412 stores event data indicating the occurrence of a positive event from the shared quantization unit 361, event data indicating the occurrence of a negative event, or event data indicating that no event has occurred. ..

The pixel array unit 31f in the sixth embodiment shown in FIG. 23 had a configuration in which a current mirror circuit was horizontally connected. Further, as shown in FIG. 24, the current sources may be connected horizontally.

The pixel array unit 31f shown in FIG. 24 is connected to the current sources of adjacent pixels. Specifically, the current source (load MOS circuit 320) of the pixels 51S-1 and the pixels 51R-1 arranged in the row direction, and the pixels 51S-2 and the pixels arranged in the row direction next to the current source (load MOS circuit 320). The current source (load MOS circuit 320) of 51R-2 is connected in a horizontal connection configuration. A switch 392 may be provided on the wiring for connecting the current source (load MOS circuit 320).

In other words, the current supply line 319 wired to the pixel 51S-1 and the pixel 51R-1 and the current supply line 319 wired to the pixel 51S-2 and the pixel 51R-2 may be connected. .. Further, a switch 392 may be provided between the current supply lines 319.

Switch 392 is turned on or off at the same time as switch 392. Therefore, as shown in FIGS. 16 to 19, when the reference pixel 51R is set, the switch 391 and the switch 392 connecting the reference pixels 51R are turned on (closed). In this way, the current sources can also be connected horizontally.

<7th embodiment>
By providing a plurality of memories 412, it is possible to configure the memory unit 411 to store event data representing the occurrence of a positive event and event data representing the occurrence of a negative event, respectively. As a seventh embodiment, a pixel array unit 31g having a memory for storing two event data will be described.

FIG. 25 is a diagram showing the configuration of the pixel array portion 31 g of the DVS chip 11 according to the seventh embodiment. In the pixel array unit 31g according to the seventh embodiment, the same parts as those of the pixel array unit 31f (FIG. 23) according to the sixth embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31g according to the seventh embodiment shown in FIG. 25 is different in that it has an on memory 421 and an off memory 422 in the memory unit 411g.

The on memory 421 is a memory that stores event data indicating the occurrence of a positive event when a threshold signal Von is supplied to the shared quantization unit 361f and event data indicating the occurrence of a positive event is detected. is there. The off memory 422 is a memory that stores the event data indicating the occurrence of the negative event when the threshold signal Voff is supplied to the shared quantization unit 361f and the event data indicating the occurrence of the negative event is detected. is there.

Also in the sixth and seventh embodiments, the configuration of the pixel array portions 31f and 31g can be miniaturized. In addition, it is possible to perform high-efficiency reading with reduced noise.

Note that the sixth and seventh embodiments can be combined with the third embodiment shown in FIG. That is, the memory unit 411 (memory unit 411 g) in the sixth and seventh embodiments may be provided after the shared quantization unit 361 included in the pixel array unit 31c shown in FIG.

The pixel array unit 31g in the seventh embodiment shown in FIG. 25 had a configuration in which a current mirror circuit was horizontally connected. Further, as shown in FIG. 26, the current sources may be connected horizontally.

The pixel array unit 31g shown in FIG. 26 is connected to the current sources of adjacent pixels. Specifically, the current source (load MOS circuit 320) of the pixels 51S-1 and the pixels 51R-1 arranged in the row direction, and the pixels 51S-2 and the pixels arranged in the row direction next to the current source (load MOS circuit 320). The current source (load MOS circuit 320) of 51R-2 is connected in a horizontal connection configuration. A switch 392 may be provided on the wiring for connecting the current source (load MOS circuit 320).

In other words, the current supply line 319 wired to the pixel 51S-1 and the pixel 51R-1 and the current supply line 319 wired to the pixel 51S-2 and the pixel 51R-2 may be connected. .. Further, a switch 392 may be provided between the current supply lines 319.

Switch 392 is turned on or off at the same time as switch 392. Therefore, as shown in FIGS. 16 to 19, when the reference pixel 51R is set, the switch 391 and the switch 392 connecting the reference pixels 51R are turned on (closed). In this way, the current sources can also be connected horizontally.

<Eighth Embodiment>
FIG. 27 is a diagram showing the configuration of the pixel array unit 31h of the DVS chip 11 according to the eighth embodiment. In the pixel array unit 31h according to the eighth embodiment, the same parts as those of the pixel array unit 31e (FIG. 21) according to the fifth embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31c in the third embodiment, the pixel array unit 31e in the fifth embodiment, the pixel array unit 31f in the sixth embodiment, and the pixel array unit 31g in the seventh embodiment are respectively. It is common in that it includes a shared quantization unit 361. Further, the shared quantization unit 361 is common in that it outputs event data indicating the occurrence of positive or negative events.

As the pixel array unit 31h in the eighth embodiment, a shared quantization unit that outputs event data indicating the occurrence of a positive event and a shared quantization unit that outputs event data indicating the occurrence of a negative event. The pixel array unit 31h including the two will be described.

In the pixel array unit 31h according to the eighth embodiment shown in FIG. 27, the shared quantization unit 361e of the pixel array unit 31e according to the fifth embodiment is the shared quantization unit 431 and the shared quantization unit 432-2. The difference is that it is composed of two quantization units.

The shared quantization unit 431 is configured to include a MOSFET transistor 441, an MIMO transistor 442, and a switch 443. Similarly, the shared quantization unit 432 is configured to include a NMOS transistor 451, an MIMO transistor 452, and a switch 453.

The signal read from the pixel 51 is supplied to the gate of the MIMO transistor 441 of the shared quantization unit 431 and the gate of the MIMO transistor 451 of the shared quantization unit 432, respectively.

A threshold signal Von is supplied to the NMOS transistor 442 of the shared quantization unit 431. The shared quantization unit 431 detects event data representing the occurrence of a positive event. When the shared quantization unit 431 detects event data indicating the occurrence of a positive event, and the switch 443 is closed, a signal is supplied to the vertical signal line 444.

A threshold signal Voff is supplied to the NMOS transistor 452 of the shared quantization unit 432. The shared quantization unit 432 detects event data representing the occurrence of a negative event. When the shared quantization unit 432 detects event data indicating the occurrence of a negative event, and the switch 453 is closed, a signal is supplied to the vertical signal line 454.

In this way, the two shared quantization units 431 and 432 can be provided to detect positive and negative events, respectively.

Also in the eighth embodiment, the configuration of the pixel array unit 31h can be miniaturized. In addition, it is possible to perform high-efficiency reading with reduced noise.

The eighth embodiment can be combined with the third embodiment shown in FIG. That is, the shared quantization unit 431 and the shared quantization unit 432 according to the eighth embodiment may be provided after the shared quantization unit 361 included in the pixel array unit 31c shown in FIG.

The pixel array unit 31h in the eighth embodiment shown in FIG. 27 had a configuration in which a current mirror circuit was horizontally connected. Further, as shown in FIG. 28, the current sources may be connected horizontally.

The pixel array unit 31h shown in FIG. 28 is connected to the current sources of adjacent pixels. Specifically, the current source (load MOS circuit 320) of the pixels 51S-1 and the pixels 51R-1 arranged in the row direction, and the pixels 51S-2 and the pixels arranged in the row direction next to the current source (load MOS circuit 320). The current source (load MOS circuit 320) of 51R-2 is connected in a horizontal connection configuration. A switch 392 may be provided on the wiring for connecting the current source (load MOS circuit 320).

In other words, the current supply line 319 wired to the pixel 51S-1 and the pixel 51R-1 and the current supply line 319 wired to the pixel 51S-2 and the pixel 51R-2 may be connected. .. Further, a switch 392 may be provided between the current supply lines 319.

Switch 392 is turned on or off at the same time as switch 392. Therefore, as shown in FIGS. 16 to 19, when the reference pixel 51R is set, the switch 391 and the switch 392 connecting the reference pixels 51R are turned on (closed). In this way, the current sources can also be connected horizontally.

<9th embodiment>
FIG. 29 is a diagram showing the configuration of the pixel array unit 31i of the DVS chip 11 according to the ninth embodiment. In the pixel array unit 31i according to the ninth embodiment, the same parts as those of the pixel array unit 31d (FIG. 15) according to the fourth embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31i in the ninth embodiment is different from the pixel array unit 31 in the first to eighth embodiments in that the portion constituting the current mirror circuit is provided outside the pixel 51. ..

As a current mirror circuit for the pixel 51S-1 set as the read pixel and the pixel 51R-1 set as the reference pixel, the MIMO transistor 511-1 and the MIMO transistor 512-1 are outside the pixel 51, and the pixel array. It is provided in the section 31. Further, the switch 513-1 and the switch 514-1 are also provided outside the pixel 51 and inside the pixel array unit 31.

Further, a switch 501S-1 is provided in the pixel 51S-1, and when the switch 501S-1 is closed, the drain of the MIMO transistor 511-1 and the drain of the MIMO transistor 314S are connected to each other. Similarly, a switch 501R-1 is provided in the pixel 51R-1, and when the switch 501R-1 is closed, the drain of the MIMO transistor 512-1 and the drain of the MIMO transistor 314R are connected to each other.

The MIMO transistor 511-1 corresponds to, for example, the PMOS transistor 315S-1 in the pixel 51S-1 of the pixel array unit 31d shown in FIG. The epitaxial transistor 512-1 corresponds to, for example, the MIMO transistor 315R-1 in the pixel 51R-1 of the pixel array unit 31d shown in FIG. Further, the switch 513-1 corresponds to, for example, the switch 343S in the pixel 51S-1 of the pixel array unit 31d shown in FIG. Further, the switch 514-1 corresponds to, for example, the switch 342S in the pixel 51S-1 of the pixel array unit 31d shown in FIG.

The switch 514-1 is a switch that is closed when the pixel 51S-1 functions as a read pixel. The switch 513-1 is a switch that is closed when the pixel 51S does not function as a read pixel, and is a switch that is closed when the pixel 51R-1 functions as a reference pixel.

Switch 513-1 and switch 514-1 are controlled so that when one is closed, the other is open. When the switch 314-1 is closed, the difference between the pixel 51S-1 as the read pixel and the pixel 51R-1 as the reference pixel is supplied to the vertical signal line 516-1. When the switch 313-1 is closed, the difference between the pixel 51R-1 as the read pixel and the pixel 51S-1 as the reference pixel is supplied to the vertical signal line 515-1.

The same configuration as that of the pixel 51S-1 and the pixel 51R-1 is formed in the pixel 51S-2 and the pixel 51R-2. That is, as a current mirror circuit for the pixel 51S-2 set as the read pixel and the pixel 51R-2 set as the reference pixel, the MIMO transistor 511-2, the MIMO transistor 512-2, the switch 513-2, and the switch 514-2 is outside the pixel 51 and is provided inside the pixel array unit 31.

The current mirror circuits are connected by a horizontal connecting wire 531. The horizontal connecting wire 531 is connected to a wiring that connects the gate of the MIMO transistor 511-1 and the gate of the MIMO transistor 512-1 and a wiring that connects the switch 513-1 and the switch 514-1. Further, the horizontal connecting wire 531 is connected with a wiring for connecting the gate of the MIMO transistor 511-2 and the gate of the MIMO transistor 512-2 and a wiring for connecting the switch 513-2 and the switch 514-2.

In this case, the bias voltage of the current mirror circuit is connected horizontally. By performing the horizontal connection in this way, it is possible to suppress the generation of noise.

As shown in FIG. 29, the switch 532 may be provided on the horizontal connecting wire 531. When the switch 532 is closed, the bias voltage of the current mirror circuit becomes a horizontal connection state. Therefore, such a horizontal connection state and a non-horizontal connection state should be controlled by opening and closing the switch 532. You can also.

In the example shown in FIG. 29, the part of the current mirror circuit is shared by two pixels of the pixel 51S-1 and the pixel 51R-1, but the configuration is such that it is shared by two or more pixels 51. Is also possible. In other words, the current mirror circuit can be provided as a circuit shared by a plurality of lines.

By configuring the MIMO transistors 511, 512 that make up the current mirror circuit outside the pixel 51, the configuration of the pixel 51 can be miniaturized. Further, by making the current mirror circuit shared by a plurality of pixels 51, the configuration of the pixel array unit 31i can be miniaturized. Therefore, also in the ninth embodiment, the configuration of the pixel array unit 31i can be miniaturized. In addition, it is possible to perform high-efficiency reading with reduced noise.

The pixel array unit 31i in the ninth embodiment shown in FIG. 29 had a configuration in which a current mirror circuit was horizontally connected. Further, as shown in FIG. 30, a configuration in which current sources are connected horizontally may be used.

The pixel array unit 31i shown in FIG. 30 is connected to the current sources of adjacent pixels. Specifically, the current source (load MOS circuit 320) of the pixels 51S-1 and the pixels 51R-1 arranged in the row direction, and the pixels 51S-2 and the pixels arranged in the row direction next to the current source (load MOS circuit 320). The current source (load MOS circuit 320) of 51R-2 is connected in a horizontal connection configuration. A switch 392 may be provided on the wiring for connecting the current source (load MOS circuit 320).

In other words, the current supply line 319 wired to the pixel 51S-1 and the pixel 51R-1 and the current supply line 319 wired to the pixel 51S-2 and the pixel 51R-2 may be connected. .. Further, a switch 392 may be provided between the current supply lines 319.

Switch 392 is turned on or off at the same time as switch 392. Therefore, as shown in FIGS. 16 to 19, when the reference pixel 51R is set, the switch 391 and the switch 392 connecting the reference pixels 51R are turned on (closed). In this way, the current sources can also be connected horizontally.

<10th Embodiment>
FIG. 31 is a diagram showing a configuration of a pixel array unit 31j in the DVS chip 11 according to the tenth embodiment. In the pixel array unit 31j according to the tenth embodiment, the same parts as those of the pixel array unit 31i (FIG. 29) according to the ninth embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31j according to the tenth embodiment shown in FIG. 31 is different from the pixel array unit 31i (FIG. 29) according to the ninth embodiment except that the current mirror circuit is arranged outside the pixel array unit 31. , Is the same.

That is, the pixel array unit 31j in the tenth embodiment shown in FIG. 31 and the pixel array unit 31i in the ninth embodiment shown in FIG. 29 have the same configuration, but are outside the pixels 51. The difference is that the current mirror circuit formed in the pixel array unit 31i is outside the pixel 51, and the current mirror circuit is formed at a position outside the pixel array unit 31j.

The MIMO transistors 511, 512, switches 513, 514, etc. that make up the current mirror circuit can be formed in the peripheral circuit. For example, when the data processing chip is formed as shown in FIG. 1, the current mirror circuit can be formed on the logic die 12 stacked on the DVS chip 11.

By providing the current mirror circuit outside the pixel array unit 31, the configuration of the pixel array unit 31 can be miniaturized. Therefore, also in the tenth embodiment, the configuration of the pixel array unit 31j can be miniaturized. In addition, it is possible to perform high-efficiency reading with reduced noise.

The pixel array unit 31j in the tenth embodiment shown in FIG. 31 had a configuration in which a current mirror circuit was horizontally connected. Further, as shown in FIG. 32, the current sources may be connected horizontally.

The pixel array unit 31j shown in FIG. 32 is connected to the current sources of adjacent pixels. Specifically, the current source (load MOS circuit 320) of the pixels 51S-1 and the pixels 51R-1 arranged in the row direction, and the pixels 51S-2 and the pixels arranged in the row direction next to the current source (load MOS circuit 320). The current source (load MOS circuit 320) of 51R-2 is connected in a horizontal connection configuration. A switch 392 may be provided on the wiring for connecting the current source (load MOS circuit 320).

In other words, the current supply line 319 wired to the pixel 51S-1 and the pixel 51R-1 and the current supply line 319 wired to the pixel 51S-2 and the pixel 51R-2 may be connected. .. Further, a switch 392 may be provided between the current supply lines 319.

Switch 392 is turned on or off at the same time as switch 392. Therefore, as shown in FIGS. 16 to 19, when the reference pixel 51R is set, the switch 391 and the switch 392 connecting the reference pixels 51R are turned on (closed). In this way, the current sources can also be connected horizontally.

<11th Embodiment>
FIG. 33 is a diagram showing the configuration of the pixel array portion 31k of the DVS chip 11 according to the eleventh embodiment. In the pixel array unit 31k according to the eleventh embodiment, the same parts as those of the pixel array unit 31j (FIG. 31) according to the tenth embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31k in the eleventh embodiment shown in FIG. 33 has a configuration in which a memory 551 is added in the pixel 51 as compared with the pixel array unit 31j in the tenth embodiment shown in FIG. 31. The other points are the same.

In FIG. 33, the pixels 51S-2 and the pixels 51R-2 located on the right side of the pixel array unit 31j shown in FIG. 31 are not shown, but they are connected in a horizontally connected configuration as in the case shown in FIG. There is. In the following embodiments, as in FIG. 33, the pixels 51S-2 and 51R-2 shown on the right side are not shown, but are horizontally connected.

The pixel 51S is provided with a memory 551S, and the pixel 51R is provided with a memory 551R. If an event is detected while the pixel 51S is set as the read pixel, the memory 551S stores the event data. Similarly, the memory 551R stores the event data when an event is detected when the pixel 51R is set as the read pixel.

By providing the memory 551 in the pixel 51 and storing the event data in this way, it is possible to reduce the occurrence of distortion (artifact). For example, if the reading timings of the upper row and the lower row are different, distortion may occur due to the difference in the reading timing when shooting a fast-moving object.

By providing the memory 551, a two-phase (2-Phase) global shutter can be realized. In the configuration shown in FIG. 33, the signal for controlling the opening and closing of the switch 514 is referred to as the control signal SELa, and the signal for controlling the opening and closing of the switch 513 is referred to as the control signal SELb. Further, a signal for controlling the timing of writing event data to the memory 551S is referred to as a control signal MemWRa, and a signal for controlling the timing of writing event data to the memory 551R is referred to as a control signal MemWRb.

The control signal SELa and the control signal MemWRa are signals shared by all odd-numbered lines, and the control signal SELb and control signal MemWRb are signals shared by all even-numbered lines.

In Phase 1, the control signal SELa and the control signal MemWRa are activated, and the result of the luminance change (event data) is written to the pixels 51 in the odd-numbered rows. At the time of phase 2, the control signal SELb and the control signal Mem WRb are activated, and the result of the luminance change (event data) is written to the pixels 51 in the even-numbered rows. Such a two-phase global shutter can be realized.

Also in the eleventh embodiment, the configuration of the pixel array unit 31k can be miniaturized. In addition, it is possible to perform high-efficiency reading with reduced noise. In addition, it becomes possible to perform shooting with reduced distortion.

The pixel array unit 31k in the eleventh embodiment shown in FIG. 33 had a configuration in which a current mirror circuit was horizontally connected. Further, although not shown, for example, the configuration shown in FIG. 32 may be applied to horizontally connect the current sources.

<12th Embodiment>
FIG. 34 is a diagram showing the configuration of the pixel array portion 31m of the DVS chip 11 in the twelfth embodiment. In the pixel array unit 31m according to the twelfth embodiment, the same parts as those of the pixel array unit 31k (FIG. 33) according to the eleventh embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31m in the twelfth embodiment shown in FIG. 34 has a quantization unit 552 added in the pixel 51 as compared with the pixel array unit 31k in the eleventh embodiment shown in FIG. 33. The difference is that the configuration is the same, and the other points are the same.

The pixel 51S is provided with a quantization unit 552S, and the pixel 51R is provided with a quantization unit 552R.

The pixel array unit 31m according to the twelfth embodiment shown in FIG. 34 includes a memory 551 that stores the result quantized by the quantization unit 552 and the quantization unit 552 in the pixel 51. The quantization unit 552 and the memory 551 can be, for example, parts corresponding to the shared quantization unit 361f and the memory 412 in the pixel array unit 31f shown in FIG. 23.

By providing the memory 551, it is possible to realize a global shutter with less distortion as described above. Further, by providing the quantization unit 552, the operation speed can be improved. The pixel array unit 31m is configured to include a differential amplifier circuit as in the above-described embodiment. The pixel array unit 31m is further configured to include a quantization unit 552 having an amplification function in the subsequent stage of the differential amplifier circuit. Therefore, the amplification factor can be increased and the operating speed can be improved.

It is also possible to store two threshold values in the quantization unit 552 so that quantization can be performed using the two threshold values. The two threshold values can be, for example, the threshold values corresponding to the threshold value signal Von and the threshold value signal Voff input to the shared quantization unit 361f in the pixel array unit 31f shown in FIG. 23. By setting the two threshold values in the quantization unit 552, it is possible to detect a case where the brightness increases, that is, a positive electrode property, and a case where the brightness decreases, that is, a negative electrode property.

Also in the twelfth embodiment, the configuration of the pixel array unit 31 m can be miniaturized. In addition, it is possible to perform high-efficiency reading with reduced noise. In addition, it becomes possible to perform shooting with reduced distortion.

The pixel array unit 31m in the twelfth embodiment shown in FIG. 34 had a configuration in which a current mirror circuit was horizontally connected. Further, although not shown, for example, the configuration shown in FIG. 32 may be applied to horizontally connect the current sources.

<13th Embodiment>
FIG. 35 is a diagram showing the configuration of the pixel array unit 31n of the DVS chip 11 according to the thirteenth embodiment. In the pixel array unit 31n according to the thirteenth embodiment, the same parts as those of the pixel array unit 31j (FIG. 31) according to the tenth embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31n in the thirteenth embodiment shown in FIG. 35 adds a quantization unit 571 to the outside of the pixel 51 as compared with the pixel array unit 31j in the tenth embodiment shown in FIG. 31. The difference is that the configuration is the same, and the other points are the same.

The pixel array unit 31n according to the thirteenth embodiment shown in FIG. 35 includes a quantization unit 571 outside the pixel array unit 31n. This quantization unit 571 corresponds to, for example, the shared quantization unit 361 of the pixel array unit 31c in the third embodiment shown in FIG. 14, and is provided as a quantization unit shared by a plurality of pixels 51. be able to.

It is also possible to store two threshold values in the quantization unit 571 so that quantization can be performed using the two threshold values. The two threshold values can be, for example, the threshold values corresponding to the threshold value signal Von and the threshold value signal Voff input to the shared quantization unit 361f in the pixel array unit 31f shown in FIG. 23. By setting the two threshold values in the quantization unit 571, it is possible to detect a case where the brightness increases, that is, a positive electrode property, and a case where the brightness decreases, that is, a negative electrode property.

Also in the thirteenth embodiment, the configuration of the pixel array unit 31n can be miniaturized. In addition, it is possible to perform high-efficiency reading with reduced noise.

The pixel array unit 31n in the thirteenth embodiment shown in FIG. 35 had a configuration in which a current mirror circuit was horizontally connected. Further, although not shown, for example, the configuration shown in FIG. 32 may be applied to horizontally connect the current sources.

<14th Embodiment>
FIG. 36 is a diagram showing the configuration of the pixel array portion 31p of the DVS chip 11 in the 14th embodiment. In the pixel array unit 31p according to the fourteenth embodiment, the same parts as those of the pixel array unit 31d (FIG. 15) according to the fourth embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31p in the 14th embodiment shown in FIG. 36 has a capacitor 601 and a capacitor 602 added to the pixel 51 as compared with the pixel array unit 31d in the fourth embodiment shown in FIG. The difference is that the configuration is the same, and the other points are the same.

In FIG. 36, the pixel 51S-2 shown in FIG. 15 and the pixel 51 corresponding to the pixel 51R-2 are not shown, but they have a horizontally connected configuration and are connected to the pixel 51R-2 (not shown). .. The same applies to FIG. 38, which will be described later.

The pixel 51S has a capacitor 601S and a capacitor 602S. A signal VTHa1 having a predetermined voltage value is supplied from the outside to one end of the capacitor 601S, and the other end is connected to the gate side of the NMOS transistor 314S. Similarly, a signal VTHa2 having a predetermined voltage value is supplied from the outside to one end of the capacitor 602S, and the other end is connected to the gate side of the NMOS transistor 314S.

Similarly, the pixel 51R has a capacitor 601R and a capacitor 602R. A signal VTHb1 having a predetermined voltage value is supplied from the outside to one end of the capacitor 601R, and the other end is connected to the gate side of the NMOS transistor 314R. Similarly, a signal VTHb2 having a predetermined voltage value is supplied from the outside to one end of the capacitor 602R, and the other end is connected to the gate side of the NMOS transistor 314R.

The configuration of the pixel array unit 31p shown in FIG. 36 is an example in which a horizontally connected configuration is adopted. The capacitor 601 and the capacitor 602 are provided as one of the purposes for alleviating the variation in capacitance in the horizontal connection.

In the configuration of the pixel array unit 31p shown in FIG. 36, the portion corresponding to the differential amplifier circuit operates as the quantization unit 84 (FIG. 5) of the event detection unit 52. The operation of the pixel array unit 31p shown in FIG. 36 will be described with reference to the timing chart of FIG. 37.

Here, a case where the pixel 51S is a read pixel and the pixel 51R is a reference pixel will be described as an example. Since the horizontal connection configuration is adopted, the comparison is made with the average voltage of the row (reference row) in which the reference pixel is arranged. Specifically, the pixel 51S set as the read pixel is compared with the average voltage of the reference line, and the brightness change of the pixel 51S is high, low, or no change. Is detected as event data.

At time t51, when the control signal SELa is set to H level, the pixel 51S is set as the read pixel and the switch 342S is turned on. From time t51 to time t54, the control signal SELb is maintained at the L level, the signal VTHa1 is maintained at the H level, and the signal VTHa2 is maintained at the L level.

From time t52 to time t53, an OFF event, that is, a negative event in this case, is detected. At time t52, the signal VTHb1 is switched from the H level to the L level, and the signal VTHb2 is maintained at the L level. That is, in this case, both the signal VTHb1 and the signal VTHb2 are set to the L level. When the signal VTHb1 and the signal VTHb2 are at the L level and the output to the vertical signal line 321 becomes High, it means that a negative event has been detected.

From time t53 to time t54, an ON event, that is, a positive event in this case, is detected. At time t53, the signal VTHb1 is switched from L level to H level and the signal VTHb2 is switched from L level to H level. When both the signal VTHb1 and the signal VTHb2 are at H level and the output to the vertical signal line 321 becomes LOW, it means that a positive electrode event has been detected.

In this way, by providing a capacitor in the pixel 51 and controlling the signal VTHb1 and the signal VTHb2 supplied to the pixel 51 as the reference pixel, the part corresponding to the differential amplifier circuit functions as a quantization unit. The occurrence of an event can be detected. Also in the fourteenth embodiment, the configuration of the pixel array unit 31p can be miniaturized.

The pixel array unit 31p in the fourteenth embodiment shown in FIG. 36 had a configuration in which a current mirror circuit was horizontally connected. Further, although not shown, for example, the configuration shown in FIG. 32 may be applied to horizontally connect the current sources.

<Fifteenth Embodiment>
FIG. 38 is a diagram showing the configuration of the pixel array portion 31q of the DVS chip 11 according to the fifteenth embodiment. In the pixel array unit 31q in the fifteenth embodiment, the same parts as the pixel array unit 31p (FIG. 36) in the fourteenth embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The pixel array unit 31q in the fifteenth embodiment shown in FIG. 38 has a configuration in which a shared quantization unit 361q is added as compared with the pixel array unit 31p in the fourteenth embodiment shown in FIG. 36. The points are different, and the other points are the same. Further, the shared quantization unit 361q corresponds to the shared quantization unit 361e of the pixel array unit 31e in the fifth embodiment shown in FIG. 21, has the same configuration, and basically performs the same operation. ..

In the configuration of the pixel array unit 31q shown in FIG. 38, the portion corresponding to the differential amplifier circuit operates as the subtraction unit 83 (FIG. 5) of the event detection unit 52. Further, in the configuration of the pixel array unit 31q shown in FIG. 38, the shared quantization unit 361q operates as the quantization unit 84 (FIG. 5) of the event detection unit 52. The operation of the pixel array unit 31q shown in FIG. 38 will be described with reference to the timing chart of FIG. 39.

Refer to the timing chart shown in A of FIG. 39. The control signal SELa, the control signal SELbVTHa1, the signal VTHa2, the signal VTHb1, and the signal VTHb2 are the same as those shown in FIG. 37. That is, the operation performed by the pixels 51S and 51R is the same as the pixels 51S and 51R of the pixel array unit 31p in the fourteenth embodiment.

A signal Von and a signal Voff are supplied to the NMOS transistor 372 in the shared quantization unit 361q in a time-division manner. In the timing chart shown in FIG. 39A, the signal Von and the signal Voff are signals having constant values, and the levels do not change from time t61 to time t64. In this way, the signal supplied to the shared quantization unit 361q is set to a constant value, and the bias voltage of the shared quantization unit 361q is controlled to be one.

Alternatively, control based on the timing chart shown in B of FIG. 39 may be performed. The timing chart shown in FIG. 39B shows an example in which the signal Von and the signal Voff are supplied in a time-division manner.

When a negative event is detected from time t72 to time t73, a signal Voff (L level signal) is supplied. When a positive event is detected from time t73 to time t74, a signal Von (H level signal) is supplied.

In this way, the configuration may include the shared quantization unit 361q to detect the occurrence of an event. Also in the fifteenth embodiment, the configuration of the pixel array unit 31q can be miniaturized.

The pixel array unit 31q in the fifteenth embodiment shown in FIG. 38 had a configuration in which a current mirror circuit was horizontally connected. Further, although not shown, for example, the configuration shown in FIG. 32 may be applied to horizontally connect the current sources.

In the fourth to fifteenth embodiments, the case where the horizontal connection configuration in the row direction is applied has been described as an example, but the horizontal connection configuration may be applied to each block.

In the first to fifteenth embodiments, the case of processing in units of 51 pixels has been described as an example, but it can also be applied to the case of processing in block units.

Further, in the first to fifteenth embodiments, the read pixel and the reference pixel have been described with reference to an example in which the read pixel and the reference pixel are sequentially switched and read. However, a predetermined pixel is fixed as a reference pixel and the reference pixel is fixed. The difference from the reference pixel may be read out. Further, the reference pixel may be a light-shielded pixel.

It should be noted that an embodiment in which the first to fifteenth embodiments are combined is also possible.

By applying this technology, the pixel area can be reduced. Further, the threshold voltage can be generated in the vicinity of the pixel. Therefore, high-speed reading can be realized. Further, since adjacent pixels are used, the temperature characteristics can be canceled and the influence of flicker can be suppressed.

<Example of application to mobiles>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.

FIG. 40 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 40, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (Interface) 12053 are shown.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 provides a driving force generator for generating the driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating a braking force of a vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, blinkers or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.

The vehicle outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or characters on the road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects the in-vehicle information. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing.

The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.

Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver can control the driver. It is possible to perform coordinated control for the purpose of automatic driving that runs autonomously without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the external information detection unit 12030, and performs coordinated control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.

The audio image output unit 12052 transmits the output signal of at least one of the audio and the image to the output device capable of visually or audibly notifying the passenger or the outside of the vehicle of the information. In the example of FIG. 40, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.

FIG. 41 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 41, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

The imaging units 12101, 12102, 12103, 12104, 12105 are provided at positions such as, for example, the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirrors mainly acquire images of the side of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 41 shows an example of the photographing range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range of the imaging units 12102 and 12103. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 has a distance to each three-dimensional object within the imaging range 12111 to 12114 based on the distance information obtained from the imaging units 12101 to 12104, and a temporal change of this distance (relative velocity with respect to the vehicle 12100). By obtaining, it is possible to extract as the preceding vehicle a three-dimensional object that is the closest three-dimensional object on the traveling path of the vehicle 12100 and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle in advance, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.

For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. Such pedestrian recognition includes, for example, a procedure for extracting feature points in an image captured by an imaging unit 12101 to 12104 as an infrared camera, and pattern matching processing for a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

Note that the effects described in this specification are merely examples and are not limited, and other effects may be obtained.

The embodiment of the present technology is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present technology.

The present technology can also have the following configurations.
(1)
The first photoelectric conversion element and
The second photoelectric conversion element and
A differential amplifier circuit is provided as a circuit that generates a difference signal corresponding to the difference in voltage between the first photoelectric conversion element and the second photoelectric conversion element.
An event detection device that detects the occurrence of an event that is a change in a signal based on a signal from the differential amplifier circuit.
(2)
The transistors constituting the differential amplifier circuit are dispersedly arranged in a first pixel including the first photoelectric conversion element and a second pixel including the second photoelectric conversion element (1). ). The event detection device.
(3)
When one of the first pixel and the second pixel is a read pixel and the other is a reference pixel, the differential amplifier circuit determines the difference between the signal from the read pixel and the signal from the reference pixel. The event detection device according to (2) above, which outputs.
(4)
Of the first transistor and the second transistor constituting the current mirror circuit included in the differential amplifier circuit, the first transistor is included in the first pixel, and the second transistor is the second transistor. The event detection device according to (2) above, which is included in the pixel.
(5)
The first transistor and the second transistor constituting the current mirror circuit included in the differential amplifier circuit are included in the pixel array portion in which the first pixel and the second pixel are arranged (2). ). The event detection device.
(6)
The first transistor and the second transistor constituting the current mirror circuit included in the differential amplifier circuit are arranged outside the pixel array portion in which the first pixel and the second pixel are arranged. The event detection device according to (2) above.
(7)
The event detection according to any one of (2) to (6) above, wherein the reset of the signal in the first pixel and the reset of the signal in the second pixel are performed synchronously by a signal from the outside. apparatus.
(8)
The reset of the signal in the first pixel and the reset of the signal in the second pixel are performed asynchronously by the signal generated in each pixel in any of the above (2) to (6). The event detector described.
(9)
The first pixel and the second pixel are, respectively, a first switch that is closed when the read pixel is set and a second switch that is closed when the reference pixel is set. The event detection device according to any one of (3) to (8) above.
(10)
The event detection according to (9) above, further comprising a quantization unit that outputs a comparison result comparing a signal output via the first switch with a predetermined threshold value as event data indicating the occurrence of the event. apparatus.
(11)
The event detection device according to (10), further including a memory unit that stores an output from the quantization unit.
(12)
The event detection according to (11) above, wherein the memory unit includes a first memory for storing the result compared with the first threshold value and a second memory for storing the result compared with the second threshold value. apparatus.
(13)
A first quantization unit that outputs a comparison result comparing the signal output via the first switch and the first threshold value as event data indicating the occurrence of the event, and the first quantization unit.
(9) The above (9) further includes a second quantization unit that outputs a comparison result comparing the signal output via the first switch and the second threshold value as event data indicating the occurrence of the event. The event detection device described in.
(14)
The reference pixels are connected and
The event detection device according to any one of (3) to (13), wherein a transistor included in the reference pixel and forming a current mirror circuit included in the differential amplifier circuit is connected.
(15)
The first pixel includes a first memory for storing event data representing the occurrence of the event.
The second pixel includes a second memory for storing event data representing the occurrence of the event.
The event detection device according to any one of (2) to (14), wherein the writing to the first memory and the writing to the second memory are performed at different timings.
(16)
The first pixel includes a first quantization unit that compares an output from the differential amplifier circuit with a predetermined threshold value.
The second pixel includes a second quantization unit that compares the output from the differential amplifier circuit with a predetermined threshold value.
The first memory stores the output from the first quantization unit, and stores the output from the first quantization unit.
The event detection device according to (15), wherein the second memory stores an output from the second quantization unit.
(17)
A quantization unit for comparing the output from the differential amplifier circuit with a predetermined threshold value is further provided.
The first transistor and the second transistor constituting the current mirror circuit included in the differential amplifier circuit, and the quantization unit are pixel array units in which the first pixel and the second pixel are arranged. The event detection device according to (2) above, which is arranged outside.
(18)
A first capacitor to which the first threshold signal is supplied and a second capacitor to which the second threshold signal is supplied are further provided.
The event detection device according to (1), wherein the first capacitor and the second capacitor are connected between a photoelectric conversion element and a transistor constituting a differential amplifier circuit.
(19)
The event detection device according to (18), wherein the first threshold signal and the second threshold signal are supplied to a reference pixel that supplies a reference signal to the differential amplifier circuit.
(20)
When the comparison result between the output from the differential amplifier circuit and the first threshold value is detected as the event, both the first threshold value signal and the second threshold value signal are H-level signals.
When the comparison result between the output from the differential amplifier circuit and the second threshold value is detected as the event, both the first threshold value signal and the second threshold value signal are L-level signals. 19) The event detection device according to.

11 DVS chip, 12 logic die, 21 event generation unit, 22 data processing unit, 31 pixel array unit, 32 drive unit, 33 arbiter, 34 output unit, 41 pixel block, 51 pixels, 52 event detection unit, 60 nodes, 61 Photoelectric conversion element, 81 current-voltage conversion unit, 82 buffer, 83 subtraction unit, 84 quantization unit, 85 transfer unit, 91 transistor, 92 transistor, 93 transistor, 101 transistor, 102 operational capacitor, 103 capacitor, 104 switch, 111, 112. Comparer, 113 output unit, 312 condenser, 313,314 switch, 315 MIMO transistor, 316 OR circuit, 317, 318 switch, 319 current supply line, 320 load MOS circuit, 321 vertical signal line, 322 ACK signal line, 323 switch, 341 capacitor, 342, 343 switch, 361 shared quantization unit, 371 MIMO transistor, 372 NMOS transistor, 373 switch, 391,392 switch, 411 memory unit, 412 memory, 421 on memory, 422 off memory, 431,432 shared quantum Kabu, 441 MIMO transistor, 442 MIMO transistor, 443 switch, 444 vertical signal line, 451 MIMO transistor, 452 MIMO transistor, 453 switch, 454 vertical signal line, 501 switch, 511,512 MIMO transistor, 513,514 switch, 515. , 516 vertical signal line, 531 horizontal connecting line, 532 switch, 551 memory, 552 quantization part, 571 quantization part, 601,602 capacitor

Claims (20)

1. The first photoelectric conversion element and
   The second photoelectric conversion element and
   A differential amplifier circuit is provided as a circuit that generates a difference signal corresponding to the difference in voltage between the first photoelectric conversion element and the second photoelectric conversion element.
   An event detection device that detects the occurrence of an event that is a change in a signal based on a signal from the differential amplifier circuit.
2. Claim 1 in which the transistors constituting the differential amplifier circuit are dispersedly arranged in a first pixel including the first photoelectric conversion element and a second pixel including the second photoelectric conversion element. The event detection device described in.
3. When one of the first pixel and the second pixel is a read pixel and the other is a reference pixel, the differential amplifier circuit determines the difference between the signal from the read pixel and the signal from the reference pixel. The event detection device according to claim 2, which outputs.
4. Of the first transistor and the second transistor constituting the current mirror circuit included in the differential amplifier circuit, the first transistor is included in the first pixel, and the second transistor is the second transistor. The event detection device according to claim 2, which is included in a pixel.
5. The first transistor and the second transistor constituting the current mirror circuit included in the differential amplifier circuit are included in the pixel array portion in which the first pixel and the second pixel are arranged. The event detection device described in.
6. The first transistor and the second transistor constituting the current mirror circuit included in the differential amplifier circuit are arranged outside the pixel array portion in which the first pixel and the second pixel are arranged. The event detection device according to claim 2.
7. The event detection device according to claim 2, wherein the reset of the signal in the first pixel and the reset of the signal in the second pixel are performed in synchronization with a signal from the outside.
8. The event detection device according to claim 2, wherein the reset of the signal in the first pixel and the reset of the signal in the second pixel are performed asynchronously by the signal generated in each pixel.
9. The first pixel and the second pixel each further include a first switch that is closed when set to the read pixel and a second switch that is closed when set to the reference pixel, respectively. The event detection device according to claim 3.
10. The event detection device according to claim 9, further comprising a quantization unit that outputs a comparison result of comparing a signal output via the first switch with a predetermined threshold value as event data indicating the occurrence of the event. ..
11. The event detection device according to claim 10, further comprising a memory unit for storing the output from the quantization unit.
12. The event detection device according to claim 11, wherein the memory unit includes a first memory for storing the result compared with the first threshold value and a second memory for storing the result compared with the second threshold value. ..
13. A first quantization unit that outputs a comparison result comparing the signal output via the first switch and the first threshold value as event data indicating the occurrence of the event, and the first quantization unit.
    The ninth aspect of the present invention further includes a second quantization unit that outputs a comparison result comparing the signal output via the first switch and the second threshold value as event data indicating the occurrence of the event. The event detector described.
14. The reference pixels are connected and
    The event detection device according to claim 3, wherein a transistor included in the reference pixel and forming a current mirror circuit included in the differential amplifier circuit is connected.
15. The first pixel includes a first memory for storing event data representing the occurrence of the event.
    The second pixel includes a second memory for storing event data representing the occurrence of the event.
    The event detection device according to claim 2, wherein the writing to the first memory and the writing to the second memory are performed at different timings.
16. The first pixel includes a first quantization unit that compares an output from the differential amplifier circuit with a predetermined threshold value.
    The second pixel includes a second quantization unit that compares the output from the differential amplifier circuit with a predetermined threshold value.
    The first memory stores the output from the first quantization unit, and stores the output from the first quantization unit.
    The event detection device according to claim 15, wherein the second memory stores an output from the second quantization unit.
17. A quantization unit for comparing the output from the differential amplifier circuit with a predetermined threshold value is further provided.
    The first transistor and the second transistor constituting the current mirror circuit included in the differential amplifier circuit, and the quantization unit are pixel array units in which the first pixel and the second pixel are arranged. The event detection device according to claim 2, which is arranged outside.
18. A first capacitor to which the first threshold signal is supplied and a second capacitor to which the second threshold signal is supplied are further provided.
    The event detection device according to claim 1, wherein the first capacitor and the second capacitor are connected between a photoelectric conversion element and a transistor constituting a differential amplifier circuit.
19. The event detection device according to claim 18, wherein the first threshold signal and the second threshold signal are supplied to a reference pixel that supplies a reference signal to the differential amplifier circuit.
20. When the comparison result between the output from the differential amplifier circuit and the first threshold value is detected as the event, both the first threshold value signal and the second threshold value signal are H-level signals.
    When the comparison result between the output from the differential amplifier circuit and the second threshold value is detected as the event, the first threshold value signal and the second threshold value signal are both L-level signals. 19. The event detection device according to 19.

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