WO2022134721A1 - Procédé et appareil de recherche de cellule rapide 5g sur la base d'une synchronisation de liaison descendante et d'une combinaison de bits souples - Google Patents

Procédé et appareil de recherche de cellule rapide 5g sur la base d'une synchronisation de liaison descendante et d'une combinaison de bits souples Download PDF

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WO2022134721A1
WO2022134721A1 PCT/CN2021/121707 CN2021121707W WO2022134721A1 WO 2022134721 A1 WO2022134721 A1 WO 2022134721A1 CN 2021121707 W CN2021121707 W CN 2021121707W WO 2022134721 A1 WO2022134721 A1 WO 2022134721A1
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domain data
data
synchronization signal
frequency
soft
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PCT/CN2021/121707
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English (en)
Chinese (zh)
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刘鹏军
常越
田炜
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浪潮软件科技有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J11/00—Orthogonal multiplex systems, e.g. using WALSH codes
    • H04J11/0069—Cell search, i.e. determining cell identity [cell-ID]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J11/00—Orthogonal multiplex systems, e.g. using WALSH codes
    • H04J11/0023—Interference mitigation or co-ordination
    • H04J11/005—Interference mitigation or co-ordination of intercell interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J11/00—Orthogonal multiplex systems, e.g. using WALSH codes
    • H04J2011/0096—Network synchronisation

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  • the present invention relates to the technical field of 5G physical layer, and in particular, to a cell search method and device for 5G fast downlink synchronization and soft bit combining.
  • the configuration of 5G wireless system parameters is an important parameter that affects system performance and system indicators.
  • the Physical Broadcast Channel (PBCH) and SSB (SS/PBCH block) in the 5G system carry synchronization information and system information for terminal access. , including the Primary Synchronization Signal (PSS), the Secondary Synchronization Signal (SSS), and the Master Information Block (MIB).
  • PSS Primary Synchronization Signal
  • SSS Secondary Synchronization Signal
  • MIB Master Information Block
  • the flexible time-frequency domain configuration of 5G SSB is suitable for applications in more vertical industries, but because the 5G frequency band is higher than Long Term Evolution (LTE), network coverage and inter-cell interference problems follow.
  • LTE Long Term Evolution
  • the cell search process of the terminal mainly includes three parts: primary synchronization signal search, secondary synchronization signal search and physical broadcast channel detection.
  • the terminal can obtain the most basic information required to access the 5G cell by demodulating the signal transmitted on the PBCH, including the transmission position of MIB and Remaining Minimum System Information (RMSI).
  • the terminal obtains the physical cell ID (Physical Cell ID, PCI), frequency synchronization and downlink time synchronization (including radio frame timing, time slot timing and symbol timing) of the cell through cell search.
  • the present invention provides a cell search method and device for 5G fast downlink synchronization and soft bit combining, which can improve the signal-to-noise ratio of PBCH channels in the scenario of long-distance coverage and large interference.
  • the present invention provides a 5G fast downlink synchronization and soft bit combining cell search method, comprising the following steps:
  • the frequency domain data of the secondary synchronization signal is obtained, and the sliding correlation operation is performed on the frequency domain data of the secondary synchronization signal to obtain the sliding maximum correlation value of the frequency domain data of the secondary synchronization signal and the corresponding second sequence number, and obtaining a physical cell identity based on the first sequence number and the second sequence number;
  • the physical broadcast channel is detected to obtain the main information block information; wherein, the detection of the physical broadcast channel includes the first polar code decoding and after the first polar code decoding fails
  • the second polar code decoding is performed after combining the same soft bits.
  • the first position of the time domain data of the preset time length after frequency shifting and the The first serial number corresponding to the first position specifically includes the following steps:
  • the historical frame header is a valid value, obtain the relative position of the maximum peak value of the primary synchronization signal that was successfully synchronized last time in the time domain data of the preset time length according to the frame header information of the historical frame header;
  • Low-pass filtering and sliding correlation operation are performed on the time-domain data of the preset time length after frequency shifting in the form of time-domain data of two symbol lengths adjacent to the maximum peak relative position of the primary synchronization signal, to obtain the The first position and the corresponding first sequence number; wherein, the first position is the position of the maximum correlation value of the primary synchronization signal in the time domain data of the preset time length.
  • the relative position of the maximum peak value of the primary synchronization signal for the time domain data of the preset time length after frequency shifting is adjacent to two symbols
  • Low-pass filtering and sliding correlation operation are performed by means of time-domain data of the length to obtain the first position and the corresponding first sequence number, which specifically includes the following steps:
  • Low-pass filtering is performed on the time domain data of the preset time length after frequency shifting with the length data of two adjacent symbols at the relative position of the maximum peak value of the main synchronization signal, and traversing the local sequence of the main synchronization signal and the adjacent two symbols. Perform a sliding correlation operation on the filtered time domain data of the time domain data of the symbol length to obtain the sliding correlation value of the main synchronization signal;
  • the maximum value search is performed on the sliding correlation value of the primary synchronization signal to obtain the sliding correlation maximum value of the primary synchronization signal and its second position in the time domain data of two adjacent symbol lengths. According to the second position and the adjacent The position of the time domain data of two symbol lengths in the time domain data of the preset time length is to obtain the first position and the corresponding first sequence number.
  • the first position of the time domain data of the preset time length after frequency shifting and the The first serial number corresponding to the first position further includes the following steps:
  • the maximum value search is performed on the sliding correlation value of the primary synchronization signal to obtain the first position and the corresponding first sequence number.
  • the frequency domain data of the secondary synchronization signal is obtained according to the first position, and a sliding correlation operation is performed on the frequency domain data of the secondary synchronization signal to obtain the secondary synchronization
  • the sliding maximum correlation value of the frequency domain data of the signal and the corresponding second sequence number, and based on the first sequence number and the second sequence number, the physical cell identifier is obtained, which specifically includes the following steps:
  • the physical broadcast channel is detected according to the physical cell identifier to obtain the main information block information, which specifically includes the following steps:
  • a descrambling sequence is calculated according to the lower 3 bits and the lower 2 bits of the frame number, and the first decoding data is descrambled once to obtain the first descrambling data, and de-interleaving the first descrambled data to extract main information block information;
  • Detect the soft merging flag bit if the soft merging flag bit is 1, start the soft merging process, traverse the descrambling sequence to descramble the LLRs, accumulate the descrambled LLRs into the corresponding LLRbuffer, and perform operations on the merged corresponding LLRbuffer.
  • the polar code decoding for the second time if the polar code decoding for the second time is successful, a descrambling sequence is calculated according to the lower 3 bits and the lower 2 bits of the frame number, and the second decoding data is performed. One descrambling is performed to obtain the second descrambled data, and the second descrambled data is deinterleaved to extract the main information block information.
  • the physical broadcast channel is detected according to the physical cell identifier to obtain the main information block information, further comprising the following steps:
  • the soft combining flag bit is set to 1, and the rate matching data is stored in LLRData1.
  • the physical broadcast channel is detected according to the physical cell identifier to obtain the main information block information, further comprising the following steps:
  • the second polar code decoding succeeds and fails, continue to traverse the descrambling sequence once until all the decoding is performed with the complete descrambling sequence and the polar code.
  • the physical broadcast channel is detected according to the physical cell identifier to obtain the main information block information, further comprising the following steps:
  • the soft combining flag is 0, the synchronization is exited and the main information block information code stream is reported to the media intervention control layer and the synchronization history frame header is updated.
  • the present invention also provides a 5G fast downlink synchronization and soft bit combining cell search device, including:
  • a frequency-shifting module for acquiring time-domain data and storing it in a buffer with a preset time length, performing frequency-shifting processing on the time-domain data, and moving the data to near zero frequency;
  • a first acquisition module configured to acquire, based on the validity of the historical frame header, the first position of the time domain data of the preset time length after frequency shifting and the first sequence number corresponding to the first position;
  • the second acquisition module acquires the frequency domain data of the secondary synchronization signal according to the first position, and performs a sliding correlation operation on the frequency domain data of the secondary synchronization signal to obtain the sliding maximum correlation value of the frequency domain data of the secondary synchronization signal and the corresponding first two serial numbers, and based on the first serial number and the second serial number, a physical cell identity is obtained;
  • a detection module configured to detect the physical broadcast channel according to the physical cell identifier to obtain main information block information; wherein, the detection of the physical broadcast channel includes the first polar code decoding and the first polar code After the code decoding fails, the same soft bits are combined for the second polar code decoding.
  • the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, when the processor executes the program, the 5G fast downlink as described in any of the above is implemented. Synchronization and soft bits combine steps of a cell search method.
  • the present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, realizes the 5G fast downlink synchronization and soft-bit combining cell search method described in any of the above. step.
  • the present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of any of the above-mentioned 5G fast downlink synchronization and soft-bit combining cell search methods.
  • the 5G fast downlink synchronization and soft bit combining cell search method and device provided by the present invention can quickly complete the initial cell search based on the historical frame header position in the downlink synchronization process, and effectively improve the cell PSS peak search efficiency.
  • the initial synchronization 20ms time domain data PSS search requires sliding correlation calculation of 560 OFDM symbols, but the 5G fast downlink synchronization and soft bit combining cell search method and device provided by the present invention only needs to process 2 symbols to perform PSS search based on the historical frame header position.
  • FIG. 1 is a schematic flowchart of a 5G fast downlink synchronization and soft bit combining cell search method provided by the present invention
  • FIG. 2 is a schematic diagram of obtaining PSS peak value based on historical frame header position sliding correlation operation in the 5G fast downlink synchronization and soft bit combining cell search method provided by the present invention
  • FIG. 3 is a schematic diagram of a merged flow diagram of MIB0 and scrambling sequence SCR0 assuming the first 20ms received in the 5G fast downlink synchronization and soft-bit combining cell search method provided by the present invention
  • FIG. 4 is a schematic diagram of a merged flow diagram of MIB0 and scrambling sequence SCR1 assuming the first 20ms received in the 5G fast downlink synchronization and soft-bit combining cell search method provided by the present invention
  • FIG. 5 is a schematic diagram of a merged flow diagram of MIB0 and scrambling sequence SCR2 assuming that the first 20ms is received in the 5G fast downlink synchronization and soft-bit merging cell search method provided by the present invention
  • FIG. 6 is a schematic diagram of a merged flow diagram of MIB0 and scrambling sequence SCR3 assuming that the first 20ms is received in the 5G fast downlink synchronization and soft-bit merging cell search method provided by the present invention
  • FIG. 7 is a schematic structural diagram of an interpretable strategy game multi-player style evaluation device provided by the present invention.
  • FIG. 8 is a schematic structural diagram of an electronic device provided by the present invention.
  • the descrambling data appearing in the text is the soft bit information, and the soft bit is also called the maximum log-likelihood ratio Log-Likelihood Ratio , referred to as LLR.
  • the PSS search of the terminal determines the time-frequency domain resource positions of other symbols of all SSBs, and the PBCH detection determines the demodulation performance of the physical broadcast channel. Therefore, for the 5G weak coverage and high interference scenarios, the 5G fast downlink synchronization and soft bit combining cell search method and device provided by the present invention aim to improve and optimize from the above two points.
  • the 5G fast downlink synchronization and soft bit combining cell search method of the present invention is described below with reference to FIG. 1 , and the method includes the following steps:
  • the terminal receives the time domain data, and stores the time domain data in a double-rate synchronous dynamic random access memory (Double Data Rate, DDR) buffer of a digital signal processor (Digital Signal Process, DSP) in a pipelined form, each The buffer stores the time-domain data of a preset time length, and calls the Field-Programmable Gate Array (FPGA) or accelerator to perform frequency-shift processing on the time-domain data, and moves the time-domain data to the vicinity of zero frequency for the following Prepare for low pass filtering.
  • DDR double-rate synchronous dynamic random access memory
  • DSP Digital Signal Process
  • step S100 the preset time is 20ms, since the number of fast Fourier transform points of each symbol is fixed, and the number of symbols of 20ms data under each subcarrier interval is fixed, so the total number of sampling points of 20ms time domain data is fixed, marked as 20msTimeDataLen , the time domain data of the preset time length is TimeData20ms.
  • TimeData20ms of the preset time length read the time-domain data of the remaining three PBCH symbols of the SSB according to the first position PssMaxPos, perform fast Fourier transform processing, and obtain these three Frequency domain data PBCHFreData of PBCH symbols.
  • the 5G fast downlink synchronization and soft bit combining cell search method provided by the present invention can quickly complete the initial cell search based on the historical frame header position in the downlink synchronization process, effectively improve the cell PSS peak search efficiency, compared with the initial synchronization in the traditional method.
  • 20ms time domain data PSS search requires sliding correlation calculation of 560 OFDM symbols, but the 5G fast downlink synchronization and soft bit combining cell search method and device provided by the present invention only needs to process 2 symbols to perform PSS search based on historical frame header positions; At the same time, in the process of detecting PBCH, after a decoding failure, the same soft bits are combined and then decoded again, thereby improving the signal-to-noise ratio of the PBCH channel in the scenario of long-distance coverage and large interference.
  • Step S200 specifically includes the following steps:
  • step S210 it is necessary to judge the validity of the historical frame header in the system.
  • the goal is to get the first position PssMaxPos.
  • the historical frame header will be saved in the shared memory of the system after the synchronization is successful, and it will be updated every time the synchronization is successful.
  • After the terminal is powered on it is initialized to an invalid value, that is, the first synchronization when the terminal is powered on cannot be synchronized based on the historical frame header.
  • the historical frame header information should also be changed to an invalid value.
  • step S210 the frame header information of 20ms will be saved after the system downlink synchronization is successful, that is, a 20ms frame header is calculated by the relative position of the maximum peak position of the successfully synchronized PSS at 20ms.
  • the maximum peak relative position HistoryPSSMaxPos of the PSS that has been successfully synchronized last time in the time domain data TimeData20ms of the preset time length can be calculated, and then start to search for the PSS peak.
  • Step S230 specifically includes:
  • the DSP performs low-pass filtering on the time domain data TimeData20ms of the preset time length after frequency shifting in the DDR buffer, and the time domain data of two symbol lengths adjacent to the relative position of the PSS maximum peak value, and traverses and uses three PSS local sequences and The filtered time domain data of the two symbol lengths are subjected to sliding correlation operation to obtain the sliding correlation value of the PSS, and the sliding correlation value of the PSS is stored in the corresponding memory CorBuffer1.
  • step S231 low-pass filtering is performed by taking HistoryPSSMaxPos as the center to read the length data of two symbols before and after, that is, the number of sampling points of two fast Fourier transform window lengths.
  • Step S200 further includes the following steps:
  • the DSP performs low-pass filtering on the time-domain data TimeData20ms of the preset time length after frequency shifting in the DDR buffer (one symbol is read at a time, that is, the number of sampling points with a fast Fourier transform window length), and traverses and uses
  • the three PSS local sequences perform sliding correlation operation with the filtered time domain data of the symbol to obtain the sliding correlation value of PSS, and access the sliding correlation value of PSS to the corresponding memory CorBuffer1 until the time domain data of preset time length TimeData20ms
  • Step S300 specifically includes the following steps:
  • TimeData20ms the first position PssMaxPos is shifted backward by an orthogonal frequency division multiplexing (Orthogonal Frequency Division Multiplexing, OFDM) symbol data, and the time domain data of the SSS symbol is taken out, and the fast Fourier transform is performed to obtain the SSS The frequency domain data of SSSFreData.
  • OFDM Orthogonal Frequency Division Multiplexing
  • the PCI can be calculated according to the protocol by using the second serial number NID1 and the first serial number NID2.
  • Step S400 specifically includes the following steps:
  • the demodulated data DeModuData traverses the descrambling sequence for secondary descrambling and the output is obtained.
  • the second descramble data DeScr2Data is performed, and the rate matching data DeRMData is obtained by performing rate matching on the second descramble data DeScr2Data.
  • a descrambling sequence is calculated according to the lower 3 bits and the lower 2 bits of the frame number, and the decoded data DePolarData is descrambled once, the descrambled data DeScr1Data is output, and DeScr1Data is performed De-interleave and extract MIB information.
  • the second Polar decoding is performed on the combined corresponding LLRbuffer. If the second Polar decoding is successful, deinterleaving is performed to extract MIB information.
  • Step S400 also includes the following steps:
  • step S480 specifically, the descrambling sequence is traversed once in the order of SCR1, SCR2, SCR3 and SCR4, and LLRData1 is descrambled and accumulated into LLRBuf1-LLRBuf4 respectively.
  • step S400 is repeated until the L SSBIdx of all SSB configurations are traversed.
  • step S400 For each time domain data TimeData20ms, the above step S400 is repeated until the decoding is successful, and the process ends.
  • the time domain data TimeData of each preset time length is 20ms
  • the preset initial synchronization time is 20ms period
  • the PBCH repetition period is 80ms
  • the corresponding merging times are also different. If the corresponding primary and secondary scrambling sequences are all four, the maximum number of combinations is six. If the CRC check is still unsuccessful after more than six times of combined decoding, it is considered that the wireless channel environment is too poor during this period, exceeding the PBCH detection limit of the terminal, and the combined decoding process ends.
  • Figure 3 to Figure 4 show the corresponding relationship and process of accumulating and merging the corresponding LLRs into the Buffer after one descrambling.
  • the bold boxes in each figure represent the MIB and the scrambling/descrambling sequence information in the combined buffer to be decoded, and the 4 kinds of scrambling/descrambling sequences correspond one-to-one.
  • the goal of combined decoding is to combine and decode all the time. If the decoding fails all the time, the combined decoding attempt process ends until the MIB and adding/descrambling information shown in the bold box appear in the combined soft-bit buffer. . In the four cases listed in FIG. 3 to FIG.
  • the maximum number of times of merging attempts is 6, and the same MIB information can be traversed through all the corresponding adding/descrambling sequences. If the CRC check is still unsuccessful after 6 times of combined decoding, it is considered that the wireless channel environment is too bad during this period, exceeding the PBCH detection limit of the terminal, and the combined decoding process ends.
  • the 5G fast downlink synchronization and soft bit combination cell search apparatus described below and the 5G fast downlink synchronization and soft bit combination cell search method described above can be referred to each other correspondingly.
  • the 5G fast downlink synchronization and soft bit combining cell search device of the present invention is described below with reference to FIG. 7 , and the device includes:
  • the frequency shift module 100 is used for the terminal to receive the time domain data, store the time domain data in the DDR buffer of the DSP in the form of pipeline, each buffer saves the time domain data of a preset time length, and calls the FPGA or accelerator to synchronize the time
  • the domain data is frequency-shifted, and the time-domain data is moved to the vicinity of the zero frequency to prepare for the subsequent low-pass filtering.
  • the preset time is 20ms. Since the number of fast Fourier transform points of each symbol is fixed, and the number of symbols of 20ms data under each subcarrier interval is fixed, the total number of sampling points of 20ms time domain data is fixed, and the mark is 20msTimeDataLen, and the time domain data of the preset time length is TimeData20ms.
  • the first obtaining module 200 is configured to obtain, based on the validity of the historical frame header, the first position of the time domain data TimeData20ms of the preset time length after the frequency shift and the first sequence number corresponding to the first position.
  • the second obtaining module 300 is configured to obtain the frequency domain data SSSFreData of the SSS according to the first position PssMaxPos, and perform a sliding correlation operation on the frequency domain data of the SSS to obtain the sliding maximum correlation value of the frequency domain data SSSFreData of the SSS and the corresponding first Two serial numbers, and based on the first serial number and the second serial number, the PCI is obtained.
  • TimeData20ms of the preset time length read the time-domain data of the remaining three PBCH symbols of the SSB according to the first position PssMaxPos, perform fast Fourier transform processing, and obtain these three Frequency domain data PBCHFreData of PBCH symbols.
  • the detection module 400 is configured to detect the PBCH according to the PCI to obtain MIB information, and the detection of the PBCH includes the first polar code decoding and merging the same soft bits after the first polar code decoding fails After the second polar code decoding.
  • the 5G fast downlink synchronization and soft bit combining cell search method provided by the present invention can quickly complete the initial cell search based on the historical frame header position in the downlink synchronization process, effectively improve the cell PSS peak search efficiency, compared with the initial synchronization in the traditional method.
  • 20ms time domain data PSS search requires sliding correlation calculation of 560 OFDM symbols, but the 5G fast downlink synchronization and soft bit combining cell search method and device provided by the present invention only needs to process 2 symbols to perform PSS search based on historical frame header positions; At the same time, in the process of detecting PBCH, after a decoding failure, the same soft bits are combined and then decoded again, thereby improving the signal-to-noise ratio of the PBCH channel in the scenario of long-distance coverage and large interference.
  • the first acquisition module 200 specifically includes:
  • the first judging unit 210 judges whether the history frame header in the system is valid.
  • the validity of the historical frame header in the system needs to be judged.
  • the goal is to get the first position PssMaxPos.
  • the historical frame header will be saved in the shared memory of the system after the synchronization is successful, and it will be updated every time the synchronization is successful.
  • After the terminal is powered on it is initialized to an invalid value, that is, the first synchronization when the terminal is powered on cannot be synchronized based on the historical frame header.
  • the historical frame header information should also be changed to an invalid value.
  • the frame header information of 20ms will be saved after the system downlink synchronization is successful, that is, a 20ms frame header is calculated by the relative position of the maximum peak position of the successfully synchronized PSS at 20ms.
  • the first obtaining unit 220 is used to calculate the maximum peak relative position HistoryPSSMaxPos of the PSS that has been successfully synchronized last time in the time domain data TimeData20ms of the preset time length according to the frame header information of the historical frame header if the historical frame header is a valid value, and start searching for PSS peaks afterwards.
  • the second acquisition unit 230 is configured to perform low-pass filtering and sliding correlation operation on the time-domain data after the frequency shift with the maximum peak relative position of PSS HistoryPSSMaxPos and the time-domain data of two adjacent symbol lengths, to obtain the first position and the corresponding first serial number.
  • the second obtaining unit 230 specifically includes:
  • the first processing unit 231 is used for the DSP to perform low-pass filtering on the time-domain data TimeData20ms of the preset time length after frequency shifting in the DDR buffer with the time-domain data of two symbol lengths adjacent to the relative position of the PSS maximum peak value, and traverse and use the time domain data of two symbol lengths.
  • the three PSS local sequences and the filtered time domain data of the two symbol lengths perform sliding correlation operation to obtain the sliding correlation value of the PSS, and store the sliding correlation value of the PSS into the corresponding memory CorBuffer1.
  • low-pass filtering is performed by reading the length data of the two symbols before and after the HistoryPSSMaxPos as the center, that is, the number of sampling points with the length of two fast Fourier transform windows.
  • the second processing unit 232 is configured to perform maximum search on the sliding correlation value of the PSS in the memory CorBuffer1, and find the sliding correlation maximum value of the PSS and its second position TempPssPos in the time domain data of the two symbol lengths. , according to the second position TempPssPos and the position of these two symbols in the time domain data TimeData20ms of the preset time length, obtain the first position PssMaxPos in the time domain data TimeData20ms of the preset time length (this position is the PSS The position of the maximum correlation value in 20msTimeDataLen) and the corresponding first sequence number NID2.
  • the first obtaining module 200 further includes:
  • the third acquisition unit 240 is used for the DSP to perform low-frequency data TimeData20ms (one symbol is read at a time, that is, the number of sampling points with a fast Fourier transform window length) in the DDR buffer with a preset time length after frequency shifting. Pass filtering, and traverse the three PSS local sequences and the filtered time domain data of the symbol to perform sliding correlation operation to obtain the sliding correlation value of PSS, and access the sliding correlation value of PSS to the corresponding memory CorBuffer1 until the preset time.
  • the sliding correlation operation of all symbols in the length of time domain data TimeData20ms ends;
  • the fourth acquisition unit 250 is used to perform maximum search for the sliding correlation value of the PSS in the memory CorBuffer1, find the sliding correlation maximum value of the PSS and its first position PssMaxPos and the time domain data TimeData20ms of the preset time length. Corresponding serial number NID2.
  • the second obtaining module 300 specifically includes:
  • the third processing unit 310 is configured to offset backward one Orthogonal Frequency Division Multiplexing (OFDM) symbol data at the first position PssMaxPos in the time domain data TimeData20ms, and extract the time domain data of the SSS symbols, and perform The frequency domain data SSSFreData of SSS is obtained by fast Fourier transform processing.
  • OFDM Orthogonal Frequency Division Multiplexing
  • the fifth acquisition unit 320 is used to traverse the sliding correlation value of 336 kinds of SSS local sequences and the frequency domain data SSSFreData of the SSS, access the sliding correlation value of the frequency domain data SSSFreData of the SSS and find the maximum correlation value SssMaxValue of the SSS and the corresponding The second serial number NID1;
  • the sixth obtaining unit 330 is configured to calculate the PCI according to the protocol through the second serial number NID1 and the first serial number NID2.
  • the detection module 400 specifically includes:
  • the first detection unit 410 is configured to obtain frequency domain data of a demodulation reference signal (Demodulation Reference Signal, DMRS) according to the PCI, and traverse the SSBIdx to generate a DMRS local sequence.
  • a demodulation reference signal (Demodulation Reference Signal, DMRS) according to the PCI
  • the second detection unit 420 is configured to perform channel estimation on the DMRS frequency domain data and obtain an equalization factor, de-equalize the PBCH data through the equalization factor, and perform Quadrature Phase Shift Keying (QPSK) on the equalized output. Demodulate, and output the demodulated data DeModuData.
  • QPSK Quadrature Phase Shift Keying
  • the third detection unit 430 has four types of scrambling sequences used in the scrambling process, so the descrambling sequences also correspond to four types, which are SCR1, SCR2, SCR3 and SCR4 respectively.
  • the secondary descrambling output obtains the secondary descrambling data DeScr2Data, and the rate matching data DeScr2Data is descrambled for the secondary descrambling data DeScr2Data to obtain the rate matching data DeRMData.
  • the fourth detection unit 440 is used to perform the first polar code (Polar) decoding (first attempt) on the rate matching data DeRMData, the Polar decoding output is the decoded data DePolarData, and the cyclic redundancy check code (Cyclic Redundancy Check, CRC) check to determine whether the first Polar decoding is successful.
  • the first polar code Polar
  • the Polar decoding output is the decoded data DePolarData
  • the cyclic redundancy check code Cyclic Redundancy Check, CRC
  • the fifth detection unit 450 is configured to calculate a descrambling sequence according to the lower 3 bits and the lower 2 bits of the frame number if the first Polar decoding is successful, and descramble the decoded data DePolarData once, and output the descrambled data DeScr1Data, and de-interleave DeScr1Data to extract MIB information.
  • the detection module 400 also includes:
  • the seventh detection unit 410 is configured to set the soft combining flag LLRCombFlag to 1 if the first Polar decoding fails, and store the rate matching data DeRMData in LLRData1.
  • the eighth detection unit 480 is configured to continue traversing the descrambling sequence once if the second Polar decoding succeeds and fails until all the four descrambling sequences and Polar decoding are used up.
  • the eighth detection unit 480 specifically traverses the descrambling sequence once in the order of SCR1, SCR2, SCR3, and SCR4, and descrambles LLRData1 and accumulates them into LLRBuf1-LLRBuf4 respectively.
  • step S400 is repeated until the L SSBIdx of all SSB configurations are traversed.
  • the above-mentioned detection module 400 is repeated until the decoding is successful, and the process ends.
  • the time domain data TimeData of each preset time length is 20ms
  • the preset initial synchronization time is 20ms period
  • the PBCH repetition period is 80ms
  • the corresponding merging times are also different. If the corresponding primary and secondary scrambling sequences are all four, the maximum number of combinations is six. If the CRC check is still unsuccessful after more than six times of combined decoding, it is considered that the wireless channel environment is too poor during this period, exceeding the PBCH detection limit of the terminal, and the combined decoding process ends.
  • FIG. 8 illustrates a schematic diagram of the physical structure of an electronic device.
  • the electronic device may include: a processor (processor) 810, a communication interface (Communications Interface) 820, a memory (memory) 830 and a communication bus 840,
  • the processor 810 , the communication interface 820 , and the memory 830 communicate with each other through the communication bus 840 .
  • the processor 810 can invoke the logic instructions in the memory 830 to execute the 5G fast downlink synchronization and soft bit combining cell search method, and the method includes the following steps:
  • the frequency domain data of the secondary synchronization signal is obtained, and the sliding correlation operation is performed on the frequency domain data of the secondary synchronization signal to obtain the sliding maximum correlation value of the frequency domain data of the secondary synchronization signal and the corresponding second sequence number, and obtaining a physical cell identity based on the first sequence number and the second sequence number;
  • the physical broadcast channel is detected to obtain the main information block information; wherein, the detection of the physical broadcast channel includes the first polar code decoding and after the first polar code decoding fails
  • the second polar code decoding is performed after combining the same soft bits.
  • the above-mentioned logic instructions in the memory 830 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.
  • the technical solution of the present invention can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.
  • the aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .
  • the present invention also provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer can Execute the 5G fast downlink synchronization and soft bit combining cell search method provided by the above methods, and the method includes the following steps:
  • the frequency domain data of the secondary synchronization signal is obtained, and the sliding correlation operation is performed on the frequency domain data of the secondary synchronization signal to obtain the sliding maximum correlation value of the frequency domain data of the secondary synchronization signal and the corresponding second sequence number, and obtaining a physical cell identity based on the first sequence number and the second sequence number;
  • the physical broadcast channel is detected to obtain the main information block information; wherein, the detection of the physical broadcast channel includes the first polar code decoding and after the first polar code decoding fails
  • the second polar code decoding is performed after combining the same soft bits.
  • the present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored, and the computer program is implemented by a processor to execute the 5G fast downlink synchronization and soft bit combining provided by the above methods.
  • Cell search method the method includes the following steps:
  • the frequency domain data of the secondary synchronization signal is obtained, and the sliding correlation operation is performed on the frequency domain data of the secondary synchronization signal to obtain the sliding maximum correlation value of the frequency domain data of the secondary synchronization signal and the corresponding second sequence number, and obtaining a physical cell identity based on the first sequence number and the second sequence number;
  • the physical broadcast channel is detected to obtain the main information block information; wherein, the detection of the physical broadcast channel includes the first polar code decoding and after the first polar code decoding fails
  • the second polar code decoding is performed after combining the same soft bits.
  • the device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in One place, or it can be distributed over multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort.
  • each embodiment can be implemented by means of software plus a necessary general hardware platform, and certainly can also be implemented by hardware.
  • the above-mentioned technical solutions can be embodied in the form of software products in essence or the parts that make contributions to the prior art, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, magnetic A disc, an optical disc, etc., includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the methods described in various embodiments or some parts of the embodiments.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Databases & Information Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

La présente invention se rapporte au domaine technique des couches physiques 5G, et concerne un procédé et un appareil de recherche de cellule rapide 5G sur la base d'une synchronisation de liaison descendante et d'une combinaison de bits souples. Le procédé fait appel aux étapes suivantes : l'acquisition de données de domaine temporel et le stockage de celles-ci dans une mémoire tampon selon une durée prédéfinie, et la mise en œuvre d'un traitement de décalage de fréquence sur les données de domaine temporel, de façon à décaler les données pour qu'elles soient proches de la fréquence zéro ; sur la base de la validité d'un en-tête de trame historique, l'acquisition d'une première position des données de domaine temporel de la durée prédéfinie après un décalage de fréquence, et d'un premier numéro de séquence qui correspond à la première position ; l'acquisition de données de domaine fréquentiel d'un signal de synchronisation secondaire selon la première position, et la mise en œuvre d'une opération de corrélation de glissement sur les données de domaine fréquentiel du signal de synchronisation secondaire, de façon à obtenir la valeur de corrélation de glissement maximale des données de domaine fréquentiel du signal de synchronisation secondaire et un second numéro de séquence correspondant, et l'obtention d'un identifiant de cellule physique sur la base du premier numéro de séquence et du second numéro de séquence ; et la détection d'un canal de diffusion physique selon l'identifiant de cellule physique, de façon à obtenir des informations d'un bloc d'informations maître. Au moyen de la présente invention, le rapport signal sur bruit d'un PBCH peut être amélioré dans un scénario avec une couverture à longue distance et une interférence relativement importante.
PCT/CN2021/121707 2020-12-24 2021-09-29 Procédé et appareil de recherche de cellule rapide 5g sur la base d'une synchronisation de liaison descendante et d'une combinaison de bits souples WO2022134721A1 (fr)

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