WO2022134211A1 - 一种基于纳米电流通道的相变存储器 - Google Patents

一种基于纳米电流通道的相变存储器 Download PDF

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WO2022134211A1
WO2022134211A1 PCT/CN2021/070271 CN2021070271W WO2022134211A1 WO 2022134211 A1 WO2022134211 A1 WO 2022134211A1 CN 2021070271 W CN2021070271 W CN 2021070271W WO 2022134211 A1 WO2022134211 A1 WO 2022134211A1
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phase change
layer
nano
insulating
current channel
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French (fr)
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程晓敏
李瀚�
曾运韬
朱云来
刘香君
缪向水
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华中科技大学
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/828—Current flow limiting means within the switching material region, e.g. constrictions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H10N70/8616—Thermal insulation means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the invention belongs to the technical field of phase change memory, and more particularly, relates to a phase change memory based on nanometer current channels.
  • phase-change memory fabricated by utilizing the phase-change properties of materials has great potential in the semiconductor market.
  • phase change memory The basic principle of phase change memory is that phase change materials can be reversibly converted between crystalline and amorphous states, and use the huge difference in resistance between different states of the material to achieve "1" and "0" data storage.
  • the commonly used phase change materials are chalcogenide compounds. By controlling the amplitude and pulse width of the applied pulse current, the conversion of chalcogenide compounds between crystalline and amorphous states can be easily controlled. Fetch the binary data stored in the phase change memory.
  • Phase change memory has the advantages of fast read and write speed, high storage density, and compatibility with traditional CMOS technology.
  • phase change memory is positioned to replace DRAM. Although its speed has reached the order of DRAM speed, its power consumption needs to be further reduced, especially when further improving integration such as 3D storage. In some cases, reducing the power consumption of the phase-change memory cells is also beneficial to reducing thermal crosstalk between cells.
  • the phase change memory uses the thermal effect of the current to realize the change of the internal temperature of the device, so as to realize the reversible transformation of the phase change material between the crystalline state and the amorphous state
  • the write current of the PCRAM cell is proportional to the amount of material involved in the phase change , the smaller the cell size, the lower the write power consumption of the cell.
  • strictly controlling the heat generation efficiency of the write current increasing the current density of the phase change region, improving the heat generation efficiency of the phase change material, and reducing its melting temperature, etc.
  • heat dissipation conditions are also conducive to reducing Small device power consumption.
  • the methods for reducing the power consumption of phase-change memory cells are mainly divided into two categories, one is to use a new type of low-power phase change material with high heating efficiency and low melting temperature, and the other is to change the device structure.
  • the most direct way to change the device structure is to reduce the amount of phase change material and increase the current density by reducing the device size, such as confinement type phase change memory cell structure, etc., but this method requires higher process and process costs. High and difficult.
  • Other methods of changing the device structure such as edge contact type, asymmetric structure, ring electrode structure, adding two-dimensional material thermal resistance layer, etc.
  • the amount of material or the heat dissipation of the device can be reduced to reduce the write power consumption of the phase change unit, but these methods all require major changes to the device structure and process, and have problems of high process cost and difficulty.
  • the present invention provides a phase change memory based on nano-current channels, which aims to solve the problems of high process cost and difficulty in reducing the writing power consumption by changing the structure of the existing device, and
  • the current density in the contact area is increased, the heat generation efficiency is improved, and the heat utilization efficiency is improved, so that the phase change memory can reduce the writing power consumption without reducing the cell size and improving the process process.
  • the present invention provides a phase-change memory based on nano-current channels, comprising a nano-current channel layer arranged between a phase-change layer and an electrode layer, and the nano-current channel layer is an insulating material containing metal nano-crystal grains running through the film thickness of the layer.
  • the thermal insulation layer, the metal nanocrystal grains directly connect the electrode layer and the phase change layer, the current only reaches the phase change layer from the electrode layer through the nano-current channel formed by the metal nanocrystal grains, and the phase change layer only passes through the metal nanocrystal grains.
  • Contact with the electrode layer effectively reduces the contact area between the phase change layer and the electrode layer, improves the utilization efficiency of electric heat in the phase change layer, and reduces the power consumption of the device.
  • the contact area between the phase change layer and the electrode layer is reduced, the local current density is increased, and the heat generation efficiency is improved; at the same time, the insulating material part of the nano-current channel layer can prevent heat It is dissipated from the phase change layer to the electrode layer and has a thermal resistance effect. Therefore, the addition of the nanocurrent channel layer can significantly reduce the power consumption of the phase change memory.
  • the nano-current channel layer is a thin film structure jointly formed by an insulating and heat-insulating material and metal nano-crystal grains embedded in the insulating and heat-insulating material, and the metal nano-crystal grains run through the layer to form a nano-current channel.
  • the phase change memory further includes: a first electrode layer, a second electrode layer and a phase change material layer; the first electrode layer is adjacent to the phase change material, the phase change material layer is adjacent to the nano current channel layer, and the second electrode layer The nanometer current channel layer is adjacent to the nanometer current channel layer;
  • the material of the metal nanocrystalline grains is at least one of Fe, Pt, W, Cu, Zn, Al, Ni, Ti, Au, Ag elemental metallic materials, or composed of elemental metallic materials Fe, Pt, W, Cu, Alloy material formed by any two or more of Zn, Al, Ni, Ti, Au, Ag, or elemental metal material Fe, Pt, W, Cu, Zn, Al, Ni, Ti, Au, Ag with good conductivity compound of.
  • the metal nanocrystal grains of the nanocurrent channel layer have higher electrical conductivity than the insulating and heat insulating material.
  • the insulating and heat-insulating material has low thermal conductivity
  • the insulating and heat-insulating material is silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, zinc oxide, tungsten oxide, titanium oxide, boron nitride and silicon carbide. any kind.
  • the thickness of the nano-current channel layer is 1 nm ⁇ 30 nm.
  • the size of the metal nanocrystal grains in the insulating layer is 1 nm ⁇ 30 nm, and the size of the metal nanocrystal grains in the direction perpendicular to the thin film is not less than the thickness of the nanometer current channel layer.
  • the phase change layer material layer includes a chalcogenide compound
  • the chalcogenide compound includes any one of S, Se and Te or an alloy compound formed with other non-chalcogenide materials, wherein the non-chalcogenide material includes Ge , one or more of Sb, Ga, Bi, In, Sn, Pb, Ag, N and O.
  • the phase change material layer includes GeTe, GeSb, Ge 2 Sb 2 Te 5 , Ge 1 Sb 2 Te 4 , Sb 2 Te 3 , AgInSbTe, and superlattice phase change materials or heterostructure phase change materials containing chalcogenide compounds Materials, including (GeTe)/(Sb 2 Te 3 ), (GeTe)/(Bi 2 Te 3 ), (Sb 2 Te 3 )/(TiTe 2 ), GeTe/Sb, (Ge-Sb-Te)/( Sb-Te) or (Ge-Sb-Te)/C.
  • the phase change material layer includes a compound formed by doping and modifying a chalcogenide compound, wherein the doping element includes at least one of C, N, O, Cu, Cr, Sc, and Ti.
  • phase change material layer includes a single element phase change material Sb or Te.
  • the thickness of the phase change material layer is 20 nm ⁇ 200 nm.
  • the material of the first electrode and the material of the second electrode include simple metals Au, Ta, Pt, Al, W, Ti, Cu, Ir and their metal alloys and metal compounds, such as TiW, TiN.
  • the thickness of the material of the first electrode and the material of the second electrode is 20 nm to 300 nm.
  • the present invention can break through the process limitation, further reduce the effective contact area between the electrode and the phase-change material under a looser process, and greatly improve the current density in the contact area. , improve the heat production efficiency; at the same time, the insulating material with low thermal conductivity in the nano-current channel layer can effectively reduce the heat loss and improve the heat utilization efficiency; with the reduction of the effective contact area, the volume of the phase change area is also reduced accordingly, and the phase change The total energy required is also lower, enabling the phase change memory to reduce write power consumption without reducing cell size or increasing process technology.
  • the present invention does not need to change the structure of the device too much, only needs to add It is only one nanometer current channel layer, and the preparation method of the nanometer current channel layer is also very simple, which is compatible with the preparation method of the phase change layer, and has the advantage of a simple process while greatly reducing the power consumption of the device.
  • FIG. 1 is a cross-sectional view of an exemplary structure of a conventional phase change memory
  • FIG. 2 is a cross-sectional view of an exemplary structure of a phase change memory with a nano-current channel layer according to Embodiment 1 of the present invention
  • Figures 3(a)-(i) respectively show the process flow of preparing a device structure containing nano-current channels in Example 3 of the present invention
  • Figure 4(a) is a TEM image of the nano-current channel layer containing Ag crystal grains (the material of the insulating part is SiO 2 ) made in Example 4 of the present invention;
  • Fig. 4(b) is the V-R relationship curve of the phase change memory device with the nano current channel layer containing Ag crystal grains made in Example 4 of the present invention and the phase change device with the same structure without the layer, wherein the applied voltage RESET pulse
  • the pulse width is 50ns;
  • Figure 5(a) is a TEM image of the nano-current channel layer containing Au crystal grains made in Example 5 of the present invention (the material of the insulating and heat insulating part is SiO 2 );
  • Figure 5(b) is the V-R relationship curve of the phase change memory device containing the Au nano-current channel layer and the phase change device of the same structure without the layer made in Example 5 of the present invention, wherein the pulse width of the applied voltage RESET pulse is 50ns;
  • Figure 6 is the mean square displacement MSD of several atoms in Example 6 of the present invention running 4ps under the condition of 1200K in SiO 2 ;
  • FIG. 7 is the radial distribution function of several atoms in Example 6 of the present invention after running for 10 ps under the condition of 1200K in SiO 2 .
  • the present invention provides a phase-change memory based on nano-current channels, in particular, a nano-current channel layer is inserted between an electrode and a phase-change layer in the phase-change memory, and the nano-current channel layer is made of high-conductivity metal Or the metal compound grows and aggregates in the insulating material with low electrical conductivity and low thermal conductivity to form nanocrystalline grains, and the nanocrystalline grains can grow through the insulating layer under certain process conditions to form conductive nano-current channels.
  • the nano-current channel layer is used to limit the path of the current, so that the current flows from the high-conductivity nano-grains into the phase change layer when flowing through the layer, and the current is confined in the nano-current channel, which greatly reduces the size of the nano-scale conductive channel.
  • the contact area between the phase change layer and the electrode layer greatly increases the current density at the local contact portion, and improves the heat generation efficiency of the current in the phase change layer.
  • the part other than the high-conductivity nano-grains in the nano-current channel layer is an insulating material with low electrical conductivity and low thermal conductivity. The effect of improving the electrothermal utilization efficiency of the phase change layer is beneficial to further reduce the writing power consumption of the device.
  • the structure of a phase change memory using nano-current channels provided by the present invention sequentially includes:
  • Nano-current channel layer the nano-current channel layer is adjacent to the phase change material, and is an insulating layer monolayer containing metal nano-grains throughout the entire layer;
  • the second electrode is adjacent to the nano-current channel layer.
  • the nano-current channel layer is a thin film structure jointly formed by an insulating and heat-insulating material and metal nano-crystal grains embedded in the insulating and heat-insulating material, and the metal nano-crystal grains run through the layer to form a nano-current channel.
  • the material of the metal nanocrystal grains includes metal element, metal compound and metal alloy.
  • the metal nanograin material is at least one of Fe, Pt, W, Cu, Zn, Al, Ni, Ti, Au, Ag elemental metallic materials, or is composed of elemental metallic materials Fe, Pt, W, Cu, Alloy material formed by any two or more of Zn, Al, Ni, Ti, Au, Ag, or elemental metal material Fe, Pt, W, Cu, Zn, Al, Ni, Ti, Au, Ag with good conductivity compound of.
  • the insulating material is at least one of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, zinc oxide, tungsten oxide, titanium oxide, boron nitride, and silicon carbide. Insulation materials need to have low thermal conductivity.
  • the thickness of the nano-current channel layer is 1 nm ⁇ 30 nm.
  • the size of the metal nanocrystal grains in the insulating layer is 1 nm to 30 nm, and the size of the metal nanocrystal grains in the direction perpendicular to the thin film is not less than the thickness of the nanometer current channel layer.
  • Phase change layer materials include chalcogenide compounds and single element phase change materials.
  • the chalcogenide compounds include alloy compounds formed by one of S, Se, Te and other non-chalcogenide materials, wherein the non-chalcogenide materials include Ge, Sb, Ga, Bi, In, Sn, Pb, Ag, One or more of N and O.
  • the chalcogenide compounds include GeTe, GeSb, Ge 2 Sb 2 Te 5 , Ge 1 Sb 2 Te 4 , Sb 2 Te 3 , and AgInSbTe.
  • the chalcogenide compound includes a compound formed by doping and modifying the above-mentioned alloy compound, wherein the doping element includes at least one of C, N, O, Cu, Cr, Sc, and Ti.
  • Phase change materials also include superlattice phase change materials or heterostructure phase change materials containing chalcogenide compounds, including (GeTe)/(Sb 2 Te 3 ), (GeTe)/(Bi 2 Te 3 ), (Sb 2 Te 3 )/(TiTe 2 ), GeTe/Sb, (Ge-Sb-Te)/(Sb-Te), (Ge-Sb-Te)/C.
  • the phase change layer material also includes a single element phase change material, such as Sb or Te.
  • the present invention also provides a method for screening, matching and preparing nano-current channel layer materials. It is characterized in that the mean square displacement, formation energy, radial distribution function, etc. of metal atoms in insulating and insulating materials are calculated by first principles and molecular dynamics through VASP, Materials Studio, LAMMPS and other software for screening and insulating materials. Matching metal element and metal alloy.
  • the present invention provides a nano-current channel layer and a method for preparing a phase change memory containing the nano-current channel layer, characterized in that magnetron sputtering, chemical vapor deposition, plasma enhanced chemical Any one of vapor deposition method, physical vapor deposition method, laser pulse deposition method, evaporation method, electrochemical growth method, ion implantation method, molecular beam epitaxy method, atomic vapor deposition method and atomic layer deposition method.
  • the present invention also provides a preparation method of a phase change memory based on nano-current channels, the purpose of which is to increase the local current density without reducing the size of the device, so that the material can complete the phase change, so as to reduce the requirements of the device. purpose of power consumption.
  • phase change memory based on nano-current channels provided by the embodiments of the present invention, the following details are described in conjunction with specific embodiments as follows:
  • FIG. 1 a cross-sectional view of an exemplary structure of a conventional phase change memory is shown in FIG. 1 .
  • the bottom electrode 10 is formed on the SiO 2 substrate, and the material of the bottom electrode 10 is selected from W, Pt, Au, Al, Cu, Ti, Ta and other metal materials and conductive materials of their alloys.
  • the phase change material layer 30 is formed on the bottom electrode 10 , and the phase change layer material 30 includes a chalcogenide compound.
  • the chalcogenide compound includes an alloy compound formed by one of S, Se, Te and other non-chalcogenide materials, wherein the non-chalcogenide materials include Ge, Sb, Ga, Bi, In, Sn, Pb, Ag, N, One or more of O; preferably, the chalcogenide compounds include GeTe, GeSb, Ge 2 Sb 2 Te 5 , Ge 1 Sb 2 Te 4 , Sb 2 Te 3 , AgInSbTe; more preferably, the chalcogenide compounds include The above alloy compound is a compound formed by doping modification, wherein the doping element includes at least one of C, N, O, Cu, Cr, Sc, and Ti.
  • Phase change materials also include superlattice phase change materials or heterostructure phase change materials containing chalcogenide compounds, including (GeTe)/(Sb 2 Te 3 ), (GeTe)/(Bi 2 Te 3 ), (Sb 2 Te 3 )/(TiTe 2 ), GeTe/Sb, (Ge-Sb-Te)/(Sb-Te), (Ge-Sb-Te)/C.
  • the phase change layer material also includes single-element phase change materials, such as Sb and Te.
  • the upper electrode 40 is formed on the phase change material layer 30, and the material of the upper electrode 40 is selected from W, Pt, Au, Al, Cu, Ti, Ta and other metal materials and conductive materials of their alloys.
  • FIG. 2 a cross-sectional view of an exemplary structure of a phase change memory with a nano-current channel layer is shown in FIG. 2 .
  • the bottom electrode 10 is formed on the SiO 2 substrate, and the material of the bottom electrode 10 is selected from W, Pt, Au, Al, Cu, Ti, Ta and other metal materials and conductive materials of their alloys.
  • the nano-current channel 20 is formed on the bottom electrode 10.
  • the nano-current channel 20 is composed of insulating and heat-insulating material 22 and conductive nano-crystal grains 21 embedded in the middle of the insulating and heat-insulating material layer.
  • the thickness of the nano-current channel layer 20 is 1 nm ⁇ 30 nm.
  • the size of the conductive nanoparticles in the insulating layer is 1 nm ⁇ 30 nm, and the size of the conductive nanoparticles 21 in the direction perpendicular to the thin film is not less than the thickness of the nano current channel layer 20 .
  • the conductive nanocrystalline grains 21 have lower resistivity
  • the phase change material layer 30 is formed on the nano current channel 20
  • the phase change layer material 30 includes a chalcogenide compound.
  • the chalcogenide compound includes an alloy compound formed by one of S, Se, Te and other non-chalcogenide materials, wherein the non-chalcogenide materials include Ge, Sb, Ga, Bi, In, Sn, Pb, Ag, One or more of N and O; preferably, chalcogenide compounds include GeTe, GeSb, Ge 2 Sb 2 Te 5 , Ge 1 Sb 2 Te 4 , Sb 2 Te 3 , AgInSbTe; more preferably, chalcogenide compounds It includes compounds formed by doping and modifying the above alloy compounds, wherein the doping elements include at least one of C, N, O, Cu, Cr, Sc, and Ti.
  • Phase change materials also include superlattice phase change materials or heterostructure phase change materials containing chalcogenide compounds, including (GeTe)/(Sb 2 Te 3 ), (GeTe)/(Bi 2 Te 3 ), (Sb 2 Te 3 )/(TiTe 2 ), GeTe/Sb, (Ge-Sb-Te)/(Sb-Te), (Ge-Sb-Te)/C.
  • the phase-change layer material also includes single-element phase-change materials, such as Sb and Te.
  • the upper electrode 40 is formed on the phase change material layer 30, and the material of the upper electrode 40 is selected from W, Pt, Au, Al, Cu, Ti, Ta and other metal materials and conductive materials of their alloys.
  • the simplest three-layer phase-change memory cell structure is shown in the figure of Example 1. It is not limited to the three-layer structure, but can also be a T-type structure or a restricted-type structure; it can also be a phase-change memory cell with an additional gate tube. structure.
  • finite element simulation is performed on the writing process of the phase-change memory structure with the nano-current channel layer and the conventional phase-change memory structure.
  • This simulation uses the simplest three-layer phase-change memory cell structure in Example 1.
  • the material parameters used in the simulation are listed in Table 1 (the thermal and electrical parameters of the specific materials used in the finite element analysis).
  • the layer material is Ge 2 Sb 2 Te 5
  • the thickness of the upper and lower electrodes, the insulating layer, and the phase change layer are all 100 nm
  • the diameter of the unit device is 100 nm.
  • the thickness of the nano current channel layer is set. 5nm
  • the insulating part of this layer is made of SiO2 material
  • Ag is used as the nanocurrent channel
  • its diameter is 6nm.
  • a RESET current pulse with an amplitude of 60uA and a pulse width of 50ns was applied to the two structural models respectively.
  • the maximum temperature and current density maxima of the phase change layer after applying the same RESET current pulse in the two different structures were compared.
  • the results show that the highest temperature reached by the phase change layer in the cell containing the nanocurrent channel layer is 963K, the maximum current density is 5*10 9 A/m 2 , and the maximum current density is near the nanocurrent channel.
  • the highest temperature reached in the phase change layer is 845K.
  • the maximum current density is 9*10 8 A/m 2 , and the current density is relatively uniform in Ge 2 Sb 2 Te 5 .
  • the highest temperature that the device unit containing the nanocurrent channel layer structure can reach under the same current pulse is higher than that of the ordinary pinhole structure, which indicates that the nanocurrent channel layer structure can achieve lower power consumption under the same current pulse.
  • Complete the RESET operation of the phase change memory which has the advantage of low power consumption.
  • the manufacturing process of the T-type phase change memory cell containing the nano-current channel layer is as follows:
  • the SiO 2 /Si(100) substrate was selected, and the SiO 2 /Si(100) substrate was ultrasonicated in an acetone solution with a power of 40W for 15 minutes to clean the surface, dust particles and organic impurities, and then deionized water rinse;
  • the bottom electrode 10 is grown on the substrate 00 using a magnetron sputtering method, and the bottom electrode 10 is made of Pt material, and high-purity argon gas is introduced as the sputtering gas during preparation,
  • the sputtering gas pressure is 0.5 Pa
  • the power supply is 35 W
  • the thickness of the bottom electrode 10 is usually 20 nm to 300 nm.
  • a physical vapor deposition (PECVD) method is used to deposit an insulating layer 60 on the bottom electrode 50 layer.
  • the insulating layer 60 is SiO 2 and has a thickness of 100 nanometers.
  • a layer of photoresist 61 is evenly spread on the insulating layer 60 by using a glue spreader.
  • a photoresist mask 61 with circular apertures having a diameter of 250 nm is formed on the insulating layer 60 using an electron beam exposure system (EBL).
  • EBL electron beam exposure system
  • the insulating layer 60 is etched by plasma etching technology (ICP), since the part covered by the photoresist 61 is protected and will not be etched, but there is no photoresist The exposed part covered by 61 will be etched away until the bottom electrode 10 is exposed.
  • ICP plasma etching technology
  • the nano-current channel layer 20 is prepared by processes such as magnetron sputtering, ion implantation and annealing.
  • the metal nanocrystal grains 21 grow and aggregate in the nanocurrent channel layer 20 to form a conductive channel.
  • the insulating and heat insulating material in the nanometer current channel layer is selected from SiO 2
  • the metal conductive material is selected from Ag.
  • a square hole structure of 100 ⁇ m ⁇ 100 ⁇ m is overlaid on the small hole by using an ultraviolet photolithography system.
  • the square hole is aligned with the center of the circular small hole etched by ICP (not shown in the figure).
  • phase change material layer 30 is deposited in the square hole by magnetron sputtering, and the phase change material of the phase change material layer 30 includes a chalcogenide compound.
  • Chalcogenide compounds include S, Se, Te
  • the phase change layer material 30 includes chalcogenide compounds.
  • the chalcogenide compound includes an alloy compound formed by one of S, Se, Te and other non-chalcogenide materials, wherein the non-chalcogenide materials include Ge, Sb, Ga, Bi, In, Sn, Pb, Ag, N, One or more of O; preferably, the chalcogenide compound includes GeTe, GeSb, Ge 2 Sb 2 Te 5 , Ge 1 Sb 2 Te 4 , Sb 2 Te 3 , AgInSbTe; more preferably, the chalcogenide compound It includes compounds formed by doping and modifying the above alloy compounds, wherein the doping elements include at least one of C, N, O, Cu, Cr, Sc, and Ti.
  • Phase change materials also include superlattice phase change materials or heterostructure phase change materials containing chalcogenide compounds, including (GeTe)/(Sb 2 Te 3 ), (GeTe)/(Bi 2 Te 3 ), (Sb 2 Te 3 )/(TiTe 2 ), GeTe/Sb, (Ge-Sb-Te)/(Sb-Te), (Ge-Sb-Te)/C.
  • the phase-change layer material also includes single-element phase-change materials, such as Sb and Te.
  • One of the alloy compounds formed with other non-chalcogenide materials wherein the non-chalcogenide materials include Ge, Sb, Ga, Bi, In, Sn, Pb; the phase change material used in this embodiment is Ge 2 Sb 2 Te 5 example.
  • high-purity argon gas was introduced as sputtering gas, the sputtering pressure was 0.5pa, the power supply was 35W, the distance between the target and the substrate was 180mm, and the thickness of the phase change material layer 30 was 100nm.
  • the upper electrode layer 40 is deposited by magnetron sputtering, and the upper electrode layer is also made of Pt metal electrode material. After the completion, the photoresist of the ultraviolet lithography is removed by a lift-off process, and the final effect diagram is as shown in FIG. 3(i).
  • the microscopic test of the film containing the Ag nanocurrent channel layer was carried out, and a high-resolution image of SiO 2 -Ag was obtained.
  • the thickness of the nano current channel layer was 5nm.
  • image 4 (a) it can be clearly seen that there are clusters in the SiO
  • the cluster diameter is 10 nm, which can penetrate the SiO2 layer, and it can be seen from the composition analysis that the formed cluster is Ag. This indicates that Ag grains can aggregate and grow in SiO2 , making the nanocurrent channel layer conductive, and the current can be conducted from the lower electrode layer to the phase change layer through the Ag nanograins.
  • Figure 4(b) is the VR relationship curve of the device containing the above-mentioned Ag nano-current channel layer and the control group traditional structure device RESET in Example 4 of the present invention. Except for the above-mentioned 5 nm Ag nanocurrent channel layer, the two devices are identical in material and structure of other layers.
  • the materials of the phase change layer are all Ge 2 Sb 2 Te 5 (GST), and the thickness is 100 nm.
  • the diameter of the device unit is 250 nm
  • the insulating layer material is SiO 2 with a thickness of 100 nm
  • the upper and lower electrodes are made of TiN with a thickness of 100 nm.
  • the RESET test method of the device is as follows: The B1500A semiconductor tester is used to apply a RESET pulse with a pulse width of 50ns, a rising edge and a falling edge of 10ns respectively, and the voltage gradually increasing.
  • the results show that the RESET voltage of the device containing the Ag- SiO2 nanocurrent channel layer is 0.6V, and the required power consumption is 3.3* 10-5 J, while the RESET voltage of the traditional device structure is 1.6V, and the required power consumption is 2.1*10 -4 J, it can be concluded that the current channel layer containing Ag nanograins can effectively reduce the power consumption during the phase transition of the device.
  • the thickness of the nanometer current channel layer is 3nm, in image 5 (a ), it can be clearly seen that there are clusters in SiO 2 , the diameter of the clusters is 3 nm, and they can penetrate the SiO 2 layer. It can be seen from the composition analysis that the clusters formed are Au. This indicates that Au-containing can aggregate and grow in SiO2 , so that the nanocurrent channel layer is turned on, and the current can be conducted from the lower electrode layer to the phase change layer through the Au nanograins.
  • FIG. 5( b ) is the VR relationship curve of the device containing the above-mentioned Au nano-current channel layer and the conventional structure device RESET of the control group in Example 5 of the present invention. Except for the above-mentioned 5 nm-thick Au nanocurrent channel layer, the two devices are identical in material and structure of other layers.
  • the materials of the phase change layer are all Ge 2 Sb 2 Te 5 (GST), and the thickness is 100 nm.
  • the diameter of the device unit is 250 nm
  • the insulating layer material is SiO 2
  • the thickness is 100 nm.
  • the upper and lower electrodes are made of TiN with a thickness of 100 nm.
  • the RESET test method of the device is as follows: The B1500A semiconductor tester is used to apply a RESET pulse with a pulse width of 50ns, a rising edge and a falling edge of 10ns respectively, and the voltage gradually increasing.
  • the results show that the RESET voltage of the device containing the Au- SiO2 nanocurrent channel layer is 0.5V, and the required power dissipation is 1.25* 10-4 J, while the RESET voltage of the conventional device structure is 1.6V, and the required power dissipation is 2.1*10 -4 J, it can be concluded that the current channel layer containing Au nanograins can effectively reduce the power consumption during the phase transition of the device.
  • the insulating and heat-insulating material and the nano-current channel material in the nano-current channel are selected and matched to ensure that the selected metal conductive material can be used in the insulating and heat-insulating material. It grows easily and aggregates into grains.
  • the selection and matching methods of the two materials are as follows:
  • the insulating and heat-insulating material needs to have a large resistivity and a low thermal conductivity.
  • the large resistivity ensures that the current will not conduct in the entire layer, but will only enter the phase transition through the nano-current channel.
  • the low thermal conductivity can make the part of the layer other than the nano-current channel to have a heat preservation effect on the heat generation in the phase change layer, reduce the heat loss during the erasing and writing process, and further reduce the power consumption.
  • the choice of the material can also be determined according to the experimental conditions. In this embodiment, SiO 2 is selected as the insulating and heat insulating material in the nano-current channel layer.
  • MSD calculation of mean square displacement randomly add atoms of a certain nano-current channel material selected by the plan into amorphous SiO 2 , optimize its structure, run 4ps molecular dynamics calculation at 1200K, and count its Mean Square Displacement MSD.
  • the magnitude of the mean square displacement represents the ease of migration of the selected element atoms in the selected insulating and heat-insulating material (SiO 2 in this embodiment). The larger the mean square displacement value in the same time, the more vigorous the movement of atoms in the selected insulating material, that is, the easier it is to achieve migration.
  • Table 2 is the calculated formation energies of atoms of several nanocurrent channel materials in SiO2, and Figure 6 is the mean square displacement MSD of these material atoms in SiO2 at 1200K.
  • the formation energy of Ag and Au in SiO 2 is positive, which is easier to aggregate and grow than Al, Ti and W; the mean square displacement of Ag and Au in SiO 2 is higher than that of Al, W, The high Ti indicates that Ag and Au migrate more easily in SiO 2 than Al, W, and Ti.
  • the peaks corresponding to Au and Ag are higher, and the degree of aggregation is more obvious. Therefore, Ag and Au are more likely to form metal nanograins in SiO2 than other materials, thereby forming nanocurrent channels.
  • Embodiment 7 Preparation process method of nano-current channel layer 1
  • the method for preparing a nanometer current channel layer is characterized in that a sputtering method can be used, and the specific sputtering method is any one of the following four types: (1) Co-sputtering of a metal target and an insulating and heat insulating material target. (2) Alternate sputtering of metal targets and targets of insulating and heat-insulating materials. (3) The metal sheet is directly placed on the target of insulating and heat-insulating material for doping sputtering. (4) The insulating and heat-insulating material sheet is directly placed on the metal target for doping sputtering.
  • the SiO nanometer current channel layer containing Ag crystal grains is used as an example, and the nanometer current channel layer is sputtered by the method of magnetron sputtering.
  • the specific preparation method includes the following steps:
  • the annealing temperature and holding time in step (d) can be optimized according to the thickness ratio of the SiO 2 layer and the Ag layer. For example, the larger the thickness ratio, the higher the annealing temperature and the longer the holding time. Ag grows in SiO and agglomerates to form nano - metal grains throughout the thickness of the SiO layer.
  • Embodiment 8 Preparation process method 2 of nanometer current channel layer
  • the method for preparing a nanometer current channel layer is characterized in that a sputtering method can be used, and the specific sputtering method is any one of the following four types: (1) Co-sputtering of a metal target and an insulating and heat-insulating material target. (2) Alternate sputtering of the metal target and the target of insulating and heat-insulating material. (3) The metal sheet is directly placed on the insulating and heat-insulating material target for doping sputtering. (4) The insulating material sheet is directly placed on the metal target for doping sputtering.
  • the SiO 2 nano-current channel layer containing Au crystal grains is used as an example, and the nano-current channel layer 30 is sputtered by the method of magnetron sputtering.
  • the specific preparation method includes the following steps:
  • the annealing temperature and holding time in step (d) can be optimized according to the number of Au sheets (or the area of the Au sheet covering the etching ring). For example, the smaller the number of Au sheets (the smaller the area covering the etching ring), the more The higher the annealing temperature and the longer the holding time, the optimization goal is to make the metal Au grow in the SiO2 layer and agglomerate to form nano-metal grains throughout the thickness of the SiO2 layer.
  • the co-sputtering method in this embodiment can also replace the subsequent annealing process by increasing the temperature of the substrate during the sputtering process.
  • the increase of substrate temperature is beneficial to increase the migration kinetic energy of metal atoms, promote the aggregation of metal atoms and the growth of crystal grains, and the goal is also to form nano metal crystal grains through the thickness of the nano current channel layer.

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Abstract

本发明公开了一种基于纳米电流通道的相变存储器，使用的纳米电流通道层结构用以限制电流的路径，使得电流在流经该层时从高电导率纳米晶粒进入相变层，电流被限制在纳米电流通道中，该纳米级导电通道大大减小了相变层与电极层之间的接触面积，并极大地提高了局部接触部位的电流密度，提高了电流在相变层中的产热效率。同时，低电导率低热导率的绝缘绝热材料阻止了相变层中的热量向电极层散失，提高了相变层的电热利用效率。与采用更先进制程制作的尽可能小的相变单元相比，本发明能够突破工艺限制，进一步缩小电极与相变材料的有效接触面积，工艺简单，使得相变存储器能够轻松实现操作功耗降低。

Description

一种基于纳米电流通道的相变存储器 【技术领域】
本发明属于相变存储技术领域，更具体地，涉及一种基于纳米电流通道的相变存储器。
【背景技术】
随着信息时代的到来，存储器在生活中占据了越来越重要的地位，目前存储器的研究一直朝着高速度、低功耗、高稳定性的方向发展。其中，利用材料相变性能制作的相变存储器(PCRAM)在半导体市场中有着巨大的潜力。
相变存储器的基本原理在于：相变材料可以在晶态与非晶态之间进行可逆转换，利用材料的不同状态之间呈现的巨大阻值差异来实现“1”和“0”数据存储。通常使用的相变材料为硫系化合物，通过控制施加脉冲电流的幅值和脉宽就可以很轻松地控制硫系化合物在晶态和非晶态之间的转换，并通过对电阻的测量读取出存储在相变存储器中的二进制数据。相变存储器具有读写速度快、存储密度高、与传统CMOS工艺相兼容等优点。
在目前所有新型存储器技术中，相变存储器的定位是取代DRAM，虽然目前其速度已达到了DRAM速度的量级，但其功耗还需要进一步降低，特别是在进一步提高集成度如3D存储的情况下，降低相变存储单元的功耗也有利于减小单元间的热串扰。
由于相变存储器是利用电流的热效应实现器件内部温度的变化，从而实现相变材料在晶态与非晶态之间的可逆变换，因此PCRAM单元的写入电流与参与相变的材料量成比例，单元尺寸越小，单元的写入功耗越小。另外，在器件单元尺寸不变的情况下，严格控制写入电流的产热效率(提高相变区域的电流密度、改善相变材料的发热效率及降低其熔化温度等)和散热条件也有利于减小器件功耗。
目前减小相变存储单元功耗的方法主要分为两类，一类是采用新型高发热 效率、低熔化温度的低功耗相变材料，另一类是改变器件结构。其中，改变器件结构最直接的方法是通过减小器件尺寸来减少相变材料的量同时提高电流密度，如限制型相变存储单元结构等，但这种方法需要更高的工艺制程，工艺成本高、难度大。其他的改变器件结构的方法，如边接触型、非对称结构、环状电极结构、增加二维材料热阻层等，都是在不提高工艺制程的前提下，通过尽量减小参与相变的材料量或减少器件的散热来实现降低相变单元的写入功耗的，但这些方法都需要对器件结构和工艺进行大的改变，存在工艺成本较高、难度较大的问题。
【发明内容】
针对现有技术的缺陷，本发明提供了一种基于纳米电流通道的相变存储器，其目的在于解决通过改变现有器件的结构来降低写入功耗的工艺成本高、难度大的问题，并提高接触区域的电流密度，提高产热效率，提高热利用效率，使得相变存储器能够在不减小单元尺寸、不提高工艺制程的条件下减小写入功耗。
本发明提供了一种基于纳米电流通道的相变存储器，包括设置在相变层与电极层之间的纳米电流通道层，纳米电流通道层为含有贯穿该层膜厚的金属纳米晶粒的绝缘绝热层，金属纳米晶粒直接连通电极层和相变层，电流仅通过金属纳米晶粒所形成的纳米电流通道从所述电极层到达所述相变层，相变层仅通过金属纳米晶粒与电极层接触，有效减小了相变层与电极层之间的接触面积，提高了相变层中的电热利用效率，降低了器件功耗。
由于金属纳米晶粒所形成的纳米电流通道减小了相变层与电极层的接触面积，提高了局部电流密度，从而提高了产热效率；同时，纳米电流通道层的绝缘绝热材料部分可阻止热量从相变层向电极层散失，起到热阻效果。因此，纳米电流通道层的加入能显著降低相变存储器功耗。
其中，纳米电流通道层为由绝缘绝热材料和嵌入于绝缘绝热材料中的金属纳米晶粒共同形成的薄膜结构，且所述金属纳米晶粒贯穿该层形成纳米电流通道。
更进一步地，相变存储器还包括：第一电极层，第二电极层和相变材料层； 第一电极层与相变材料邻接，相变材料层与纳米电流通道层邻接，第二电极层与纳米电流通道层邻接；纳米电流通道层为含有贯穿整层的金属纳米晶粒的绝缘层单层。
其中，金属纳米晶粒的材料为Fe、Pt、W、Cu、Zn、Al、Ni、Ti、Au、Ag单质金属材料中的至少一种，或由单质金属材料Fe、Pt、W、Cu、Zn、Al、Ni、Ti、Au、Ag任意两种及以上形成的合金材料，或由单质金属材料Fe、Pt、W、Cu、Zn、Al、Ni、Ti、Au、Ag生成的导电性良好的化合物。
更进一步地，纳米电流通道层的金属纳米晶粒相比于绝缘绝热材料具有较高的电导率。
更进一步地，绝缘绝热材料具有较低的热导率，绝缘绝热材料为氧化硅、氮化硅、氧化铝、氮化铝、氧化锌、氧化钨、氧化钛、氮化硼和碳化硅中的任意一种。
更进一步地，纳米电流通道层的厚度为1nm～30nm。
更进一步地，金属纳米晶粒在绝缘层中的尺寸为1nm～30nm，所述金属纳米晶粒在垂直于薄膜方向上的尺寸不小于纳米电流通道层的厚度。
更进一步地，相变层材料层包括硫系化合物，所述硫系化合物包括S、Se和Te中任意一种或与其他非硫系材料形成的合金化合物，其中所述非硫系材料包括Ge、Sb、Ga、Bi、In、Sn、Pb、Ag、N和O中的一种或多种。
其中，相变材料层包括GeTe、GeSb、Ge 2Sb 2Te 5、Ge 1Sb 2Te 4，Sb 2Te 3、AgInSbTe，以及含硫系化合物的超晶格相变材料或异质结构相变材料，包括(GeTe)/(Sb 2Te 3)，(GeTe)/(Bi 2Te 3)，(Sb 2Te 3)/(TiTe 2)、GeTe/Sb、(Ge-Sb-Te)/(Sb-Te)或(Ge-Sb-Te)/C。
其中，相变材料层包括对硫系化合物掺杂改性形成的化合物，其中掺杂元素包括C，N，O，Cu，Cr，Sc，Ti中至少一种。
其中，相变材料层包括单元素相变材料Sb或Te。
更进一步地，相变材料层的厚度为20nm～200nm。
更进一步地，第一电极的材料和第二电极的材料包括金属单质Au、Ta、 Pt、Al、W、Ti、Cu、Ir及其金属合金和金属化合物，如TiW，TiN。
其中，第一电极的材料和第二电极的材料的厚度为20nm～300nm。
与采用更先进制程制作尽可能小的相变存储单元相比，本发明能够突破工艺限制，在较宽松的工艺制程下进一步缩小电极与相变材料的有效接触面积，大大提高接触区域的电流密度，提高产热效率；同时纳米电流通道层中低热导率的绝缘绝热材料能有效减少热量散失，提高热利用效率；随着有效接触面积的减小，相变区域的体积也相应减少，相变所需要的总能量也更低，从而使得相变存储器能够在不减小单元尺寸、不提高工艺制程的条件下减小写入功耗。
另外，与其他改变器件结构的方法(如边接触型、非对称结构、环状电极结构、增加二维材料热阻等)相比，本发明不需要太多地改变器件的结构，只需要加一层纳米电流通道层而已，而纳米电流通道层的制备方法也非常简单，与相变层的制备方法兼容，在大大降低器件功耗的同时，具有工艺简单的优势。
【附图说明】
图1为传统相变存储器示范性结构剖视图；
图2为本发明实施例1提供的具有纳米电流通道层相变存储器示范性结构剖视图；
图3(a)～(i)分别为本发明实施例3中表示含有纳米电流通道的器件结构制备工艺流程；
图4(a)为本发明实施例4中所做的含有Ag晶粒的纳米电流通道层(绝缘部分的材料为SiO 2)的TEM图像；
图4(b)为本发明实施例4中所做的含Ag晶粒的纳米电流通道层的相变存储器件与无该层的相同结构相变器件的V-R关系曲线，其中所施加电压RESET脉冲的脉宽为50ns；
图5(a)为本发明实施例5中所做的含有Au晶粒的纳米电流通道层(绝缘绝热部分的材料为SiO 2)的TEM图像；
图5(b)为本发明实施例5中所做的含Au纳米电流通道层的相变存储器件与无该层的相同结构相变器件的V-R关系曲线，其中所施加电压RESET脉冲 的脉宽为50ns；
图6为本发明实施例6中几种原子在SiO 2中1200K条件下运行4ps的均方位移MSD；
图7为本发明实施例6中几种原子在SiO 2中1200K条件下运行10ps后的径向分布函数。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明提供了一种基于纳米电流通道的相变存储器，具体是在相变存储器中的电极与相变层之间插入一层纳米电流通道层，该纳米电流通道层是由高电导率的金属或金属化合物在低电导率低热导率的绝缘绝热材料中生长聚集形成纳米晶粒，纳米晶粒在一定工艺条件下生长可以贯穿绝缘层而形成导电的纳米电流通道。该纳米电流通道层用以限制电流的路径，使得电流在流经该层时从高电导率纳米晶粒进入相变层，电流被限制在纳米电流通道中，该纳米级导电通道大大减小了相变层与电极层之间的接触面积，并极大地提高了局部接触部位的电流密度，提高了电流在相变层中的产热效率。同时，纳米电流通道层中高电导率纳米晶粒之外的部分为低电导率低热导率的绝缘绝热材料，其低热导率阻止了相变层中的热量向电极层散失，从而起到了热阻的效果，提高了相变层的电热利用效率，有利于进一步降低器件的写入功耗。
作为本发明的一个实施例，本发明提供的一种使用纳米电流通道的相变存储器的结构依次包括：
第一电极层，与相变材料邻接；
相变材料层；
纳米电流通道层，纳米电流通道层邻接相变材料，且是含有贯穿整层的金属纳米晶粒的绝缘层单层；
第二电极，与纳米电流通道层邻接。
其中，纳米电流通道层是由绝缘绝热材料和嵌入于绝缘绝热材料中的金属纳米晶粒共同形成的薄膜结构，金属纳米晶粒贯穿该层形成纳米电流通道。
其中，金属纳米晶粒的材料包含金属单质，金属化合物以及金属合金。
优选的，金属纳米晶粒材料为Fe、Pt、W、Cu、Zn、Al、Ni、Ti、Au、Ag单质金属材料中的至少一种，或由单质金属材料Fe、Pt、W、Cu、Zn、Al、Ni、Ti、Au、Ag任意两种及以上形成的合金材料，或由单质金属材料Fe、Pt、W、Cu、Zn、Al、Ni、Ti、Au、Ag生成的导电性良好的化合物。
绝缘绝热材料为氧化硅、氮化硅、氧化铝、氮化铝、氧化锌、氧化钨、氧化钛、氮化硼、碳化硅中的至少一种。绝缘绝热材料需要具有较低的热导率。
其中，纳米电流通道层的厚度在1nm～30nm。金属纳米晶粒在绝缘层中的尺寸为1nm～30nm，金属纳米晶粒在垂直于薄膜方向上的尺寸不小于纳米电流通道层的厚度。
相变层材料包括硫系化合物及单元素相变材料。
优选的，硫系化合物包括S、Se、Te其中一种与其他非硫系材料形成的合金化合物，其中所述非硫系材料包括Ge、Sb、Ga、Bi、In、Sn、Pb、Ag、N、O中的一种或多种。
优选的，硫系化合物包括GeTe、GeSb、Ge 2Sb 2Te 5、Ge 1Sb 2Te 4，Sb 2Te 3、AgInSbTe。
更优选的，硫系化合物包括对上述合金化合物掺杂改性形成的化合物，其中掺杂元素包括C，N，O，Cu，Cr，Sc，Ti中至少一种。
相变材料还包括含硫系化合物的超晶格相变材料或异质结构相变材料，包括(GeTe)/(Sb 2Te 3)，(GeTe)/(Bi 2Te 3)，(Sb 2Te 3)/(TiTe 2)、GeTe/Sb、(Ge-Sb-Te)/(Sb-Te)、(Ge-Sb-Te)/C。
相变层材料还包括单元素相变材料，如Sb或Te。
按照本发明的又一方面，本发明还提供了一种纳米电流通道层材料筛选、匹配及制备方法。其特征在于，通过VASP，Materials Studio，LAMMPS等软件通过第一性原理以及分子动力学计算金属原子在绝缘绝热材料中的均方位移， 形成能，径向分布函数等用以筛选与绝缘绝热材料相匹配的金属单质及金属合金。
按照本发明的再一方面，本发明提供一种纳米电流通道层及含有纳米电流通道层的相变存储器的制备方法，其特征在于，采用磁控溅射法、化学气相沉积法、等离子增强化学气相沉积法、物理气相沉积法、激光脉冲沉积法、蒸发法、电化学生长法、离子注入法、分子束外延法、原子气相沉积法及原子层沉积法中任意一种。
本发明还提供了一种基于纳米电流通道的相变存储器的制备方法，其目的在于不减小器件尺寸的情况下增大局部的电流密度从而使材料能够完成相变，达到减小器件所需功耗的目的。
为了更进一步的说明本发明实施例提供的基于纳米电流通道的相变存储器，以下结合具体实施例详述如下：
实施例1：
按照本发明的第1实施例，传统相变存储器示范性结构剖视图以图1示出。
底电极10形成于SiO 2衬底上，底电极10的材料选自W，Pt，Au，Al，Cu，Ti，Ta等金属材料及其合金的导电材料。相变材料层30形成于底电极10上，相变层材料30包括硫系化合物。优选的，硫系化合物包括S、Se、Te其中一种与其他非硫系材料形成的合金化合物，其中非硫系材料包括Ge、Sb、Ga、Bi、In、Sn、Pb、Ag、N、O中的一种或多种；优选的，硫系化合物包括GeTe、GeSb、Ge 2Sb 2Te 5、Ge 1Sb 2Te 4，Sb 2Te 3、AgInSbTe；更优选的，硫系化合物包括对上述合金化合物掺杂改性形成的化合物，其中掺杂元素包括C，N，O，Cu，Cr，Sc，Ti中至少一种。相变材料还包括含硫系化合物的超晶格相变材料或异质结构相变材料，包括(GeTe)/(Sb 2Te 3)，(GeTe)/(Bi 2Te 3)，(Sb 2Te 3)/(TiTe 2)、GeTe/Sb、(Ge-Sb-Te)/(Sb-Te)、(Ge-Sb-Te)/C。所述相变层材料还包括单元素相变材料，如Sb、Te。上电极40形成于相变材料层30上，上电极40的材料选自W，Pt，Au，Al，Cu，Ti，Ta等金属材料及其合金的导电材料。
按照本发明的第1实施例，具有纳米电流通道层相变存储器示范性结构剖 视图以图2示出。底电极10形成于SiO 2衬底上，底电极10的材料选自W，Pt，Au，Al，Cu，Ti，Ta等金属材料及其合金的导电材料。纳米电流通道20形成于底电极10上，纳米电流通道20由绝缘绝热材料22以及嵌于绝缘绝热材料层中间的导电纳米晶粒21构成，其中，纳米电流通道层20的厚度在1nm～30nm。导电纳米粒子在绝缘层中的尺寸为1nm～30nm，导电纳米粒子21在垂直于薄膜方向上的尺寸不小于纳米电流通道层20的厚度。与绝缘绝热材料22相比，导电纳米晶粒21具有更小的电阻率，相变材料层30形成于纳米电流通道20上，相变层材料30包括硫系化合物。优选的，所述硫系化合物包括S、Se、Te其中一种与其他非硫系材料形成的合金化合物，其中非硫系材料包括Ge、Sb、Ga、Bi、In、Sn、Pb、Ag、N、O中的一种或多种；优选的，硫系化合物包括GeTe、GeSb、Ge 2Sb 2Te 5、Ge 1Sb 2Te 4，Sb 2Te 3、AgInSbTe；更优选的，硫系化合物包括对上述合金化合物掺杂改性形成的化合物，其中掺杂元素包括C，N，O，Cu，Cr，Sc，Ti中至少一种。相变材料还包括含硫系化合物的超晶格相变材料或异质结构相变材料，包括(GeTe)/(Sb 2Te 3)，(GeTe)/(Bi 2Te 3)，(Sb 2Te 3)/(TiTe 2)、GeTe/Sb、(Ge-Sb-Te)/(Sb-Te)、(Ge-Sb-Te)/C。相变层材料还包括单元素相变材料，如Sb、Te。上电极40形成于相变材料层30上，上电极40的材料选自W，Pt，Au，Al，Cu，Ti，Ta等金属材料及其合金的导电材料。
实施例1图中所示为最简单的三层相变存储单元结构，并不仅仅限于三层结构，也可以是T型结构、限制型结构；还可以是附加选通管的相变存储器单元结构。
实施例2：
按照本发明的第2实施例，具有纳米电流通道层相变存储器结构以及传统的相变存储器结构写入过程进行有限元仿真。
该仿真采用实施例1中的最简单的三层相变存储单元结构。仿真使用的材料参数在表1(有限元分析使用的具体各种材料的热学与电学参数)中列出，两种单元结构的上下电极材料均为Pt，单元间绝缘材料为SiO 2以及相变层材料为Ge 2Sb 2Te 5，上下电极、绝缘层、相变层的厚度均为100nm，单元器件的直径为 100nm，在有纳米电流通道层的结构中，设定纳米电流通道层的厚度为5nm，该层绝缘绝热部分采用SiO 2材料，使用Ag作为纳米电流通道，其直径为6nm。分别对两种结构模型施加幅值为60uA，脉宽为50ns的RESET电流脉冲。
Figure PCTCN2021070271-appb-000001
表1
对比在两种不同结构中施加相同的RESET电流脉冲后相变层的最高温度和电流密度最大值。结果显示，含有纳米电流通道层的单元中相变层达到的最高温度为963K，电流密度最大为5*10 9A/m 2，且电流密度最大处在纳米电流通道附近。在普通单元结构中，相变层中达到的最高温度为845K。电流密度最大为9*10 8A/m 2，且电流密度在Ge 2Sb 2Te 5中分布较为均匀。由此分析得知，含有纳米电流通道层结构的器件单元在相同的电流脉冲作用下能够达到的最高温度高于普通的小孔结构，这表明纳米电流通道层结构能够在更低的功耗下完成相变存储器的RESET操作，具有低功耗优势。
实施例3：
按照本发明的第3实施例，含有纳米电流通道层的T型相变存储单元制备工艺流程如下：
(1)选取SiO 2/Si(100)基片，将SiO 2/Si(100)基片在丙酮溶液中用40W的功率超声15分钟，用于清洗表面、灰尘颗粒和有机杂质，再去离子水冲洗；
(2)将处理后的基片在乙醇溶液中用40w的功率超声15分钟，用去离子水冲洗，高纯N 2气吹干表面和背面，得到待溅射基片。
(3)如图3(a)所示，使用磁控溅射法将底电极10生长于衬底00上，该底电极10使用Pt材料，制备时通入高纯氩气作为溅射气体，溅射气压为0.5Pa，电源功率为35W，该底电极10厚度通常为20nm～300nm。
(4)如图3(b)所示，利用物理气相沉积(PECVD)方法在底电极50层 上沉积绝缘层60，绝缘层60为SiO 2，厚度为100纳米。
(5)如图3(c)所示，利用匀胶机在绝缘层60上均匀平铺一层光刻胶61。
(6)如图3(d)所示，利用电子束曝光系统(EBL)在绝缘层60上形成带250nm直径的圆形小孔的光刻胶掩膜61。
(7)如图3(e)所示，利用等离子体刻蚀技术(ICP)刻蚀绝缘层60，由于被光刻胶61覆盖的部分受到保护，不会被刻蚀，而没有光刻胶61覆盖的部分暴露在外会被刻蚀掉，直到露出底电极10。
(8)如图3(f)所示，使用磁控溅射，离子注入及退火等工艺制备纳米电流通道层20。其中金属纳米晶粒21在纳米电流通道层20中生长聚集，形成导电通道。本实施例中，纳米电流通道层中绝缘绝热材料选用SiO 2，金属导电材料选用Ag。
(9)利用去胶液去除光刻胶61，最终获得如图3(g)所示的最终效果。
(10)利用紫外光刻系统在小孔上套刻出100μm×100μm的方形孔结构。该方形孔与ICP刻蚀出的圆形小孔中心对准(图中未示出)。
(11)如图3(h)所示，在方形孔内利用磁控溅射沉积出相变材料层30，相变材料层30的相变材料包括硫系化合物。硫系化合物包括S、Se、Te相变层材料30包括硫系化合物。优选的，硫系化合物包括S、Se、Te其中一种与其他非硫系材料形成的合金化合物，其中非硫系材料包括Ge、Sb、Ga、Bi、In、Sn、Pb、Ag、N、O中的一种或多种；优选的，所述硫系化合物包括GeTe、GeSb、Ge 2Sb 2Te 5、Ge 1Sb 2Te 4，Sb 2Te 3、AgInSbTe；更优选的，硫系化合物包括对上述合金化合物掺杂改性形成的化合物，其中掺杂元素包括C，N，O，Cu，Cr，Sc，Ti中至少一种。相变材料还包括含硫系化合物的超晶格相变材料或异质结构相变材料，包括(GeTe)/(Sb 2Te 3)，(GeTe)/(Bi 2Te 3)，(Sb 2Te 3)/(TiTe 2)、GeTe/Sb、(Ge-Sb-Te)/(Sb-Te)、(Ge-Sb-Te)/C。相变层材料还包括单元素相变材料，如Sb、Te。其中一种与其他非硫系材料形成的合金化合物，其中非硫系材料包括Ge、Sb、Ga、Bi、In、Sn、Pb；本实施例使用的相变材料以Ge 2Sb 2Te 5为例。制备时通入高纯氩气作为溅射气体，溅射气压为0.5pa，电源功率为35W， 靶和基片的距离180mm，该相变材料层30的厚度为100nm。
(12)利用磁控溅射沉积上电极层40，上电极层同样为Pt金属电极材料。完成之后利用剥离工艺去除紫外光刻的光刻胶，最终的效果图如图3(i)所示的结构。
实施例4：
对含有Ag纳米电流通道层薄膜进行微观测试，得到SiO 2-Ag高分辨图像，纳米电流通道层的厚度为5nm，在图像4(a)中明显能够看到SiO 2中有团簇生成，团簇直径为10nm，能够贯穿SiO 2层，通过成分分析可以看出形成的团簇为Ag。这表明Ag晶粒能够在SiO 2中聚集生长，使得纳米电流通道层导通，电流可以通过Ag纳米晶粒从下电极层传导至相变层。
图4(b)为本发明的实施例4中含有上述Ag纳米电流通道层的器件和对照组传统结构器件RESET的V-R关系曲线。除了上述5nm的Ag纳米电流通道层外，两个器件在其它层的材料和结构上都完全相同。其中，相变层材料均为Ge 2Sb 2Te 5(GST)，厚度为100nm。器件单元直径为250nm，绝缘层材料为SiO 2，厚度为100nm，上下电极材料为TiN，厚度为100nm。
器件的RESET测试方法如下：通过B1500A半导体测试仪对两者分别施加脉宽为50ns，上升沿和下降沿分别为10ns，电压逐步增加的RESET脉冲。结果显示，含有Ag-SiO 2纳米电流通道层的器件的RESET电压为0.6V，所需的功耗为3.3*10 -5J，而传统器件结构RESET电压为1.6V，所需的功耗为2.1*10 -4J，两者对比可以得出含有Ag纳米晶粒的电流通道层能有效降低器件相变过程中所需的功耗。
实施例5：
改变纳米电流通道层中的金属材料，对含有Au纳米晶粒的电流通道层薄膜进行微观测试，得到SiO 2-Au高分辨透射电镜图像，纳米电流通道层的厚度为3nm，在图像5(a)中明显能够看到SiO 2中有团簇生成，团簇直径在3nm，能够贯穿SiO 2层，通过成分分析可以看出形成的团簇为Au。这表明含Au能够在SiO 2中聚集生长，使得纳米电流通道层导通，电流可以通过Au纳米晶粒从下电 极层传导至相变层。
图5(b)为本发明的实施例5中含有上述Au纳米电流通道层的器件和对照组传统结构器件RESET的V-R关系曲线。除了上述5nm厚的Au纳米电流通道层外，两个器件在其它层的材料和结构上都完全相同。其中，相变层材料均为Ge 2Sb 2Te 5(GST)，厚度为100nm。器件单元直径为250nm，绝缘层材料为SiO 2，厚度为100nm。上下电极材料为TiN，厚度为100nm。
器件的RESET测试方法如下：通过B1500A半导体测试仪对两者分别施加脉宽为50ns，上升沿和下降沿分别为10ns，电压逐步增加的RESET脉冲。结果显示，含有Au-SiO 2纳米电流通道层的器件的RESET电压为0.5V，所需的功耗为1.25*10 -4J，而传统器件结构RESET电压为1.6V，所需的功耗为2.1*10 -4J，两者对比可以得出含有Au纳米晶粒的电流通道层能有效降低器件相变过程中所需的功耗。
实施例6：
按照本发明的第6实施例，如图6和图7所示，对纳米电流通道中的绝缘绝热材料和纳米电流通道材料进行选择和匹配，以确保选定的金属导电材料能在绝缘绝热材料中很容易地生长并聚集成晶粒。两种材料的选择及匹配方法如下：
(1)首先选定绝缘绝热材料，绝缘绝热材料需要有较大的电阻率和较低的热导率，大电阻率保证电流不会在整层导通，只会通过纳米电流通道进入相变层，低热导率可以使得该层除纳米电流通道之外的部分对相变层内的产热起到保温的效果，减少擦写过程中的热量散失，进一步降低功耗。该材料的选择也可以根据实验条件确定。本实施例中选择SiO 2作为纳米电流通道层中的绝缘绝热材料。
(2)建立晶体SiO 2模型，使用VASP软件对晶体SiO 2模型升温至5000K，使其融化，再降温至300K运行2ps得到非晶SiO 2模型。
(3)形成能计算：在非晶SiO 2中掺入计划选择的某一种纳米电流通道材料的原子，对其进行结构优化，计算其结构能量，通过公式E f＝E nx@绝缘绝热材料-E 绝缘绝 热材料-nE x计算形成能，其中E nx@绝缘绝热材料表示n个原子在绝缘绝热材料(SiO 2)中的体系的总能量，E 绝缘绝热材料表示绝缘绝热材料(SiO 2)的能量，nE x表示n个掺入原子的总原子势。通常情况下，形成能为正表示选定的元素原子可以在选定的绝缘绝热材料(本实施例中为SiO 2)中生长并聚集成晶粒，正的形成能数值越大，表明越容易聚集成晶粒并形成纳米电流通道。
(4)均方位移MSD计算：在非晶SiO 2中随机掺入计划选择的某一种纳米电流通道材料的原子，对其进行结构优化，在1200K下运行4ps的分子动力学计算，统计其均方位移MSD。均方位移大小表示选定的元素原子在选定的绝缘绝热材料(本实施例中为SiO 2)中迁移的难易程度。在相同时间内均方位移数值越大，表明原子在选定的绝缘绝热材料中运动越剧烈，即越容易实现迁移。
(5)径向分布函数的计算：在非晶SiO 2中随机掺入计划一定比例(原子数之比，本实施例中为12％)的某一种纳米电流通道材料的原子，对其进行结构优化，在1200K下运行10ps的分子动力学计算，统计其掺入原子间的径向分布函数。径向分布函数的峰值的大小反应其聚集程度，峰值越大，表示原子在选定的绝缘绝热材料中聚集程度越高，越容易生长成核，并形成大的晶粒。
(6)综合考虑原子在SiO 2中的形成能和均方位移以及径向分布函数筛选出适合在SiO 2中生长聚集的材料。
表2是计算得到的几种纳米电流通道材料的原子在SiO 2中的形成能，图6是这些材料原子1200K时在SiO 2中的均方位移MSD。
Ag Au Al W Ti
0.198eV 2.536eV -4.548eV -5.731eV -5.670eV
表2
根据形成能对比可以看出，Ag和Au在SiO 2中的形成能为正，相比于Al、Ti和W更容易聚集生长；Ag、Au在SiO 2中的均方位移比Al、W、Ti高，说明Ag、Au相比于Al、W、Ti更容易在SiO 2中迁移；在图7径向分布函数中能够发现Au和Ag对应的峰值较高，聚集程度较为明显。因此，Ag、Au相比于其他材料更容易在SiO 2中形成金属纳米晶粒，进而形成纳米电流通道。
实施例7：纳米电流通道层的制备工艺方法1
纳米电流通道层制备方法，其特征在于，可以采用溅射法，具体溅射方式为以下四种中任意一种：(1)金属靶材与绝缘绝热材料靶材共溅射。(2)金属靶材与绝缘绝热材料靶材交替溅射。(3)将金属片直接放置在绝缘绝热材料靶材上进行掺杂溅射。(4)将绝缘绝热材料片直接放置在金属靶材上进行掺杂溅射。
本实施例以含Ag晶粒的SiO 2纳米电流通道层为例，使用磁控溅射的方法溅射纳米电流通道层，具体制备方法包括以下步骤：
(a)在溅射腔内放入SiO 2靶和Ag靶，并将真空度抽至10 -4Pa；
(b)使用高纯Ar气作为溅射气体，设定Ar气流稳定为10sccm，并将溅射气压调节至0.5pa，靶和基片的距离120mm；
(c)设定交流溅射电源功率为200W，接SiO 2靶位，溅射100s，生长2nmSiO 2后关闭交流电源，设定直流溅射电源功率为30W，接Ag靶位，溅射10s，生长1nmAg后关闭直流电源，再次打开交流电源溅射100sSiO 2，生长2nmSiO 2后关闭电源；
(d)将溅射得到的基片放入真空退火炉中，退火炉以15℃/min的速度升温至400℃，并在400℃下保温30min。使金属Ag在SiO 2中生长并团聚形成贯穿SiO 2层厚度的纳米金属晶粒，如图4(a)。
步骤(d)中的退火温度及保温时间，可以根据SiO 2层和Ag层的厚度比来优化，如厚度比越大，需要的退火温度越高、保温时间越长，优化的目标是使金属Ag在SiO 2中生长并团聚形成贯穿SiO 2层厚度的纳米金属晶粒。
实施例8：纳米电流通道层的制备工艺方法2
纳米电流通道层制备方法，其特征在于，可以采用溅射法，具体溅射方式为以下四种中任意一种：(1)金属靶材与绝缘绝热材料靶材共溅射。(2)金属靶材与绝缘绝热材料靶材交替溅射。(3)将金属片直接放置在绝缘绝热材料靶材上进行掺杂溅射。(4)将绝缘绝热材料片直接放置在金属靶材上进行掺杂溅射。
本实施例以含Au晶粒的SiO 2纳米电流通道层为例，使用磁控溅射的方法溅射纳米电流通道层30，具体制备方法包括以下步骤：
(a)在SiO 2靶材表面刻蚀环处放8片1cm*0.5cm大小的Au片，并将真空抽至10 -4Pa；
(b)使用高纯Ar气作为溅射气体，设定Ar气流稳定为10sccm，并将溅射气压调节至0.5Pa，靶和基片的距离120mm；
(c)设定交流溅射电源功率为200W，溅射200s；
(d)将溅射得到的基片放入真空退火炉中，退火炉以15℃/min的速度升温至400℃，并在400℃下保温30min。使金属Au在SiO 2层中生长并团聚形成贯穿SiO 2层厚度的纳米金属晶粒，如图5(a)。
步骤(d)中的退火温度及保温时间，可以根据Au片的数量(或Au片覆盖刻蚀环的面积大小)优化，如Au片数量越少(覆盖刻蚀环的面积越小)，需要的退火温度越高、保温时间越长，优化的目标是使金属Au在SiO 2层中生长并团聚形成贯穿SiO 2层厚度的纳米金属晶粒。
本实施例中的共溅射方法，也可以通过提高溅射过程中基片的温度来替代后续的退火工艺。基片温度的提高有利于增加金属原子的迁移动能，促进金属原子的聚集及其晶粒的生长，目标同样是形成贯穿纳米电流通道层厚度的纳米金属晶粒。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种基于纳米电流通道的相变存储器，其特征在于，包括设置在相变层与电极层之间的纳米电流通道层，所述纳米电流通道层为含有贯穿该层膜厚的金属纳米晶粒的绝缘绝热层，金属纳米晶粒直接连通电极层和相变层，电流仅通过金属纳米晶粒所形成的纳米电流通道从所述电极层到达所述相变层，相变层仅通过金属纳米晶粒与电极层接触，有效减小了相变层与电极层之间的接触面积，提高了相变层中的电热利用效率，降低了器件功耗。
  2. 如权利要求1所述的相变存储器，其特征在于，所述纳米电流通道层为由绝缘绝热材料和嵌入于绝缘绝热材料中的金属纳米晶粒共同形成的薄膜结构，且所述金属纳米晶粒贯穿该层形成纳米电流通道。
  3. 如权利要求1或2所述的相变存储器，其特征在于，所述相变存储器还包括：第一电极层，第二电极层和相变材料层；
    所述第一电极层与所述相变材料邻接，所述相变材料层与所述纳米电流通道层邻接，所述第二电极层与纳米电流通道层邻接；
    所述纳米电流通道层为含有贯穿整层的金属纳米晶粒的绝缘层单层。
  4. 如权利要求1-3任一项所述的相变存储器，其特征在于，所述金属纳米晶粒的材料为Fe、Pt、W、Cu、Zn、Al、Ni、Ti、Au、Ag单质金属材料中的至少一种，或由单质金属材料Fe、Pt、W、Cu、Zn、Al、Ni、Ti、Au、Ag任意两种及以上形成的合金材料，或由单质金属材料Fe、Pt、W、Cu、Zn、Al、Ni、Ti、Au、Ag生成的导电性良好的化合物。
  5. 如权利要求2-4任一项所述的相变存储器，其特征在于，所述纳米电流通道层的金属纳米晶粒相比于绝缘绝热材料具有较高的电导率。
  6. 如权利要求2-5任一项所述的相变存储器，其特征在于，所述绝缘绝热材料具有较低的热导率，所述绝缘绝热材料为氧化硅、氮化硅、氧化铝、氮化铝、氧化锌、氧化钨、氧化钛、氮化硼和碳化硅中的任意一种。
  7. 如权利要求1-6任一项所述的相变存储器，其特征在于，所述纳米电流 通道层的厚度为1nm～30nm。
  8. 如权利要求1-7任一项所述的相变存储器，其特征在于，所述金属纳米晶粒在绝缘层中的尺寸为1nm～30nm，所述金属纳米晶粒在垂直于薄膜方向上的尺寸不小于纳米电流通道层的厚度。
  9. 如权利要求3-8任一项所述的相变存储器，其特征在于，所述相变层材料层包括硫系化合物，所述硫系化合物包括S、Se和Te中任意一种或与其他非硫系材料形成的合金化合物，其中所述非硫系材料包括Ge、Sb、Ga、Bi、In、Sn、Pb、Ag、N和O中的一种或多种。
  10. 如权利要求3-8任一项所述的相变存储器，其特征在于，所述相变材料层包括GeTe、GeSb、Ge 2Sb 2Te 5、Ge 1Sb 2Te 4，Sb 2Te 3、AgInSbTe，以及含硫系化合物的超晶格相变材料或异质结构相变材料，包括(GeTe)/(Sb 2Te 3)，(GeTe)/(Bi 2Te 3)，(Sb 2Te 3)/(TiTe 2)、GeTe/Sb、(Ge-Sb-Te)/(Sb-Te)或(Ge-Sb-Te)/C。
  11. 如权利要求3-8任一项所述的相变存储器，其特征在于，所述相变材料层包括对硫系化合物掺杂改性形成的化合物，其中掺杂元素包括C，N，O，Cu，Cr，Sc，Ti中至少一种。
  12. 如权利要求3-8任一项所述的相变存储器，其特征在于，所述相变材料层包括单元素相变材料Sb或Te。
  13. 如权利要求3-12任一项所述的相变存储器，其特征在于，所述相变材料层的厚度为20nm～200nm。
  14. 如权利要求3-13任一项所述的相变存储器，其特征在于，所述第一电极的材料和所述第二电极的材料包括金属单质Au、Ta、Pt、Al、W、Ti、Cu、Ir及其金属合金和金属化合物，如TiW，TiN。
  15. 如权利要求3-14任一项所述的相变存储器，其特征在于，所述第一电极的材料和所述第二电极的材料的厚度为20nm～300nm。
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