WO2022134042A1 - 恒定摆率的信号驱动系统 - Google Patents

恒定摆率的信号驱动系统 Download PDF

Info

Publication number
WO2022134042A1
WO2022134042A1 PCT/CN2020/139546 CN2020139546W WO2022134042A1 WO 2022134042 A1 WO2022134042 A1 WO 2022134042A1 CN 2020139546 W CN2020139546 W CN 2020139546W WO 2022134042 A1 WO2022134042 A1 WO 2022134042A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
voltage
slew rate
output
driving system
Prior art date
Application number
PCT/CN2020/139546
Other languages
English (en)
French (fr)
Inventor
李智
赵建中
周玉梅
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to PCT/CN2020/139546 priority Critical patent/WO2022134042A1/zh
Publication of WO2022134042A1 publication Critical patent/WO2022134042A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

Definitions

  • the present disclosure relates to the technical field of circuit design, and in particular, to a signal driving system with a constant slew rate.
  • Low-speed digital interfaces in integrated circuits generally use high and low levels to represent the logic state of signals, such as TTL (transistor transistor logic) level, CMOS (Complementary Metal Oxide Semiconductor PMOS+NMOS) level, low-voltage TTL level, low-voltage CMOS level, etc. .
  • TTL transistor transistor logic
  • CMOS Complementary Metal Oxide Semiconductor PMOS+NMOS
  • TTL transistor logic
  • CMOS Complementary Metal Oxide Semiconductor PMOS+NMOS
  • Low-voltage TTL level low-voltage CMOS level
  • CMOS Complementary Metal Oxide Semiconductor PMOS+NMOS
  • the fluctuation of the output slew rate will also cause the signal transmission process.
  • the impedance in the circuit is discontinuous, resulting in electromagnetic interference, which will eventually cause the circuit function to fail or cause the entire system to fail to work normally. This phenomenon becomes more and more obvious with the decrease of the integrated circuit process size.
  • the present disclosure provides a signal driving system with a constant slew rate, comprising: a stepped voltage generating unit configured to provide multiple voltage signals with equal gradients; a multiplexer, an input terminal of which is connected to the stepped voltage generating unit to receiving a plurality of equidistant gradient voltage signals, and the other input terminal is connected to a control signal generating unit, and is configured to select multiple equidistant gradient voltage signals under the control of the control signal sent by the control signal generating unit
  • a voltage follower unit, connected with the multiplexer plays an isolation role and improves the driving capability; an output follower unit, connected with the voltage follower unit, is configured to drive the subsequent load unit.
  • the stepped voltage generating unit includes a series-connected current source, a plurality of equal-value resistors, and a signal triode module.
  • the collector of the signal triode module is connected to the base, and the emitter is grounded.
  • the voltage follower unit is an operational amplifier in the form of a voltage follower, and its input voltage is consistent with the output voltage.
  • the output follower unit is a current source biased emitter follower composed of a driving triode module and a bias current source.
  • the input end of the output follower unit is connected to the base of the driving triode module, and the output end is connected to the emitter of the driving triode module, and has the ability to drive heavy loads.
  • the ratio of the unit values of the driving triode module and the signal triode module is M 1 /M 0 equal to the current value ratio I 1 /I 0 of the bias current source and the current source, that is:
  • the emitter junction voltage of the signal triode module is made the same as the emitter junction voltage of the driving triode module.
  • control signal generating unit includes a rising edge detection module, a falling edge detection module and an up and down counter, and generates a control signal required by the multiplexer by detecting the rising edge or falling edge of the input signal.
  • the number of equivalent resistors is n-1.
  • the final output voltage signal of the signal driving system starts to increase from 0V, and the incremental step is ⁇ V until the final The output voltage signal is (n-1) ⁇ V, then the low level of the output voltage signal is 0V, and the high level is (n-1) ⁇ V.
  • the slew rate SlewRate of the output voltage signal is :
  • T is the clock period
  • the signal driving system can obtain output voltage signals with different slopes and high-level voltages by setting the clock period, ⁇ V , and n parameters to meet different application requirements.
  • the signal driving system control signal generating unit of the constant slew rate of the present disclosure sequentially selects the incremental step voltage output based on the clock cycle, and the output slew rate is constant and controllable and does not change with the load; the step voltage generating unit and the output follower unit are well optimized, so that the Compared with the process, the emitter junction voltages with different temperature change trends cancel each other out to obtain a consistent output signal and improve the chip production yield.
  • Fig. 1 schematically shows a structural schematic diagram of a signal driving system with a constant slew rate according to an embodiment of the present disclosure
  • FIG. 2 schematically shows a timing waveform diagram of a signal driving system with a constant slew rate according to an embodiment of the present disclosure
  • FIG. 3 schematically shows a structural schematic diagram of a control signal generating unit in a signal driving system with a constant slew rate according to an embodiment of the present disclosure
  • I 0 - a current source with a current value of I 0 ; C 0 , C 1 , C 2 .. C n-1 - n voltage output output nodes of the stepped voltage generating unit; A 0 , A 1 , A 2 ..
  • the present disclosure provides a signal driving system with a constant slew rate, which utilizes a control signal generating unit to sequentially select an incremental step voltage output based on a clock cycle, and the output slew rate is constant and controllable and does not vary with the load.
  • the inventor found that the slew rate of the output signal can be reduced in series with a resistor or a capacitor in parallel at the signal output node, and a slowly changing rise time or fall time can be obtained, which can improve power integrity and reduce electromagnetic compatibility. , but this method increases the cost of circuit production, and is susceptible to changes in integrated circuit technology, or changes in temperature and power supply voltage. Therefore, the stepped voltage generation unit and the output follower unit are cleverly designed, so that the voltage of the emitter junction with different trends of temperature changes with the process and temperature cancels each other out, so as to obtain a consistent output signal and improve the yield of chip production.
  • a signal driving system with a constant slew rate includes:
  • the stepped voltage generating unit includes a series-connected current source, a plurality of equal-value resistors, and a signal triode module, and is configured to provide a multi-channel equal-gradient voltage signal;
  • one input terminal is connected to the step voltage generating unit to receive the plurality of equidistant gradient voltage signals, the other input terminal is connected to a control signal generating unit, and is configured to be used in the control Under the control of the control signal sent by the signal generating unit, the multi-channel equidistant gradient voltage signal is selectively output;
  • a voltage follower unit connected with the multiplexer, to isolate and improve the driving capability
  • the output follower unit connected to the voltage follower unit, includes a current source biased emitter follower composed of a driving triode module and a bias current source, and is configured to drive a subsequent load unit.
  • (n-1) ⁇ V equals the high-level
  • the multiplexer has n input terminals, which are respectively A 0 , A 1 , A 2 . . . A n-2 , A n-1 , and the step voltage generating units C 0 , C 1 , C 2 . . . C n-1 ports are connected, the output signal port OUT is connected to the input end of the voltage follower unit, and the control signal input port is connected to the output end of the control signal generating unit.
  • the voltage follower unit is configured to isolate the front and rear two-stage circuits and provide a large driving capability to drive the latter-stage circuit, and its input voltage is consistent with the output voltage. It can be composed of an op amp connected in the form of a voltage follower. The input terminal is connected to the output signal port OUT of the multiplexer, and the output terminal is connected to the input terminal of the output follower unit. Because it has a large input impedance voltage , the follower circuit will not affect the front multiplexer and the step voltage generating unit, and because of its small output impedance, it can provide a large driving ability to drive the subsequent circuit, thus realizing the isolation of the front and rear circuits. ; The output voltage signal VB of the voltage follower unit is consistent with the input voltage signal VA.
  • the output follower unit includes a current source biased emitter follower formed by a driving triode module and a bias current source, and the input end of the output follower unit is the base of the driving triode module Q1, and the output end of the voltage follower unit is connected, the output end is the emitter of the driving triode module Q 1 , which has the ability to drive heavy loads; the number of units of the driving triode module Q 1 is M 1 , and the bias current source of the bias current is I 1 . , the voltage drop across the emitter junction of the drive transistor module is V BE1 .
  • the output follower unit is connected to the subsequent load unit, the load unit includes a load capacitor CL and a load resistance RL , and the final output voltage signal is V OUT , which can be obtained from the characteristics of the circuit:
  • V OUT V B -V BE1 ;
  • the input voltage signals VB of the output follower unit are respectively: V BE0 , VB E0 + ⁇ V, V BE0 +2 ⁇ V...V BE0 +(n-1) ⁇ V
  • the output voltage signals V OUT are respectively : V BE0 -V BE1 , V BE0 -V BE1 + ⁇ V , V BE0 -V BE1 +2 ⁇ V...V BE0 -V BE1 +(n-1) ⁇ V.
  • the step voltage generating unit The signal triode module Q 0 is mainly used for signal generation and does not need driving capability. Its size should not be designed too large, and the current flowing through Q 0 should be as small as possible to avoid waste of power consumption; while the output follower unit is the driving triode module Q .
  • the ratio of M values M 1 /M 0 is equal to the current ratio I 1 /I 0 of the bias current source and the current source, namely:
  • V BE0 V BE1
  • the voltage signals V B input by the output follower unit are respectively:
  • the output signals V OUT are: 0, ⁇ V, 2 ⁇ V, .. .(n-1) ⁇ V .
  • the control signal generating unit includes a rising edge detection module, a falling edge detection module and an up-and-down counter, whose input clock signal (CLK) has a cycle of T, and generates a multiplexer by detecting the rising or falling edge of the input logic signal (IN).
  • CLK input clock signal
  • the required control signal when the system inputs the logic signal IN into the control signal generating unit, the rising edge detection module will give an increment (INC) pulse signal after detecting the rising edge of the logic signal IN. Increment from 0, increase by 1 every clock cycle until n-1, and then remain unchanged; when the falling edge of IN comes, the falling edge detection module gives a decrement (DEC) pulse signal, and the reversible counter is changed by n-1 Start decrementing by 1 every clock cycle until 0.
  • DEC decrement
  • the slew rate SlewRate of the output signal can be approximately considered as:
  • T is the clock period
  • the circuit can obtain different slopes and high-level voltages by setting parameters such as T, ⁇ V , and n to meet different application requirements.
  • the present disclosure provides a signal driving system with constant slew rate, including a stepped voltage generating unit, a multiplexer, a voltage follower unit, an output follower unit, and a control signal generating unit; the stepped voltage generating unit generates multiple Step voltage, and superimpose the V BE0 voltage of a signal triode module; under the control of the control signal, the multiplexer selects one of the multi-channel step voltages for output, and the voltage follower is configured to provide greater drive capability
  • the output follower unit provides a voltage driving capability of 1:1, while subtracting a voltage (V BE1 ) consistent with the V BE0 value superimposed in the stepped voltage generating unit and finally driving the load unit, the present disclosure It can realize the function that the output signal rises or falls with a fixed step as the step, so as to obtain a constant output slew rate that does not change with the load, and effectively reduce the electromagnetic interference of the signal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)

Abstract

本公开提供一种恒定摆率的信号驱动系统，包括：阶梯电压产生单元，被配置用于提供多路等差递变的电压信号；多路选择器，一输入端与所述阶梯电压产生单元相连以接收所述多个等差递变的电压信号，另一输入端与一控制信号产生单元相连，被配置用于在所述控制信号产生单元发出的控制信号控制下对多路等差递变的电压信号进行选择性输出；电压跟随单元，与所述多路选择器相连，起隔离作用并提高驱动能力；输出跟随单元，与所述电压跟随单元相连，被配置用于驱动后接的负载单元。

Description

恒定摆率的信号驱动系统 技术领域
本公开涉及电路设计技术领域，尤其涉及一种恒定摆率的信号驱动系统。
背景技术
集成电路中低速数字接口普遍采用高低电平来表示信号的逻辑状态，如TTL(transistor transistor logic)电平、CMOS(Complementary Metal Oxide Semiconductor PMOS+NMOS)电平、低压TTL电平、低压CMOS电平等。当信号逻辑电平发生变化时，信号上升沿下降沿非常陡峭，输出摆率极小，这样会引起电路瞬时功耗过高，引起电源完整性问题，输出摆率的波动还会引起信号传输过程中的阻抗不连续，产生电磁干扰，最终会引起电路功能失效或者导致整个系统无法正常工作，这种现象随着集成电路工艺尺寸的递减越来越明显。
因此，亟需能提供一种输出摆率恒定的逻辑信号驱动电路以解决上述问题。
发明内容
本公开提供一种恒定摆率的信号驱动系统，包括：阶梯电压产生单元，被配置用于提供多路等差递变的电压信号；多路选择器，一输入端与阶梯电压产生单元相连以接收多个等差递变的电压信号，另一输入端与一控制信号产生单元相连，被配置用于在控制信号产生单元发出的控制信号控制下对多路等差递变的电压信号进行选择性输出；电压跟随单元，与多路选择器相连，起隔离作用并提高驱动能力；输出跟随单元，与电压跟随单元相连，被配置用于驱动后接的负载单元。
在本公开实施例中，阶梯电压产生单元包括串接的电流源、多个等值电阻、以及信号三极管模块。
在本公开实施例中，信号三极管模块的集电极与基极相连，射极接地。
在本公开实施例中，电压跟随单元为电压跟随器形式的运放，其输入电压与输出电压一致。
在本公开实施例中，输出跟随单元为驱动三极管模块以及偏置电流源 构成的电流源偏置的射极跟随器。
在本公开实施例中，输出跟随单元的输入端连接驱动三极管模块的基极，输出端连接驱动三极管模块的射极，具有驱动重负载能力。
在本公开实施例中，满足驱动三极管模块与信号三极管模块的单元个数值之比为M 1/M 0与偏置电流源及电流源的电流值比值I 1/I 0相等，即：
Figure PCTCN2020139546-appb-000001
使得信号三极管模块的发射结电压与驱动三极管模块的发射结电压相同。
在本公开实施例中，控制信号产生单元包括上升沿检测模块、下降沿检测模块以及可逆计数器，通过检测输入信号的上升沿或下降沿产生多路选择器所需的控制信号。
在本公开实施例中，等值电阻数量为n-1，当控制信号产生单元的输入信号的上升沿到来时，信号驱动系统最终输出电压信号从0V开始递增，递增台阶为 ΔV，直至最终输出电压信号为(n-1) ΔV，则输出电压信号低电平为0V，高电平为(n-1) ΔV，当n趋于无穷大时，其输出电压信号的摆率SlewRate为：
Figure PCTCN2020139546-appb-000002
其中，T为时钟周期，信号驱动系统能够通过设置时钟周期、 ΔV、n参数来获得不同斜率的输出电压信号，以及高电平电压，以满足不同应用需求。
本公开恒定摆率的信号驱动系统控制信号产生单元基于时钟周期依次选择递增的台阶电压输出，输出摆率恒定可控不随负载变化；很好的优化了阶梯电压产生单元及输出跟随单元，使其中与工艺，温度变化趋势不同的发射结电压相互抵消从而获得一致的输出信号，提高了芯片生产良率。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1示意性示出了本公开实施例的恒定摆率的信号驱动系统的组成结 构示意图；
图2示意性示出了本公开实施例的恒定摆率的信号驱动系统的时序波形图；
图3示意性示出了本公开实施例的恒定摆率的信号驱动系统中控制信号产生单元的组成结构示意图；
附图标记：
I 0-电流值为I 0的电流源；C 0、C 1、C 2...C n-1-阶梯电压产生单元的n个电压输出输出节点；A 0、A 1、A 2...A n-2、A n-1-多路选择器的n个输入端；Q0-信号三极管模块；CON-控制信号；OUT-多路选择器的的输出信号端口；V A-多路选择器的输出电压信号；V B-电压跟随单元的输出电压信号；I 1-偏置电流；Q 1-驱动三极管模块；C L-负载电容；R L-负载电阻；V OUT-最终输出电压信号；CLK-时钟信号；IN-输入逻辑信号；INC-递增脉冲信号；DEC-递减脉冲信号。
具体实施方式
本公开提供了一种恒定摆率的信号驱动系统，利用控制信号产生单元基于时钟周期依次选择递增的台阶电压输出，输出摆率恒定可控，不随负载变化。
在实现本公开的过程中发明人发现，在信号输出节点串联电阻或者并联电容能降低输出信号的摆率，获得缓慢变化的上升时间或下降时间，对提高电源完整性、降低电磁兼容有改善效果，但此方法增加了电路生产的成本，而且易受集成电路工艺而变化，或者易受温度、电源电压而变化。从而巧妙地设计了阶梯电压产生单元及输出跟随单元，使其中与随工艺，温度变化趋势不同的发射结电压相互抵消从而获得一致的输出信号，提高了芯片生产良率。
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
在本公开实施例中，提供一种恒定摆率的信号驱动系统，结合图1至图3所示，所述恒定摆率的信号驱动系统，包括：
阶梯电压产生单元，包括串接的电流源、多个等值电阻、以及信号三极管模块，被配置用于提供多路等差递变的电压信号；
多路选择器，一输入端与所述阶梯电压产生单元相连以接收所述多个等差递变的电压信号，另一输入端与一控制信号产生单元相连，被配置用于在所述控制信号产生单元发出的控制信号控制下对多路等差递变的电压信号进行选择性输出；
电压跟随单元，与所述多路选择器相连，起隔离作用并提高驱动能力；
输出跟随单元，与所述电压跟随单元相连，包括驱动三极管模块以及偏置电流源构成的电流源偏置的射极跟随器，被配置用于驱动后接的负载单元。
在本公开实施例中，所述阶梯电压产生单元，包括n-1个阻值为R的电阻以串联形式连接，最上端连接一电流值为I 0的电流源至电源端，每个电阻产生的压降为 ΔV＝I 0*R；最下端连接信号三极管模块Q 0到地，其集电极与基极相连，发射极接地，该信号三极管模块Q 0的单元个数值(M值)为M 0，在电流值为I 0的电流源的作用下产生的发射结电压为V BE0，n-1个电阻形成n个电压输出结点，从下到上依次为C 0、C 1、C 2...C n-1，输出电压分别为V BE0、V BE0+ ΔV、V BE0+2 ΔV...V BE0+(n-1) ΔV。其中(n-1) ΔV等于高电平电压。
在本公开实施例中，所述多路选择器具有n个输入端，分别为A 0、A 1、A 2...A n-2、A n-1，与阶梯电压产生单元C 0、C 1、C 2...C n-1端口连接，其输出信号端口OUT与电压跟随单元输入端连接，其控制信号输入端口与控制信号产生单元的输出端连接，当输入的控制信号CON＝0时，输出信号端口OUT与A 0连接、CON＝1时，输出信号端口OUT与A 1连接依此类推，当控制信号CON＝n-1时输出信号端口OUT与输入端A n-1连接，因此当控制信号CON由0逐次递增到n-1时，多路选择器的输出电压信号V A以 ΔV为阶梯由V BE0递增至V BE0+(n-1) ΔV，如果n足够大，可近似认为此过程中V A以线性方式从V BE0递增至V BE0+(n-1) ΔV。
所述电压跟随单元被配置用于隔离前后两级电路并提供较大的驱动能力以驱动后级电路，其输入电压与输出电压一致。可由一连接成电压跟随器形式的运放构成，输入端与多路选择器的输出信号端口OUT连接，输出端与后接的输出跟随单元的输入端连接，由于其具有较大的输入阻抗电压，跟随电路不会对前面多路选择器及阶梯电压产生单元产生影响，又 由其具有较小的输出阻抗，能提供较大的驱动能力以驱动后级电路，从而实现了前后级电路的隔离；电压跟随单元的输出电压信号V B与输入电压信号V A一致。
所述输出跟随单元包括驱动三极管模块以及偏置电流源构成的电流源偏置的射极跟随器，该输出跟随单元输入端为驱动三极管模块Q 1的基极，与所述电压跟随单元输出端相连，输出端为驱动三极管模块Q 1的射极，其具有驱动重负载能力；所述驱动三极管模块Q 1的单元个数值为M 1，在偏置电流为I 1的偏置电流源的作用下，驱动三极管模块的发射结压降为V BE1。
所述输出跟随单元与后接的负载单元相连，所述负载单元包括负载电容C L以及负载电阻R L，最终输出电压信号为V OUT，由该电路特点可以得出：
V OUT＝V B-V BE1；
输出跟随单元的输入电压信号V B分别为：V BE0、VB E0+ ΔV、V BE0+2 ΔV...V BE0+(n-1) ΔV时，其输出电压信号V OUT分别为：V BE0-V BE1、V BE0-V BE1+ ΔV、V BE0-V BE1+2 ΔV...V BE0-V BE1+(n-1) ΔV。
由于三极管模块的发射结压降随电流，温度，工艺偏差变化而变化，且对于不同参数的三极管变化趋势不一定相同，因此对于前述信号三极管模块Q 0及驱动三极管模块Q 1，阶梯电压产生单元中的信号三极管模块Q 0主要用于信号产生，无需驱动能力，其尺寸不宜设计过大，同时流经Q 0的电流尽可能小以避免功耗浪费；而输出跟随单元中的驱动三极管模块Q 1被配置用于驱动重负载，其尺寸大，偏置电流大是不可避免的，因此这两个三极管的尺寸不同，偏置电流不同，通过使驱动三极管模块Q 1与信号三极管模块Q 0的M值之比M 1/M 0与所述偏置电流源及电流源的电流比值I 1/I 0相等，即：
Figure PCTCN2020139546-appb-000003
从而可得到信号三极管模块Q 0的发射结电压与驱动三极管模块Q 1的发射结电压相同的效果，即V BE0＝V BE1；结合前述分析，当输出跟随单元输入的电压信号V B分别为：V BE0、V BE0+ ΔV、V BE0+2 ΔV、...V BE0+(n-1) ΔV时，其输出信号V OUT分别为：0、 ΔV、2 ΔV、...(n-1) ΔV。
所述控制信号产生单元包括上升沿检测模块、下降沿检测模块以及可逆计数器，其输入时钟信号(CLK)周期为T，通过检测输入逻辑信号(IN)的上升沿或下降沿产生多路选择器所需的控制信号，当系统将逻辑信号IN输入控制信号产生单元时，上升沿检测模块在检测到逻辑信号IN上升沿后给出一递增(INC)脉冲信号，在该脉冲触发下，可逆计数器从0开始递增，每个时钟周期加1，直至n-1，后保持不变；在IN下降沿到来时，下降沿检测模块给出递减(DEC)脉冲信号，此时可逆计数器由n-1开始递减每个时钟周期减1，直至0。
结合前述分析，当输入信号IN的上升沿到来时，电路最终输出电压信号V OUT从0V开始递增，递增台阶为 ΔV直至(n-1) ΔV。输出信号低电平为0V，高电平为(n-1) ΔV，当n足够大时，可近似认为其输出信号的摆率SlewRate为：
Figure PCTCN2020139546-appb-000004
其中，T为时钟周期，电路可通过设置T、 ΔV、n等参数来获得不同的斜率，以及高电平电压，以满足不同应用需求。
至此，已经结合附图对本公开实施例进行了详细描述。需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。
依据以上描述，本领域技术人员应当对本公开恒定摆率的信号驱动系统有了清楚的认识。
综上所述，本公开提供了一种恒定摆率的信号驱动系统，包括阶梯电压产生单元、多路选择器、电压跟随单元，输出跟随单元，以及控制信号产生单元；阶梯电压产生单元产生多路阶梯电压，并叠加一个信号三极管模块的V BE0电压；多路选择器在控制信号的控制下选择选择多路阶梯电压中的一路进行输出，电压跟随器被配置用于提供较大的驱动能力以驱动后级输出跟随单元，输出跟随单元提供1∶1的电压驱动能力，同时减去一个与阶梯电压产生单元中叠加的V BE0值一致的电压(V BE1)并最终驱动负载单元，本公开能实现输出信号以固定阶梯为步长上升或者下降的功能，从而 获得不随负载变化的恒定输出摆率，有效降低信号电磁干扰。
本领域技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能器件的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将信号驱动系统的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的信号驱动系统的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；在不冲突的情况下，本公开实施例中的特征可以任意组合；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (9)

  1. 一种恒定摆率的信号驱动系统，包括：
    阶梯电压产生单元，被配置用于提供多路等差递变的电压信号；
    多路选择器，一输入端与所述阶梯电压产生单元相连以接收所述多个等差递变的电压信号，另一输入端与一控制信号产生单元相连，被配置用于在所述控制信号产生单元发出的控制信号控制下对多路等差递变的电压信号进行选择性输出；
    电压跟随单元，与所述多路选择器相连，起隔离作用并提高驱动能力；
    输出跟随单元，与所述电压跟随单元相连，被配置用于驱动后接的负载单元。
  2. 根据权利要求1所述的恒定摆率的信号驱动系统，所述阶梯电压产生单元包括串接的电流源、多个等值电阻、以及信号三极管模块。
  3. 根据权利要求2所述的恒定摆率的信号驱动系统，所述信号三极管模块的集电极与基极相连，射极接地。
  4. 根据权利要求3所述的恒定摆率的信号驱动系统，所述电压跟随单元为电压跟随器形式的运放，其输入电压与输出电压一致。
  5. 根据权利要求4所述的恒定摆率的信号驱动系统，所述输出跟随单元为驱动三极管模块以及偏置电流源构成的电流源偏置的射极跟随器。
  6. 根据权利要求5所述的恒定摆率的信号驱动系统，所述输出跟随单元的输入端连接驱动三极管模块的基极，输出端连接驱动三极管模块的射极，具有驱动重负载能力。
  7. 根据权利要求1所述的恒定摆率的信号驱动系统，满足所述驱动三极管模块与信号三极管模块的单元个数值之比为M 1/M 0与所述偏置电流源及电流源的电流值比值I 1/I 0相等，即：
    Figure PCTCN2020139546-appb-100001
    使得信号三极管模块的发射结电压与驱动三极管模块的发射结电压相同。
  8. 根据权利要求1所述的恒定摆率的信号驱动系统，所述控制信号产生单元包括上升沿检测模块、下降沿检测模块以及可逆计数器，通过检测输入信号的上升沿或下降沿产生多路选择器所需的控制信号。
  9. 根据权利要求8所述的恒定摆率的信号驱动系统，所述等值电阻数量为n-1，当所述控制信号产生单元的输入信号的上升沿到来时，信号驱动系统最终输出电压信号从0V开始递增，递增台阶为 ΔV，直至最终输出电压信号为(n-1) ΔV，则输出电压信号低电平为0V，高电平为(n-1) ΔV，当n趋于无穷大时，其输出电压信号的摆率SlewRate为：
    Figure PCTCN2020139546-appb-100002
    其中，T为时钟周期，信号驱动系统能够通过设置时钟周期、 ΔV、n参数来获得不同斜率的输出电压信号，以及高电平电压，以满足不同应用需求。
PCT/CN2020/139546 2020-12-25 2020-12-25 恒定摆率的信号驱动系统 WO2022134042A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/139546 WO2022134042A1 (zh) 2020-12-25 2020-12-25 恒定摆率的信号驱动系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/139546 WO2022134042A1 (zh) 2020-12-25 2020-12-25 恒定摆率的信号驱动系统

Publications (1)

Publication Number Publication Date
WO2022134042A1 true WO2022134042A1 (zh) 2022-06-30

Family

ID=82157261

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/139546 WO2022134042A1 (zh) 2020-12-25 2020-12-25 恒定摆率的信号驱动系统

Country Status (1)

Country Link
WO (1) WO2022134042A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101989454A (zh) * 2009-08-03 2011-03-23 索尼公司 半导体存储器件及其操作方法
CN105573396A (zh) * 2016-01-29 2016-05-11 佛山中科芯蔚科技有限公司 一种低压差线性稳压器电路
CN106059503A (zh) * 2016-05-31 2016-10-26 上海华虹宏力半导体制造有限公司 电压缓冲放大器
US9946279B1 (en) * 2016-06-25 2018-04-17 Active-Semi, Inc. Programmable voltage setting with open and short circuit protection
CN108462476A (zh) * 2018-02-08 2018-08-28 芯原微电子(上海)有限公司 一种功率放大器及其功率控制方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101989454A (zh) * 2009-08-03 2011-03-23 索尼公司 半导体存储器件及其操作方法
CN105573396A (zh) * 2016-01-29 2016-05-11 佛山中科芯蔚科技有限公司 一种低压差线性稳压器电路
CN106059503A (zh) * 2016-05-31 2016-10-26 上海华虹宏力半导体制造有限公司 电压缓冲放大器
US9946279B1 (en) * 2016-06-25 2018-04-17 Active-Semi, Inc. Programmable voltage setting with open and short circuit protection
CN108462476A (zh) * 2018-02-08 2018-08-28 芯原微电子(上海)有限公司 一种功率放大器及其功率控制方法

Similar Documents

Publication Publication Date Title
US5227679A (en) Cmos digital-controlled delay gate
EP0584946B1 (en) Logic interface circuits
WO2020241048A1 (ja) 回路システム
US10804888B1 (en) Delay circuit and electronic system equipped with delay circuit
US5191234A (en) Pulse signal generator and cascode differential amplifier
KR20050056151A (ko) 반도체회로
US20080001668A1 (en) Impedance control device and impedance control method
WO2022134042A1 (zh) 恒定摆率的信号驱动系统
Morales et al. Design and evaluation of an all-digital programmable delay line in 130-nm CMOS
US5243240A (en) Pulse signal generator having delay stages and feedback path to control delay time
US9577661B2 (en) Voltage-controlled oscillator and analog-digital converter
JP2990785B2 (ja) 論理回路
JPH04329712A (ja) 高速論理回路
JPS6248806A (ja) 出力回路
US6025747A (en) Logic signal selection circuit
JPH052893A (ja) 出力バツフア回路
JPH0622318B2 (ja) パルス遅延回路
US5587679A (en) Pulse generator including slew rate controller without complementary transistors
CN112383291B (zh) 数字可控延迟链
EP0795963A2 (en) Analog to digital converter
US20080238517A1 (en) Oscillator Circuit and Semiconductor Device
JP2870464B2 (ja) 可変遅延回路
JP5881512B2 (ja) クロック生成回路および撮像装置
CN112737564A (zh) 恒定摆率的信号驱动系统
JP3925765B2 (ja) タイミング調整機能を備えたクロック発生回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20966607

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20966607

Country of ref document: EP

Kind code of ref document: A1