WO2022133691A1 - 一种开关电路及开关电源 - Google Patents

一种开关电路及开关电源 Download PDF

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Publication number
WO2022133691A1
WO2022133691A1 PCT/CN2020/138143 CN2020138143W WO2022133691A1 WO 2022133691 A1 WO2022133691 A1 WO 2022133691A1 CN 2020138143 W CN2020138143 W CN 2020138143W WO 2022133691 A1 WO2022133691 A1 WO 2022133691A1
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Prior art keywords
switch
coupled
input terminal
terminal
circuit
Prior art date
Application number
PCT/CN2020/138143
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English (en)
French (fr)
Inventor
陈悦
张文林
汪家轲
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/138143 priority Critical patent/WO2022133691A1/zh
Priority to CN202080107310.7A priority patent/CN116530003A/zh
Publication of WO2022133691A1 publication Critical patent/WO2022133691A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Definitions

  • the present application relates to the technical field of electronic circuits, and in particular, to a switching circuit and a switching power supply.
  • the input voltage can be converted into a stable output voltage by controlling the ratio of the on and off time of multiple switches.
  • the structure of the switch circuit 01 is shown in FIG. 1, including a first power tube S1, a second power tube S2, a first power tube driver stage circuit 1, a second power tube driver stage circuit 2, an inductance L, Capacitor C, voltage input terminal Vin, voltage output terminal Vo, first switching signal input terminal PWML and second switching signal input terminal PWMH, the first power transistor S1 includes a first parasitic diode D1, and the second power transistor S2 includes a second parasitic diode Diode D2.
  • the first power transistor S1 is an N-type transistor
  • the second power transistor S2 is a P-type transistor
  • the first power transistor S1 and the second power transistor S2 are coupled to the switching node Lx
  • the first power transistor S1 is coupled to the switching node Between Lx and the reference ground GND
  • the second power transistor S2 is coupled between the voltage input terminal Vin and the switch node Lx
  • the control end of the first power transistor S1 is input through the first power transistor driver stage circuit 1 and the first switch signal
  • the terminal PWML is coupled
  • the control terminal of the second power tube S2 is coupled to the second switching signal input terminal PWMH through the second power tube driving stage circuit 2
  • the inductor L is coupled between the switching node Lx and the voltage output terminal Vo
  • the capacitor C is coupled between the voltage output terminal Vo and the reference ground GND.
  • FIG. 2 is a waveform diagram of signals of the switching circuit 01 shown in FIG. 1 .
  • the first switch signal input terminal PWML receives a high level signal
  • the first power transistor S1 is turned on
  • the second switch signal input terminal PWMH receives a low level signal
  • the second power transistor S2 is turned on. 1 and 2
  • the voltage provided by the voltage input terminal Vin can be output to the voltage output terminal Vo by controlling the time ratio of the first power transistor S1 and the second power transistor S2 being turned on and off alternately.
  • the voltage input terminal Vin and the reference ground GND are directly connected, thereby causing the power supply connected to the voltage input terminal Vin to burn out. Therefore, refer to Fig. 2, there is usually a period of time when the first power tube S1 and the second power tube S2 are turned on and off alternately at the same time, and the time when the first power tube S1 and the second power tube S2 are disconnected at the same time called dead time. During the dead time, the voltage of the switching node Lx gradually decreases.
  • the first parasitic diode D1 When the voltage of the switching node Lx decreases to a certain value, the first parasitic diode D1 is turned on, and the current of the inductor L depends on the first parasitic diode D1 to freewheel. In order to ensure the stable output voltage of the voltage output terminal Vo.
  • the turn-on voltage drop of the parasitic diode (for example, about 0.7V) is much larger than the turn-on voltage drop of the power transistor (for example, 10mV)
  • the power lost by the first parasitic diode D1 is relatively There are several orders of magnitude difference in the power lost due to the power transistor, so that the conduction loss of the first parasitic diode D1 greatly increases the loss of the switching circuit 01 .
  • the proportion of the dead time also increases, so the dead loss becomes one of the main losses of the high-frequency switching circuit.
  • Embodiments of the present application provide a switching circuit and a switching power supply, which can reduce dead time and dead zone loss, thereby reducing the loss of the switching circuit.
  • a switch circuit in a first aspect, includes: a first switch, a first drive stage circuit, a second switch, a high-pass filter, a logic processing circuit, a first voltage input end, a second voltage input end, a voltage output end, a first switch signal input end, The second switch signal input terminal and the first reference ground.
  • the first switch is coupled between the first node and the first reference ground; the control end of the first switch is coupled with the output end of the first driving stage circuit; the first input end of the first driving stage circuit is coupled with the output end of the logic processing circuit
  • the output terminal is coupled, the ground terminal of the first driving stage circuit is coupled to the first reference ground; the second switch is coupled between the first voltage input terminal and the first node; the control terminal of the second switch is connected to the second switch signal
  • the input end is coupled; the first input end of the high-pass filter is coupled with the first voltage input end, the second input end of the high-pass filter is coupled with the second voltage input end, and the output end of the high-pass filter is coupled with the first driving stage
  • the second input end of the circuit is coupled; the first input end of the logic processing circuit is coupled to the first switch signal input end, and the second input end of the logic processing circuit is coupled to the second switch signal input end; the logic processing circuit is used for After the second switch is turned off and before the first switch is turned on, the coupling between
  • the first switch and the second switch are turned on and off alternately, and by controlling the ratio of the on and off times of the first switch and the second switch, the first voltage input terminal can be The supplied voltage is converted into the required voltage and output from the voltage output terminal.
  • the switch circuit includes a high-pass filter, and the high-pass filter is coupled to the first voltage input terminal, the feedforward effect of the high-pass filter will cause the high-pass filter to convert the first voltage input terminal.
  • the voltage provided by the two voltage input terminals is raised and then provided to the second input terminal of the first driving stage circuit. In this way, the actual working voltage of the first driving stage circuit in the dead time is higher than that in the non-dead time.
  • the first drive stage circuit will drive the first switch to turn on in advance under the action of the feedforward voltage, that is, the actual working voltage.
  • the voltage received by the first switch signal input terminal can control the first driving stage circuit to receive the voltage provided by the second voltage input terminal and drive the first switch to be turned on.
  • the feedforward action of the high-pass filter is used to drive the first switch to conduct in advance, thereby effectively reducing the dead time, reducing the loss of the dead time, thereby reducing the loss of the switching circuit and improving the efficiency of the switching circuit.
  • the high-pass filter includes a first capacitor and a first resistor; the first capacitor is coupled between the first voltage input terminal and the second input terminal of the first driving stage circuit; the first resistor is coupled It is connected between the second voltage input terminal and the second input terminal of the first driving stage circuit.
  • the energy of the parasitic inductance raises the voltage of the first voltage input terminal. It is higher than the voltage at the input terminal of the first voltage.
  • the high-pass filter since the high-pass filter includes the first capacitor, the voltage at the other end of the first capacitor can be raised through the feedforward action of the first capacitor in the high-pass filter.
  • the first driver stage circuit provides it to the first driver stage circuit, so that the actual working voltage of the first driver stage circuit is raised, higher than the voltage provided by the second voltage input terminal controlled by its previous stage, so the first driver stage circuit is in the feedforward voltage. Under the action, the first switch is driven to be turned on in advance.
  • the logic processing circuit includes a flip-flop and an OR gate; the second switch signal input terminal is coupled to the clock terminal of the flip-flop; the reset terminal of the flip-flop is coupled to the first switch signal input terminal;
  • the device also includes an input terminal for receiving a fixed high level or a fixed low level; the output terminal of the flip-flop is coupled to the first input terminal of the OR gate, and the second input terminal of the OR gate is coupled to the first switch signal input terminal The output terminal of the OR gate is coupled to the first input terminal of the first driving stage circuit.
  • the output terminal of the flip-flop When the flip-flop includes an input terminal for receiving a fixed high level, the output terminal of the flip-flop will be triggered according to the rising or falling edge of the signal provided by the input terminal of the second switch signal received by the clock terminal, and the output terminal of the flip-flop will be triggered. High level signal of the output signal.
  • the flip-flop When the flip-flop includes an input terminal for receiving a fixed low level, the output terminal of the flip-flop will be triggered according to the rising or falling edge of the signal provided by the input terminal of the second switch signal received by the clock terminal, and the output terminal of the flip-flop will be triggered. Low level signal of the output signal.
  • the reset terminal of the flip-flop is coupled to the first switch signal input terminal, when the signal provided by the first switch signal input terminal changes from a low level to a high level, or from a high level to a low level, The signal output from the output terminal of the flip-flop is restored to the previous signal.
  • the output terminal of the OR gate will output a corresponding signal to the first input terminal of the first driver stage circuit according to the signals of its first input terminal and the second input terminal, so as to cut off the ground terminal of the first driver stage circuit and the first reference ground. coupled.
  • the logic processing circuit includes a delay circuit, a first AND gate, a second AND gate, a first inverter, a second inverter and an OR gate; the second switch signal input terminal passes through the delay circuit is coupled to the first input end of the first AND gate, and the second switch signal input end is also coupled to the second input end of the first AND gate through the first inverter; the output end of the first AND gate is connected to the second AND gate The first input end of the gate is coupled, the first switch signal input end is coupled to the second input end of the second AND gate through the second inverter, and the output end of the second AND gate is coupled to the first input end of the OR gate The second input end of the OR gate is coupled with the first switch signal input end, and the output end of the OR gate is coupled with the first input end of the first driving stage circuit.
  • the second switch After the signal received by the signal input end passes through the delay circuit, the output end of the delay circuit outputs a high-level signal, and at the same time, the signal received by the second switch signal input end passes through the first inverter and outputs a high-level signal; the first AND gate One input terminal of the delay circuit receives the high-level signal output by the output terminal of the delay circuit, and the other input terminal receives the high-level signal output by the first inverter, so the output terminal of the first AND gate outputs a high-level signal; the second The input terminal of the inverter receives the low-level signal received by the input terminal of the first switch signal, and the output terminal of the second inverter outputs the high-level signal; an input terminal of the second AND gate receives the output terminal of the first AND
  • one input terminal of the OR gate receives the high-level signal output by the output terminal of the second AND gate, and the other input terminal receives the low-level signal provided by the input terminal of the first switch signal, so the output terminal of the OR gate A high-level signal is output, and the high-level signal can control the coupling of the ground terminal of the first driving stage circuit and the first reference ground to be cut off.
  • the delay circuit includes n third inverters connected in series; wherein, n ⁇ 2, and n is a positive even number.
  • the n third inverters connected in series can delay the signal received at the input end of the second switch signal for a certain period of time and then output the signal.
  • the delay circuit includes a second capacitor and a second resistor connected in series.
  • the second capacitor and the second resistor connected in series can delay the signal received at the input end of the second switch signal for a certain period of time before outputting.
  • the first driving stage circuit includes a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and an eighth switch; the third switch and the fourth switch are coupled to the Two nodes; the control end of the first switch is coupled to the second node; the third switch is coupled between the output end of the high-pass filter and the second node, and the fourth switch is coupled between the second node and the first reference ground the fifth switch is coupled between the second voltage input terminal and the control terminal of the third switch; the sixth switch is coupled between the control terminal of the third switch and the first reference ground; the control terminal of the fifth switch and The control end of the sixth switch is coupled to the first switch signal input end; the seventh switch is coupled between the second voltage input end and the control end of the fourth switch; the eighth switch is coupled to the control end of the fourth switch and between the first reference ground; the control end of the seventh switch and the control end of the eighth switch are coupled to the output end of the logic processing circuit.
  • the third switch is a pull-up transistor in the first drive stage circuit
  • the fourth switch is a pull-down transistor in the first drive stage circuit
  • the third switch and the fourth switch are used to control the voltage of the control terminal of the first switch
  • the fifth switch and the sixth switch are used to control the voltage of the control terminal of the third switch
  • the seventh switch and the eighth switch are used to control the voltage of the control terminal of the fourth switch.
  • the switch circuit further includes a second driver stage circuit; the control terminal of the second switch is coupled to the second switch signal input terminal through the second driver stage circuit. Since the control terminal of the second switch is coupled to the second driving stage circuit, the driving capability of the control terminal of the second switch can be improved, and the turn-on or turn-off time of the second switch can be reduced.
  • the switch circuit further includes a third voltage input terminal and a second reference ground
  • the second driver stage circuit further includes a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a Thirteen switches and fourteenth switches.
  • the ninth switch is coupled between the third voltage input terminal and the control terminal of the second switch
  • the tenth switch is coupled between the control terminal of the second switch and the second reference ground.
  • the eleventh switch is coupled between the third voltage input terminal and the control terminal of the ninth switch
  • the twelfth switch is coupled between the control terminal of the ninth switch and the second reference ground
  • the control terminal of the eleventh switch and the control terminal of the twelfth switch are both coupled to the second switch signal input terminal.
  • the thirteenth switch is coupled between the third voltage input terminal and the control terminal of the tenth switch; the fourteenth switch is coupled between the control terminal of the tenth switch and the second reference ground; the control terminal of the thirteenth switch and the control terminals of the fourteenth switch are both coupled to the second switch signal input terminal.
  • the ninth switch is a pull-up transistor in the second driver stage circuit, the tenth switch is a pull-down transistor in the second driver stage circuit, and the ninth switch and the tenth switch are used to control the voltage of the control terminal of the second switch. .
  • the eleventh switch and the twelfth switch are used to control the voltage of the control terminal of the ninth switch, and the thirteenth switch and the fourteenth switch are used to control the voltage of the control terminal of the tenth switch.
  • the switch circuit further includes an inductor and a third capacitor; the inductor is coupled between the first node and the voltage output terminal; and the third capacitor is coupled between the voltage output terminal and the first reference ground.
  • the inductor can play the role of freewheeling, so that the voltage output terminal can output the voltage stably and avoid the voltage change of the voltage output terminal.
  • the third capacitor can play a role of voltage regulation, and can reduce the ripple of the output voltage of the voltage output terminal.
  • the first switch and the second switch are insulated gate bipolar transistors, metal-oxide semiconductor field effect transistors or PN junction field effect transistors.
  • the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch and the eighth switch are insulated gate bipolar transistors, metal-oxide semiconductor field effect transistors or PN Junction Field Effect Transistor.
  • a switch circuit in a second aspect, includes a first switch, a first drive stage circuit, a second switch, a high-pass filter, a logic processing circuit, a first voltage input end, a second voltage input end, a voltage output end, a first switch signal input end, a first switch signal input end, and a first voltage input end. Two switch signal input terminals and a first reference ground.
  • the first switch is coupled between the first node and the first reference ground; the control terminal of the first switch is coupled to the output terminal of the first driver stage circuit; the ground terminal of the first driver stage circuit is coupled to the first reference ground
  • the second switch is coupled between the first voltage input end and the first node; the control end of the second switch is coupled with the second switch signal input end; the first input end of the high-pass filter is coupled with the first voltage input end connected, the second input end of the high-pass filter is coupled with the second voltage input end, and the output end of the high-pass filter is coupled with the second input end of the first driving stage circuit;
  • the logic processing circuit includes a flip-flop and an OR gate;
  • the two switch signal input terminals are coupled to the clock terminal of the flip-flop; the reset terminal of the flip-flop is coupled to the first switch signal input terminal; the flip-flop also includes an input terminal for receiving a fixed high level or a fixed low level;
  • the output terminal of the OR gate is coupled with the first input terminal of the OR gate, the second input
  • the specific structures of the first driving stage circuit and the high-pass filter, the types of each switch, and other structures of the switch circuit can all refer to the above-mentioned first aspect, which will not be repeated here.
  • the switch circuit has the same technical effect as the foregoing embodiment, and thus will not be repeated here.
  • a switch circuit in a third aspect, includes a first switch, a first drive stage circuit, a second switch, a high-pass filter, a logic processing circuit, a first voltage input end, a second voltage input end, a voltage output end, a first switch signal input end, a first switch signal input end, and a first voltage input end.
  • Two switch signal input terminals and a first reference ground The first switch is coupled between the first node and the first reference ground; the control terminal of the first switch is coupled to the output terminal of the first driver stage circuit; the ground terminal of the first driver stage circuit is coupled to the first reference ground .
  • the second switch is coupled between the first voltage input terminal and the first node; the control terminal of the second switch is coupled to the second switch signal input terminal.
  • the first input end of the high-pass filter is coupled to the first voltage input end
  • the second input end of the high-pass filter is coupled to the second voltage input end
  • the output end of the high-pass filter is coupled to the second input of the first driving stage circuit terminal coupling.
  • the logic processing circuit includes a delay circuit, a first AND gate, a second AND gate, a first inverter, a second inverter, and an OR gate.
  • the second switch signal input terminal is coupled to the first input terminal of the first AND gate through the delay circuit; the second switch signal input terminal is also coupled to the second input terminal of the first AND gate through the first inverter; the first The output end of the AND gate is coupled to the first input end of the second AND gate, the first switch signal input end is coupled to the second input end of the second AND gate through the second inverter, and the output end of the second AND gate
  • the first input end of the OR gate is coupled; the second input end of the OR gate is coupled with the first switch signal input end, and the output end of the OR gate is coupled with the first input end of the first driving stage circuit.
  • the specific structures of the first driving stage circuit and the high-pass filter, the types of each switch, and other structures of the switch circuit can all refer to the above-mentioned first aspect, which will not be repeated here.
  • the switch circuit has the same technical effect as the foregoing embodiment, and thus will not be repeated here.
  • a switching power supply in a fourth aspect, includes a controller and the above-mentioned switching circuit; the first switching signal input terminal and the second switching signal input terminal are both coupled to the controller.
  • the controller is used for outputting the first switch signal, and providing the first switch signal to the input end of the first switch signal to control the on or off of the first switch, and the controller is also used for outputting the second switch signal, and
  • the second switch signal is provided to the second switch signal input terminal to control the turn-on or turn-off of the second switch.
  • the switching power supply also has the same technical effect as the foregoing embodiment, so it is not repeated here.
  • FIG. 1 is a schematic structural diagram of a switching circuit provided by the prior art
  • Fig. 2 is the waveform diagram of each signal in the switch circuit shown in Fig. 1;
  • FIG. 3 is a schematic structural diagram of a switching circuit
  • FIG. 4 is a schematic structural diagram of a switching power supply provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a switch circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a switch circuit provided by another embodiment of the present application.
  • FIG. 7a is a schematic structural diagram of a switch circuit according to another embodiment of the present application.
  • FIG. 7b is a schematic structural diagram of a switch circuit provided by still another embodiment of the present application.
  • Fig. 8 is the waveform diagram of each signal in the switch circuit shown in Fig. 7b;
  • FIG. 9 is a schematic structural diagram of a switch circuit provided by another embodiment of the present application.
  • FIG. 10 is a waveform diagram of each signal in the switching circuit shown in FIG. 9;
  • FIG. 11 is a schematic structural diagram of a switch circuit according to another embodiment of the present application.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated; It can also be indirectly connected through an intermediary.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • coupled can mean that two or more components are in direct physical or electrical contact, or it can mean that two or more components are not in direct contact with each other, but are electrically connected or interacted through an intermediary .
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • the loss during dead time (also called dead time loss) is one of the main losses of the switching circuit 01 .
  • the current speed of the switching circuit 01 is constantly increasing, which has evolved from several hundred KHz to the order of 100 MHz, and the corresponding dead zone loss is also increasing.
  • FIG. 3 provides a schematic structural diagram of a switch circuit 01 using a logic interlock dead zone scheme.
  • the switch circuit 01 includes a first power tube (also known as an upper tube) S1 and a second power tube (also known as a lower tube) S2, the first power tube S1 includes a first parasitic diode D1, and the second power tube S2 includes a second power tube S2.
  • the first power transistor S1 and the second power transistor S2 are coupled to the switch node Lx; the first power transistor S1 is coupled between the voltage input terminal Vin and the switch node Lx; the second power transistor S2 is coupled to the switch node Lx and the first power transistor S2 between a reference ground and GND.
  • the control terminal of the first power tube S1 is coupled to the first power tube driver stage circuit 1, the first power tube driver stage circuit 1 includes two inverters connected in series, the first power tube driver stage circuit 1 and the AND gate a.
  • the output end is coupled, one input end of the AND gate a is coupled with the second switching signal input end PWMH, and the other input end of the AND gate a is coupled with the control end of the second power tube S2; the control of the second power tube S2
  • the terminal is coupled to the second power tube driver stage circuit 2
  • the second power tube driver stage circuit 2 includes two inverters connected in series, the second power tube driver stage circuit 2 is coupled to the output terminal of the AND gate b, and the AND gate
  • One input end of b is coupled to the control end of the first power transistor S1 through the inverter Inv(inverter)1, and the other input end of the AND gate b is connected to the second switch signal input end through the inverter Inv(inverter)2 PWMH coupling.
  • the inductor L is coupled between the switching node Lx and the voltage output terminal Vo
  • the capacitor C is coupled between the voltage output terminal Vo and the first reference ground GND.
  • the post-drive delay is reduced by increasing the driving capability of the first power tube driver stage circuit 1 (for example, increasing the size of the driving MOS tube in the first power tube driver stage circuit 1), that is, the first power tube driver stage circuit 1 to The driving delay of the first power tube S1, and the increase in the size of the driving MOS tube in the first power tube driving stage circuit 1 will lead to the driving delay of this stage, that is, the output end of the AND gate a goes to the first power tube driving stage circuit.
  • increasing the driving capability of the second power tube driver stage circuit 2 will cause similar problems as increasing the driving capability of the first power tube driver stage circuit 1.
  • the drive delay Tdrive is always It exists and is determined by the FOM (figure of merit) value that characterizes the intrinsic nature of the process. It can only be optimized with the evolution of the process, and there is no essential breakthrough. Combining the above two aspects, it can be seen that there is a limit to reducing the dead time by using the logic interlock dead time scheme. Generally, the dead time can only be achieved in ns level, which can be applied in low frequency (kHz to MHz level) switching circuits. But it is unacceptable in high frequency (tens to hundreds of MHz) switching circuits. Based on the above, in order to reduce the dead zone loss, an embodiment of the present application provides a switching power supply, as shown in FIG. 4 , the switching power supply includes a switching circuit (also referred to as a buck (step-down) converter) 01 and a controller 02 .
  • a switching circuit also referred to as a buck (step-down) converter
  • the main structure of the above-mentioned switch circuit 01 is shown in FIG. 4, including a first switch M1, a first driver stage circuit 10, a second switch M2, a high-pass filter 20, a logic processing circuit 30, a first voltage input terminal PVDD, a second The voltage input terminal VDRIVE, the voltage output terminal Vo, the first switch signal input terminal PWML, the second switch signal input terminal PWMH and the first reference ground GND.
  • first switch signal input terminal PWML and second switch signal input terminal PWMH are both coupled to the controller 02, and the controller 02 is used to output the first switch signal PWML and provide the first switch signal PWML to the first switch signal
  • the input terminal PWML is used to control the on or off of the first switch M1; the controller 02 is also used to output the second switch signal PWMH, and provide the second switch signal PWMH to the second switch signal input terminal PWMH to control the second switch signal PWMH.
  • the two switches M2 are ORed open.
  • the first switch M1 is coupled between the first node Lx and the first reference ground GND; the control terminal LG of the first switch M1 is coupled to the output terminal p of the first driving stage circuit 10 ;
  • the first input terminal d of the first driving stage circuit 10 is coupled to the output terminal e of the logic processing circuit 30, and the ground terminal f of the first driving stage circuit 10 is coupled to the first reference ground GND.
  • the second switch M2 is coupled between the first voltage input terminal PVDD and the first node Lx; the control terminal HG of the second switch M2 is coupled to the second switch signal input terminal PWMH.
  • the first input terminal m of the high-pass filter 20 is coupled to the first voltage input terminal PVDD, the second input terminal o of the high-pass filter 20 is coupled to the second voltage input terminal VDRIVE, and the output terminal n of the high-pass filter 20 is coupled to the first voltage input terminal VDRIVE.
  • the second input terminal g of a driver stage circuit 10 is coupled.
  • the first input terminal h of the logic processing circuit 30 is coupled to the first switching signal input terminal PWML, and the second input terminal i of the logic processing circuit 30 is coupled to the second switching signal input terminal PWMH; After the two switches M2 are turned off, and before the first switch M1 is turned on, the coupling between the ground terminal f of the first driving stage circuit 10 and the first reference ground GND is cut off.
  • the first node Lx is coupled to the voltage output terminal Vo.
  • the high-pass filter 20 is used to increase the voltage provided by the second voltage input terminal VDRIVE to the first driving stage circuit 10 after the second switch M2 is turned off and before the first switch M1 is turned on.
  • the second input terminal g is used to turn on the first switch M1.
  • the ground terminal j of the logic processing circuit 30 is coupled to the first reference ground GND, and the third input terminal k of the logic processing circuit 30 is connected to the second voltage input terminal VDRIVE is coupled, and the third input terminal of the first driving stage circuit 10 is coupled to the second voltage input terminal VDRIVE.
  • a parasitic inductor will be generated between the power supply and the switch, such as the first A parasitic inductance connected in series between the first voltage input terminal PVDD and the second switch M2 is generated between the voltage input terminal PVDD and the second switch M2 (parasitic inductance is represented by L' in FIG. 4 ).
  • the parasitic inductance L' is generally in the nH level. Usually, the parasitic inductance L' is harmful and cannot be eliminated. On this basis, it should be noted that the current continuity of the inductor itself is determined.
  • the first switch M1 and the second switch M2 are power tubes arranged on the power path.
  • the type of power transistor can be an insulated gate bipolar transistor (IGBT), a metal-oxide semiconductor field effect transistor (also known as a metal oxide semiconductor field effect transistor) (metal oxide semiconductor field effect transistor, MOSFET) ) or PN junction field effect transistor (PN junction field effect transistor, PNJFET).
  • IGBT insulated gate bipolar transistor
  • MOSFET metal oxide semiconductor field effect transistor
  • PNJFET PN junction field effect transistor
  • the first switch M1 and the second switch M2 can both be N-type transistors; they can also both be P-type transistors; of course, one can be a P-type transistor and the other can be an N-type transistor, for example, the first switch M1 is an N-type transistor, and the second switch M2 is a P-type transistor.
  • the first switch M1 is a P-type transistor
  • the second switch M2 is an N-type transistor.
  • the following description and the drawings in the description take that both the first switch M1 and the second switch M2 are N-type transistors as an example for illustration.
  • the second switch M2 may be referred to as an upper tube, and the first switch M1 may be referred to as a lower tube.
  • the first switch M1 and the second switch M2 are turned on and off alternately, in order to prevent the first switch M1 and the second switch M2 from being turned on at the same time, the first voltage input terminal PVDD and the first reference ground GND are directly turned on is turned on, which in turn causes the power supply coupled to the first voltage input terminal PVDD to burn out. Therefore, in the process that the first switch M1 and the second switch M2 are turned on and off alternately, there is a period of the first switch M1 and the second switch M2 at the same time. The time to disconnect, that is, the dead time.
  • An embodiment of the present application provides a switch circuit 01, the switch circuit 01 includes a first switch M1, a first driver stage circuit 10, a second switch M2, a high-pass filter 20, a logic processing circuit 30, a first voltage input terminal PVDD, The second voltage input terminal VDRIVE, the voltage output terminal Vo, the first switching signal input terminal PWML, and the second switching signal input terminal PWMH.
  • the first switch M1 and the second switch M2 are turned on and off alternately, and by controlling the ratio of the on and off times of the first switch M1 and the second switch M2, the The voltage provided by the first voltage input terminal PVDD is converted into a required voltage and output from the voltage output terminal Vo.
  • the actual working voltage of the first drive stage circuit 10 during the dead time is higher than the voltage provided by the second voltage input terminal VDRIVE during the non-dead time period. Therefore, the feedforward voltage of the first drive stage circuit 10 is the above-mentioned actual working voltage. It will drive the first switch M1 to turn on in advance, compared with the prior art when the first switch M1 is turned off in the dead time, only in the non-dead time, the voltage received by the first switch signal input terminal PWML can be The first driving stage circuit 10 is controlled to receive the voltage provided by the second voltage input terminal VDRIVE and drive the first switch M1 to be turned on.
  • the feedforward effect of the high-pass filter 20 is used to drive the first switch M1 in advance during the dead time.
  • the switch M1 is turned on, thereby effectively reducing the dead time and the dead loss, thereby reducing the loss of the switching circuit 01 and improving the efficiency of the switching circuit 01 .
  • the logic processing circuit 30 can cut off the coupling between the ground terminal f of the first driver stage circuit 10 and the first reference ground GND, high-pass is avoided.
  • the filter 20 raises the voltage provided by the second voltage input terminal VDRIVE and is pulled down and released by the first reference ground GND.
  • the switch circuit 01 provided in the embodiment of the present application can be applied to the high-frequency switch circuit 01, and on the premise of not changing the size of the driver stage circuit, the overcurrent generated by the parasitic inductance L' after the second switch M2 is turned off is used.
  • the surge voltage enhances the driving capability of the first driving stage circuit 10 to the first switch M1 during the dead time, reduces the dead time, and reduces the loss of the switch circuit 01 .
  • the above-mentioned voltage rise of the first voltage input terminal PVDD (also called overshoot) is the result of the second switch M2 being turned off, so the feedforward of the high-pass filter 20 can ensure that the second switch M2 must be After disconnection, the first driver circuit 10 of the first switch M1 introduces the energy and then turns on the first switch M1. Therefore, in any extreme case, the first switch M1 and the second switch M2 will not be turned on at the same time.
  • the risk of punch-through that is, the risk of power burnout.
  • the above-mentioned high-pass filter 20 includes a first capacitor C1 and a first resistor R1 ; the first capacitor C1 is coupled to the first voltage input terminal PVDD and the first drive stage circuit 10 . Between the second input terminals g; the first resistor R1 is coupled between the second voltage input terminal VDRIVE and the second input terminal g of the first driving stage circuit 10 .
  • the energy of the parasitic inductance L' raises the voltage of the first voltage input terminal PVDD.
  • the high-pass filter 20 includes the first capacitor C1
  • the feedforward action of the first capacitor C1 in the high-pass filter 20 can raise the voltage at point n, and provide To the first driving stage circuit 10, the actual working voltage of the first driving stage circuit 10 is raised, higher than the voltage provided by the second voltage input terminal VDRIVE controlled by its previous stage, so the first driving stage circuit 10 is in the feedforward Under the action of the voltage, the first switch M1 is driven to be turned on in advance.
  • the above-mentioned switch circuit 01 further includes an inductor L and a third capacitor C3 .
  • the inductor L is coupled between the first node Lx and the voltage output terminal Vo
  • the third capacitor C3 is coupled between the voltage output terminal Vo and the first reference ground GND.
  • One end of the third capacitor C3 is coupled to the voltage output end Vo, and the other end is coupled to the first reference ground GND.
  • an inductor L is coupled between the first node Lx and the voltage output terminal Vo, and the inductor L can play a freewheeling function, so that the voltage output terminal Vo can output a voltage stably, and avoid the voltage output by the voltage output terminal Vo from changing.
  • a third capacitor C3 is coupled between the voltage output terminal Vo and the first reference ground GND, and the third capacitor C3 can play a role of voltage regulation and can reduce the ripple of the output voltage of the voltage output terminal Vo.
  • the above-mentioned first driving stage circuit 10 includes a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a seventh switch M7 and an eighth switch M8;
  • the third switch M3 and the fourth switch M4 are coupled to the second node p (ie, the output terminal p of the first driver stage circuit 10 ); the control terminal LG of the first switch M1 is coupled to the second node p; the third switch M3 is coupled between the output end n of the high-pass filter 20 and the second node p, the fourth switch M4 is coupled between the second node p and the first reference ground GND;
  • the fifth switch M5 is coupled to the second voltage input between the terminal VDRIVE and the control terminal of the third switch M3;
  • the sixth switch M6 is coupled between the control terminal of the third switch M3 and the first reference ground GND; the control terminal of the fifth switch M5 and the control terminal of the sixth switch M6 The terminal is coupled to the first switch signal input terminal
  • the high-pass filter 20 includes a first capacitor C1 and a first resistor R1
  • the first capacitor C1 is coupled between the first voltage input terminal PVDD and the third switch M3
  • the first resistor R1 is coupled between the second voltage input terminal VDRIVE and the third switch M3.
  • the third switch M3 and the fourth switch M4 are used to control the voltage of the control terminal LG of the first switch M1.
  • the fifth switch M5 and the sixth switch M6 are used to control the voltage of the control terminal of the third switch M3, and the seventh switch M7 and the eighth switch M8 are used to control the voltage of the control terminal of the fourth switch M4.
  • the above-mentioned third switch M3, fourth switch M4, fifth switch M5, sixth switch M6, seventh switch M7 and eighth switch M8 are power transistors.
  • the type of the power transistor may be, for example, an insulated gate bipolar transistor, a metal-oxide semiconductor field effect transistor, or a PN junction field effect transistor.
  • the third switch M3 may be a P-type tube, and the fourth switch M4 may be an N-type tube; or the third switch M3 may be an N-type tube, and the fourth switch M4 may be a P-type tube. Since the third switch M3 is coupled between the output terminal n of the high-pass filter 20 and the second node p, and the first input terminal m of the high-pass filter 20 is coupled to the first voltage input terminal PVDD, the high-pass filter 20 The second input terminal o is coupled to the second voltage input terminal VDRIVE, so the third switch M3 is a pull-up transistor (Mpush) in the first driving stage circuit 10 . Since the fourth switch M4 is coupled between the second node p and the first reference ground GND, the fourth switch M4 is a pull-down transistor (Mpull) in the first driving stage circuit 10 .
  • Mpush pull-up transistor
  • Mpull pull-down transistor
  • the fifth switch M5 and the sixth switch M6 coupled to the control end of the third switch M3 may be a P-type tube, and the sixth switch M6 may be an N-type tube; it may also be a fifth switch M5 is an N-type tube, and the sixth switch M6 is a P-type tube.
  • the seventh switch M7 and the eighth switch M8 coupled to the control end of the fourth switch M4 the seventh switch M7 may be a P-type tube, and the eighth switch M8 may be an N-type tube; or the seventh switch M7 may be a N-type tube, the eighth switch M8 is a P-type tube.
  • each switch in the switch circuit 01 will be described below by taking FIG. 6 as an example.
  • the drain of the first switch M1 is coupled to the first node Lx
  • the source is coupled to the first reference ground GND
  • the gate ie, the control terminal
  • the drain of the second switch M2 is coupled to the first voltage terminal PVDD
  • the source is coupled to the first node Lx
  • the gate is coupled to the second switch signal input terminal PWMH.
  • the source of the third switch M3 is coupled to the first capacitor C1, and the drain is coupled to the second node p.
  • the drain of the fourth switch M4 is coupled to the second node p, and the source is coupled to the first reference ground GND.
  • the source of the fifth switch M5 is coupled to the second voltage input terminal VDRIVE, the drain is coupled to the gate of the third switch M3, and the gate is coupled to the first switch signal input terminal PWML.
  • the drain of the sixth switch M6 is coupled to the gate of the third switch M3, the source is coupled to the first reference ground GND, and the gate is coupled to the first switch signal input terminal PWML.
  • the source of the seventh switch M7 is coupled to the second voltage input terminal VDRIVE, the drain is coupled to the gate of the fourth switch M4 , and the gate is coupled to the output terminal e of the logic processing circuit 30 .
  • the drain of the eighth switch M8 is coupled to the gate of the fourth switch M4 , the source is coupled to the first reference ground GND, and the gate is coupled to the output terminal e of the logic processing circuit 30 .
  • the connection relationship between the source and the drain of the switch changes accordingly.
  • the second switch M2 is a P-type transistor
  • the source of the second switch M2 is coupled to the first voltage terminal PVDD
  • the drain is coupled to the first node Lx.
  • the logic processing circuit 30 includes a flip-flop (also called a D flip-flop) 301 and an OR gate 302; the second switch signal input terminal PWMH and the clock terminal CLK of the flip-flop 301 ( The clock terminal CLK is coupled to the second input terminal i) of the logic processing circuit 30; the reset terminal RESET of the flip-flop 301 is coupled to the first switching signal input terminal PWML; Indicated by "1") or fixed low level (represented by "0") input terminal D; the output terminal of the flip-flop 301 is coupled to the first input terminal of the OR gate 302, and the second input terminal of the OR gate 302 (The second input terminal of the OR gate 302 is the first input terminal h of the logic processing circuit 30 ) is coupled to the first switch signal input terminal PWML, and the output terminal of the OR gate 302 (the output terminal of the OR gate 302 is the logic processing circuit 30 ) The output terminal e) of the first driving stage circuit 10 is coupled to the first input terminal
  • the first driving stage circuit 10 includes the third switch M3, the fourth switch M4, the fifth switch M5, the sixth switch M6, the seventh switch M7 and the eighth switch M8, the output terminal of the OR gate 302 and the seventh switch M8
  • the control terminals of the switch M7 and the eighth switch M8 are coupled.
  • Fig. 7a takes the input terminal D of the flip-flop 301 for receiving a high level (represented by "1") as an example.
  • a high level represented by "1"
  • the output terminal of the flip-flop 301 will be triggered according to the rising edge of the signal provided by the second switching signal input terminal PWMH received by the clock terminal CLK, that is, when the first switching signal is received by the clock terminal CLK.
  • the signal EN-FF output by the output terminal of the flip-flop 301 is a high-level signal;
  • the received signal provided by the second switch signal input terminal PWMH is triggered by the falling edge, that is, when the signal provided by the second switch signal input terminal PWMH changes from a high level to a low level, the output terminal of the flip-flop 301 outputs the signal EN-FF is a high level signal.
  • the logic processing circuit 30 further includes a fourth inverter 303 , and the second switching signal input terminal PWMH is coupled to the clock terminal CLK of the flip-flop 301 through the fourth inverter 303 .
  • the input end of the fourth inverter 303 (the input end of the fourth inverter 303 is the second input end i of the logic processing circuit 30 ) is coupled to the second switching signal input end PWMH, and the fourth inverter The output terminal of 303 is coupled to the clock terminal CLK.
  • the logic processing circuit 30 includes a fourth inverter
  • the fourth inverter 303 can invert the signal provided by the second switch signal input terminal PWMH, so when the signal provided by the second switch signal input terminal PWMH changes from high level to low level, the flip-flop 301 The output terminal of the flip-flop 301 will be triggered according to the rising edge of the clock terminal CLK, so that the signal EN-FF output by the output terminal of the flip-flop 301 is a high-level signal.
  • the fourth inverter 303 can invert the signal provided by the second switch signal input terminal PWMH, so when the signal provided by the second switch signal input terminal PWMH changes from low level to high level, The output terminal of the flip-flop 301 is triggered according to the falling edge of the clock terminal CLK, so that the signal EN-FF output by the output terminal of the flip-flop 301 is a high-level signal.
  • the reset terminal RESET of the flip-flop 301 is coupled to the first switch signal input terminal PWML, when the signal provided by the first switch signal input terminal PWML changes from a low level to a high level, or from a high level When the level changes to a low level, the signal EN-FF output by the output terminal of the flip-flop 301 returns to a low level signal.
  • the operation process of the switch circuit 01 shown in FIG. 7b will be described below with reference to the timing diagram shown in FIG. 8 .
  • the first switch M1 and the second switch M2 are both N-type transistors
  • the third switch M3 is a P-type transistor
  • the fourth switch M4 is an N-type transistor
  • the fifth switch M5 is a P-type transistor
  • the sixth switch M6 is an N-type tube
  • the seventh switch M7 is a P-type tube
  • the eighth switch M8 is an N-type tube, for example.
  • the first voltage terminal PVDD The voltage of PVDD is overshoot (also referred to as raising), so the voltage at point m is raised.
  • the first capacitor (also referred to as feedforward capacitor) C1 in the high-pass filter 20 simultaneously pulls up the voltage at point n.
  • the voltage VDRIVE' at point n is greater than the voltage VDRIVE provided by the second voltage terminal VDRIVE.
  • the signal received by the first switch signal input terminal PWML is the low-level signal VL. Since the fifth switch M5 is a P-type transistor and the sixth switch M6 is an N-type transistor, the fifth switch M5 is turned on, and the sixth switch M5 is turned on.
  • the switch M6 is turned off, and the voltage VDRIVE provided by the second voltage terminal VDRIVE is provided to the control terminal of the third switch M3 through the fifth switch M5.
  • the voltage of the pole) (that is, the voltage VDRIVE' of the n point) is greater than the voltage of the g pole (that is, the control terminal or the gate), so the third switch M3 will be turned on instantly, and the voltage VDRIVE' that has been raised at the n point passes through
  • the third switch M3 is provided to the second node p, and the second node p is coupled to the control terminal LG of the first switch M1, and the first switch M1 is an N-type transistor, so the first switch M1 is turned on in advance.
  • the shaded part in the waveform diagram of the signal received by the first node Lx represents the power consumption that can be reduced by the switch circuit 01 provided by the embodiment of the present application compared to the switch circuit 01 provided by the prior art.
  • the first switch M1 is turned on in advance because the second switch M2 is turned off, and the voltage of the first voltage terminal PVDD overshoots, and then the first capacitor C1 in the high-pass filter 20 is in front of the first capacitor C1 .
  • the feed-in effect causes the voltage of the n point to rise, so although the first switch M1 will be turned on in advance, the first switch M1 and the second switch M2 will not have the risk of being turned on at the same time under any circumstances.
  • the output terminal of the flip-flop 301 in the logic processing circuit 30 will be down according to the signal provided by the second switching signal input terminal PWMH received by the clock terminal CLK.
  • the signal EN-FF output from the output end of the flip-flop 301 is a high-level dead-time signal.
  • one input end of the OR gate 302 in the logic processing circuit 30 receives the signal EN-FF output from the output end of the flip-flop 301 as a high level signal VH, and the other input end receives the first switch signal input end PWML A low-level signal VL is provided, so the output terminal of the OR gate 302 outputs a high-level signal. Since the control terminals of the seventh switch M7 and the eighth switch M8 are both coupled to the output terminal of the OR gate 302, the seventh switch M7 is a P-type transistor, and the eighth switch M8 is an N-type transistor. At this time, the seventh switch M7 is turned off.
  • the eighth switch M8 is turned on, and the voltage of the first reference ground GND is provided to the control terminal of the fourth switch M4 through the eighth switch M8, so as to control the fourth switch M4 to be turned off. In this way, the first reference ground is avoided.
  • the voltage of GND is provided to the second node p through the fourth switch M4. At this time, the voltage of the second node p is pulled down from low resistance to high resistance, which ensures that the overshoot energy passed through after the third switch M3 is turned on will not be destroyed.
  • the fourth switch M4 is discharged to the ground, and the voltage of the second node p remains elevated, so that the first switch M1 is turned on in advance, reducing the actual dead time.
  • the signal EN-FF output by the output terminal of the flip-flop 301 returns to the low-level signal VL. Since one input terminal of the OR gate 302 receives the low-level signal output by the output terminal of the flip-flop 301, and the other input terminal receives the high-level signal VH provided by the first switch signal input terminal PWML, the output terminal of the OR gate 302 outputs high level signal.
  • the seventh switch M7 is turned off, the eighth switch M8 is turned on, and the voltage of the first reference ground GND is supplied to the control terminal of the fourth switch M4 through the eighth switch M8, thereby controlling the fourth switch M4 to be turned off.
  • the high-level signal VH provided by the first switch signal input terminal PWML controls the sixth switch M6 to be turned on
  • the fifth switch M5 is turned off, and the voltage of the first reference ground GND is supplied to the third switch through the sixth switch M6
  • the control terminal of the switch M3, thereby controlling the third switch M3 to be turned on.
  • the voltage provided by the second voltage input terminal VDRIVE is provided to the second node p through the third switch M3, thereby controlling the first switch M1 to be turned on. It can be seen from this that after the signal received by the first switch signal input terminal PWML is pulled high, the control terminal LG of the first switch M1 continues to be controlled by the signal received by the first switch signal input terminal PWML.
  • the logic processing circuit 30 includes a delay circuit 304 , a first AND gate 305 , a second AND gate 306 , a first inverter 307 , a second inverter 308 and an OR gate 302 .
  • the second switch signal input terminal PWMH is coupled to the first input terminal of the first AND gate 305 through the delay circuit 304 ; here, the input terminal of the delay circuit 304 (the input terminal of the delay circuit 304 is the second input of the logic processing circuit 30 )
  • the terminal i) is coupled to the second switching signal input terminal PWMH, and the output terminal PWMH-D of the delay circuit 304 is coupled to the first input terminal of the first AND gate 305; the second switching signal input terminal PWMH is also passed through the first inversion
  • the inverter 307 is coupled to the second input terminal of the first AND gate 305.
  • the input terminal of the first inverter 307 is coupled to the second switching signal input terminal PWMH, and the output terminal of the first inverter 307 is coupled to the second switching signal input terminal PWMH.
  • the second input terminal of an AND gate 305 is coupled; the output terminal PPH of the first AND gate 305 is coupled to the first input terminal of the second AND gate 306 , and the first switching signal input terminal PWML is connected to the first input terminal PWML through the second inverter 308
  • the second input terminal of the second AND gate 306 is coupled, here, the input terminal of the second inverter 308 is coupled to the first switching signal input terminal PWML, and the output terminal of the second inverter 308 is coupled to the second AND gate 306 is coupled to the second input terminal, and the output terminal of the second AND gate 306 is coupled to the first input terminal of the OR gate 302; the second input terminal of the OR gate 302 (the second input terminal of the OR gate 302 is a logic processing circuit)
  • the above-mentioned delay circuit 304 includes n third inverters connected in series; wherein, n ⁇ 2, and n is a positive even number.
  • the n third inverters connected in series can delay the signal received by the second switching signal input end PWMH for a certain period of time and then output the signal.
  • the above-mentioned delay circuit 304 includes a second capacitor C2 and a second resistor R2 connected in series.
  • the second capacitor C2 and the second resistor R2 connected in series can delay the signal received by the second switch signal input terminal PWMH for a certain period of time and then output it.
  • the operation process of the switch circuit 01 shown in FIG. 9 will be described below with reference to the timing diagram shown in FIG. 10 .
  • the first switch M1 and the second switch M2 are both N-type transistors
  • the third switch M3 is a P-type transistor
  • the fourth switch M4 is an N-type transistor
  • the fifth switch M5 is a P-type transistor
  • the sixth switch M6 is an N-type tube
  • the seventh switch M7 is a P-type tube
  • the eighth switch M8 is an N-type tube, for example.
  • the first switch signal input terminal PWML receives Before the signal VL is changed from a low level to a high level signal VH, the process of supplying the raised voltage VDRIVE' at the n point to the second node p through the third switch M3 is similar to the first implementation, here No longer.
  • the signal received by the second switch signal input terminal PWMH changes from the high-level signal VH to the low-level signal VL, that is, after the second switch M2 is turned off
  • the signal received by the first switch signal input terminal PWML is Before the low-level signal VL becomes the high-level signal VH
  • the output terminal PWMH-D of the delay circuit 304 outputs the high-level signal VH
  • the second switch signal input terminal PWMH outputs the high-level signal VH.
  • the signal received by the switch signal input terminal PWMH passes through the first inverter 307 and outputs a high-level signal VH; an input terminal of the first AND gate 305 receives the high-level signal VH output by the output terminal PWMH-D of the delay circuit 304, The other input terminal receives the high-level signal VH output by the first inverter 307, the output terminal PPH of the first AND gate 305 outputs the high-level signal VH; the input terminal of the second inverter 308 receives the first switch signal input The low-level signal VL received by the terminal PWML, the output terminal of the second inverter 308 outputs the high-level signal VH; an input terminal of the second AND gate 306 receives the high level output by the output terminal PPH of the first AND gate 305.
  • the other input terminal of the signal VH receives the high-level signal VH output by the output terminal of the second inverter 308 , and the signal EN-FF outputted by the output terminal of the second AND gate 306 is the high-level signal VH.
  • one input terminal of the OR gate 302 receives the signal EN-FF output from the output terminal of the second AND gate 306 as a high level signal VH, and the other input terminal receives the low voltage provided by the first switch signal input terminal PWML Therefore, the output terminal of the OR gate 302 outputs a high-level signal.
  • the seventh switch M7 and the eighth switch M8 are both coupled to the output terminal of the OR gate 302
  • the seventh switch M7 is a P-type transistor
  • the eighth switch M8 is an N-type transistor. At this time, the seventh switch M7 is turned off.
  • the eighth switch M8 is turned on, and the voltage of the first reference ground GND is provided to the control terminal of the fourth switch M4 through the eighth switch M8, so as to control the fourth switch M4 to be turned off. In this way, the first reference ground is avoided.
  • the voltage of GND is provided to the second node p through the fourth switch M4.
  • the voltage of the second node p is pulled down from a low resistance to a high resistance, so as to ensure that the overshoot energy passed through after the third switch M3 is turned on will not be destroyed by the third switch M3.
  • the four switches M4 are discharged to the ground, and the voltage of the second node p remains elevated, so that the first switch M1 is turned on in advance, reducing the actual dead time.
  • the control terminal LG of the first switch M1 continues to be controlled by the signal received by the first switch signal input terminal PWML. Specifically, Reference may be made to the above-mentioned embodiments, which will not be repeated here.
  • logic processing circuit 30 includes but is not limited to the above-mentioned first implementation manner and second implementation manner.
  • the above-mentioned switch circuit 01 may further include a second driving stage circuit 40 ; the control terminal HG of the second switch M2 is driven by the second The stage circuit 40 is coupled to the second switch signal input terminal PWMH.
  • the first input terminal q of the second driving stage circuit 40 is coupled to the second switching signal input terminal PWMH, and the output terminal s of the second driving stage circuit 40 is coupled to the control terminal HG of the second switch M2.
  • the above-mentioned switch circuit 01 further includes a third voltage input terminal VDRIVE-HG and a second reference ground GND-HG, and the second input terminal t of the second driving stage circuit 40 It is coupled to the third voltage input terminal VDRIVE-HG, and the ground terminal u of the second driving stage circuit 40 is coupled to the second reference ground GND-HG.
  • control terminal HG of the second switch M2 is coupled to the second driving stage circuit 40, the driving capability of the control terminal HG of the second switch M2 can be improved, and the turn-on or turn-off time of the second switch M2 can be reduced.
  • the structure of the second driving stage circuit 40 and the structure of the first driving stage circuit 10 may be the same or different.
  • the above-mentioned switch circuit 01 further includes a third voltage input terminal VDRIVE-HG and a second reference ground GND-HG
  • the above-mentioned second driver stage circuit 40 further includes a ninth switch M9, a tenth switch M9, and a tenth switch M9.
  • the ninth switch M9 is coupled between the third voltage input terminal VDRIVE-HG and the control terminal HG of the second switch M2, and the tenth switch M10 is coupled between the control terminal HG of the second switch M2 and the second reference ground GND-HG between.
  • the eleventh switch M11 is coupled between the third voltage input terminal VDRIVE-HG and the control terminal of the ninth switch M9; the twelfth switch M12 is coupled between the control terminal of the ninth switch M9 and the second reference ground GND-HG between; the control end of the eleventh switch M11 and the control end of the twelfth switch M12 are both coupled to the second switch signal input end PWMH.
  • the thirteenth switch M13 is coupled between the third voltage input terminal VDRIVE-HG and the control terminal of the tenth switch M10; the fourteenth switch M14 is coupled between the control terminal of the tenth switch M10 and the second reference ground GND-HG between; the control terminal of the thirteenth switch M13 and the control terminal of the fourteenth switch M14 are both coupled to the second switch signal input terminal PWMH.
  • the ninth switch M9 is a pull-up transistor in the second driving stage circuit 40
  • the tenth switch M10 is a pull-down transistor in the second driving stage circuit 40
  • the ninth switch M9 and the tenth switch M10 are used to The voltage of the control terminal HG of the switch M2 is controlled.
  • the eleventh switch M11 and the twelfth switch M12 are used to control the voltage of the control terminal of the ninth switch M9
  • the thirteenth switch M13 and the fourteenth switch M14 are used to control the voltage of the control terminal of the tenth switch M10.
  • the ninth switch M9, the tenth switch M10, the eleventh switch M11, the twelfth switch M12, the thirteenth switch M13 and the fourteenth switch M14 are power transistors.
  • the type of the power transistor may be, for example, an insulated gate bipolar transistor, a metal-oxide semiconductor field effect transistor, or a PN junction field effect transistor.
  • the ninth switch M9, the tenth switch M10, the eleventh switch M11, the twelfth switch M12, the thirteenth switch M13 and the fourteenth switch M14 may be N-type transistors or P-type transistors .
  • the ninth switch M9 is a P-type transistor
  • the tenth switch M10 is an N-type transistor
  • the eleventh switch M11 is a P-type transistor
  • the twelfth switch M12 is an N-type transistor
  • the thirteenth switch M13 is a P-type tube
  • the fourteenth switch M14 is an N-type tube, for example, to illustrate the working process of the second driving stage circuit 40 .
  • the eleventh switch M11 and the thirteenth switch M13 are both turned off, the twelfth switch M12 and the fourteenth switch M14 are both turned on, and the thirteenth switch M11 and the thirteenth switch M14 are both turned on.
  • the voltage provided by the second reference ground GND-HG is input to the control terminal of the ninth switch M9 through the twelfth switch M12, thereby controlling the ninth switch M9 to be turned on.
  • the voltage provided by the second reference ground GND-HG passes through the fourteenth switch M9.
  • the switch M14 is input to the control terminal of the tenth switch M10, thereby controlling the tenth switch M10 to be turned off.
  • the ninth switch M9 Since the ninth switch M9 is turned on and the tenth switch M10 is turned off, the voltage provided by the third voltage input terminal VDRIVE-HG is input to the control terminal HG of the second switch M2 through the ninth switch M9, thereby controlling the second switch M2 to conduct Pass. It can be known from this that when the voltage provided by the second switch signal input terminal PWMH is the high-level signal VH, the second switch M2 is turned on.
  • the eleventh switch M11 and the thirteenth switch M13 are both turned on, the twelfth switch M12 and the fourteenth switch M14 are both turned off, and the thirteenth switch M11 and the thirteenth switch M14 are both turned off.
  • the voltage provided by the third voltage input terminal VDRIVE-HG is input to the control terminal of the ninth switch M9 through the eleventh switch M11, thereby controlling the ninth switch M9 to be turned off.
  • the voltage provided by the third voltage input terminal VDRIVE-HG passes through the The thirteen switches M13 are input to the control terminal of the tenth switch M10, thereby controlling the tenth switch M10 to be turned on.
  • the ninth switch M9 is turned off and the tenth switch M10 is turned on, the voltage provided by the second reference ground GND-HG is input to the control terminal HG of the second switch M2 through the tenth switch M10, thereby controlling the second switch M2 to be turned off . It can be known from this that when the voltage provided by the second switch signal input terminal PWMH is the low level signal VL, the second switch M2 is turned off.
  • the second switch M2 can be controlled to be turned on or off.
  • the embodiment of the present application further provides a switch circuit 01.
  • the main structure of the switch circuit 01 is shown in FIG. 7a, including a first switch M1, a first driver stage circuit 10, a second switch M2, a high-pass filter 20, and a logic processing
  • the circuit 30 a first voltage input terminal PVDD, a second voltage input terminal VDRIVE, a voltage output terminal Vo, a first switching signal input terminal PWML, a second switching signal input terminal PWMH, and a first reference ground GND.
  • the first switch M1 is coupled between the first node Lx and the first reference ground GND; the control terminal LG of the first switch M1 is coupled to the output terminal p of the first driving stage circuit 10 ; the grounding of the first driving stage circuit 10
  • the terminal f is coupled to the first reference ground GND.
  • the second switch M2 is coupled between the first voltage input terminal PVDD and the first node Lx; the control terminal HG of the second switch M2 is coupled to the second switch signal input terminal PWMH.
  • the first input terminal m of the high-pass filter 20 is coupled to the first voltage input terminal PVDD, the second input terminal o of the high-pass filter 20 is coupled to the second voltage input terminal VDRIVE, and the output terminal n of the high-pass filter 20 is coupled to the first voltage input terminal VDRIVE.
  • the second input terminal g of a driver stage circuit 10 is coupled.
  • the logic processing circuit 30 includes a flip-flop 301 and an OR gate 302; the second switch signal input terminal PWMH is coupled to the clock terminal CLK of the flip-flop 301; the reset terminal RESET of the flip-flop 301 is coupled to the first switch signal input terminal PWML;
  • the device 301 also includes an input terminal D for receiving a fixed high level or a fixed low level; the output terminal of the flip-flop 301 is coupled to the first input terminal of the OR gate 302, and the second input terminal of the OR gate 302 is connected to the first input terminal of the OR gate 302.
  • the switch signal input terminal PWML is coupled, and the output terminal of the OR gate 302 is coupled to the first input terminal d of the first driving stage circuit 10 .
  • the logic processing circuit 30 further includes a fourth inverter 303 , and the second switching signal input terminal PWMH is coupled to the clock terminal CLK of the flip-flop 301 through the fourth inverter 303 .
  • the above-mentioned switch circuit 01 may further include a second driver stage circuit 40 ; the control terminal HG of the second switch M2 is coupled to the second switch signal input terminal PWMH through the second driver stage circuit 40 .
  • first driving stage circuit 10 the high-pass filter 20 and the second driving stage circuit 40
  • other structures of the switch circuit can all refer to the above-mentioned embodiments, which will not be repeated here. .
  • the embodiment of the present application also provides a switch circuit 01.
  • the main structure of the switch circuit 01 is shown in FIG. 9, including a first switch M1, a first driver stage circuit 10, a second switch M2, a high-pass filter 20, and a logic processing
  • the circuit 30 a first voltage input terminal PVDD, a second voltage input terminal VDRIVE, a voltage output terminal Vo, a first switching signal input terminal PWML, a second switching signal input terminal PWMH, and a first reference ground GND.
  • the first switch M1 is coupled between the first node Lx and the first reference ground GND; the control terminal LG of the first switch M1 is coupled to the output terminal p of the first driving stage circuit 10 ; the grounding of the first driving stage circuit 10
  • the terminal f is coupled to the first reference ground GND.
  • the second switch M2 is coupled between the first voltage input terminal PVDD and the first node Lx; the control terminal HG of the second switch M2 is coupled to the second switch signal input terminal PWMH.
  • the first input terminal m of the high-pass filter 20 is coupled to the first voltage input terminal PVDD
  • the second input terminal o of the high-pass filter 20 is coupled to the second voltage input terminal VDRIVE
  • the output terminal n of the high-pass filter 20 is coupled to the first voltage input terminal VDRIVE.
  • the second input terminal g of a driver stage circuit 10 is coupled.
  • the logic processing circuit 30 includes a delay circuit 304 , a first AND gate 305 , a second AND gate 306 , a first inverter 307 , a second inverter 308 , and an OR gate 302 .
  • the second switch signal input terminal PWMH is coupled to the first input terminal of the first AND gate 305 through the delay circuit 304 ; the second switch signal input terminal PWMH is also connected to the second input terminal of the first AND gate 305 through the first inverter 307
  • the output terminal PPH of the first AND gate 305 is coupled to the first input terminal of the second AND gate 306, and the first switching signal input terminal PWML passes through the second inverter 308 and the second AND gate 306.
  • the input terminal is coupled, and the output terminal of the second AND gate 306 is coupled to the first input terminal of the OR gate 302; the second input terminal of the OR gate 302 is coupled to the first switching signal input terminal PWML, and the output terminal of the OR gate 302 It is coupled to the first input terminal d of the first driving stage circuit 10 .
  • the above-mentioned switch circuit 01 may further include a second driver stage circuit 40 ; the control terminal HG of the second switch M2 is coupled to the second switch signal input terminal PWMH through the second driver stage circuit 40 .
  • first driving stage circuit 10 the high-pass filter 20 , the second driving stage circuit 40 and the delay circuit 304 , other structures of the switch circuit, and the types of each switch can all refer to the above-mentioned embodiments. It is not repeated here.
  • the embodiment of the present application further provides a power supply chip, and the power supply chip includes the above-mentioned switch circuit 01 .
  • the power supply chip provided in the embodiments of the present application can be applied to any electronic device, such as a mobile phone, a tablet computer, a wearable device (such as a smart watch), and the like.
  • the first driving stage circuit 10 , the high-pass filter 20 , the logic processing circuit 30 , the third capacitor C3 and the second driving circuit 40 in the switch circuit 01 can be integrated on one power supply chip.
  • the first switch M1, the second switch M2, and the inductor L may be integrated on the power supply chip, or may be disposed outside the power supply chip.
  • the logic for outputting the first switching signal PWML and the second switching signal PWMH may be integrated on the power supply chip, or may be integrated on other chips.

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Abstract

本申请实施例提供一种开关电路及开关电源，涉及电子电路技术领域，可以减小死区时间，降低死区损耗，进而降低开关电路的损耗。该开关电路中第一开关耦接于第一节点和第一参考地之间；第一开关的控制端与第一驱动级电路的输出端耦接；第一驱动级电路的第一输入端与逻辑处理电路的输出端耦接，接地端与第一参考地耦接；第二开关耦接于第一电压输入端和第一节点之间；第二开关的控制端与第二开关信号输入端耦接；高通滤波器的第一输入端与第一电压输入端耦接，第二输入端与第二电压输入端耦接，输出端与第一驱动级电路的第二输入端耦接；逻辑处理电路用于在第二开关断开之后，第一开关导通之前，切断第一驱动级电路的接地端与第一参考地的耦接。

Description

一种开关电路及开关电源 技术领域
本申请涉及电子电路技术领域，尤其涉及一种开关电路及开关电源。
背景技术
目前，在开关电路中，可以通过控制多个开关导通和断开的时间比例将输入电压转换成稳定的输出电压。现有技术中，开关电路01的结构如图1所示，包括第一功率管S1、第二功率管S2、第一功率管驱动级电路1、第二功率管驱动级电路2、电感L、电容C、电压输入端Vin、电压输出端Vo、第一开关信号输入端PWML以及第二开关信号输入端PWMH，第一功率管S1包括第一寄生二极管D1，第二功率管S2包括第二寄生二级管D2。其中，第一功率管S1为N型管，第二功率管S2为P型管，第一功率管S1和第二功率管S2耦接于开关节点Lx；第一功率管S1耦接于开关节点Lx和参考地GND之间；第二功率管S2耦接于电压输入端Vin和开关节点Lx之间；第一功率管S1的控制端通过第一功率管驱动级电路1与第一开关信号输入端PWML耦接；第二功率管S2的控制端通过第二功率管驱动级电路2与第二开关信号输入端PWMH耦接；电感L耦接于开关节点Lx和电压输出端Vo之间，电容C耦接于电压输出端Vo和参考地GND之间。
图2为图1所示的开关电路01的信号的波形图。第一开关信号输入端PWML接收高电平信号时，第一功率管S1导通，第二开关信号输入端PWMH接收低电平信号时，第二功率管S2导通。结合图1和图2，通过控制第一功率管S1和第二功率管S2交替导通和断开的时间比例，从而可以将电压输入端Vin提供的电压输出给电压输出端Vo。为了避免开关电路01中第一功率管S1和第二功率管S2在开关过程中同时导通造成电压输入端Vin和参考地GND直接连接，进而导致与电压输入端Vin连接的电源烧毁，因此参考图2，通常在第一功率管S1和第二功率管S2的交替导通和断开过程中有一段同时断开的时间，将第一功率管S1和第二功率管S2同时断开的时间称为死区时间。在死区时间内，开关节点Lx的电压逐渐降低，当开关节点Lx的电压降低到一定值时，第一寄生二级管D1导通，电感L电流依靠第一寄生二级管D1续流，以保证电压输出端Vo稳定地输出电压。
然而，由于寄生二极管的导通压降(例如0.7V左右)远大于功率管的导通压降(例如10mV)，因此在流过相同的电流时，第一寄生二级管D1损失的功率相对于功率管损失的功率有几个数量级的差异，这样一来，第一寄生二级管D1的导通损耗极大地增加了开关电路01的损耗。此外，随着开关电路01开关频率的增加，死区时间的占比也随之增加，因此死区损耗成为高频开关电路的主要损耗之一。
发明内容
本申请实施例提供一种开关电路及开关电源，可以减小死区时间，降低死区损耗，进而降低开关电路的损耗。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种开关电路。该开关电路包括：第一开关、第一驱动级电路、第二开关、高通滤波器、逻辑处理电路、第一电压输入端、第二电压输入端、电压输出端、第一开关信号输入端、第二开关信号输入端以及第一参考地。第一开关耦接于第一节点和第一参考地之间；第一开关的控制端与第一驱动级电路的输出端耦接；第一驱动级电路的第一输入端与逻辑处理电路的输出端耦接，第一驱动级电路的接地端与第一参考地耦接；第二开关耦接于第一电压输入端和第一节点之间；第二开关的控制端与第二开关信号输入端耦接；高通滤波器的第一输入端与第一电压输入端耦接，高通滤波器的第二输入端与第二电压输入端耦接，高通滤波器的输出端与第一驱动级电路的第二输入端耦接；逻辑处理电路的第一输入端与第一开关信号输入端耦接，逻辑处理电路的第二输入端与第二开关信号输入端耦接；逻辑处理电路用于在第二开关断开之后，第一开关导通之前，切断第一驱动级电路的接地端与第一参考地的耦接；第一节点和电压输出端耦接。在该开关电路的工作过程中，第一开关和第二开关交替导通和断开，通过控制第一开关和第二开关导通和断开的时间的比例，从而可以将第一电压输入端提供的电压转化为所需求的电压从电压输出端输出。此外，在第一开关和第二开关交替导通和断开的过程中，在第二开关断开的瞬间，第一开关导通之前，第一电压输入端和第二开关之间产生的寄生电感的能量在抬高第一电压输入端的电压的同时，由于开关电路包括高通滤波器，高通滤波器与第一电压输入端耦接，因而高通滤波器的前馈作用会使得高通滤波器将第二电压输入端提供的电压抬高后提供给第一驱动级电路的第二输入端，这样一来，第一驱动级电路在死区时间内的实际工作电压冲高，高于非死区时间内第二电压输入端提供的电压，因此第一驱动级电路在该前馈电压即上述实际工作电压的作用下会提前驱动第一开关导通，相对于现有技术在死区时间内第一开关断开，只有在非死区时间内，第一开关信号输入端接收的电压才可以控制第一驱动级电路接收第二电压输入端提供的电压，驱动第一开关导通，而本申请实施例在死区时间内，利用高通滤波器的前馈作用提前驱动第一开关导通，从而有效减小死区时间，降低死区损耗，进而降低开关电路的损耗，提升开关电路的效率。在此基础上，在第二开关断开，第一开关导通之前，由于逻辑处理电路可以将第一驱动级电路的接地端与第一参考地的耦接切断，因而避免了高通滤波器将第二电压输入端提供的电压抬高后被第一参考地下拉释放掉。
在一种可能的实施方式中，高通滤波器包括第一电容和第一电阻；第一电容耦接于第一电压输入端和第一驱动级电路的第二输入端之间；第一电阻耦接于第二电压输入端和第一驱动级电路的第二输入端之间。在第二开关断开的瞬间，第一开关导通之前，寄生电感的能量抬高第一电压输入端的电压，此时，第一电容的两端中与第一电压输入端连接的一端的电压抬高，大于第一电压输入端的电压，与此同时，由于高通滤波器包括第一电容，因而通过高通滤波器中第一电容的前馈作用可以将第一电容的另一端的电压抬高，并提供给第一驱动级电路，这样第一驱动级电路的实际工作电压抬高，高于其前级控制的第二电压输入端提供的电压，因此第一驱动级电路在该前馈电压的作用下会提前驱动第一开关导通。
在一种可能的实施方式中，逻辑处理电路包括触发器以及或门；第二开关信号输入端与触发器的时钟端耦接；触发器的复位端与第一开关信号输入端耦接；触发器还包括 用于接收固定高电平或固定低电平的输入端；触发器的输出端与或门的第一输入端耦接，或门的第二输入端与第一开关信号输入端耦接，或门的输出端与第一驱动级电路的第一输入端耦接。当触发器包括用于接收固定高电平的输入端时，触发器的输出端会根据时钟端接收到的第二开关信号输入端提供的信号的上升沿或下降沿触发，触发器的输出端输出的信号的高电平信号。当触发器包括用于接收固定低电平的输入端时，触发器的输出端会根据时钟端接收到的第二开关信号输入端提供的信号的上升沿或下降沿触发，触发器的输出端输出的信号的低电平信号。此外，由于触发器的复位端与第一开关信号输入端耦接，因而当第一开关信号输入端提供的信号由低电平变为高电平，或者由高电平变为低电平时，触发器的输出端输出的信号又恢复为之前的信号。或门的输出端会根据其第一输入端和第二输入端的信号向第一驱动级电路的第一输入端输出相应的信号，以切断第一驱动级电路的接地端与第一参考地的耦接。
在一种可能的实施方式中，逻辑处理电路包括延迟电路、第一与门、第二与门、第一反相器、第二反相器以及或门；第二开关信号输入端通过延迟电路与第一与门的第一输入端耦接，第二开关信号输入端还通过第一反相器与第一与门的第二输入端耦接；第一与门的输出端与第二与门的第一输入端耦接，第一开关信号输入端通过第二反相器与第二与门的第二输入端耦接，第二与门的输出端与或门的第一输入端耦接；或门的第二输入端与第一开关信号输入端耦接，或门的输出端与第一驱动级电路的第一输入端耦接。以第二开关信号输入端接收的信号由高电平信号变为低电平信号后，第一开关信号输入端接收的信号由低电平信号变为高电平信号之前为例，第二开关信号输入端接收的信号经过延迟电路后，延迟电路的输出端输出高电平信号，同时，第二开关信号输入端接收的信号经过第一反相器后输出高电平信号；第一与门的一个输入端接收延迟电路的输出端输出的高电平信号，另一个输入端接收第一反相器输出的高电平信号，因此第一与门的输出端输出高电平信号；第二反相器的输入端接收第一开关信号输入端接收的低电平信号，第二反相器的输出端输出高电平信号；第二与门的一个输入端接收第一与门的输出端输出的高电平信号，另一个输入端接收第二反相器的输出端输出的高电平信号，第二与门的输出端输出的信号为高电平信号。在此时间内，或门的一个输入端接收第二与门的输出端输出的高电平信号，另一个输入端接收第一开关信号输入端提供的低电平信号，因此或门的输出端输出高电平信号，该高电平信号可以控制第一驱动级电路的接地端和第一参考地的耦接切断。
在一种可能的实施方式中，延迟电路包括依次串联的n个第三反相器；其中，n≥2，n为正偶数。此处，依次串联的n个第三反相器可以将第二开关信号输入端接收的信号延迟一定时间后输出。
在一种可能的实施方式中，延迟电路包括串联的第二电容和第二电阻。此处，串联的第二电容和第二电阻可以将第二开关信号输入端接收的信号延迟一定时间后后输出。
在一种可能的实施方式中，第一驱动级电路包括第三开关、第四开关、第五开关、第六开关、第七开关和第八开关；第三开关和第四开关耦接于第二节点；第一开关的控制端耦接于第二节点；第三开关耦接于高通滤波器的输出端和第二节点之间，第四开关耦接于第二节点和第一参考地之间；第五开关耦接于第二电压输入端和第三开关的控制端之间；第六开关耦接于第三开关的控制端和第一参考地之间；第五开关的控制端和第 六开关的控制端耦接于第一开关信号输入端；第七开关耦接于第二电压输入端和第四开关的控制端之间；第八开关耦接于第四开关的控制端和第一参考地之间；第七开关的控制端和第八开关的控制端耦接于逻辑处理电路的输出端。其中，第三开关为第一驱动级电路中的上拉管，第四开关为第一驱动级电路中的下拉管，第三开关和第四开关用于对第一开关的控制端的电压进行控制。第五开关和第六开关用于对第三开关的控制端的电压进行控制，第七开关和第八开关用于对第四开关的控制端的电压进行控制。
在一种可能的实施方式中，开关电路还包括第二驱动级电路；第二开关的控制端通过第二驱动级电路与第二开关信号输入端耦接。由于第二开关的控制端与第二驱动级电路耦接，因而可以提高第二开关的控制端的驱动能力，降低第二开关导通或断开的时间。
在一种可能的实施方式中，开关电路还包括第三电压输入端和第二参考地，第二驱动级电路还包括第九开关、第十开关、第十一开关、第十二开关、第十三开关以及第十四开关。第九开关耦接于第三电压输入端和第二开关的控制端之间，第十开关耦接于第二开关的控制端和第二参考地之间。第十一开关耦接于第三电压输入端和第九开关的控制端之间；第十二开关耦接于第九开关的控制端和第二参考地之间；第十一开关的控制端和第十二开关的控制端均耦接于第二开关信号输入端。第十三开关耦接于第三电压输入端和第十开关的控制端之间；第十四开关耦接于第十开关的控制端和第二参考地之间；第十三开关的控制端和第十四开关的控制端均耦接于第二开关信号输入端。其中，第九开关为第二驱动级电路中的上拉管，第十开关为第二驱动级电路中的下拉管，第九开关和第十开关用于对第二开关的控制端的电压进行控制。第十一开关和第十二开关用于对第九开关的控制端的电压进行控制，第十三开关和第十四开关用于对第十开关的控制端的电压进行控制。
在一种可能的实施方式中，开关电路还包括电感和第三电容；电感耦接于第一节点和电压输出端之间；第三电容耦接于电压输出端和第一参考地之间。电感能够起到续流作用，使得电压输出端能够稳定地输出电压，避免电压输出端输出的电压高低变化。第三电容可以起到稳压的作用，能够降低电压输出端输出电压高低变化的纹波。
在一种可能的实施方式中，第一开关和第二开关为绝缘栅双极型晶体管、金属-氧化物半导体场效应晶体管或PN结型场效应晶体管。
在一种可能的实施方式中，第三开关、第四开关、第五开关、第六开关、第七开关和第八开关为绝缘栅双极型晶体管、金属-氧化物半导体场效应晶体管或PN结型场效应晶体管。
第二方面，提供一种开关电路。该开关电路包括第一开关、第一驱动级电路、第二开关、高通滤波器、逻辑处理电路、第一电压输入端、第二电压输入端、电压输出端、第一开关信号输入端、第二开关信号输入端以及第一参考地。第一开关耦接于第一节点和第一参考地之间；第一开关的控制端与第一驱动级电路的输出端耦接；第一驱动级电路的接地端与第一参考地耦接；第二开关耦接于第一电压输入端和第一节点之间；第二开关的控制端与第二开关信号输入端耦接；高通滤波器的第一输入端与第一电压输入端耦接，高通滤波器的第二输入端与第二电压输入端耦接，高通滤波器的输出端与第一驱动级电路的第二输入端耦接；逻辑处理电路包括触发器以及或门；第二开关信号输入端与触发器的时钟端耦接；触发器的复位端与第一开关信号输入端耦接；触发器还包括用 于接收固定高电平或固定低电平的输入端；触发器的输出端与或门的第一输入端耦接，或门的第二输入端与第一开关信号输入端耦接，或门的输出端与第一驱动级电路的第一输入端耦接。其中，第一驱动级电路和高通滤波器的具体结构、各个开关的类型以及开关电路的其它结构等均可以参考上述第一方面，此处不再赘述。此外，该开关电路具有与前述实施例相同的技术效果，因而此处不再赘述。
第三方面，提供一种开关电路。该开关电路包括第一开关、第一驱动级电路、第二开关、高通滤波器、逻辑处理电路、第一电压输入端、第二电压输入端、电压输出端、第一开关信号输入端、第二开关信号输入端以及第一参考地。第一开关耦接于第一节点和第一参考地之间；第一开关的控制端与第一驱动级电路的输出端耦接；第一驱动级电路的接地端与第一参考地耦接。第二开关耦接于第一电压输入端和第一节点之间；第二开关的控制端与第二开关信号输入端耦接。高通滤波器的第一输入端与第一电压输入端耦接，高通滤波器的第二输入端与第二电压输入端耦接，高通滤波器的输出端与第一驱动级电路的第二输入端耦接。逻辑处理电路包括延迟电路、第一与门、第二与门、第一反相器、第二反相器以及或门。第二开关信号输入端通过延迟电路与第一与门的第一输入端耦接；第二开关信号输入端还通过第一反相器与第一与门的第二输入端耦接；第一与门的输出端与第二与门的第一输入端耦接，第一开关信号输入端通过第二反相器与第二与门的第二输入端耦接，第二与门的输出端与或门的第一输入端耦接；或门的第二输入端与第一开关信号输入端耦接，或门的输出端与第一驱动级电路的第一输入端耦接。其中，第一驱动级电路和高通滤波器的具体结构、各个开关的类型以及开关电路的其它结构等均可以参考上述第一方面，此处不再赘述。此外，该开关电路具有与前述实施例相同的技术效果，因而此处不再赘述。
第四方面，提供一种开关电源。该开关电源包括控制器和上述的开关电路；第一开关信号输入端和第二开关信号输入端均与控制器耦接。控制器用于输出第一开关信号，并将第一开关信号提供给第一开关信号输入端，以控制第一开关的导通或断开，且控制器还用于输出第二开关信号，并将第二开关信号提供给第二开关信号输入端，以控制第二开关的导通或断开。该开关电源还具有与前述实施例相同的技术效果，因而此处不再赘述。
附图说明
图1为现有技术提供的一种开关电路的结构示意图；
图2为图1所示的开关电路中各个信号的波形图；
图3为一种开关电路的结构示意图；
图4为本申请的实施例提供的一种开关电源的结构示意图；
图5为本申请的实施例提供的一种开关电路的结构示意图；
图6为本申请的另一实施例提供的一种开关电路的结构示意图；
图7a为本申请的又一实施例提供的一种开关电路的结构示意图；
图7b为本申请的再一实施例提供的一种开关电路的结构示意图；
图8为图7b所示的开关电路中各个信号的波形图；
图9为本申请的另一实施例提供的一种开关电路的结构示意图；
图10为图9所示的开关电路中各个信号的波形图；
图11为本申请的又一实施例提供的一种开关电路的结构示意图。
附图标记：
01-开关电路；02-控制器；1-第一功率管驱动级电路；2-第二功率管驱动级电路；10-第一驱动级电路；20-高通滤波器；30-逻辑处理电路；40-第二驱动级电路；301-触发器；302-或门；303-第四反相器；304-延迟电路；305-第一与门；306-第二与门；307-第一反相器；308-第二反相器。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元。
本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。另外，术语“耦接”可以表示两个或两个以上部件有直接物理接触或电接触，也可以表示两个或两个以上部件彼此间并无直接接触，但通过中间媒介电连接或相互作用。
本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。
目前，死区时间内的损耗(也可以称为死区损耗)是开关电路01的主要损耗之一。出于提高开关电路01能量密度和减小输出波纹的考虑，目前开关电路01的速度在不断提高，已经从几百KHz演进到了100MHz量级，对应的死区损耗也在持续增加。
为了减小死区时间，降低死区损耗，可以采用逻辑互锁死区方案，图3提供了一种采用逻辑互锁死区方案的开关电路01的结构示意图，如图3所示，开关电路01包括第一功率管(也可以称为上管)S1和第二功率管(也可以称为下管)S2，第一功率管S1包括第一寄生二极管D1，第二功率管S2包括第二寄生二级管D2。第一功率管S1和第二功率管S2耦接于开关节点Lx；第一功率管S1耦接于电压输入端Vin和开关节点Lx之间；第二功率管S2耦接于开关节点Lx和第一参考地GND之间。第一功率管S1的控制端与第一功率管驱动级电路1耦接，第一功率管驱动级电路1包括两个串联的反相器，第一功率管驱动级电路1和与门a的输出端耦接，与门a的一个输入端与第二开关信号输入端PWMH耦接，与门a的另一个输入端与第二功率管S2的控制端耦接；第二功率管S2的控制端与第二功率管驱动级电路2耦接，第二功率管驱动级电路2包括两个串联的反相器，第二功率管驱动级电路2和与门b的输出端耦接，与门b的一个输入端通过反相器Inv(inverter)1与第一功率管S1的控制端耦接，与门b的另一个输入端通过反相器Inv(inverter)2与第二开关信号输入端PWMH耦接。电感L耦接于开关节点 Lx和电压输出端Vo之间，电容C耦接于电压输出端Vo和第一参考地GND之间。在开关电路01采用逻辑互锁死区方案的情况下，通过实时检测第一功率管S1和第二功率管S2的控制端的开关控制栅极信号，只有在确保第一功率管S1和第二功率管S2中一个的栅电压控制该功率管达到断开条件后才开启另外一个功率管，从而在减小死区时间的同时，保证两个功率管不会同时导通。
然而，采用逻辑互锁死区方案时，一方面，由于第一功率管S1的控制端和与门b的一个输入端耦接的长度，以及第二功率管S2的控制端和与门a的一个输入端耦接的长度太长，因而第一功率管S1的控制端的开关控制栅极信号传输给与门b的一个输入端，以及第二功率管S2的控制端的开关控制栅极信号传输给与门a的一个输入端的反馈信号路径太长，这样一来，限制了死区时间的减小。另一方面，由于与门a的一个输入端接收到的检测信号(即第二功率管S2的控制端的开关控制栅极信号)稳定后，还需要等待第一功率管驱动级电路1的驱动延时Tdrive后才能控制第一功率管S1动作，同理，与门b的一个输入端接收到的检测信号(即第一功率管S1的控制端的开关控制栅极信号)稳定后，还需要等待第二功率管驱动级电路2的驱动延时Tdrive后才能控制第二功率管S2动作，而这一段驱动延时成为减小死区时间的瓶颈。若通过增加第一功率管驱动级电路1的驱动能力(例如增加第一功率管驱动级电路1中驱动MOS管尺寸)来减小后级驱动延时，即第一功率管驱动级电路1到第一功率管S1的驱动延时，而第一功率管驱动级电路1中驱动MOS管的尺寸增加又会导致本级驱动延时，即与门a的输出端到第一功率管驱动级电路1的驱动延时，同样的，增加第二功率管驱动级电路2的驱动能力会产生与增加第一功率管驱动级电路1的驱动能力类似的问题，因而受工艺限制，驱动延时Tdrive始终存在并由表征工艺本征的FOM(figure of merit，性能系数)值决定，只能随着工艺演进优化，无法有本质的突破。综合以上两方面可知，采用逻辑互锁死区方案，减小死区时间是有限制的，一般死区时间只能做到ns级，这在低频(kHz到MHz级)开关电路中可以应用，但在高频(几十到几百MHz)开关电路中却无法接受。基于上述，为了降低死区损耗，本申请实施例提供一种开关电源，如图4所示，该开关电源包括开关电路(也可以称为buck(降压式)变换器)01和控制器02。
上述开关电路01的主要结构如图4所示，包括第一开关M1、第一驱动级电路10、第二开关M2、高通滤波器20、逻辑处理电路30、第一电压输入端PVDD、第二电压输入端VDRIVE、电压输出端Vo、第一开关信号输入端PWML、第二开关信号输入端PWMH以及第一参考地GND。
上述的第一开关信号输入端PWML和第二开关信号输入端PWMH均与控制器02耦接，控制器02用于输出第一开关信号PWML，并将第一开关信号PWML提供给第一开关信号输入端PWML，以控制第一开关M1的导通或断开；控制器02还用于输出第二开关信号PWMH，并将第二开关信号PWMH提供给第二开关信号输入端PWMH，以控制第二开关M2的或断开。
其中，如图4所示，第一开关M1耦接于第一节点Lx和第一参考地GND之间；第一开关M1的控制端LG与第一驱动级电路10的输出端p耦接；第一驱动级电路10的第一输入端d与逻辑处理电路30的输出端e耦接，第一驱动级电路10的接地端f与第一参考地GND耦接。第二开关M2耦接于第一电压输入端PVDD和第一节点Lx之间； 第二开关M2的控制端HG与第二开关信号输入端PWMH耦接。高通滤波器20的第一输入端m与第一电压输入端PVDD耦接，高通滤波器20的第二输入端o与第二电压输入端VDRIVE耦接，高通滤波器20的输出端n与第一驱动级电路10的第二输入端g耦接。逻辑处理电路30的第一输入端h与第一开关信号输入端PWML耦接，逻辑处理电路30的第二输入端i与第二开关信号输入端PWMH耦接；逻辑处理电路30用于在第二开关M2断开之后，第一开关M1导通之前，切断第一驱动级电路10的接地端f与第一参考地GND的耦接。第一节点Lx和电压输出端Vo耦接。
需要说明的是，高通滤波器20用于在第二开关M2断开之后，第一开关M1导通之前，将第二电压输入端VDRIVE提供的电压抬高后提供给第一驱动级电路10的第二输入端g，以使第一开关M1导通。
可以理解的是，在一些实施例中，如图4所示，逻辑处理电路30的接地端j与第一参考地GND耦接，逻辑处理电路30的第三输入端k与第二电压输入端VDRIVE耦接，第一驱动级电路10的第三输入端与第二电压输入端VDRIVE耦接。
应当理解到，在开关电路01中，由于封装、PCB(printed circuit board，印制电路板)走线或过孔设计等原因，电源和开关之间会产生寄生电感(parasitic inductor)，例如第一电压输入端PVDD和第二开关M2之间会产生串联在第一电压输入端PVDD和第二开关M2之间的寄生电感(图4中用L’表示寄生电感)。寄生电感L’一般在nH级，通常情况下，寄生电感L’是有害且无法消除的。在此基础上，需要说明的是，电感自身的电流连续性决定，在第二开关M2断开，第一开关M1导通的区间，寄生电感L’续流，寄生电感L’上的能量会猛然抬高第一电压输入端PVDD的电压，此时第二开关M2会承受额外的电应力。
此处，第一开关M1和第二开关M2为设置在功率路径上的功率管。功率管的类型可以是绝缘栅双极型晶体管(insulated gate bipolar transistor，IGBT)、金属-氧化物半导体场效应晶体管(也可以称为金氧半场效晶体管)(metal oxide semiconductor field effect transistor，MOSFET)或PN结型场效应晶体管(PN junction field effect transistor，PNJFET)。
在此基础上，第一开关M1和第二开关M2可以均为N型管；也可以均为P型管；当然还可以是一个为P型管，另一个为N型管，例如第一开关M1为N型管，第二开关M2为P型管，又例如，第一开关M1为P型管，第二开关M2为N型管。下文以及说明书附图以第一开关M1和第二开关M2均为N型管为例进行示意。
此外，可以将第二开关M2称为上管，将第一开关M1称为下管。
在第一开关M1和第二开关M2交替导通和断开的过程中，为了避免第一开关M1和第二开关M2同时导通，造成第一电压输入端PVDD和第一参考地GND直接导通，进而导致与第一电压输入端PVDD耦接的电源烧毁，因而在第一开关M1和第二开关M2交替导通和断开的过程中，有一段第一开关M1和第二开关M2同时断开的时间，即死区时间。
本申请实施例提供一种开关电路01，该开关电路01包括第一开关M1、第一驱动级电路10、第二开关M2、高通滤波器20、逻辑处理电路30、第一电压输入端PVDD、第二电压输入端VDRIVE、电压输出端Vo、第一开关信号输入端PWML以及第二开关 信号输入端PWMH。在该开关电路01的工作过程中，第一开关M1和第二开关M2交替导通和断开，通过控制第一开关M1和第二开关M2导通和断开的时间的比例，从而可以将第一电压输入端PVDD提供的电压转化为所需求的电压从电压输出端Vo输出。
在此基础上，在第一开关M1和第二开关M2交替导通和断开的过程中，在第二开关M2断开的瞬间，第一开关M1导通之前，第一电压输入端PVDD和第二开关M2之间产生的寄生电感L’的能量在抬高第一电压输入端PVDD的电压的同时，由于开关电路01包括高通滤波器20，高通滤波器20与第一电压输入端PVDD耦接，因而高通滤波器20的前馈作用会使得高通滤波器20将第二电压输入端VDRIVE提供的电压抬高后提供给第一驱动级电路10的第二输入端g，这样一来，第一驱动级电路10在死区时间内的实际工作电压冲高，高于非死区时间内第二电压输入端VDRIVE提供的电压，因此第一驱动级电路10在前馈电压即上述实际工作电压的作用下会提前驱动第一开关M1导通，相对于现有技术在死区时间内第一开关M1断开，只有在非死区时间内，第一开关信号输入端PWML接收的电压才可以控制第一驱动级电路10接收第二电压输入端VDRIVE提供的电压，驱动第一开关M1导通，而本申请实施例在死区时间内，利用高通滤波器20的前馈作用提前驱动第一开关M1导通，从而有效减小死区时间，降低死区损耗，进而降低开关电路01的损耗，提升开关电路01的效率。此外，在第二开关M2断开，第一开关M1导通之前，由于逻辑处理电路30可以将第一驱动级电路10的接地端f与第一参考地GND的耦接切断，因而避免了高通滤波器20将第二电压输入端VDRIVE提供的电压抬高后被第一参考地GND下拉释放掉。
基于此，本申请实施例提供的开关电路01可以应用于高频开关电路01中，且在不改变驱动级电路的尺寸的前提下，利用第二开关M2断开后寄生电感L’产生的过冲电压，增强死区时间内第一驱动级电路10对第一开关M1的驱动能力，减小死区时间，降低开关电路01的损耗。
需要说明的是，上述第一电压输入端PVDD的电压抬高(也可以称为过冲)是第二开关M2断开的结果，因此高通滤波器20的前馈可以保证一定是第二开关M2断开后引入，第一开关M1的第一驱动级电路10引入该能量后再开启第一开关M1，因此在任何极限情况下都不会有第一开关M1和第二开关M2同时导通导致的穿通风险，即电源烧毁的风险。
在一些实施例中，如图5所示，上述的高通滤波器20包括第一电容C1和第一电阻R1；第一电容C1耦接于第一电压输入端PVDD和第一驱动级电路10的第二输入端g之间；第一电阻R1耦接于第二电压输入端VDRIVE和第一驱动级电路10的第二输入端g之间。
参考图5，在第二开关M2断开的瞬间，第一开关M1导通之前，寄生电感L’的能量抬高第一电压输入端PVDD的电压，此时，m点的电压抬高，大于第一电压输入端PVDD的电压，与此同时，由于高通滤波器20包括第一电容C1，因而通过高通滤波器20中第一电容C1的前馈作用可以将n点的电压抬高，并提供给第一驱动级电路10，这样第一驱动级电路10的实际工作电压抬高，高于其前级控制的第二电压输入端VDRIVE提供的电压，因此第一驱动级电路10在该前馈电压的作用下会提前驱动第一开关M1导通。
在一些实施例中，如图5所示，上述开关电路01还包括电感L和第三电容C3。电感L耦接于第一节点Lx和电压输出端Vo之间，第三电容C3耦接于电压输出端Vo和第一参考地GND之间。其中，第三电容C3的一端与电压输出端Vo耦接，另一端与第一参考地GND耦接。
此处，在第一节点Lx和电压输出端Vo之间耦接电感L，电感L能够起到续流作用，使得电压输出端Vo能够稳定地输出电压，避免电压输出端Vo输出的电压高低变化。另外，在电压输出端Vo和第一参考地GND之间耦接第三电容C3，第三电容C3可以起到稳压的作用，能够降低电压输出端Vo输出电压高低变化的纹波。
在一些实施例中，如图6所示，上述第一驱动级电路10包括第三开关M3、第四开关M4、第五开关M5、第六开关M6、第七开关M7和第八开关M8；第三开关M3和第四开关M4耦接于第二节点p(即第一驱动级电路10的输出端p)；第一开关M1的控制端LG耦接于第二节点p；第三开关M3耦接于高通滤波器20的输出端n和第二节点p之间，第四开关M4耦接于第二节点p和第一参考地GND之间；第五开关M5耦接于第二电压输入端VDRIVE和第三开关M3的控制端之间；第六开关M6耦接于第三开关M3的控制端和第一参考地GND之间；第五开关M5的控制端和第六开关M6的控制端耦接于第一开关信号输入端PWML；第七开关M7耦接于第二电压输入端VDRIVE和第四开关M4的控制端之间；第八开关M8耦接于第四开关M4的控制端和第一参考地GND之间；第七开关M7的控制端和第八开关M8的控制端耦接于逻辑处理电路30的输出端e。
如图6所示，在高通滤波器20包括第一电容C1和第一电阻R1的情况下，第一电容C1耦接于第一电压输入端PVDD和第三开关M3之间；第一电阻R1耦接于第二电压输入端VDRIVE和第三开关M3之间。
需要说明的是，第三开关M3和第四开关M4用于对第一开关M1的控制端LG的电压进行控制。第五开关M5和第六开关M6用于对第三开关M3的控制端的电压进行控制，第七开关M7和第八开关M8用于对第四开关M4的控制端的电压进行控制。
此处，上述的第三开关M3、第四开关M4、第五开关M5、第六开关M6、第七开关M7和第八开关M8为功率管。功率管的类型例如可以为绝缘栅双极型晶体管、金属-氧化物半导体场效应晶体管或PN结型场效应晶体管。
此外，可以是第三开关M3为P型管，第四开关M4为N型管；也可以是第三开关M3为N型管，第四开关M4为P型管。由于第三开关M3耦接于高通滤波器20的输出端n和第二节点p之间，而高通滤波器20的第一输入端m与第一电压输入端PVDD耦接，高通滤波器20的第二输入端o与第二电压输入端VDRIVE耦接，因而第三开关M3为第一驱动级电路10中的上拉管(Mpush)。由于第四开关M4耦接于第二节点p和第一参考地GND之间，因而第四开关M4为第一驱动级电路10中的下拉管(Mpull)。
另外，对于与第三开关M3的控制端耦接的第五开关M5和第六开关M6，可以是第五开关M5为P型管，第六开关M6为N型管；也可以是第五开关M5为N型管，第六开关M6为P型管。对于与第四开关M4的控制端耦接的第七开关M7和第八开关M8，可以是第七开关M7为P型管，第八开关M8为N型管；也可以是第七开关M7为N型管，第八开关M8为P型管。
以下以图6为例，对开关电路01中各个开关的具体连接关系进行说明。参考图6，第一开关M1的漏极与第一节点Lx耦接，源极与第一参考地GND耦接，栅极(即控制端)与第二节点p耦接。第二开关M2的漏极与第一电压端PVDD耦接，源极与第一节点Lx耦接，栅极与第二开关信号输入端PWMH耦接。第三开关M3的源极与第一电容C1耦接，漏极与第二节点p耦接。第四开关M4的漏极与第二节点p耦接，源极与第一参考地GND耦接。第五开关M5的源极与第二电压输入端VDRIVE耦接，漏极与第三开关M3的栅极耦接，栅极与第一开关信号输入端PWML耦接。第六开关M6的漏极与第三开关M3的栅极耦接，源极与第一参考地GND耦接，栅极与第一开关信号输入端PWML耦接。第七开关M7的源极与第二电压输入端VDRIVE耦接，漏极与第四开关M4的栅极耦接，栅极与逻辑处理电路30的输出端e耦接。第八开关M8的漏极与第四开关M4的栅极耦接，源极与第一参考地GND耦接，栅极与逻辑处理电路30的输出端e耦接。
基于上述，应当理解到，当上述开关的类型发生变化(例如由P型管变为N型管，或者，由N型管变为P型管)时，开关的源极和漏极的连接关系发生相应变化。示例的，当第二开关M2为P型管时，第二开关M2的源极与第一电压端PVDD耦接，漏极与第一节点Lx耦接。对于本申请实施例提供的其它开关的类型变化时，各个开关的源极和漏极的连接关系，可以参考第二开关M2，此处不再赘述。
对于上述开关电路01中的逻辑处理电路30，以下示例性地提供两种具体的实现方式。
第一种实现方式：如图7a所示，逻辑处理电路30包括触发器(也可以称为D触发器)301以及或门302；第二开关信号输入端PWMH与触发器301的时钟端CLK(时钟端CLK为逻辑处理电路30的第二输入端i)耦接；触发器301的复位端RESET与第一开关信号输入端PWML耦接；触发器301还包括用于接收固定高电平(可以用“1”表示)或固定低电平(可以用“0”表示)的输入端D；触发器301的输出端与或门302的第一输入端耦接，或门302的第二输入端(或门302的第二输入端为逻辑处理电路30的第一输入端h)与第一开关信号输入端PWML耦接，或门302的输出端(或门302的输出端为逻辑处理电路30的输出端e)与第一驱动级电路10的第一输入端d耦接。
在第一驱动级电路10包括第三开关M3、第四开关M4、第五开关M5、第六开关M6、第七开关M7和第八开关M8的情况下，或门302的输出端与第七开关M7和第八开关M8的控制端耦接。
附图7a以触发器301的输入端D用于接收高电平(用“1”表示)为例。在触发器301的输入端D用于接收高电平的情况下，触发器301的输出端会根据时钟端CLK接收到的第二开关信号输入端PWMH提供的信号的上升沿触发，即当第二开关信号输入端PWMH提供的信号从低电平变为高电平时，触发器301的输出端输出的信号EN-FF为高电平信号；或者，触发器301的输出端会根据时钟端CLK接收到的第二开关信号输入端PWMH提供的信号的下升沿触发，即当第二开关信号输入端PWMH提供的信号从高电平变为低电平时，触发器301的输出端输出的信号EN-FF为高电平信号。
在一些实施例中，如图7b所示，逻辑处理电路30还包括第四反相器303，第二开关信号输入端PWMH通过第四反相器303与触发器301的时钟端CLK耦接。此处，第 四反相器303的输入端(第四反相器303的输入端为逻辑处理电路30的第二输入端i)与第二开关信号输入端PWMH耦接，第四反相器303的输出端与时钟端CLK耦接。
在第二开关信号输入端PWMH提供的信号由高电平变为低电平，而触发器301的输出端根据时钟端CLK的上升沿触发的情况下，由于逻辑处理电路30包括第四反相器303，第四反相器303可以将第二开关信号输入端PWMH提供的信号进行反相，因而当第二开关信号输入端PWMH提供的信号由高电平变为低电平时，触发器301的输出端会根据时钟端CLK的上升沿触发，从而触发器301的输出端输出的信号EN-FF为高电平信号。或者，在第二开关信号输入端PWMH提供的信号由低电平变为高电平，而触发器301的输出端根据时钟端CLK的下升沿触发的情况下，由于逻辑处理电路30包括第四反相器303，第四反相器303可以将第二开关信号输入端PWMH提供的信号进行反相，因而当第二开关信号输入端PWMH提供的信号由低电平变为高电平时，触发器301的输出端会根据时钟端CLK的下升沿触发，从而触发器301的输出端输出的信号EN-FF为高电平信号。
在此基础上，由于触发器301的复位端RESET与第一开关信号输入端PWML耦接，因而当第一开关信号输入端PWML提供的信号由低电平变为高电平，或者由高电平变为低电平时，触发器301的输出端输出的信号EN-FF又恢复为低电平信号。
以下结合图8所示的时序图，对图7b所示的开关电路01的工作过程进行介绍。图7b所示的开关电路01以第一开关M1和第二开关M2均为N型管，第三开关M3为P型管，第四开关M4为N型管，第五开关M5为P型管，第六开关M6为N型管，第七开关M7为P型管，第八开关M8为N型管为例。图8所示的时序图分别提供了第二开关信号输入端PWMH接收的信号的波形图；第一开关信号输入端PWML接收的信号的波形图；第二开关M2的控制端HG接收的信号的波形图；触发器301的输出端EN-FF输出的信号EN-FF的波形图；第一节点Lx接收的信号的波形图；第一电压端PVDD接收的信号的波形图；第二电压端VDRIVE接收的信号的波形图；第一开关M1的控制端LG接收的信号的波形图。图8中第一节点Lx接收的信号的波形图中的虚线部分，第二电压端VDRIVE接收的信号的波形图中的虚线部分以及第一开关M1的控制端LG接收的信号的波形图中的虚线部分均表示现有技术中对应信号的波形图。
参考图7b和图8，在第二开关信号输入端PWMH接收的信号由高电平信号VH变为低电平信号VL(图8中虚线圈所示)时，第二开关M2的控制端HG接收的信号由高电平信号VH变为低电平信号VL，即第二开关M2的控制端HG下拉，此时第二开关M2断开。在第二开关M2断开的瞬间，由于第一电压端PVDD和第二开关M2之间产生的寄生电感L’(图7b中未示意出寄生电感L’)续流的原因，第一电压端PVDD的电压上冲(也可以称为抬高)，因此m点的电压抬高，此时，高通滤波器20中第一电容(也可以称为前馈电容)C1同步拉高n点的电压，n点的电压VDRIVE’大于第二电压端VDRIVE提供的电压VDRIVE。与此同时，第一开关信号输入端PWML接收的信号为低电平信号VL，由于第五开关M5为P型管，第六开关M6为N型管，因而第五开关M5导通，第六开关M6断开，第二电压端VDRIVE提供的电压VDRIVE通过第五开关M5提供给第三开关M3的控制端，由于第三开关M3为P型管，且第三开关M3的源极(即s极)的电压(即n点的电压VDRIVE’)大于g极(即控制端或栅极) 的电压，因而第三开关M3会瞬间导通，这时n点已经被抬高的电压VDRIVE’通过第三开关M3提供给第二节点p，而第二节点p与第一开关M1的控制端LG耦接，且第一开关M1为N型管，因而第一开关M1会提前导通。第一节点Lx接收的信号的波形图中的阴影部分表示本申请实施例提供的开关电路01相对于现有技术提供的开关电路01能够降低的功耗。基于该开关电路01的工作过程可以看出，第一开关M1提前导通是由于第二开关M2断开，第一电压端PVDD的电压上冲，进而高通滤波器20中第一电容C1的前馈作用导致n点的电压抬高的结果，因而虽然第一开关M1会提前导通，但是第一开关M1和第二开关M2在任何情况下都不会出现同开的风险。
在此基础上，同步的，在第二开关信号输入端PWMH接收的信号由高电平信号VH变为低电平信号VL后，即第二开关M2断开后，第一开关信号输入端PWML接收的信号由低电平信号VL变为高电平信号VH之前，逻辑处理电路30中的触发器301的输出端会根据时钟端CLK接收到的第二开关信号输入端PWMH提供的信号的下升沿触发，触发器301的输出端输出的信号EN-FF为高电平的死区信号。在此时间内，逻辑处理电路30中的或门302的一个输入端接收触发器301的输出端输出的信号EN-FF为高电平信号VH，另一个输入端接收第一开关信号输入端PWML提供的低电平信号VL，因此或门302的输出端输出高电平信号。由于第七开关M7和第八开关M8的控制端都与或门302的输出端耦接，第七开关M7为P型管，第八开关M8为N型管，此时，第七开关M7断开，第八开关M8导通，第一参考地GND的电压通过第八开关M8提供给第四开关M4的控制端，从而控制第四开关M4断开，这样一来，避免了第一参考地GND的电压通过第四开关M4提供给第二节点p，此时，第二节点p的电压从低阻下拉变为高阻，保证了第三开关M3导通后通过的上冲能量不会被第四开关M4泄放到地，第二节点p的电压保持抬高，从而让第一开关M1提前导通，减少实际的死区时间。
在第一开关信号输入端PWML接收的信号拉高后，即变为高电平信号VH后，触发器301的输出端输出的信号EN-FF又恢复为低电平信号VL。由于或门302的一个输入端接收触发器301的输出端输出的低电平信号，另一个输入端接收第一开关信号输入端PWML提供的高电平信号VH，因此或门302的输出端输出高电平信号。此时，第七开关M7断开，第八开关M8导通，第一参考地GND的电压通过第八开关M8提供给第四开关M4的控制端，从而控制第四开关M4断开。与此同时，由于第一开关信号输入端PWML提供的高电平信号VH控制第六开关M6导通，第五开关M5断开，第一参考地GND的电压通过第六开关M6提供给第三开关M3的控制端，从而控制第三开关M3导通。第二电压输入端VDRIVE提供的电压通过第三开关M3提供给第二节点p，从而控制第一开关M1导通。由此可以看出，在第一开关信号输入端PWML接收的信号拉高后，第一开关M1的控制端LG继续由第一开关信号输入端PWML接收的信号控制。
第二种实现方式：如图9所示，逻辑处理电路30包括延迟电路304、第一与门305、第二与门306、第一反相器307、第二反相器308以及或门302。
第二开关信号输入端PWMH通过延迟电路304与第一与门305的第一输入端耦接；此处，延迟电路304的输入端(延迟电路304的输入端为逻辑处理电路30的第二输入端i)与第二开关信号输入端PWMH耦接，延迟电路304的输出端PWMH-D与第一与 门305的第一输入端耦接；第二开关信号输入端PWMH还通过第一反相器307与第一与门305的第二输入端耦接，此处，第一反相器307的输入端与第二开关信号输入端PWMH耦接，第一反相器307的输出端与第一与门305的第二输入端耦接；第一与门305的输出端PPH与第二与门306的第一输入端耦接，第一开关信号输入端PWML通过第二反相器308与第二与门306的第二输入端耦接，此处，第二反相器308的输入端与第一开关信号输入端PWML耦接，第二反相器308的输出端与第二与门306的第二输入端耦接，第二与门306的输出端与或门302的第一输入端耦接；或门302的第二输入端(或门302的第二输入端为逻辑处理电路30的第一输入端h)与第一开关信号输入端PWML耦接，或门302的输出端(或门302的输出端为逻辑处理电路30的输出端e)与第一驱动级电路10的第一输入端d耦接。
在一些实施例中，上述的延迟电路304包括依次串联的n个第三反相器；其中，n≥2，n为正偶数。此处，依次串联的n个第三反相器可以将第二开关信号输入端PWMH接收的信号延迟一定时间后输出。
在另一些实施例中，上述的延迟电路304包括串联的第二电容C2和第二电阻R2。此处，串联的第二电容C2和第二电阻R2可以将第二开关信号输入端PWMH接收的信号延迟一定时间后输出。
以下结合图10所示的时序图，对图9所示的开关电路01的工作过程进行介绍。图9所示的开关电路01以第一开关M1和第二开关M2均为N型管，第三开关M3为P型管，第四开关M4为N型管，第五开关M5为P型管，第六开关M6为N型管，第七开关M7为P型管，第八开关M8为N型管为例。图10所示的时序图分别提供了第二开关信号输入端PWMH提供的信号的波形图；延迟电路304的输出端PWMH-D提供的信号的波形图；第一与门305的输出端PPH提供的信号的波形图；第一开关信号输入端PWML接收的信号的波形图；第二与门306的输出端输出的信号EN-FF的波形图。
参考图9和图10，在第二开关信号输入端PWMH接收的信号由高电平信号VH变为低电平信号VL后，即第二开关M2断开后，第一开关信号输入端PWML接收的信号由低电平变信号VL为高电平信号VH之前，n点已经被抬高的电压VDRIVE’通过第三开关M3提供给第二节点p的过程与第一种实现方式相似，此处不再赘述。与此同时，在第二开关信号输入端PWMH接收的信号由高电平信号VH变为低电平信号VL后，即第二开关M2断开后，第一开关信号输入端PWML接收的信号由低电平信号VL变为高电平信号VH之前，第二开关信号输入端PWMH接收的信号经过延迟电路304后，延迟电路304的输出端PWMH-D输出高电平信号VH，同时，第二开关信号输入端PWMH接收的信号经过第一反相器307后输出高电平信号VH；第一与门305的一个输入端接收延迟电路304的输出端PWMH-D输出的高电平信号VH，另一个输入端接收第一反相器307输出的高电平信号VH，第一与门305的输出端PPH输出高电平信号VH；第二反相器308的输入端接收第一开关信号输入端PWML接收的低电平信号VL，第二反相器308的输出端输出高电平信号VH；第二与门306的一个输入端接收第一与门305的输出端PPH输出的高电平信号VH，另一个输入端接收第二反相器308的输出端输出的高电平信号VH，第二与门306的输出端输出的信号EN-FF为高电平信号VH。在此时间内，或门302的一个输入端接收第二与门306的输出端输出的信号EN-FF为 高电平信号VH，另一个输入端接收第一开关信号输入端PWML提供的低电平信号VL，因此或门302的输出端输出高电平信号。由于第七开关M7和第八开关M8的控制端都与或门302的输出端耦接，第七开关M7为P型管，第八开关M8为N型管，此时，第七开关M7断开，第八开关M8导通，第一参考地GND的电压通过第八开关M8提供给第四开关M4的控制端，从而控制第四开关M4断开，这样一来，避免了第一参考地GND的电压通过第四开关M4提供给第二节点p，此时，第二节点p的电压从低阻下拉变为高阻，保证第三开关M3导通后通过的上冲能量不会被第四开关M4泄放到地，第二节点p的电压保持抬高，从而让第一开关M1提前导通，减少实际的死区时间。
此外，在第一开关信号输入端PWML接收的信号拉高后，即变为高电平信号VH后，第一开关M1的控制端LG继续由第一开关信号输入端PWML接收的信号控制，具体可以参考上述实施例，此处不再赘述。
需要说明的是，上述的逻辑处理电路30包括但不限于上述第一种实现方式和第二种实现方式。
在一些实施例中，如图5、图6、图7a、图7b和图9所示，上述开关电路01还可以包括第二驱动级电路40；第二开关M2的控制端HG通过第二驱动级电路40与第二开关信号输入端PWMH耦接。
此处，第二驱动级电路40的第一输入端q与第二开关信号输入端PWMH耦接，第二驱动级电路40的输出端s与第二开关M2的控制端HG耦接。在此基础上，应当理解到，在一些实施例中，上述开关电路01还包括第三电压输入端VDRIVE-HG和第二参考地GND-HG，第二驱动级电路40的第二输入端t与第三电压输入端VDRIVE-HG耦接，第二驱动级电路40的接地端u与第二参考地GND-HG耦接。
由于第二开关M2的控制端HG与第二驱动级电路40耦接，因而可以提高第二开关M2的控制端HG的驱动能力，降低第二开关M2导通或断开的时间。
此外，第二驱动级电路40的结构和第一驱动级电路10的结构可以相同，也可以不相同。
在一些示例中，如图11所示，上述开关电路01还包括第三电压输入端VDRIVE-HG和第二参考地GND-HG，上述第二驱动级电路40还包括第九开关M9、第十开关M10、第十一开关M11、第十二开关M12、第十三开关M13以及第十四开关M14。第九开关M9耦接于第三电压输入端VDRIVE-HG和第二开关M2的控制端HG之间，第十开关M10耦接于第二开关M2的控制端HG和第二参考地GND-HG之间。第十一开关M11耦接于第三电压输入端VDRIVE-HG和第九开关M9的控制端之间；第十二开关M12耦接于第九开关M9的控制端和第二参考地GND-HG之间；第十一开关M11的控制端和第十二开关M12的控制端均耦接于第二开关信号输入端PWMH。第十三开关M13耦接于第三电压输入端VDRIVE-HG和第十开关M10的控制端之间；第十四开关M14耦接于第十开关M10的控制端和第二参考地GND-HG之间；第十三开关M13的控制端和第十四开关M14的控制端均耦接于第二开关信号输入端PWMH。
此处，第九开关M9为第二驱动级电路40中的上拉管，第十开关M10为第二驱动级电路40中的下拉管，第九开关M9和第十开关M10用于对第二开关M2的控制端HG的电压进行控制。第十一开关M11和第十二开关M12用于对第九开关M9的控制端的 电压进行控制，第十三开关M13和第十四开关M14用于对第十开关M10的控制端的电压进行控制。
需要说明的是，第九开关M9、第十开关M10、第十一开关M11、第十二开关M12、第十三开关M13以及第十四开关M14为功率管。功率管的类型例如可以为绝缘栅双极型晶体管、金属-氧化物半导体场效应晶体管或PN结型场效应晶体管。
在此基础上，第九开关M9、第十开关M10、第十一开关M11、第十二开关M12、第十三开关M13以及第十四开关M14可以是N型管，也可以是P型管。
此外，对于第二驱动级电路40中第九开关M9、第十开关M10、第十一开关M11、第十二开关M12、第十三开关M13以及第十四开关M14的源极和漏极的连接关系可以参考上述对图6所示的各个开关的源极和漏极的连接关系的说明，此处不再赘述。
基于上述第二驱动级电路40的结构，以下以第九开关M9为P型管，第十开关M10为N型管，第十一开关M11为P型管，第十二开关M12为N型管，第十三开关M13为P型管，第十四开关M14为N型管为例，对第二驱动级电路40的工作过程进行说明。
在第二开关信号输入端PWMH接收的电压为高电平信号VH时，第十一开关M11和第十三开关M13均断开，第十二开关M12和第十四开关M14均导通，第二参考地GND-HG提供的电压通过第十二开关M12输入给第九开关M9的控制端，从而控制第九开关M9导通，同时，第二参考地GND-HG提供的电压通过第十四开关M14输入给第十开关M10的控制端，从而控制第十开关M10断开。由于第九开关M9导通，第十开关M10断开，因而第三电压输入端VDRIVE-HG提供的电压通过第九开关M9输入给第二开关M2的控制端HG，从而控制第二开关M2导通。由此可知，当第二开关信号输入端PWMH提供的电压为高电平信号VH时，第二开关M2导通。
在第二开关信号输入端PWMH接收的电压为低电平信号VL时，第十一开关M11和第十三开关M13均导通，第十二开关M12和第十四开关M14均断开，第三电压输入端VDRIVE-HG提供的电压通过第十一开关M11输入给第九开关M9的控制端，从而控制第九开关M9断开，同时，第三电压输入端VDRIVE-HG提供的电压通过第十三开关M13输入给第十开关M10的控制端，从而控制第十开关M10导通。由于第九开关M9断开，第十开关M10导通，因而第二参考地GND-HG提供的电压通过第十开关M10输入给第二开关M2的控制端HG，从而控制第二开关M2断开。由此可知，当第二开关信号输入端PWMH提供的电压为低电平信号VL时，第二开关M2断开。
基于上述，通过第二开关信号输入端PWMH接收的电压以及第二驱动级电路40，可以控制第二开关M2导通或断开。
本申请实施例还提供一种开关电路01，该开关电路01的主要结构如图7a所示，包括第一开关M1、第一驱动级电路10、第二开关M2、高通滤波器20、逻辑处理电路30、第一电压输入端PVDD、第二电压输入端VDRIVE、电压输出端Vo、第一开关信号输入端PWML、第二开关信号输入端PWMH以及第一参考地GND。第一开关M1耦接于第一节点Lx和第一参考地GND之间；第一开关M1的控制端LG与第一驱动级电路10的输出端p耦接；第一驱动级电路10的接地端f与第一参考地GND耦接。第二开关M2耦接于第一电压输入端PVDD和第一节点Lx之间；第二开关M2的控制端HG与第二开关信号输入端PWMH耦接。高通滤波器20的第一输入端m与第一电压输入 端PVDD耦接，高通滤波器20的第二输入端o与第二电压输入端VDRIVE耦接，高通滤波器20的输出端n与第一驱动级电路10的第二输入端g耦接。逻辑处理电路30包括触发器301以及或门302；第二开关信号输入端PWMH与触发器301的时钟端CLK耦接；触发器301的复位端RESET与第一开关信号输入端PWML耦接；触发器301还包括用于接收固定高电平或固定低电平的输入端D；触发器301的输出端与或门302的第一输入端耦接，或门302的第二输入端与第一开关信号输入端PWML耦接，或门302的输出端与第一驱动级电路10的第一输入端d耦接。
在一些实施例中，如图7b所示，逻辑处理电路30还包括第四反相器303，第二开关信号输入端PWMH通过第四反相器303与触发器301的时钟端CLK耦接。
在一些实施例中，上述开关电路01还可以包括第二驱动级电路40；第二开关M2的控制端HG通过第二驱动级电路40与第二开关信号输入端PWMH耦接。
需要说明的是，第一驱动级电路10、高通滤波器20以及第二驱动级电路40的具体结构、开关电路的其它结构、各个开关的类型等均可以参考上述实施例，此处不再赘述。
本申请实施例还提供一种开关电路01，该开关电路01的主要结构如图9所示，包括第一开关M1、第一驱动级电路10、第二开关M2、高通滤波器20、逻辑处理电路30、第一电压输入端PVDD、第二电压输入端VDRIVE、电压输出端Vo、第一开关信号输入端PWML、第二开关信号输入端PWMH以及第一参考地GND。第一开关M1耦接于第一节点Lx和第一参考地GND之间；第一开关M1的控制端LG与第一驱动级电路10的输出端p耦接；第一驱动级电路10的接地端f与第一参考地GND耦接。第二开关M2耦接于第一电压输入端PVDD和第一节点Lx之间；第二开关M2的控制端HG与第二开关信号输入端PWMH耦接。高通滤波器20的第一输入端m与第一电压输入端PVDD耦接，高通滤波器20的第二输入端o与第二电压输入端VDRIVE耦接，高通滤波器20的输出端n与第一驱动级电路10的第二输入端g耦接。逻辑处理电路30包括延迟电路304、第一与门305、第二与门306、第一反相器307、第二反相器308以及或门302。第二开关信号输入端PWMH通过延迟电路304与第一与门305的第一输入端耦接；第二开关信号输入端PWMH还通过第一反相器307与第一与门305的第二输入端耦接；第一与门305的输出端PPH与第二与门306的第一输入端耦接，第一开关信号输入端PWML通过第二反相器308与第二与门306的第二输入端耦接，第二与门306的输出端与或门302的第一输入端耦接；或门302的第二输入端与第一开关信号输入端PWML耦接，或门302的输出端与第一驱动级电路10的第一输入端d耦接。
在一些实施例中，上述开关电路01还可以包括第二驱动级电路40；第二开关M2的控制端HG通过第二驱动级电路40与第二开关信号输入端PWMH耦接。
需要说明的是，第一驱动级电路10、高通滤波器20、第二驱动级电路40以及延迟电路304的具体结构、开关电路的其它结构、各个开关的类型等均可以参考上述实施例，此处不再赘述。
本申请实施例还提供一种供电芯片，供电芯片包括上述的开关电路01。本申请实施例提供的供电芯片可以应用于任意的电子设备中，例如手机、平板电脑、可穿戴设备(例如智能手表)等。
需要说明的是，上述开关电路01中的第一驱动级电路10、高通滤波器20、逻辑处理电路30、第三电容C3以及第二驱动电路40等可以集成在一个供电芯片上。此外，第一开关M1、第二开关M2、电感L可以集成在供电芯片上，也可以设置在供电芯片外。
此外，输出第一开关信号PWML和第二开关信号PWMH的逻辑可以集成在供电芯片上，也可以集成在其它芯片上。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种开关电路，其特征在于，包括：第一开关、第一驱动级电路、第二开关、高通滤波器、逻辑处理电路、第一电压输入端、第二电压输入端、电压输出端、第一开关信号输入端、第二开关信号输入端以及第一参考地；
    所述第一开关耦接于第一节点和所述第一参考地之间；所述第一开关的控制端与所述第一驱动级电路的输出端耦接；所述第一驱动级电路的第一输入端与所述逻辑处理电路的输出端耦接，所述第一驱动级电路的接地端与所述第一参考地耦接；
    所述第二开关耦接于所述第一电压输入端和所述第一节点之间；所述第二开关的控制端与所述第二开关信号输入端耦接；
    所述高通滤波器的第一输入端与所述第一电压输入端耦接，所述高通滤波器的第二输入端与所述第二电压输入端耦接，所述高通滤波器的输出端与所述第一驱动级电路的第二输入端耦接；
    所述逻辑处理电路的第一输入端与所述第一开关信号输入端耦接，所述逻辑处理电路的第二输入端与所述第二开关信号输入端耦接；所述逻辑处理电路用于在所述第二开关断开之后，所述第一开关导通之前，切断所述第一驱动级电路的接地端与所述第一参考地的耦接；
    所述第一节点和所述电压输出端耦接。
  2. 根据权利要求1所述的开关电路，其特征在于，所述高通滤波器包括第一电容和第一电阻；
    所述第一电容耦接于所述第一电压输入端和所述第一驱动级电路的第二输入端之间；
    所述第一电阻耦接于所述第二电压输入端和所述第一驱动级电路的第二输入端之间。
  3. 根据权利要求1或2所述的开关电路，其特征在于，所述逻辑处理电路包括触发器以及或门；
    所述第二开关信号输入端与所述触发器的时钟端耦接；所述触发器的复位端与所述第一开关信号输入端耦接；所述触发器还包括用于接收固定高电平或固定低电平的输入端；
    所述触发器的输出端与所述或门的第一输入端耦接，所述或门的第二输入端与所述第一开关信号输入端耦接，所述或门的输出端与所述第一驱动级电路的第一输入端耦接。
  4. 根据权利要求1或2所述的开关电路，其特征在于，所述逻辑处理电路包括延迟电路、第一与门、第二与门、第一反相器、第二反相器以及或门；
    所述第二开关信号输入端通过所述延迟电路与所述第一与门的第一输入端耦接，所述第二开关信号输入端还通过所述第一反相器与所述第一与门的第二输入端耦接；
    所述第一与门的输出端与所述第二与门的第一输入端耦接，所述第一开关信号输入端通过所述第二反相器与所述第二与门的第二输入端耦接，所述第二与门的输出端与所述或门的第一输入端耦接；
    所述或门的第二输入端与所述第一开关信号输入端耦接，所述或门的输出端与所 述第一驱动级电路的第一输入端耦接。
  5. 根据权利要求4所述的开关电路，其特征在于，所述延迟电路包括依次串联的n个第三反相器；其中，n≥2，n为正偶数。
  6. 根据权利要求4所述的开关电路，其特征在于，所述延迟电路包括串联的第二电容和第二电阻。
  7. 根据权利要求1-6任一项所述的开关电路，其特征在于，所述第一驱动级电路包括第三开关、第四开关、第五开关、第六开关、第七开关和第八开关；
    所述第三开关和所述第四开关耦接于第二节点；所述第一开关的控制端耦接于所述第二节点；
    所述第三开关耦接于所述高通滤波器的输出端和所述第二节点之间，所述第四开关耦接于所述第二节点和所述第一参考地之间；
    所述第五开关耦接于所述第二电压输入端和所述第三开关的控制端之间；所述第六开关耦接于所述第三开关的控制端和所述第一参考地之间；所述第五开关的控制端和所述第六开关的控制端耦接于所述第一开关信号输入端；
    所述第七开关耦接于所述第二电压输入端和所述第四开关的控制端之间；所述第八开关耦接于所述第四开关的控制端和所述第一参考地之间；所述第七开关的控制端和所述第八开关的控制端耦接于所述逻辑处理电路的输出端。
  8. 根据权利要求1-7任一项所述的开关电路，其特征在于，所述开关电路还包括第二驱动级电路；
    所述第二开关的控制端通过所述第二驱动级电路与所述第二开关信号输入端耦接。
  9. 根据权利要求1-8任一项所述的开关电路，其特征在于，所述开关电路还包括电感和第三电容；
    所述电感耦接于所述第一节点和所述电压输出端之间；
    所述第三电容耦接于所述电压输出端和所述第一参考地之间。
  10. 根据权利要求1所述的开关电路，其特征在于，所述第一开关和所述第二开关为绝缘栅双极型晶体管、金属-氧化物半导体场效应晶体管或PN结型场效应晶体管。
  11. 根据权利要求7所述的开关电路，其特征在于，所述第三开关、所述第四开关、所述第五开关、所述第六开关、所述第七开关和所述第八开关为绝缘栅双极型晶体管、金属-氧化物半导体场效应晶体管或PN结型场效应晶体管。
  12. 一种开关电源，其特征在于，包括控制器和如权利要求1-11任一项所述的开关电路；
    第一开关信号输入端和第二开关信号输入端均与所述控制器耦接。
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