WO2022130827A1 - Procédé de détection de température pour élément semi-conducteur commandé en tension et dispositif d'attaque - Google Patents

Procédé de détection de température pour élément semi-conducteur commandé en tension et dispositif d'attaque Download PDF

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Publication number
WO2022130827A1
WO2022130827A1 PCT/JP2021/040996 JP2021040996W WO2022130827A1 WO 2022130827 A1 WO2022130827 A1 WO 2022130827A1 JP 2021040996 W JP2021040996 W JP 2021040996W WO 2022130827 A1 WO2022130827 A1 WO 2022130827A1
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voltage
circuit
gate
semiconductor element
controlled semiconductor
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PCT/JP2021/040996
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English (en)
Japanese (ja)
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裕章 市川
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富士電機株式会社
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Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to DE112021001992.9T priority Critical patent/DE112021001992T5/de
Priority to CN202180038235.8A priority patent/CN115698732A/zh
Priority to JP2022569765A priority patent/JPWO2022130827A1/ja
Publication of WO2022130827A1 publication Critical patent/WO2022130827A1/fr
Priority to US17/994,131 priority patent/US20230088396A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G01R31/2628—Circuits therefor for testing field effect transistors, i.e. FET's for measuring thermal properties thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/18—Modifications for indicating state of switch
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch

Definitions

  • the present invention relates to a method for detecting the chip temperature of a voltage-controlled semiconductor element for detecting the chip temperature of the voltage-controlled semiconductor element and a drive device for the voltage-controlled semiconductor element having a function of outputting the detected chip temperature to the outside.
  • semiconductor devices that switch and control inductive loads and perform power conversion.
  • Some such semiconductor devices include a semiconductor switching element and a drive device for driving the semiconductor switching element.
  • a voltage control type semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used.
  • the allowable temperature is defined by the absolute maximum rating.
  • the semiconductor chip may be thermally destroyed.
  • monitor the chip temperature and if the chip temperature is expected to be high, operate or stop the voltage-controlled semiconductor element below the rated value. I'm letting you.
  • a thermistor is provided in the semiconductor device, the temperature inside the case is detected, and the chip temperature is predicted from the operating conditions. Further, a temperature detection diode is integrally formed on a chip of a voltage control type semiconductor element, and the chip temperature is directly measured from the temperature characteristics of the temperature detection diode.
  • the method of predicting the chip temperature by the thermistor has the characteristic that since the thermistor is mounted at a position away from the semiconductor chip, it cannot follow the sudden temperature rise due to the overcurrent flowing due to the load fluctuation.
  • the active area is reduced because the temperature detection diode is built on the semiconductor chip, and the active area is further increased because the diode-dedicated electrode is provided on the semiconductor chip. Decrease. Therefore, when the temperature detection diode is mounted on the chip of the semiconductor switching element having a small current rating, the chip size becomes large.
  • Patent Document 1 a method of detecting the temperature of a chip of a voltage-controlled semiconductor element without using a thermistor or a diode for temperature detection has been proposed (see, for example, Patent Document 1 and Patent Document 2).
  • the duration of the mirror plateau is detected when the IGBT is turned off, and the temperature is detected by converting the length of the duration of the mirror plateau into the temperature. That is, in the technique of Patent Document 1, the time delay of the mirror plateau is interdependent with the junction temperature of the IGBT, and the junction temperature of the IGBT is determined from the time delay of the mirror plateau.
  • the time change of the gate voltage during the switching operation of the semiconductor device is measured, and the time change of the gate voltage is measured by utilizing the fact that the time change of the gate voltage is temperature-dependent with the temperature of the semiconductor device.
  • the temperature of the semiconductor device is estimated from the change.
  • Patent Document 1 has a problem that it is difficult to accurately detect the Miller effect period, which is the time delay of the mirror plateau.
  • the technique of Patent Document 2 has a configuration in which the gate voltage rise time is measured and the temperature of the semiconductor device corresponding to the gate voltage rise time is calculated by a microcomputer with reference to the temperature dependence information. There is a problem that the device becomes large.
  • the present invention has been made in view of such a point, and the temperature of the semiconductor chip can be monitored with high accuracy, and the voltage control does not increase the size of the configuration for detecting the temperature of the semiconductor chip. It is an object of the present invention to provide a temperature detection method and a driving device for a type semiconductor element.
  • one proposal provides a temperature detection method for a voltage-controlled semiconductor device.
  • the gate voltage that drives the gate of the voltage-controlled semiconductor element is monitored, and the gate voltage changes transiently when the voltage-controlled semiconductor element is turned on or off.
  • the voltage during the mirror effect period generated in the above is detected, and the gate voltage during the mirror effect period is output as a signal that is temperature-dependent with the chip temperature of the voltage-controlled semiconductor element.
  • the present invention provides a drive device for a voltage-controlled semiconductor element.
  • the drive device that drives this voltage-controlled semiconductor element is a drive circuit that drives the gate of the voltage-controlled semiconductor element, a gate resistor installed between the drive circuit and the gate of the voltage-controlled semiconductor element, and a drive circuit.
  • a delay circuit that delays the drive signal output by the device by a predetermined time until it reaches the mirror effect period that occurs during the period when the gate voltage changes transiently, and the rising edge or standing edge of the delay signal output by the delay circuit.
  • a one-shot circuit that outputs a pulse signal with a pulse width shorter than the mirror effect period from the trailing edge, and a gate voltage that is temperature-dependent with the chip temperature of the voltage-controlled semiconductor element as a reference voltage corresponding to the overheat detection threshold voltage. It is equipped with a comparer for comparison, and an AND circuit that inputs a pulse signal output by a one-shot circuit and an output signal of the comparer and outputs an overheat detection signal when the gate voltage exceeds a reference voltage.
  • the present invention provides yet another drive device for a voltage-controlled semiconductor element.
  • the drive device for driving this voltage-controlled semiconductor element is a drive circuit for driving the gate of the voltage-controlled semiconductor element, a gate resistor installed between the drive circuit and the gate of the voltage-controlled semiconductor element, and a drive circuit.
  • a delay circuit that delays the drive signal output by the circuit by a predetermined time until it reaches the mirror effect period that occurs during the period when the gate voltage changes transiently, and the rising edge or standing edge of the delay signal output by the delay circuit.
  • a one-shot circuit that outputs a pulse signal with a pulse width shorter than the mirror effect period from the trailing edge, and a gate voltage that is temperature-dependent with the chip temperature of the voltage-controlled semiconductor element are captured during the period when the pulse signal is input. , It is equipped with a sample hold circuit that holds and outputs the gate voltage when the input of the pulse signal is lost.
  • the present invention provides yet another drive device for a voltage-controlled semiconductor element.
  • the drive device that drives this voltage-controlled semiconductor element is a drive circuit that drives the gate of the voltage-controlled semiconductor element, a gate resistor installed between the drive circuit and the gate of the voltage-controlled semiconductor element, and a drive circuit.
  • a delay circuit that delays the drive signal output by the device by a predetermined time until it reaches the mirror effect period that occurs during the period when the gate voltage changes transiently, and the rising edge or standing edge of the delay signal output by the delay circuit.
  • a one-shot circuit that outputs a pulse signal with a pulse width shorter than the mirror effect period from the trailing edge, and a gate voltage that is temperature-dependent with the chip temperature of the voltage-controlled semiconductor element as a reference voltage corresponding to the overheat detection threshold voltage.
  • An AND circuit that inputs the comparer to be compared, the pulse signal output by the one-shot circuit and the output signal of the comparer, and outputs an overheat detection signal when the gate voltage exceeds the reference voltage, and the chip of the voltage control type semiconductor element. It is equipped with a sample hold circuit that captures the gate voltage, which is temperature-dependent and has a temperature, during the period when the pulse signal is input, and holds and outputs the gate voltage when the pulse signal is no longer input.
  • the temperature detection method and drive device for the voltage-controlled semiconductor element having the above configuration can directly and in real time monitor the chip temperature of the voltage-controlled semiconductor element, the chip temperature can be monitored with high accuracy.
  • a configuration for detecting the chip temperature can be realized with a small-scale circuit configuration.
  • FIG. 1 is a circuit diagram showing a configuration example of an IGBT drive device according to the first embodiment
  • FIG. 2 is a diagram showing the relationship between the gate voltage and the chip temperature during the Miller effect period
  • FIG. 3 is a diagram showing the relationship between the chip temperature and the first embodiment. It is a time chart explaining the operation of the driving device of the IGBT which concerns on a form.
  • FIG. 1 shows an IGBT 10 which is a semiconductor switching element and a drive device 20 which drives the IGBT 10.
  • the IGBT 10 and the drive device 20 form, for example, a semiconductor device incorporated in one package and called an intelligent power module.
  • the IGBT 10 is connected in anti-parallel to the FWD (Free Wheeling Diode) 12 that functions to return the energy stored in the inductive load to the power supply side when the IGBT 10 is turned off. That is, the anode of the FWD 12 is connected to the emitter of the IGBT 10, and the cathode of the FWD 12 is connected to the collector of the IGBT 10.
  • FWD Free Wheeling Diode
  • the drive device 20 includes a pre-driver 22, a drive circuit 24, and a gate resistor 26.
  • the pre-driver 22 has a terminal IN to which a PWM (Pulse Width Modulation) signal is input from an external host device, and the output terminal of the pre-driver 22 is connected to an input terminal of the drive circuit 24.
  • the output terminal of the drive circuit 24 is connected to one terminal of the gate resistor 26, and the other terminal of the gate resistor 26 is connected to the terminal G connected to the gate of the IGBT 10.
  • the drive circuit 24 is also connected to a terminal E connected to the emitter of the IGBT 10.
  • the PWM signal input to the terminal IN is converted into a drive signal SDRV via the predriver 22 and the drive circuit 24, and the drive signal SDRV becomes a gate voltage VGE via the gate resistor 26 and is supplied to the terminal G.
  • the drive device 20 also includes a delay circuit 28, a one-shot circuit 30, resistors 32 and 34, a comparator 36, and an AND circuit 38.
  • the input terminal of the delay circuit 28 is connected to the connection portion between the output terminal of the drive circuit 24 and one terminal of the gate resistor 26, and the output terminal of the delay circuit 28 is connected to the input terminal of the one-shot circuit 30. ..
  • One terminal of the resistor 32 is connected to the power line, the other terminal of the resistor 32 is connected to one terminal of the resistor 34, and the other terminal of the resistor 34 is connected to the ground.
  • the resistors 32 and 34 form a voltage divider circuit and output a reference voltage Vref.
  • the reference voltage Vref corresponds to the overheat detection threshold voltage, and is, for example, a voltage corresponding to 175 ° C., which is the upper limit of the guaranteed operating temperature of the IGBT 10.
  • the non-inverting input terminal is connected to the connection between the other terminal of the gate resistor 26 and the terminal G, and the inverting input terminal is connected to the connection between the other terminal of the resistor 32 and one terminal of the resistor 34. It is connected.
  • the output terminal of the one-shot circuit 30 is connected to the first input terminal of the AND circuit 38, and the output terminal of the comparator 36 is connected to the second input terminal of the AND circuit 38.
  • the output terminal of the AND circuit 38 is connected to an alarm output terminal ALM that notifies an external higher-level device of an overheat detection signal.
  • the gate voltage VGE in the Miller effect period at the time of turn-on has a temperature dependence with the chip temperature Tvj of the IGBT 10.
  • the temperature dependence is a characteristic that the gate voltage VGE changes linearly with respect to the chip temperature Tvj, so that the chip temperature Tvj can be detected from the gate voltage VGE.
  • the drive signal SDRV output by the drive circuit 24 the gate voltage VGE between the terminals G and E, the delay signal output by the delay circuit 28, and the one-shot circuit 30 are output.
  • the pulse signal to be used and the overheat detection signal of the alarm output terminal ALM are shown.
  • the drive signal SDRV rises from the low (L) level to the high (H) level
  • the voltage at the H level charges the gate-emitter capacitance of the IGBT 10 via the gate resistor 26.
  • the charge voltage of the gate-emitter capacitance exceeds the on-threshold voltage of the IGBT 10
  • the IGBT 10 turns on and the collector-emitter of the IGBT 10 is almost short-circuited.
  • the gate-emitter capacitance and the gate-collector capacitance are connected to the gate of the IGBT 10, and the IGBT 10 operates as a mirror integrator.
  • the gate voltage VGE maintains a constant state.
  • the gate of the IGBT 10 is further charged, so that the gate voltage VGE rises until it reaches the H level of the drive signal SDRV.
  • the drive signal SDRV After the drive signal SDRV reaches the L level, it follows a change opposite to the change in the gate voltage VGE when the IGBT 10 turns on, and the gate voltage VGE drops until it reaches the potential of the L level of the drive signal SDRV.
  • the drive signal SDRV is also input to the delay circuit 28.
  • the delay circuit 28 outputs a delay signal whose drive signal SDRV is delayed by the delay time Td.
  • This delay time Td is the time from the time of the rising leading edge of the drive signal SDRV to an arbitrary time point during the Miller effect period Tm of the gate voltage VGE, and is determined based on the switching characteristics of the IGBT 10.
  • the delay signal is input to the one-shot circuit 30, and outputs a pulse signal having a constant width from the time of the rising leading edge of the delay signal.
  • the pulse signal output by the one-shot circuit 30 has a pulse width shorter than the Miller effect period Tm, and is a signal for acquiring the gate voltage VGE in the Miller effect period Tm.
  • the gate voltage VGE is also supplied to the non-inverting input terminal of the comparator 36. Since the comparator 36 receives the reference voltage Vref corresponding to the overheat detection threshold voltage at its inverting input terminal, it constitutes a binarization circuit for determining whether or not the gate voltage VGE has reached the overheat detection threshold voltage. There is. The comparator 36 outputs an L level signal when the gate voltage VGE is less than the reference voltage Vref corresponding to the overheat detection threshold voltage, and outputs an H level signal when the gate voltage VGE is equal to or higher than the reference voltage Vref.
  • the AND circuit 38 receives the pulse signal output by the one-shot circuit 30 at the first input terminal, and receives the output signal of the comparator 36 at the second input terminal. As a result, the AND circuit 38 allows the output signal of the comparator 36 to pass only during the period of receiving the pulse signal.
  • the gate voltage VGE of the Miller effect period Tm is less than the reference voltage Vref, so that the comparator 36 outputs an L level signal. Therefore, the AND circuit 38 outputs an L level signal.
  • the gate voltage VGE of the Miller effect period Tm becomes equal to or higher than the reference voltage Vref, so that the comparator 36 outputs an H level signal and an AND circuit. 38 outputs an H level signal.
  • This H level signal is notified from the alarm output terminal ALM to an external higher-level device as an overheat detection signal.
  • the overheat detection signal is output from the alarm output terminal ALM to the outside, but the IGBT 10 may be forcibly turned off by inputting it to an overheat detection protection circuit (not shown).
  • FIG. 4 is a circuit diagram showing a configuration example of the IGBT drive device according to the second embodiment.
  • the drive device 20a of the IGBT 10 according to the second embodiment detects the chip temperature in real time while the drive device 20 of the first embodiment detects the overheating of the IGBT 10 and outputs an alarm. It is configured to output.
  • the drive device 20a includes a pre-driver 22, a drive circuit 24, a gate resistor 26, a delay circuit 28, and a one-shot circuit 30, which are included in the drive device 20 of the first embodiment. Since it is the same as the one, detailed description is omitted here.
  • the drive device 20a also includes a sample hold circuit 40.
  • the sample hold circuit 40 includes an operational amplifier 42, a switch element 44, a capacitor 46, and an operational amplifier 48.
  • the operational amplifier 42 connects an inverting input terminal to its own output terminal to form a voltage follower circuit, and the non-inverting input terminal is connected to a terminal G connected to the gate of the IGBT 10.
  • the output terminal of the operational amplifier 42 is connected to one terminal of the switch element 44, and the other terminal of the switch element 44 is connected to one terminal of the capacitor 46 and the non-inverting input terminal of the operational amplifier 48.
  • the other terminal of the capacitor 46 is connected to ground.
  • the control terminal of the switch element 44 is connected to the output terminal of the one-shot circuit 30.
  • the operational amplifier 48 constitutes a voltage follower circuit by connecting an inverting input terminal to its own output terminal.
  • the output terminal of the operational amplifier 48 is connected to the chip temperature output terminal TMP.
  • the influence of connecting the sample hold circuit 40 to the terminal G is minimized by configuring the operational amplifier 42 having a high input impedance to receive the gate voltage VGE. Since the operational amplifier 42 constitutes a voltage follower circuit, the gate voltage VGE input to the non-inverting input terminal is output as it is.
  • the switch element 44 receives the H level pulse signal output by the one-shot circuit 30 to the control terminal, it is turned on (conducting) only during the period in which the pulse signal is received, and the voltage output by the operational amplifier 42 ( ⁇ gate voltage VGE). Is applied to the capacitor 46. At this time, the terminal voltage of the capacitor 46 becomes a voltage that follows the voltage output by the operational amplifier 42.
  • the switch element 44 When the pulse signal output by the one-shot circuit 30 reaches the L level, the switch element 44 is turned off (non-conducting), and the terminal voltage of the capacitor 46 is held at the voltage when the switch element 44 is turned off.
  • the voltage held in the capacitor 46 is directly output as a chip temperature detection signal by the operational amplifier 48 constituting the voltage follower circuit, and is notified from the chip temperature output terminal TMP to an external higher-level device.
  • the chip temperature detection signal when the chip temperature detection signal is received from the drive device 20a, the chip temperature is obtained from the chip temperature detection signal. That is, the host device has data showing the relationship between the gate voltage VGE and the chip temperature Tvj during the Miller effect period shown in FIG. 2, and the gate voltage VGE indicated by the chip temperature detection signal is set to the corresponding chip temperature Tvj. Convert.
  • the drive device 20a can directly and in real time monitor the chip temperature of the IGBT 10, so that the chip temperature can be monitored with high accuracy, and the chip temperature can be detected. It can be realized with a small circuit configuration.
  • FIG. 5 is a circuit diagram showing a configuration example of an IGBT drive device according to a third embodiment.
  • the drive device 20b of the IGBT 10 according to the third embodiment has the overheat detection function of the IGBT 10 included in the drive device 20 of the first embodiment and the chip temperature of the IGBT 10 included in the drive device 20a of the second embodiment. It has a detection function.
  • the drive device 20b includes a predriver 22, a drive circuit 24, a gate resistor 26, a delay circuit 28, a one-shot circuit 30, resistors 32 and 34, a comparator 36, an AND circuit 38, and a sample hold circuit. It has 40 and.
  • the components of the drive device 20b described above are the same as those included in the drive device 20 of the first embodiment and the drive device 20a of the second embodiment. However, the gate voltage VGE input to the non-inverting input terminal of the comparator 36 is acquired from the output terminal of the operational amplifier 42 of the sample hold circuit 40.
  • the drive device 20b is the same as that provided in the drive device 20 of the first embodiment and the drive device 20a of the second embodiment, and the operation is also the same as the operation of the drive devices 20 and 20a. Therefore, a detailed description will be omitted here. According to this drive device 20b, both overheat detection and temperature detection can be realized.
  • the gate voltage VGE during the Miller effect period when the IGBT 10 is turned on is detected, and the chip temperature corresponding to the gate voltage VGE is obtained.
  • the gate voltage VGE may be modified to detect the Miller effect period when the IGBT 10 is turned off or both the Miller effect period when the IGBT 10 is turned on and off to determine the chip temperature.
  • the delay circuit 28 outputs a delay signal delayed by a time from the point of the trailing edge of the drive signal SDRV to an arbitrary time point during the Miller effect period Tm of the gate voltage VGE.
  • the drive devices 20 and 20a may be devices for driving the MOSFET instead of the IGBT 10.

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Abstract

La présente invention surveille, avec une précision élevée, la température d'une puce semi-conductrice d'un élément semi-conducteur commandé en tension.　Un signal d'attaque SDRV délivré par un circuit d'attaque (24) est retardé dans un circuit de retard (28) de telle sorte qu'un front avant d'attaque d'un signal de retard retardé dans le circuit de retard (28) atteint une période d'effet miroir tandis qu'un IGBT (10) est allumé, et un circuit monostable (30) reçoit le signal de retard et délivre un signal d'impulsion ayant une largeur d'impulsion qui est plus courte que la période d'effet miroir. Un comparateur (36) compare une tension de grille VGE avec une tension de référence Vref correspondant à une tension de seuil de détection de surchauffe, et délivre un signal de détection de surchauffe si la tension de grille VGE atteint ou dépasse la tension de seuil de détection de surchauffe. En surveillant la tension de grille VGE qui dépend de la température sur la température de puce de l'IGBT (10), la température de puce de l'IGBT (10) est directement surveillée.
PCT/JP2021/040996 2020-12-17 2021-11-08 Procédé de détection de température pour élément semi-conducteur commandé en tension et dispositif d'attaque WO2022130827A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE112021001992.9T DE112021001992T5 (de) 2020-12-17 2021-11-08 Temperaturmessverfahren und treibervorrichtung für spannungsgesteuertes halbleiterelement
CN202180038235.8A CN115698732A (zh) 2020-12-17 2021-11-08 电压控制型半导体元件的温度检测方法及驱动装置
JP2022569765A JPWO2022130827A1 (fr) 2020-12-17 2021-11-08
US17/994,131 US20230088396A1 (en) 2020-12-17 2022-11-25 Drive device for voltage-controlled semiconductor element

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JP2020209306 2020-12-17
JP2020-209306 2020-12-17

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US17/994,131 Continuation US20230088396A1 (en) 2020-12-17 2022-11-25 Drive device for voltage-controlled semiconductor element

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WO2022130827A1 true WO2022130827A1 (fr) 2022-06-23

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Title
HILLER SEBASTIAN, ZHANG JIANJIE, LUTZ JOSEF: "Estimating the chip temperature in an inverter by measuring the temperature sensitive Miller plateau during turn-off", PCIM EUROPE 2019, 7 May 2019 (2019-05-07) - 9 May 2019 (2019-05-09), pages 1091 - 1096, XP055942380, ISBN: 978-3-8007-4938-6 *

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CN115698732A (zh) 2023-02-03
JPWO2022130827A1 (fr) 2022-06-23
US20230088396A1 (en) 2023-03-23

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