WO2022124262A1 - Module haute fréquence et appareil de communication - Google Patents

Module haute fréquence et appareil de communication Download PDF

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Publication number
WO2022124262A1
WO2022124262A1 PCT/JP2021/044707 JP2021044707W WO2022124262A1 WO 2022124262 A1 WO2022124262 A1 WO 2022124262A1 JP 2021044707 W JP2021044707 W JP 2021044707W WO 2022124262 A1 WO2022124262 A1 WO 2022124262A1
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WIPO (PCT)
Prior art keywords
high frequency
electronic component
frequency module
mounting board
chip inductor
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PCT/JP2021/044707
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English (en)
Japanese (ja)
Inventor
浩之 山本
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株式会社村田製作所
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Publication of WO2022124262A1 publication Critical patent/WO2022124262A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving

Definitions

  • the present invention generally relates to a high frequency module and a communication device, and more particularly to a high frequency module including a mounting board and a communication device including a high frequency module.
  • Patent Document 1 describes a module component (high frequency module) including a substrate (mounting substrate) containing an inductor conductor.
  • Module parts as described in Patent Document 1 are desired to be small in size and to suppress deterioration of characteristics due to wiring length.
  • An object of the present invention is to provide a high frequency module and a communication device that can be miniaturized and can suppress characteristic deterioration due to wiring length.
  • the high frequency module includes a mounting board, a first electronic component, a second electronic component, an external connection terminal, and one or more chip inductors.
  • the mounting board has a first main surface and a second main surface facing each other.
  • the first electronic component is mounted on the first main surface of the mounting board.
  • the second electronic component is mounted on the second main surface of the mounting board.
  • the external connection terminal is arranged on the second main surface of the mounting board.
  • the chip inductor is built in the mounting board.
  • the first electronic component overlaps with the chip inductor in a plan view from the thickness direction of the mounting substrate.
  • the communication device includes the high frequency module and a signal processing circuit.
  • the signal processing circuit is connected to the high frequency module.
  • the high frequency module and the communication device it is possible to reduce the size and suppress the deterioration of characteristics due to the wiring length.
  • FIG. 1 is a cross-sectional view of the high frequency module according to the first embodiment.
  • FIG. 2 is a schematic configuration diagram of a chip inductor of the same high frequency module.
  • FIG. 3 is a circuit configuration diagram of a communication device including the same high frequency module.
  • FIG. 4 is a cross-sectional view of the high frequency module according to the first modification of the first embodiment.
  • FIG. 5 is a cross-sectional view of the high frequency module according to the second modification of the first embodiment.
  • FIG. 6 is a cross-sectional view of the high frequency module according to the third modification of the first embodiment.
  • FIG. 7 is a cross-sectional view of the high frequency module according to the second embodiment.
  • FIG. 8A is a cross-sectional view showing a first example of the manufacturing process of the high frequency module of the same.
  • FIG. 8B is a cross-sectional view showing a second example of the manufacturing process of the same high frequency module.
  • FIG. 9 is a cross-sectional view of the high frequency module according to the first modification of the second embodiment.
  • FIG. 10 is a cross-sectional view of the high frequency module according to the third embodiment.
  • FIG. 11 is a cross-sectional view of the high frequency module according to the first modification of the third embodiment.
  • FIGS. 1, 2 and 4 to 11 referred to in the following embodiments and the like are schematic views, and the ratio of the size and the thickness of each component in the figure is not necessarily the actual dimension. It does not always reflect the ratio.
  • the high frequency module 100 includes a mounting board 10, a first electronic component 201, a second electronic component 202, an external connection terminal 8, and one or more chip inductors 33.
  • the high frequency module 100 according to the first embodiment includes one chip inductor 33 as shown in FIGS. 1 and 2.
  • the mounting board 10 has a first main surface 101 and a second main surface 102 facing each other.
  • the first electronic component 201 is mounted on the first main surface 101 of the mounting board 10.
  • the first electronic component 201 is an electronic component constituting the first filter 4B.
  • the second electronic component 202 is mounted on the second main surface 102 of the mounting board 10.
  • the second electronic component 202 is an IC chip 27 including a second switch 6 and a low noise amplifier 9.
  • the external connection terminal 8 is arranged on the second main surface 102 of the mounting board 10.
  • the chip inductor 33 is built in the mounting board 10.
  • the entire chip inductor 33 is built in the mounting board 10.
  • the first electronic component 201 overlaps with the chip inductor 33 in a plan view from the thickness direction D1 of the mounting substrate 10.
  • the high frequency module 100 is used, for example, in the communication device 300.
  • the communication device 300 is, for example, a mobile phone (for example, a smartphone), but is not limited to this, and may be, for example, a wearable terminal (for example, a smart watch).
  • the high frequency module 100 is a module capable of supporting, for example, a 4G (4th generation mobile communication) standard, a 5G (5th generation mobile communication) standard, and the like.
  • the 4G standard is, for example, a 3GPP (Third Generation Partnership Project) LTE (Long Term Evolution) standard.
  • the 5G standard is, for example, 5G NR (New Radio).
  • the high frequency module 100 is a module capable of supporting carrier aggregation and dual connectivity, for example.
  • the high frequency module 100 can support simultaneous communication using a plurality of frequency bands (first frequency band and second frequency band) simultaneously in the uplink (two in the first embodiment).
  • the high frequency module 100 is configured so that a transmission signal (high frequency signal) in the first frequency band input from the signal processing circuit 301 can be amplified by the first power amplifier 1 and output to the first antenna 311. Further, the high frequency module 100 is configured so that the transmission signal (high frequency signal) in the second frequency band input from the signal processing circuit 301 can be amplified by the second power amplifier 2 and output to the second antenna 312.
  • the high frequency module 100 further includes a low noise amplifier 9, and can amplify a received signal (high frequency signal) in the first frequency band input from the first antenna 311 by the low noise amplifier 9 and output it to the signal processing circuit 301.
  • the signal processing circuit 301 is not a component of the high frequency module 100, but a component of the communication device 300 including the high frequency module 100.
  • the high frequency module 100 is controlled by, for example, the signal processing circuit 301 included in the communication device 300.
  • the communication device 300 includes a high frequency module 100 and a signal processing circuit 301.
  • the communication device 300 further includes a first antenna 311 and a second antenna 312.
  • the communication device 300 further includes a circuit board on which the high frequency module 100 is mounted.
  • the circuit board is, for example, a printed wiring board.
  • the circuit board has a ground electrode to which a ground potential is applied.
  • the signal processing circuit 301 includes, for example, an RF signal processing circuit 302 and a baseband signal processing circuit 303.
  • the RF signal processing circuit 302 is, for example, an RFIC (Radio Frequency Integrated Circuit).
  • the RF signal processing circuit 302 performs signal processing on a high frequency signal.
  • the RF signal processing circuit 302 performs signal processing such as up-conversion on the high-frequency signal (transmission signal) output from the baseband signal processing circuit 303, and transfers the signal-processed high-frequency signal to the high-frequency module 100. Output.
  • the RF signal processing circuit 302 performs signal processing such as down-conversion on the high frequency signal (received signal) output from the high frequency module 100, and uses the processed high frequency signal as a baseband signal processing circuit. Output to 303.
  • the baseband signal processing circuit 303 is, for example, a BBIC (Baseband Integrated Circuit).
  • the baseband signal processing circuit 303 generates an I-phase signal and a Q-phase signal from the baseband signal.
  • the baseband signal is, for example, an audio signal, an image signal, or the like input from the outside.
  • the baseband signal processing circuit 303 performs IQ modulation processing by synthesizing an I-phase signal and a Q-phase signal, and outputs a transmission signal.
  • the transmission signal is generated as a modulation signal (IQ signal) in which a carrier signal having a predetermined frequency is amplitude-modulated with a period longer than the period of the carrier signal.
  • the received signal processed by the baseband signal processing circuit 303 is used, for example, for displaying an image as an image signal or for a call as an audio signal.
  • the high frequency module 100 transmits a high frequency signal (received signal, transmitted signal) between the first antenna 311 and the second antenna 312 and the RF signal processing circuit 302 of the signal processing circuit 301.
  • the high frequency module 100 includes a first power amplifier 1, a second power amplifier 2, a switch 3 (hereinafter, also referred to as a first switch 3), a plurality of (for example, two) first filters 4, and a second filter. It is equipped with 5. Further, the high frequency module 100 further includes a controller 20. Further, the high frequency module 100 further includes a first output matching circuit 13, a second output matching circuit 14, a plurality of (for example, two) first matching circuits 15, and a second matching circuit 16. .. Further, the high frequency module 100 further includes a low noise amplifier 9 and an input matching circuit 19. Further, the high frequency module 100 further includes a second switch 6 as a switch other than the first switch 3.
  • the high frequency module 100 further includes a first low-pass filter 17 and a second low-pass filter 18. Further, the high frequency module 100 further includes a third switch 7, a fourth switch 23, and a fifth switch 24 as switches other than the first switch 3.
  • Each of the plurality of first filters 4 is a duplexer having a transmit filter 41 and a receive filter 42. In the following, for convenience of explanation, when the two first filters 4 are described separately, one of the two first filters 4 may be referred to as a first filter 4A and the other may be referred to as a first filter 4B.
  • the second filter 5 is a duplexer having a transmission filter 51 and a reception filter 52.
  • the high frequency module 100 is provided with a plurality of external connection terminals 8.
  • the plurality of external connection terminals 8 include a first antenna terminal 81, a second antenna terminal 82, two first signal input terminals 83, two second signal input terminals 84, and a plurality (four) control terminals. It includes 85, a signal output terminal 86, and a plurality of ground terminals 87 (see FIG. 1). In FIG. 3, only one of the four control terminals 85 is shown.
  • the plurality of ground terminals 87 are terminals that are electrically connected to the ground electrode of the above-mentioned circuit board included in the communication device 300 and are given a ground potential.
  • the first power amplifier 1 has a first input terminal 11 and a first output terminal 12.
  • the first power amplifier 1 amplifies the transmission signal of the first frequency band input to the first input terminal 11 and outputs it from the first output terminal 12.
  • the first frequency band includes, for example, a transmission band of a communication band for FDD (Frequency Division Duplex). More specifically, the first frequency band includes the transmission band of the first communication band for FDD and the transmission band of the second communication band for FDD.
  • the first communication band corresponds to the transmission signal passing through the transmission filter 41 of the first filter 4A, for example, 3GPP LTE standard Band1, Band3, Band2, Band25, Band4, Band66, Band39, Band34 or 5G NR n1, n3.
  • the second communication band corresponds to the transmission signal passing through the transmission filter 41 of the first filter 4B, and is, for example, n50 and n51 of 5G NR.
  • the first input terminal 11 of the first power amplifier 1 is selectively connected to the two first signal input terminals 83 via the fourth switch 23.
  • the first input terminal 11 of the first power amplifier 1 is connected to the signal processing circuit 301 via one of the two first signal input terminals 83.
  • the two first signal input terminals 83 are terminals for inputting a high frequency signal (transmission signal) from an external circuit (for example, a signal processing circuit 301) to the high frequency module 100.
  • One of the two first signal input terminals 83 is a terminal for inputting a transmission signal corresponding to the 4G standard to the high frequency module 100, and the other is a terminal for inputting a transmission signal corresponding to the 5G standard to the high frequency module 100. It is a terminal for.
  • the first output terminal 12 of the first power amplifier 1 is connected to the first common terminal 30A of the first switch 3 via the first output matching circuit 13. Therefore, the first output terminal 12 of the first power amplifier 1 can be connected to a plurality of first filters 4 via the first switch 3.
  • the first power amplifier 1 is, for example, a multi-stage amplifier, a common mode synthesis amplifier, a differential synthesis amplifier, or a Doherty amplifier.
  • the second power amplifier 2 has a second input terminal 21 and a second output terminal 22.
  • the second power amplifier 2 amplifies the transmission signal of the second frequency band input to the second input terminal 21 and outputs it from the second output terminal 22.
  • the second frequency band is a frequency band on the higher frequency side than the first frequency band.
  • the first frequency band is a midband frequency band
  • the second frequency band is a high band frequency band.
  • the frequency band of the mid band is, for example, 1450 MHz or more and 2200 MHz or less.
  • the frequency band of the high band is, for example, 2300 MHz or more and 2700 MHz or less.
  • the second frequency band includes, for example, a transmission band of a communication band for TDD (Time Division Duplex).
  • the second frequency band includes the transmission band of the third communication band for TDD.
  • the third communication band corresponds to the transmission signal passing through the transmission filter 51 of the second filter 5, and is, for example, 3GPP LTE standard Band 40 or Band 41 and 5G NR n40, n41.
  • the second input terminal 21 of the second power amplifier 2 is selectively connected to the two second signal input terminals 84 via the fifth switch 24.
  • the second input terminal 21 of the second power amplifier 2 is connected to the signal processing circuit 301 via one of the two second signal input terminals 84.
  • the two second signal input terminals 84 are terminals for inputting a high frequency signal (transmission signal) from an external circuit (for example, a signal processing circuit 301) to the high frequency module 100.
  • One of the two second signal input terminals 84 is a terminal for inputting a transmission signal corresponding to the 4G standard to the high frequency module 100, and the other is a terminal for inputting a transmission signal corresponding to the 5G standard to the high frequency module 100. It is a terminal for.
  • the second output terminal 22 of the second power amplifier 2 is connected to the second common terminal 30B of the first switch 3 via the second output matching circuit 14. Therefore, the second output terminal 22 of the second power amplifier 2 can be connected to the second filter 5 via the first switch 3.
  • the second power amplifier 2 is, for example, a multi-stage amplifier, a common-mode synthesis amplifier, a differential synthesis amplifier, or a Doherty amplifier.
  • the first switch 3 is connected to the first common terminal 30A, the second common terminal 30B, a plurality of (for example, two) first selection terminals 31 connectable to the first common terminal 30A, and the second common terminal 30B. It has a second selection terminal 32 that can be connected.
  • the first common terminal 30A is connected to the first output terminal 12 of the first power amplifier 1 via the first output matching circuit 13.
  • one of the two first selection terminals 31 may be referred to as a first selection terminal 31A, and the other may be referred to as a first selection terminal 31B.
  • the second common terminal 30B is connected to the second output terminal 22 of the second power amplifier 2 via the second output matching circuit 14.
  • the first selection terminal 31A is connected to the input terminal of the transmission filter 41 of the first filter 4A
  • the first selection terminal 31B is connected to the input terminal of the transmission filter 41 of the first filter 4B.
  • the second selection terminal 32 is connected to the input terminal of the transmission filter 51 of the second filter 5.
  • the first switch 3 is, for example, a switch capable of connecting at least one or more of the plurality of first selection terminals 31 to the first common terminal 30A.
  • the first switch 3 is, for example, a switch capable of one-to-one and one-to-many connections.
  • the first switch 3 is, for example, a switch IC (Integrated Circuit).
  • the first switch 3 is controlled by, for example, the controller 20.
  • the first switch 3 is controlled by the controller 20, and the connection state between the first common terminal 30A and the plurality of first selection terminals 31 and the connection between the second common terminal 30B and the second selection terminal 32.
  • the first switch 3 has, for example, a connection state between the first common terminal 30A and a plurality of first selection terminals 31 and a second common terminal 30B and a second selection terminal according to a digital control signal input from the controller 20. It suffices if it is configured to switch the connection state with 32.
  • the first switch 3 may be controlled by the signal processing circuit 301.
  • the first switch 3 follows the control signal from the RF signal processing circuit 302 of the signal processing circuit 301, and the connection state between the first common terminal 30A and the plurality of first selection terminals 31 and the second common terminal 30B. And the second selection terminal 32 are switched.
  • Each of the plurality of first filters 4 is a duplexer having a transmission filter 41 and a reception filter 42, as described above.
  • the transmission filter 41 of the first filter 4A is, for example, a bandpass filter having the transmission band of the first communication band as a pass band.
  • the transmission filter 41 of the first filter 4B is, for example, a bandpass filter having the transmission band of the second communication band as a pass band.
  • the reception filter 42 of the first filter 4A is, for example, a bandpass filter having a reception band of the first communication band as a pass band.
  • the reception filter 42 of the first filter 4B is, for example, a bandpass filter having a reception band of the second communication band as a pass band.
  • the second filter 5 is a duplexer having a transmission filter 51 and a reception filter 52.
  • the transmission filter 51 of the second filter 5 is, for example, a bandpass filter whose pass band is the transmission band of the third communication band.
  • the reception filter 52 of the second filter 5 is, for example, a bandpass filter having the reception band of the third communication band as a pass band.
  • the controller 20 is connected to the first power amplifier 1 and the second power amplifier 2. Further, the controller 20 is connected to the signal processing circuit 301 via a plurality of (for example, four) control terminals 85. In FIG. 3, only one of the four control terminals 85 is shown.
  • the plurality of control terminals 85 are terminals for inputting a control signal from an external circuit (for example, a signal processing circuit 301) to the controller 20.
  • the controller 20 controls the first power amplifier 1 and the second power amplifier 2 based on the control signals acquired from the plurality of control terminals 85.
  • the controller 20 controls the first power amplifier 1 and the second power amplifier 2 according to the control signal from the RF signal processing circuit 302 of the signal processing circuit 301.
  • the controller 20 may be configured to control the first power amplifier 1 and the second power amplifier 2 based on, for example, a digital control signal acquired from the signal processing circuit 301.
  • the first output matching circuit 13 is provided in the signal path between the first output terminal 12 of the first power amplifier 1 and the first common terminal 30A of the first switch 3.
  • the first output matching circuit 13 is a circuit for achieving impedance matching between the first power amplifier 1 and the transmission filters 41 of the two first filters 4.
  • the first output matching circuit 13 is composed of, for example, one inductor, but is not limited to this, and may be configured including, for example, a plurality of inductors and a plurality of capacitors, or may be configured to include a transformer. good.
  • the second output matching circuit 14 is provided in the signal path between the second output terminal 22 of the second power amplifier 2 and the second common terminal 30B of the first switch 3.
  • the second output matching circuit 14 is a circuit for achieving impedance matching between the second power amplifier 2 and the transmission filter 51 of the second filter 5.
  • the second output matching circuit 14 is composed of, for example, one inductor, but is not limited to this, and may be configured including, for example, a plurality of inductors and a plurality of capacitors, or may be configured to include a transformer. good.
  • the plurality of (for example, two) first matching circuits 15 have a one-to-one correspondence with the plurality of first filters 4.
  • the first matching circuit 15 corresponding to the first filter 4A among the plurality of first matching circuits 15 will be referred to as the first matching circuit 15A
  • the first matching circuit 15 corresponding to the first filter 4B will be referred to. It may also be referred to as a first matching circuit 15B.
  • the first matching circuit 15A is provided in the signal path between the first filter 4A and the third switch 7.
  • the first matching circuit 15A is a circuit for achieving impedance matching between the first filter 4A and the third switch 7.
  • the first matching circuit 15B is provided in the signal path between the first filter 4B and the third switch 7.
  • the first matching circuit 15B is a circuit for achieving impedance matching between the first filter 4B and the third switch 7.
  • Each of the plurality of first matching circuits 15 is composed of, for example, one inductor, but is not limited to this, and may be configured including, for example, a plurality of inductors and a plurality of capacitors.
  • the second matching circuit 16 is provided in the signal path between the second filter 5 and the third switch 7.
  • the second matching circuit 16 is a circuit for achieving impedance matching between the second filter 5 and the third switch 7.
  • the second matching circuit 16 is composed of, for example, one inductor, but is not limited to this, and may be configured including, for example, a plurality of inductors and a plurality of capacitors.
  • the low noise amplifier 9 has an input terminal 91 and an output terminal 92.
  • the low noise amplifier 9 amplifies the received signal of the first frequency band input to the input terminal 91 and outputs it from the output terminal 92.
  • the input terminal 91 of the low noise amplifier 9 is connected to the common terminal 60 of the second switch 6 via the input matching circuit 19.
  • the output terminal 92 of the low noise amplifier 9 is connected to the signal output terminal 86.
  • the output terminal 92 of the low noise amplifier 9 is connected to the signal processing circuit 301 via, for example, the signal output terminal 86.
  • the signal output terminal 86 is a terminal for outputting a high frequency signal (received signal) from the low noise amplifier 9 to an external circuit (for example, a signal processing circuit 301).
  • the input matching circuit 19 is provided in the signal path between the input terminal 91 of the low noise amplifier 9 and the common terminal 60 of the second switch 6.
  • the input matching circuit 19 is a circuit for impedance matching between the low noise amplifier 9 and the receiving filter 42 of each first filter 4.
  • the input matching circuit 19 is composed of, for example, one inductor (chip inductor 33) and one capacitor (chip capacitor 34), but is not limited to this, and includes, for example, a plurality of inductors and a plurality of capacitors. It may be configured.
  • the second switch 6 has a common terminal 60 and a plurality of (for example, three) selection terminals 61.
  • the common terminal 60 is connected to the input terminal 91 of the low noise amplifier 9 via the input matching circuit 19.
  • one of the three selection terminals 61 is connected to the output terminal of the reception filter 42 of the first filter 4A, and the other selection terminal 61 receives the reception of the first filter 4B. It is connected to the output terminal of the filter 42, and the remaining one selection terminal 61 is connected to the output terminal of the reception filter 52 of the second filter 5.
  • the second switch 6 is, for example, a switch capable of connecting at least one or more of the plurality of selection terminals 61 to the common terminal 60.
  • the second switch 6 is, for example, a switch capable of one-to-one and one-to-many connections.
  • the second switch 6 is, for example, a switch IC.
  • the second switch 6 is controlled by, for example, the signal processing circuit 301.
  • the second switch 6 switches the connection state between the common terminal 60 and the plurality of selection terminals 61 according to the control signal from the RF signal processing circuit 302 of the signal processing circuit 301.
  • the second switch 6 may be configured to switch the connection state between the common terminal 60 and the plurality of selection terminals 61 according to, for example, a digital control signal input from the signal processing circuit 301.
  • the second switch 6 may be controlled by the controller 20 instead of being controlled by the signal processing circuit 301.
  • the third switch 7 is connected to the first common terminal 70A, the second common terminal 70B, a plurality of (for example, two) first selection terminals 71 that can be connected to the first common terminal 70A, and the second common terminal 70B. It has a second selection terminal 72 that can be connected.
  • the first common terminal 70A is connected to the first antenna terminal 81 via the first low-pass filter 17.
  • the first antenna 311 is connected to the first antenna terminal 81.
  • the plurality of first selection terminals 71 are connected one-to-one to the plurality of first matching circuits 15.
  • the plurality of first selection terminals 71 are connected to the connection points between the output terminal of the transmission filter 41 and the input terminal of the reception filter 42 in the corresponding first filter 4 among the plurality of first filters 4.
  • the second common terminal 70B is connected to the second antenna terminal 82 via the second low-pass filter 18.
  • the second antenna 312 is connected to the second antenna terminal 82.
  • the second selection terminal 72 is connected to the connection point between the output terminal of the transmission filter 51 and the input terminal of the reception filter 52 in the second filter 5 via the second matching circuit 16.
  • the third switch 7 is, for example, a switch capable of connecting at least one or more of the plurality of first selection terminals 71 to the first common terminal 70A.
  • the third switch 7 is, for example, a switch capable of one-to-one and one-to-many connections.
  • the third switch 7 is, for example, a switch IC.
  • the third switch 7 is controlled by, for example, the signal processing circuit 301.
  • the third switch 7 follows the control signal from the RF signal processing circuit 302 of the signal processing circuit 301, and is connected to the first common terminal 70A and the plurality of first selection terminals 71, and the second common terminal 70B. And the second selection terminal 72 are switched.
  • the third switch 7 has, for example, the connection state between the first common terminal 70A and the plurality of first selection terminals 71, and the second common terminals 70B and the second according to the digital control signal input from the signal processing circuit 301. It may be configured to switch the connection state with the selection terminal 72.
  • the third switch 7 may be controlled by the controller 20 instead of being controlled by the signal processing circuit 301.
  • the fourth switch 23 has a common terminal 230 and a plurality of (for example, two) selection terminals 231.
  • the common terminal 230 is connected to the first input terminal 11 of the first power amplifier 1.
  • the two selection terminals 231 are connected one-to-one to the two first signal input terminals 83.
  • the fourth switch 23 is, for example, a switch IC.
  • the fourth switch 23 is controlled by, for example, the controller 20.
  • the fourth switch 23 is controlled by the controller 20 to switch the connection state between the common terminal 230 and the plurality of selection terminals 231.
  • the fourth switch 23 may be configured to switch the connection state between the common terminal 230 and the plurality of selection terminals 231 according to, for example, a digital control signal input from the controller 20.
  • the fourth switch 23 may be controlled by the signal processing circuit 301. In this case, the fourth switch 23 switches the connection state between the common terminal 230 and the plurality of selection terminals 231 according to the control signal from the RF signal processing circuit 302 of the signal processing circuit 301.
  • the fifth switch 24 has a common terminal 240 and a plurality of (for example, two) selection terminals 241.
  • the common terminal 240 is connected to the second input terminal 21 of the second power amplifier 2.
  • the two selection terminals 241 are connected one-to-one to the two second signal input terminals 84.
  • the fifth switch 24 is, for example, a switch IC.
  • the fifth switch 24 is controlled by, for example, the controller 20.
  • the fifth switch 24 is controlled by the controller 20 to switch the connection state between the common terminal 240 and the plurality of selection terminals 241.
  • the fifth switch 24 may be configured to switch the connection state between the common terminal 240 and the plurality of selection terminals 241 according to, for example, a digital control signal input from the controller 20.
  • the fifth switch 24 may be controlled by the signal processing circuit 301. In this case, the fifth switch 24 switches the connection state between the common terminal 240 and the plurality of selection terminals 241 according to the control signal from the RF signal processing circuit 302 of the signal processing circuit 301.
  • the first low-pass filter 17 is connected between the first antenna terminal 81 and the first common terminal 70A of the third switch 7.
  • the first low-pass filter 17 includes, for example, a plurality of inductors and capacitors.
  • the first low-pass filter 17 may be an IPD (Integrated Passive Device) including a plurality of inductors and capacitors.
  • the second low-pass filter 18 is connected between the second antenna terminal 82 and the second common terminal 70B of the third switch 7.
  • the second low-pass filter 18 includes, for example, a plurality of inductors and capacitors.
  • the second low-pass filter 18 may be an IPD including a plurality of inductors and capacitors.
  • the high frequency module 100 further includes a mounting board 10.
  • the mounting board 10 has a first main surface 101 and a second main surface 102 facing each other in the thickness direction D1 of the mounting board 10.
  • the mounting substrate 10 is, for example, a multilayer substrate including a plurality of dielectric layers and a plurality of conductive layers.
  • the plurality of dielectric layers and the plurality of conductive layers are laminated in the thickness direction D1 of the mounting substrate 10.
  • the plurality of conductive layers are formed in a predetermined pattern defined for each layer.
  • Each of the plurality of conductive layers includes one or a plurality of conductor pattern portions 40 (see FIG. 1) in one plane orthogonal to the thickness direction D1 of the mounting substrate 10.
  • the material of each conductive layer is, for example, copper.
  • the plurality of conductive layers include a ground layer.
  • a plurality of ground terminals 87 and a ground layer are electrically connected via a via conductor 50 (see FIG. 1) included in the mounting substrate 10.
  • the mounting substrate 10 is, for example, an LTCC (Low Temperature Co-fired Ceramics) substrate.
  • the mounting substrate 10 is not limited to the LTCC substrate, and may be, for example, a printed wiring board, an HTCC (High Temperature Co-fired Ceramics) substrate, or a resin multilayer substrate.
  • the mounting board 10 is not limited to the LTCC board, and may be, for example, a wiring structure.
  • the wiring structure is, for example, a multi-layer structure.
  • the multilayer structure includes at least one insulating layer and at least one conductive layer.
  • the insulating layer is formed in a predetermined pattern. When there are a plurality of insulating layers, the plurality of insulating layers are formed in a predetermined pattern determined for each layer.
  • the conductive layer is formed in a predetermined pattern different from the predetermined pattern of the insulating layer. When there are a plurality of conductive layers, the plurality of conductive layers are formed in a predetermined pattern determined for each layer.
  • the conductive layer may include one or more rewiring portions.
  • the first surface is the first main surface 101 of the mounting board 10
  • the second surface is the second main surface 102 of the mounting board 10.
  • the wiring structure may be, for example, an interposer.
  • the interposer may be an interposer using a silicon substrate or a substrate composed of multiple layers.
  • the first main surface 101 and the second main surface 102 of the mounting board 10 are separated in the thickness direction D1 of the mounting board 10 and intersect with the thickness direction D1 of the mounting board 10.
  • the first main surface 101 of the mounting board 10 is orthogonal to the thickness direction D1 of the mounting board 10, but may include, for example, the side surface of the conductor pattern portion 40 as a surface not orthogonal to the thickness direction D1.
  • the second main surface 102 of the mounting board 10 is orthogonal to the thickness direction D1 of the mounting board 10, but includes, for example, the side surface of the conductor pattern portion 40 as a surface not orthogonal to the thickness direction D1. You may.
  • first main surface 101 and the second main surface 102 of the mounting substrate 10 may be formed with fine irregularities, concave portions or convex portions.
  • the inner surface of the recess is included in the first main surface 101.
  • the circuit components of the first group among the plurality of circuit components are mounted on the first main surface 101 of the mounting board 10.
  • the circuit components of the first group include a first power amplifier 1, a second power amplifier 2, a plurality of first filters 4, a second filter 5, a first output matching circuit 13, and a second output matching circuit 14.
  • a plurality of first matching circuits 15, a second matching circuit 16, a first low-pass filter 17, and a second low-pass filter 18 are included.
  • the circuit component is mounted on the first main surface 101 of the mounting board 10 means that the circuit component is arranged on the first main surface 101 of the mounting board 10 (mechanically connected). And that the circuit component is electrically connected to the mounting board 10 (appropriate conductor pattern portion 40).
  • the circuit components of the second group among the plurality of circuit components are mounted on the second main surface 102 of the mounting board 10.
  • the circuit components of the second group include a first switch 3, a second switch 6, a third switch 7, a low noise amplifier 9, a controller 20, a fourth switch 23, and a fifth switch 24.
  • the circuit component is mounted on the second main surface 102 of the mounting board 10 means that the circuit component is arranged on the second main surface 102 of the mounting board 10 (mechanically connected). And that the circuit component is electrically connected to the mounting board 10 (appropriate conductor pattern portion 40).
  • FIG. 1 illustrates only the first filter 4B among the circuit components of the first group mounted on the first main surface 101 of the mounting board 10. Further, FIG. 1 illustrates only the IC chip 27 including the second switch 6 and the low noise amplifier 9 among the circuit components of the second group mounted on the second main surface 102 of the mounting board 10.
  • the first electronic component 201 constitutes the first filter 4B
  • the second electronic component 202 constitutes the IC chip 27.
  • the first circuit component 33 and the second circuit component 34 constituting the input matching circuit 19 are built in the mounting board 10.
  • the first circuit component 33 is a chip inductor and the second circuit component 34 is a chip capacitor.
  • the first power amplifier 1 is an IC chip including a circuit unit having a first amplification transistor. Although not shown, the first power amplifier 1 is flip-chip mounted on the first main surface 101 of the mounting board 10. The outer peripheral shape of the first power amplifier 1 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting board 10.
  • the first amplification transistor is, for example, an HBT (Heterojunction Bipolar Transistor).
  • the IC chip constituting the first power amplifier 1 is, for example, a GaAs-based IC chip.
  • the first amplification transistor is not limited to a bipolar transistor such as an HBT, and may be, for example, a FET (Field Effect Transistor).
  • the FET is, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).
  • the IC chip constituting the first power amplifier 1 is not limited to the GaAs-based IC chip, and may be, for example, a Si-based IC chip, a SiGe-based IC chip, or a GaN-based IC chip.
  • the second power amplifier 2 is an IC chip including a circuit unit having a second amplification transistor. Although not shown, the second power amplifier 2 is flip-chip mounted on the first main surface 101 of the mounting board 10. The outer peripheral shape of the second power amplifier 2 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting board 10.
  • the second amplification transistor is, for example, an HBT.
  • the IC chip constituting the second power amplifier 2 is, for example, a GaAs-based IC chip.
  • the second amplification transistor is not limited to a bipolar transistor such as an HBT, and may be, for example, an FET.
  • the IC chip constituting the second power amplifier 2 is not limited to the GaAs-based IC chip, and may be, for example, a Si-based IC chip, a SiGe-based IC chip, or a GaN-based IC chip.
  • Each of the transmit filter 41 and the receive filter 42 of the two first filters 4 is, for example, a ladder type filter, and has a plurality of (for example, four) series arm resonators and a plurality of (for example, three) parallel arms. It has a resonator.
  • Each of the two transmit filters 41 and the two receive filters 42 is, for example, an elastic wave filter.
  • each of the plurality of series arm resonators and the plurality of parallel arm resonators is composed of elastic wave resonators.
  • the surface acoustic wave filter is, for example, a surface acoustic wave filter that utilizes a surface acoustic wave.
  • each of the plurality of series arm resonators and the plurality of parallel arm resonators is, for example, a SAW (Surface Acoustic Wave) resonator.
  • the surface elastic wave filter is, for example, formed on a piezoelectric substrate and a piezoelectric substrate, and has a plurality of IDT (Interdigital Transducer) electrodes having a one-to-one correspondence with a plurality of series arm resonators and a piezoelectric substrate. It is formed and has a plurality of IDT electrodes having a one-to-one correspondence with the plurality of parallel arm resonators.
  • the piezoelectric substrate is, for example, a piezoelectric substrate.
  • the piezoelectric substrate is, for example, a lithium niobate substrate, a lithium tantalate substrate, or a quartz substrate.
  • the piezoelectric substrate is not limited to the piezoelectric substrate, and is a laminated type including, for example, a silicon substrate, a high sound velocity film on the silicon substrate, a low sound velocity film on the high sound velocity film, and a piezoelectric layer on the low sound velocity film. It may be a substrate.
  • the material of the piezoelectric layer is, for example, lithium niobate or lithium tantalate.
  • the bass sound film is a film in which the sound velocity of the bulk wave propagating in the bass velocity film is lower than the sound velocity of the bulk wave propagating in the piezoelectric layer.
  • the material of the low sound velocity film is, for example, silicon oxide.
  • the high sound velocity film is a film in which the sound velocity of the bulk wave propagating in the high sound velocity film is higher than the sound velocity of the elastic wave propagating in the piezoelectric layer.
  • the material of the high sound velocity film is, for example, silicon nitride.
  • the first filter 4A is mounted on the first main surface 101 of the mounting board 10.
  • the outer peripheral shape of the first filter 4A is a quadrangular shape in a plan view from the thickness direction D1 of the mounting substrate 10.
  • the first filter 4B is mounted on the first main surface 101 of the mounting board 10.
  • the outer peripheral shape of the first filter 4B is a quadrangular shape in a plan view from the thickness direction D1 of the mounting substrate 10.
  • Each of the transmit filter 51 and the receive filter 52 of the second filter 5 is, for example, a ladder type filter, and has a plurality of (for example, four) series arm resonators and a plurality of (for example, three) parallel arm resonators. And have.
  • Each of the transmission filter 51 and the reception filter 52 is, for example, an elastic wave filter.
  • each of the plurality of series arm resonators and the plurality of parallel arm resonators is composed of elastic wave resonators.
  • the surface acoustic wave filter is, for example, a surface acoustic wave filter that utilizes a surface acoustic wave.
  • the second filter 5 is mounted on the first main surface 101 of the mounting board 10.
  • the outer peripheral shape of the second filter 5 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting substrate 10.
  • the circuit component (inductor) of the first output matching circuit 13 is mounted on the first main surface 101 of the mounting board 10.
  • the outer peripheral shape of the circuit component of the first output matching circuit 13 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting board 10.
  • the circuit component of the first output matching circuit 13 is, for example, a chip inductor.
  • the first output matching circuit 13 may include an inner layer inductor provided in the mounting board 10.
  • the circuit component (inductor) of the second output matching circuit 14 is mounted on the first main surface 101 of the mounting board 10.
  • the outer peripheral shape of the circuit component of the second output matching circuit 14 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting board 10.
  • the circuit component of the second output matching circuit 14 is, for example, a chip inductor.
  • the second output matching circuit 14 may include an inner layer inductor provided in the mounting board 10.
  • each circuit component of the two first matching circuit 15 and the second matching circuit 16 is mounted on the first main surface 101 of the mounting board 10.
  • the outer peripheral shape of each circuit component of the two first matching circuit 15 and the second matching circuit 16 is a quadrangular shape.
  • Each circuit component of the two first matching circuit 15 and the second matching circuit 16 is, for example, a chip inductor.
  • Each of the two first matching circuit 15 and the second matching circuit 16 may include an inner layer inductor provided in the mounting board 10.
  • the first circuit component 33 of the input matching circuit 19 is a chip inductor (hereinafter, also referred to as “chip inductor 33”).
  • the second circuit component 34 of the input matching circuit 19 is a chip capacitor (hereinafter, also referred to as “chip capacitor 34”).
  • the first circuit component 33 and the second circuit component 34 of the input matching circuit 19 are built in the mounting board 10.
  • the entire first circuit component 33 is built in the mounting board 10, but for example, a part of the first circuit component 33 may be built in the mounting board 10.
  • the entire second circuit component 34 is built in the mounting board 10, but for example, even if a part of the second circuit component 34 is built in the mounting board 10. good.
  • the circuit parts are built in the mounting board 10 means that all the circuit parts are built in the mounting board 10 and that some of the circuit parts are built in the mounting board 10. ,including.
  • the outer peripheral shape of the first circuit component 33 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting board 10.
  • the outer peripheral shape of the second circuit component 34 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting board 10.
  • the first circuit component 33 and the second circuit component 34 are arranged along the second direction D2 which intersects (orthogonally) the first direction D1 which is the thickness direction of the mounting board 10.
  • the first low-pass filter 17 and the second low-pass filter 18 are mounted on the first main surface 101 of the mounting board 10.
  • the cutoff frequency of the first low-pass filter 17 is higher than the upper limit of the first frequency band.
  • the cutoff frequency of the second low-pass filter 18 is higher than the upper limit of the second frequency band.
  • each of the first switch 3, the fourth switch 23, and the fifth switch 24 is mounted on the second main surface 102 of the mounting board 10.
  • the outer peripheral shape of each of the first switch 3, the fourth switch 23, and the fifth switch 24 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting board 10.
  • Each of the first switch 3, the fourth switch 23, and the fifth switch 24 has, for example, a substrate having a first main surface and a second main surface facing each other, and a circuit formed on the first main surface side of the substrate. It is an IC chip including a part.
  • the substrate is, for example, a silicon substrate.
  • the circuit unit includes a plurality of FETs as a plurality of switching elements.
  • Each of the plurality of switching elements is not limited to the FET, and may be, for example, a bipolar transistor.
  • the first main surface of the first main surface and the second main surface of the board is on the second main surface 102 side of the mounting board 10.
  • a flip chip is mounted on the second main surface 102 of the mounting board 10.
  • Two or three of the first switch 3, the fourth switch 23, and the fifth switch 24 may be included in one IC chip.
  • the third switch 7 is mounted on the second main surface 102 of the mounting board 10.
  • the outer peripheral shape of the third switch 7 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting board 10.
  • the third switch 7 is an IC chip including, for example, a substrate having a first main surface and a second main surface facing each other, and a circuit portion formed on the first main surface side of the substrate.
  • the substrate is, for example, a silicon substrate.
  • the circuit unit includes a plurality of FETs as a plurality of switching elements. Each of the plurality of switching elements is not limited to the FET, and may be, for example, a bipolar transistor.
  • the third switch 7 is a flip chip on the second main surface 102 of the mounting board 10 so that the first main surface of the first main surface and the second main surface of the board is on the second main surface 102 side of the mounting board 10. It has been implemented.
  • the third switch 7 may be included in the IC chip 27.
  • the controller 20 is mounted on the second main surface 102 of the mounting board 10.
  • the outer peripheral shape of the controller 20 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting board 10.
  • the controller 20 is an IC chip including, for example, a substrate having a first main surface and a second main surface facing each other, and a circuit unit formed on the first main surface side of the substrate.
  • the substrate is, for example, a silicon substrate.
  • the circuit unit includes a control circuit that controls the first power amplifier 1 and the second power amplifier 2 according to the control signal from the signal processing circuit 301.
  • the controller 20 may be included in one IC chip together with at least one of the first switch 3, the fourth switch 23, and the fifth switch 24.
  • the IC chip 27 including the second switch 6 and the low noise amplifier 9 is mounted on the second main surface 102 of the mounting board 10.
  • the outer peripheral shape of the IC chip 27 is a quadrangular shape in a plan view from the thickness direction D1 of the mounting substrate 10.
  • the IC chip 27 is a Si-based IC chip, but is not limited to this.
  • the plurality of external connection terminals 8 are arranged on the second main surface 102 of the mounting board 10. "The external connection terminal 8 is arranged on the second main surface 102 of the mounting board 10" means that the external connection terminal 8 is mechanically connected to the second main surface 102 of the mounting board 10 and that it is external. The connection terminal 8 is electrically connected to the mounting board 10 (appropriate conductor pattern portion 40).
  • the material of the plurality of external connection terminals 8 is, for example, a metal (for example, copper, a copper alloy, etc.).
  • Each of the plurality of external connection terminals 8 is a columnar electrode.
  • the columnar electrode is, for example, a columnar electrode.
  • the plurality of external connection terminals 8 are bonded to the conductor pattern portion 40 of the mounting substrate 10, for example, by soldering, but the present invention is not limited to this, and for example, a conductive adhesive (for example, a conductive paste) is used. It may be joined by soldering, or it may be directly joined.
  • a conductive adhesive for example, a conductive paste
  • the plurality of external connection terminals 8 include a first antenna terminal 81, a second antenna terminal 82, a plurality of first signal input terminals 83, a plurality of second signal input terminals 84, and a plurality of controls. It includes a terminal 85, a signal output terminal 86, and a plurality of ground terminals 87.
  • the plurality of ground terminals 87 are electrically connected to the ground layer of the mounting board 10.
  • the ground layer is the circuit ground of the high frequency module 100, and the plurality of circuit components of the high frequency module 100 include circuit components that are electrically connected to the ground layer.
  • the high frequency module 100 further includes a first resin layer 105.
  • the first resin layer 105 covers each of the circuit components of the first group mounted on the first main surface 101 of the mounting board 10.
  • the first resin layer 105 contains a resin (for example, an epoxy resin).
  • the first resin layer 105 may contain a filler in addition to the resin.
  • the high frequency module 100 further includes a second resin layer 107 in addition to the first resin layer 105 arranged on the first main surface 101 of the mounting substrate 10.
  • the second resin layer 107 covers the circuit components of the second group mounted on the second main surface 102 of the mounting board 10, and the outer peripheral surfaces of each of the plurality of external connection terminals 8.
  • the second resin layer 107 contains a resin (for example, an epoxy resin).
  • the second resin layer 107 may contain a filler in addition to the resin.
  • the material of the second resin layer 107 may be the same material as the material of the first resin layer 105, or may be a different material.
  • the second resin layer 107 is formed so as to expose the main surface of each of the circuit components of the second group mounted on the second main surface 102 of the mounting board 10 on the side opposite to the mounting board 10 side. May be good.
  • the high frequency module 100 further includes a conductive layer 106.
  • the conductive layer 106 has conductivity.
  • the conductive layer 106 is provided for the purpose of electromagnetic shielding inside and outside the high frequency module 100.
  • the conductive layer 106 has a multilayer structure in which a plurality of metal layers are laminated, but the present invention is not limited to this, and may be one metal layer.
  • the metal layer contains one or more metals.
  • the conductive layer 106 covers the main surface 151 of the first resin layer 105 on the side opposite to the mounting substrate 10, the outer peripheral surface 153 of the first resin layer 105, and the outer peripheral surface 103 of the mounting substrate 10.
  • the conductive layer 106 also covers the outer peripheral surface 173 of the second resin layer 107.
  • the conductive layer 106 is in contact with at least a part of the outer peripheral surface of the ground layer of the mounting substrate 10. Thereby, the potential of the conductive layer 106 can be made the same as the potential of the ground layer.
  • the chip inductor 33 is formed in a rectangular parallelepiped shape with the second direction D2 as the longitudinal direction.
  • the second direction D2 is a direction (horizontal direction in FIG. 1) that intersects (orthogonally) the first direction D1, which is the thickness direction of the mounting substrate 10.
  • the chip inductor 33 has a first electrode 335 and a second electrode 336.
  • the first electrode 335 is located on the first main surface 101 side of the mounting substrate 10 with respect to the coil 330 of the chip inductor 33 in the first direction D1.
  • the second electrode 336 is located on the second main surface 102 side of the mounting substrate 10 with respect to the coil 330 of the chip inductor 33 in the first direction D1.
  • the chip inductor 33 further has a coil (inductor conductor) 330.
  • the coil 330 is formed by spirally winding a conductor so that the direction of the winding shaft P1 (see FIG. 1) is parallel to the first direction D1 which is the thickness direction of the mounting substrate 10 (FIG. 2). reference).
  • the first end portion 3301 of the coil 330 is connected to the first electrode 335.
  • the second end portion 3302 of the coil 330 is connected to the second electrode 336.
  • the winding interval (winding pitch) H1 of the coil 330 in the first direction D1 is narrower than the interval (pitch) H2 of the conductor pattern portion 40 of the mounting substrate 10 in the first direction D1.
  • the Q value of the inductor can be increased as compared with the case where the winding interval of the coil (inductor conductor) is the same as the interval of the conductor pattern portion 40 (that is, when only the coil is built in the mounting board 10). It becomes.
  • the input matching circuit 19 is composed of one chip inductor 33 and one chip capacitor 34.
  • the chip inductor 33 is formed in a rectangular parallelepiped shape having a first surface 331, a second surface 332, a third surface 333, and a fourth surface 334.
  • the first surface 331 and the second surface 332 face each other in the thickness direction D1 of the mounting substrate 10. Further, in the thickness direction D1 of the mounting board 10, the first surface 331 faces the first main surface 101 of the mounting board 10, and the second surface 332 faces the second main surface 102 of the mounting board 10.
  • the third surface 333 and the fourth surface 334 face each other in the second direction D2 which intersects (orthogonally) the first direction D1 which is the thickness direction of the mounting substrate 10. Further, the fourth surface 334 faces the third surface 343 of the chip capacitor 34 in the second direction D2.
  • the chip inductor 33 further has a first electrode 335 and a second electrode 336.
  • the first electrode 335 is an electrode for electrically connecting the first electronic component 201 and the chip inductor 33. That is, the chip inductor 33 is electrically connected to the first electronic component 201 via the first electrode 335.
  • the chip inductor 33 is electrically connected to the first electronic component 201 means that the chip inductor 33 is connected to the first electronic component 201 only by a conductor without using an insulator. .. In the example of FIG. 1, the chip inductor 33 is electrically connected to the first electronic component 201 via a first electrode 335 and a via conductor 50, each of which is a conductor. Further, in the example of FIG.
  • the first electrode 335 is provided on the first surface 331 of the chip inductor 33. This makes it possible to shorten the wiring length between the first electronic component 201 and the chip inductor 33.
  • the second electrode 336 is an electrode for electrically connecting the second electronic component 202 and the chip inductor 33.
  • the chip inductor 33 is electrically connected to the second electronic component 202 via a second electrode 336 and a via conductor 50, each of which is a conductor.
  • the second electrode 336 is provided on the second surface 332 of the chip inductor 33. This makes it possible to shorten the wiring length between the second electronic component 202 and the chip inductor 33.
  • the chip inductor 33 further has a coil 330 formed by spirally winding a conductor.
  • the direction of the winding shaft P1 of the coil 330 is a direction parallel to the thickness direction D1 of the mounting substrate 10.
  • the length L1 of the chip inductor 33 in the first direction D1 which is the thickness direction of the mounting board 10 is the chip inductor 33 in the second direction D2 which intersects (orthogonally) the first direction D1. Is shorter than the length L2. That is, in the high frequency module 100 according to the first embodiment, the chip inductor 33 is arranged horizontally in the mounting substrate 10. As a result, the high frequency module 100 can be made smaller (that is, thinner) in the thickness direction D1 of the mounting board 10 as compared with the case where the chip inductor 33 is arranged vertically in the mounting board 10. ..
  • the chip capacitor 34 is formed in a rectangular parallelepiped shape having a first surface 341, a second surface 342, a third surface 343, and a fourth surface 344.
  • the first surface 341 and the second surface 342 face each other in the thickness direction D1 of the mounting substrate 10. Further, in the thickness direction D1 of the mounting board 10, the first surface 341 faces the first main surface 101 of the mounting board 10, and the second surface 342 faces the second main surface 102 of the mounting board 10.
  • the third surface 343 and the fourth surface 344 face each other in the second direction D2 which intersects (orthogonally) the first direction D1 which is the thickness direction of the mounting substrate 10. Further, the third surface 343 faces the fourth surface 334 of the chip inductor 33 in the second direction D2.
  • the chip capacitor 34 further has a first electrode 345 and a second electrode 346.
  • the first electrode 345 is an electrode for electrically connecting the chip capacitor 34 and the chip inductor 33.
  • the first electrode 345 is formed in an L shape and is provided so as to straddle the second surface 342 and the third surface 343 of the chip capacitor 34.
  • the second electrode 336 of the chip inductor 33 and the first electrode 345 of the chip capacitor 34 are electrically connected to each other via the conductor pattern portion 40 of the mounting substrate 10.
  • the side surface of the second electrode 336 of the chip inductor 33 and the side surface of the chip capacitor 34 are connected via the conductor pattern portion 40.
  • the lower surface of the chip capacitor 34 may be connected to the lower surface of the chip capacitor 34 via the conductor pattern portion 40.
  • the second electrode 346 is an electrode for electrically connecting the ground terminal 87 and the chip capacitor 34.
  • the second electrode 346 is formed in an L shape and is provided so as to straddle the second surface 342 and the fourth surface 344 of the chip capacitor 34.
  • the second electrode 346 of the chip capacitor 34 and the ground terminal 87 are electrically connected via the via conductor 50 in the mounting substrate 10.
  • the inductor configured by the chip inductor 33 is connected in series to the signal path between the output terminal of the receive filter 42 of the first filter 4B and the input terminal 91 of the low noise amplifier 9. .. Further, the capacitor configured by the chip capacitor 34 is connected between the input terminal 91 of the low noise amplifier 9 and the connection point of the inductor and the ground.
  • the first electronic component 201 is mounted on the first main surface 101 of the mounting board 10. As described above, the first electronic component 201 is an electronic component constituting the first filter 4B. Further, in the high frequency module 100 according to the first embodiment, as shown in FIG. 1, the second electronic component 202 is mounted on the second main surface 102 of the mounting board 10. As described above, the second electronic component 202 is an IC chip 27 including the second switch 6 and the low noise amplifier 9. Further, in the high frequency module 100 according to the first embodiment, as shown in FIG. 1, the chip inductor 33 and the chip capacitor 34 are built in the mounting substrate 10. As described above, the chip inductor 33 and the chip capacitor 34 are circuit components constituting the input matching circuit 19. The chip inductor 33 and the chip capacitor 34 are arranged along a second direction D2 (horizontal direction in FIG. 1) that intersects (orthogonally) the first direction D1 that is the thickness direction of the mounting substrate 10.
  • the first electronic component 201 and the second electronic component 202 overlap each other in a plan view from the thickness direction D1 of the mounting board 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the first electronic component 201 and the entire second electronic component 202 overlap each other. In a plan view from the thickness direction D1 of the mounting substrate 10, a part of the first electronic component 201 and a part of the second electronic component 202 may overlap with each other, or may overlap with the whole of the first electronic component 201. A part of the second electronic component 202 may overlap, or the entire first electronic component 201 and the entire second electronic component 202 may overlap.
  • the first electronic component 201 and the second electronic component 202 overlap each other in the plan view from the thickness direction D1 of the mounting board 10 means that "the first electronic component 201 and the second electronic component 202 overlap each other" in the plan view from the thickness direction D1 of the mounting board 10. , At least a part of the first electronic component 201 and at least a part of the second electronic component 202 overlap.
  • the first electronic component 201 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting board 10. More specifically, in a plan view from the thickness direction D1 of the mounting board 10, a part of the first electronic component 201 and the entire chip inductor 33 (first circuit component) overlap each other. In a plan view from the thickness direction D1 of the mounting board 10, all of the first electronic components 201 and all of the chip inductors 33 may overlap, or all of the first electronic components 201 and the chip inductor 33 may overlap. A part of the first electronic component 201 may overlap with a part of the chip inductor 33.
  • the first electronic component 201 and the chip inductor 33 overlap each other in the plan view from the thickness direction D1 of the mounting board 10
  • the first electronic component 201 and the chip inductor 33 overlap each other in the plan view from the thickness direction D1 of the mounting board 10. 1 It means that at least a part of the electronic component 201 and at least a part of the chip inductor 33 overlap each other.
  • the chip inductor 33 is the first circuit component.
  • the second electronic component 202 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting board 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, all of the second electronic components 202 and all of the chip inductor 33 overlap. In a plan view from the thickness direction D1 of the mounting board 10, a part of the second electronic component 202 and the entire chip inductor 33 may overlap, or the entire second electronic component 202 and the chip inductor 33 may overlap. A part of the second electronic component 202 may overlap with a part of the chip inductor 33.
  • the second electronic component 202 and the chip inductor 33 overlap each other in the plan view from the thickness direction D1 of the mounting board 10
  • the second electronic component 202 and the chip inductor 33 overlap each other in the plan view from the thickness direction D1 of the mounting board 10. 2 It means that at least a part of the electronic component 202 and at least a part of the chip inductor 33 overlap each other.
  • the high frequency module 100 includes a mounting board 10, a first electronic component 201, a second electronic component 202, an external connection terminal 8, and one or more chips.
  • the inductor 33 is provided.
  • the mounting board 10 has a first main surface 101 and a second main surface 102 facing each other.
  • the first electronic component 201 is mounted on the first main surface 101 of the mounting board 10.
  • the second electronic component 202 is mounted on the second main surface 102 of the mounting board 10.
  • the external connection terminal 8 is arranged on the second main surface 102 of the mounting board 10.
  • the chip inductor 33 is built in the mounting board 10.
  • the first electronic component 201 overlaps with the chip inductor 33 in a plan view from the thickness direction D1 of the mounting substrate 10.
  • the first electronic component 201 is mounted on the first main surface 101 of the mounting board 10, and the second electronic component 202 is mounted on the second main surface 102 of the mounting board 10. It is mounted and the chip inductor 33 is built in the mounting board 10. This makes it possible to reduce the size of the high frequency module 100 as compared with the case where, for example, the first electronic component, the second electronic component, and the chip inductor are mounted on the first main surface of the mounting board. Further, in the high frequency module 100 according to the first embodiment, as described above, the first electronic component 201 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. As a result, it is possible to shorten the wiring length between the first electronic component 201 and the chip inductor 33, and it is possible to suppress deterioration of the characteristics of the high frequency module 100 due to the wiring length.
  • the chip inductor 33 is built in the mounting board 10.
  • the winding interval H1 of the coil 330 can be narrowed as compared with the case where only the coil (inductor conductor) is built in the mounting board 10. This makes it possible to suppress a decrease in the Q value of the inductor composed of the chip inductor 33. Then, by suppressing the decrease in the Q value of the inductor, it is possible to suppress the deterioration of the characteristics of the high frequency module 100.
  • the coil pattern can be finely processed by forming the electrodes by the photolithography method, it is possible to reduce the size and have high Q characteristics, and at the same time, the inductance value (L). It is possible to have a lineup of narrow deviations (values) and fine inductance values for steps.
  • the communication device 300 includes the above-mentioned high frequency module 100 and a signal processing circuit 301.
  • the signal processing circuit 301 is connected to the high frequency module 100.
  • the communication device 300 according to the first embodiment includes the high frequency module 100, the high frequency module 100 can be miniaturized and the deterioration of the characteristics of the high frequency module 100 due to the wiring length can be suppressed.
  • the communication device 300 since the communication device 300 according to the first embodiment includes the high frequency module 100, it is possible to suppress a decrease in the Q value of the inductor. Then, by suppressing the decrease in the Q value of the inductor, it is possible to suppress the deterioration of the characteristics of the high frequency module 100.
  • the plurality of electronic components constituting the signal processing circuit 301 may be mounted on, for example, the above-mentioned circuit board, or a circuit board (first circuit board) different from the circuit board (first circuit board) on which the high frequency module 100 is mounted. It may be mounted on the second circuit board).
  • Modification example (3.1) Modification example 1 The high frequency module 100a according to the first modification of the first embodiment will be described with reference to FIG. Regarding the high frequency module 100a according to the first modification, the same components as the high frequency module 100 according to the first embodiment are designated by the same reference numerals and the description thereof will be omitted.
  • the circuit configuration of the high frequency module 100a is the same as the circuit configuration of the high frequency module 100 according to the first embodiment described with reference to FIG.
  • the first electrode 345 of the chip capacitor 34 is provided so as to straddle the first surface 341 and the third surface 343 of the chip capacitor 34, and the high frequency according to the first embodiment is provided. Different from module 100.
  • the first electrode 345 of the chip capacitor 34 is formed in an L shape as shown in FIG. 4, and the first surface 341 and the third surface 343 of the chip capacitor 34 are formed. It is provided across the area.
  • the first electrode 335 of the chip inductor 33 and the first electrode 345 of the chip capacitor 34 are electrically connected via the conductor pattern portion 40 of the mounting substrate 10.
  • the inductor configured by the chip inductor 33 is connected in series with respect to the signal path between the output terminal of the reception filter 42 of the first filter 4B and the input terminal 91 of the low noise amplifier 9. It is connected. Further, the capacitor configured by the chip capacitor 34 is connected between the output terminal of the reception filter 42 and the connection point of the inductor and the ground.
  • the first electronic component 201 mounted on the first main surface 101 of the mounting board 10 and the second electronic component 202 mounted on the second main surface 102 of the mounting board 10 Is different from the high frequency module 100 according to the first embodiment in that the mounting board 10 does not overlap in a plan view from the thickness direction D1.
  • the first electronic component 201 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the first electronic component 201 and a part of the chip inductor 33 overlap each other. In a plan view from the thickness direction D1 of the mounting board 10, all of the first electronic components 201 and all of the chip inductors 33 may overlap, or all of the first electronic components 201 and the chip inductor 33 may overlap. A part of the first electronic component 201 may overlap with the entire chip capacitor 33.
  • the first electronic component 201 and the chip capacitor 34 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the first electronic component 201 and the entire chip capacitor 34 overlap each other. In a plan view from the thickness direction D1 of the mounting substrate 10, all of the first electronic components 201 and all of the chip capacitors 34 may overlap, or all of the first electronic components 201 and the chip capacitors 34 may overlap. A part of the first electronic component 201 may overlap with a part of the chip capacitor 34.
  • the second electronic component 202 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the second electronic component 202 and a part of the chip inductor 33 overlap each other. In a plan view from the thickness direction D1 of the mounting board 10, all of the second electronic components 202 and all of the chip inductor 33 may overlap, or all of the second electronic components 202 and the chip inductor 33 may overlap. A part of the second electronic component 202 may overlap with the whole of the chip inductor 33.
  • the first electronic component 201 and the second electronic component 202 do not overlap in a plan view from the thickness direction D1 of the mounting substrate 10.
  • the high frequency module 100c according to the third modification is different from the high frequency module 100 according to the first embodiment in that a plurality of external connection terminals 8 are ball bumps. Further, the high frequency module 100c according to the third modification is different from the high frequency module 100 according to the first embodiment in that the second resin layer 107 of the high frequency module 100 according to the first embodiment is not provided.
  • the high-frequency module 100c according to the third modification is between the circuit component of the second group (for example, the IC chip 27) mounted on the second main surface 102 of the mounting board 10 and the second main surface 102 of the mounting board 10. An underfill portion provided in the gap between the two may be provided.
  • the material of the ball bumps constituting each of the plurality of external connection terminals 8 is, for example, gold, copper, solder, or the like.
  • the plurality of external connection terminals 8 may be a mixture of an external connection terminal 8 formed of ball bumps and an external connection terminal 8 formed in a columnar shape.
  • the high frequency module 100d according to the second embodiment will be described with reference to FIGS. 7, 8A and 8B.
  • the same components as the high frequency module 100 according to the first embodiment are designated by the same reference numerals and the description thereof will be omitted.
  • the circuit configuration of the high frequency module 100d is the same as the circuit configuration of the high frequency module 100 according to the first embodiment described with reference to FIG.
  • the high frequency module 100d according to the second embodiment is different from the high frequency module 100 according to the first embodiment in that the input matching circuit 19 is configured by only one chip inductor 33. That is, in the high frequency module 100d according to the second embodiment, the input matching circuit 19 is composed of one inductor composed of the chip inductor 33.
  • the input matching circuit 19 is composed of one chip inductor 33 as shown in FIG. 7.
  • One chip inductor 33 is built in the mounting board 10.
  • the first electronic component 201 is mounted on the first main surface 101 of the mounting board 10.
  • the first electronic component 201 is an electronic component constituting the first filter 4B.
  • the second electronic component 202 is mounted on the second main surface 102 of the mounting board 10.
  • the second electronic component 202 is an IC chip 27 including a second switch 6 and a low noise amplifier 9.
  • the first electronic component 201 and the second electronic component 202 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the first electronic component 201 and the entire second electronic component 202 overlap each other. In a plan view from the thickness direction D1 of the mounting board 10, all of the first electronic components 201 and all of the second electronic components 202 may overlap, or all of the first electronic components 201 and the second electronic component 201 may overlap. A part of the electronic component 202 may overlap, or a part of the first electronic component 201 and a part of the second electronic component 202 may overlap.
  • the first electronic component 201 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the first electronic component 201 and the entire chip inductor 33 overlap each other. In a plan view from the thickness direction D1 of the mounting board 10, all of the first electronic components 201 and all of the chip inductors 33 may overlap, or all of the first electronic components 201 and the chip inductor 33 may overlap. A part of the first electronic component 201 may overlap with a part of the chip inductor 33.
  • the second electronic component 202 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, all of the second electronic components 202 and all of the chip inductor 33 overlap. In a plan view from the thickness direction D1 of the mounting board 10, a part of the second electronic component 202 and the entire chip inductor 33 may overlap, or the entire second electronic component 202 and the chip inductor 33 may overlap. A part of the second electronic component 202 may overlap with a part of the chip inductor 33.
  • the chip inductor 33 constituting the input matching circuit 19 is electrically connected to the first electronic component 201 via the first electrode 335 and the via conductor 50. Further, in the high frequency module 100d according to the second embodiment, the chip inductor 33 is electrically connected to the second electronic component 202 via the second electrode 336 and the via conductor 50.
  • the inductor configured by the chip inductor 33 is connected in series with respect to the signal path between the output terminal of the reception filter 42 of the first filter 4B and the input terminal 91 of the low noise amplifier 9. It is connected.
  • the first electronic component 201 is mounted on the first main surface 101 of the mounting board 10, and the second electronic component 202 is mounted on the second main surface 102 of the mounting board 10. It is mounted and all of the chip inductor 33 is built in the mounting board 10.
  • the high frequency module 100d can be downsized as compared with the case where the first electronic component, the second electronic component, and the chip inductor are mounted on the first main surface of the mounting board.
  • the first electronic component 201 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. As a result, it is possible to shorten the wiring length between the first electronic component 201 and the chip inductor 33, and it is possible to suppress deterioration of the characteristics of the high frequency module 100d due to the wiring length.
  • the chip inductor 33 constituting the input matching circuit 19 is built in the mounting board 10. This makes it possible to narrow the winding interval H1 (see FIG. 1) of the coil 330 as compared with the case where only the coil (inductor conductor) is built in the mounting board 10, and as a result, the Q value of the inductor is reduced. It becomes possible to suppress it. Then, by suppressing the decrease in the Q value of the inductor, it is possible to suppress the deterioration of the characteristics of the high frequency module 100d.
  • FIG. 8A is a cross-sectional view showing a first example of a process of incorporating the chip inductor 33 in the mounting substrate 10.
  • the chip inductor 33 is arranged on the surface (upper surface) of the first base material 111 which is a part of the mounting board 10, as shown in FIG. 8A.
  • the resin layer 35 is arranged on the upper surface of the first base material 111 so as to cover the chip inductor 33 arranged on the upper surface of the first base material 111.
  • the material of the resin layer 35 is different from, for example, the material of the first base material 111 of the mounting substrate 10.
  • the material of the first base material 111 of the mounting substrate 10 is FR4, and the material of the resin layer 35 is an epoxy resin or a polyimide resin.
  • the material of the chip inductor 33 is, for example, a low dielectric constant ceramic. That is, in the high frequency module 100d according to the second embodiment, the material of the mounting substrate 10 and the material of the chip inductor 33 are different. Therefore, in the high frequency module 100d according to the second embodiment, the dielectric constant of the mounting substrate 10 and the dielectric constant of the chip inductor 33 are different. More specifically, the dielectric constant of the mounting substrate 10 is lower than the dielectric constant of the chip inductor 33.
  • the second base material 112 which is the remaining part of the mounting board 10, is formed so as to cover the chip inductor 33 and the resin layer 35 arranged on the upper surface of the first base material 111 of the mounting board 10.
  • at least one conductor pattern portion 40 and at least one via conductor 50 are formed in the second base material 112 of the mounting substrate 10.
  • one via conductor 50 is formed in the second base material 112 of the mounting substrate 10.
  • Each of the first base material 111 and the second base material 112 in the first example is a multilayer substrate including two or more dielectric layers and two or more conductor layers.
  • FIG. 8B is a cross-sectional view showing a second example of a process of incorporating the chip inductor 33 in the mounting substrate 10.
  • a recess 110 is formed on the surface (upper surface) of the first base material 111 which is a part of the mounting substrate 10 during the manufacturing of the mounting substrate 10.
  • the recess 110 is large enough to accommodate the chip inductor 33.
  • the resin layer 35 covers the periphery of the chip inductor 33.
  • the second base material 112 which is the remaining portion of the mounting board 10, is formed so as to cover the chip inductor 33 accommodated in the recess 110 of the first base material 111 of the mounting board 10.
  • at least one conductor pattern portion 40 and at least one via conductor 50 are formed in the second base material 112 of the mounting substrate 10.
  • one via conductor 50 is formed in the second base material 112 of the mounting substrate 10.
  • Each of the first base material 111 and the second base material 112 in the second example is a multilayer substrate including two or more dielectric layers and two or more conductor layers.
  • the high frequency module 100e according to the first modification is different from the high frequency module 100e according to the second embodiment in that a plurality of chip inductors 33 are built in the mounting substrate 10.
  • a plurality of (for example, two) chip inductors 33 are built in the mounting board 10.
  • the plurality of chip inductors 33 include a first chip inductor 33A and a second chip inductor 33B.
  • the first chip inductor 33A and the second chip inductor 33B are arranged along the second direction D2.
  • the second direction D2 is a direction that intersects (orthogonally) the first direction D1, which is the thickness direction of the mounting substrate 10.
  • the first chip inductor 33A is a circuit component constituting the input matching circuit 19.
  • the first chip inductor 33A is built in the mounting board 10 so that the direction of the winding shaft P1 of the coil (inductor conductor) 330 is parallel to the first direction D1 which is the thickness direction of the mounting board 10. That is, in the high frequency module 100e according to the first modification, the first chip inductor 33A is arranged horizontally in the mounting substrate 10.
  • the second chip inductor 33B is, for example, a circuit component constituting the second matching circuit 16.
  • the second chip inductor 33B is built in the mounting substrate 10 so that the direction of the winding axis P2 of the coil (inductor conductor) 330 is parallel to the second direction D2 which intersects (orthogonally) the first direction D1. .. That is, in the high frequency module 100e according to the first modification, the second chip inductor 33B is arranged vertically in the mounting substrate 10.
  • the direction of the winding shaft P2 of the second chip inductor 33B is parallel to the second direction D2, so that the magnetic flux generated by the second chip inductor 33B causes the first.
  • the 1-chip inductor 33A and the 2nd chip inductor 33B are coupled. Therefore, in the high frequency module 100e according to the first modification, as shown in FIG. 9, a shield electrode 337 is provided on the second surface 332 of the second chip inductor 33B. In other words, the shield electrode 337 is arranged between the coil 330 of the second chip inductor 33B and the coil 330 of the first chip inductor 33A in the second direction D2.
  • the magnetic flux generated by the second chip inductor 33B and directed toward the first chip inductor 33A can be shielded by the shield electrode 337, and as a result, the first chip inductor 33A and the second chip inductor can be shielded. It is possible to suppress the binding with 33B.
  • the second chip inductor 33B of the first chip inductor 33A and the second chip inductor 33B has a shield electrode 337, but the present invention is not limited to this.
  • the first chip inductor 33A may have a shield electrode, or both the first chip inductor 33A and the second chip inductor 33B may have a shield electrode.
  • the high frequency module 100f according to the third embodiment will be described with reference to FIG. Regarding the high frequency module 100f according to the third embodiment, the same components as the high frequency module 100 according to the first embodiment are designated by the same reference numerals and the description thereof will be omitted.
  • the circuit configuration of the high frequency module 100f is the same as the circuit configuration of the high frequency module 100 according to the first embodiment described with reference to FIG.
  • the high frequency module 100f according to the third embodiment is different from the high frequency module 100 according to the first embodiment in that the first electronic component 201 mounted on the first main surface 101 of the mounting board 10 is the second power amplifier 2. do. Further, in the high frequency module 100f according to the third embodiment, the high frequency module 100 according to the first embodiment is different from the high frequency module 100 according to the first embodiment in that the second electronic component 202 mounted on the second main surface 102 of the mounting board 10 is the first switch 3. It's different. Further, in the high frequency module 100f according to the third embodiment, the high frequency module 100 according to the first embodiment is in that the chip inductor 33 and the chip capacitor 34 built in the mounting board 10 form the second output matching circuit 14. Is different from.
  • the first electronic component 201 is mounted on the first main surface 101 of the mounting substrate 10.
  • the first electronic component 201 is an electronic component that constitutes the second power amplifier 2.
  • the second electronic component 202 is mounted on the second main surface 102 of the mounting board 10.
  • the second electronic component 202 is an electronic component constituting the first switch 3. That is, the second electronic component 202 is the first switch 3 that switches a plurality of signal paths W1, W2, W3 (see FIG. 3) having different communication bands from each other.
  • one chip inductor 33 and one chip capacitor 34 are built in the mounting board 10.
  • one chip inductor 33 and one chip capacitor 34 are circuit components constituting the second output matching circuit 14.
  • the chip inductor 33 and the chip capacitor 34 are arranged along the second direction D2.
  • the second direction D2 is a direction (left-right direction in FIG. 10) that intersects (orthogonally) the thickness direction D1 of the mounting substrate 10.
  • the first electronic component 201 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the first electronic component 201 and a part of the chip inductor 33 overlap each other. In a plan view from the thickness direction D1 of the mounting board 10, a part of the first electronic component 201 and the entire chip inductor 33 may overlap, or the entire first electronic component 201 and the chip inductor 33 may overlap. May overlap with a part of the first electronic component 201, or all of the first electronic component 201 and all of the chip inductor 33 may overlap. In the high frequency module 100f according to the third embodiment, the chip inductor 33 is the first circuit component.
  • the second electronic component 202 and the chip capacitor 34 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the second electronic component 202 and a part of the chip capacitor 34 overlap each other. In a plan view from the thickness direction D1 of the mounting board 10, a part of the second electronic component 202 and the entire chip capacitor 34 may overlap, or the entire second electronic component 202 and the chip capacitor 34 may overlap. May overlap with a part of the second electronic component 202, or may overlap with all of the second electronic component 202 and all of the chip capacitor 34. In the high frequency module 100f according to the third embodiment, the chip capacitor 34 is a second circuit component.
  • the high frequency module 100f further includes a penetrating via 80.
  • the penetrating via 80 penetrates the mounting board 10 in the thickness direction D1 of the mounting board 10.
  • the penetrating via 80 overlaps with the first electronic component 201 in a plan view from the thickness direction D1 of the mounting substrate 10.
  • the penetrating via 80 is connected to the first electronic component 201.
  • the penetrating via 80 is a thermal via for radiating heat generated by the first electronic component 201 constituting the second power amplifier 2.
  • the material of the penetrating via 80 is, for example, a metal (eg, copper, copper alloy, etc.).
  • the penetrating via 80 is formed in a columnar shape.
  • the first electronic component 201 and the penetrating via 80 overlap in the thickness direction D1 of the mounting substrate 10. Therefore, in the high frequency module 100f according to the third embodiment, as shown in FIG. 10, the first electron mounted on the first main surface 101 of the mounting board 10 in a plan view from the thickness direction D1 of the mounting board 10. The component 201 and the second electronic component 202 mounted on the second main surface 102 of the mounting board 10 do not overlap.
  • the chip inductor 33 and the chip capacitor 34 constituting the second output matching circuit 14 arranged between the second power amplifier 2 and the first switch 3 are built in the mounting board 10. ing. This makes it possible to narrow the coil winding interval as compared with the case where only the coil (inductor conductor) is built in the mounting board 10, and as a result, the Q value of the inductor constituting the second output matching circuit 14 It is possible to suppress the decrease. Then, by suppressing the decrease in the Q value of the inductor, it is possible to suppress the deterioration of the characteristics of the high frequency module 100f.
  • the heat generated by the second power amplifier 2 is externally transmitted through the penetrating via 80 arranged directly under the first electronic component 201 constituting the second power amplifier 2. It is possible to dissipate heat to (for example, the circuit board described above).
  • the third electronic component 203 constituting the first switch 3 is mounted on the first main surface 101 of the mounting board 10, and the high frequency module 100f according to the third embodiment is used. It's different.
  • the third electronic component 203 is, for example, an electronic component constituting the first switch 3.
  • the first electronic component 201 constituting the second power amplifier 2 and the chip inductor 33 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the first electronic component 201 and a part of the chip inductor 33 overlap each other. This makes it possible to shorten the wiring length between the first electronic component 201 and the chip inductor 33. In a plan view from the thickness direction D1 of the mounting board 10, a part of the first electronic component 201 and the entire chip inductor 33 may overlap, or the entire first electronic component 201 and the chip inductor 33 may overlap. May overlap with a part of the first electronic component 201, or all of the first electronic component 201 and all of the chip inductor 33 may overlap.
  • the third electronic component 203 constituting the first switch 3 and the chip capacitor 34 overlap each other in a plan view from the thickness direction D1 of the mounting substrate 10. More specifically, in a plan view from the thickness direction D1 of the mounting substrate 10, a part of the third electronic component 203 and a part of the chip capacitor 34 overlap each other. This makes it possible to shorten the wiring length between the second electronic component 202 and the chip capacitor 34. In a plan view from the thickness direction D1 of the mounting board 10, a part of the second electronic component 202 and the entire chip capacitor 34 may overlap, or the entire second electronic component 202 and the chip capacitor 34 may overlap.
  • the chip capacitor 34 constitutes a circuit component constituting the second output matching circuit 14.
  • the chip inductor 33 and the chip capacitor 34 constituting the second output matching circuit 14 are built in the mounting board 10. Therefore, it is possible to narrow the coil winding interval as compared with the case where only the coil (inductor conductor) is built in the mounting substrate 10, and as a result, it is possible to suppress a decrease in the Q value of the inductor. Then, by suppressing the decrease in the Q value of the inductor, it is possible to suppress the deterioration of the characteristics of the high frequency module 100 g.
  • the heat generated by the second power amplifier 2 is externally transmitted through the penetrating via 80 arranged directly under the first electronic component 201 constituting the second power amplifier 2. It is possible to dissipate heat to (for example, the circuit board described above).
  • the conductive layer 106 is not limited to the case where the entire main surface 151 of the first resin layer 105 is covered, but the first resin layer 105. It may cover at least a part of the main surface 151 of the above.
  • each of the plurality of transmission filters 41 and 51 and the plurality of reception filters 42 and 52 is not limited to the surface acoustic wave filter, and may be, for example, a BAW (Bulk Acoustic Wave) filter.
  • the resonator in the BAW filter is, for example, FBAR (Film Bulk Acoustic Resonator) or SMR (Solidly Mounted Resonator).
  • the BAW filter has a substrate.
  • the substrate is, for example, a silicon substrate.
  • each of the plurality of transmission filters 41 and 51 and the plurality of reception filters 42 and 52 is not limited to the ladder type filter, and may be, for example, a longitudinally coupled resonator type elastic surface wave filter.
  • the above-mentioned elastic wave filter is an elastic wave filter that utilizes a surface acoustic wave or a bulk elastic wave, but is not limited to this, and may be, for example, an elastic wave filter that utilizes an elastic boundary wave, a plate wave, or the like. good.
  • the circuit configuration of the high frequency module 100 to 100 g is not limited to the example of FIG. 3 described above. Further, the high frequency module 100 to 100 g may have, for example, a MIMO (Multi Input Multi Output) compatible high frequency front end circuit as a circuit configuration.
  • MIMO Multi Input Multi Output
  • the communication device 300 may include any one of the high frequency modules 100a, 100b, 100c, 100d, 100e, 100f, and 100g instead of the high frequency module 100.
  • the first electronic component 201 may be, for example, an electronic component constituting the second filter 5. Further, the second electronic component 202 may be, for example, an electronic component constituting the third switch 7. In this case, the chip inductor constituting the second matching circuit 16 is built in the mounting board 10.
  • the chip inductor 33 is arranged horizontally in the mounting board 10, but the present invention is not limited to this.
  • the chip inductor 33 may be arranged vertically in the mounting board 10, for example.
  • the first chip inductor 33A arranged horizontally and the second chip inductor 33B arranged vertically are arranged along the second direction D2.
  • a plurality of vertically arranged chip inductors may be arranged along the second direction D2, or a plurality of horizontally arranged chip inductors may be stacked along the first direction D1. good.
  • the high-frequency module (100; 100a to 100g) includes a mounting board (10), a first electronic component (201), a second electronic component (202), an external connection terminal (8), and the like. It comprises one or more chip inductors (33).
  • the mounting substrate (10) has a first main surface (101) and a second main surface (102) facing each other.
  • the first electronic component (201) is mounted on the first main surface (101) of the mounting board (10).
  • the second electronic component (202) is mounted on the second main surface (102) of the mounting board (10).
  • the external connection terminal (8) is arranged on the second main surface (102) of the mounting board (10).
  • the chip inductor (33) is built in the mounting board (10).
  • the first electronic component (201) overlaps with the chip inductor (33) in a plan view from the thickness direction (D1) of the mounting substrate (10).
  • the second electronic component (202) is viewed in a plan view from the thickness direction (D1) of the mounting substrate (10). It overlaps with the chip inductor (33).
  • the high frequency module (100 g) according to the third aspect further includes a third electronic component (203) in the first or second aspect. Unlike the first electronic component (201), the third electronic component (203) is mounted on the first main surface (101) of the mounting board (10).
  • the chip inductor (33) constitutes a matching circuit (14) together with at least one circuit component (34).
  • the third electronic component (203) overlaps with the circuit component (34) in a plan view from the thickness direction (D1) of the mounting substrate (10).
  • the chip inductor (33) constitutes a matching circuit (14) together with at least one circuit component (34).
  • the second electronic component (202) overlaps with the circuit component (34) in a plan view from the thickness direction (D1) of the mounting substrate (10).
  • the second electronic component (202) is the first electronic component in a plan view from the thickness direction (D1) of the mounting substrate (10). It does not overlap with (201).
  • the high frequency module (100f) further includes a penetrating via (80) in the fifth aspect.
  • the penetrating via (80) penetrates the mounting board (10) along the thickness direction (D1) of the mounting board (10), and is viewed in a plan view from the thickness direction (D1) of the mounting board (10). It overlaps with the first electronic component (201).
  • the first electronic component (201) is a power amplifier connected to the penetrating via (80).
  • the heat generated in the first electronic component (201) can be dissipated through the penetrating via (80).
  • the second electronic component (202) includes a switch (3) for switching to signal paths (W1, W2, W3) having different communication bands from each other. ..
  • the first direction (D1) which is the thickness direction (D1) of the mounting substrate (10).
  • the length (L1) of the chip inductor (33) is shorter than the length (L2) of the chip inductor (33) in the second direction (D2) intersecting the first direction (D1).
  • the entire chip inductor (33) is built in the mounting substrate (10).
  • the chip inductor (33) has a first surface (331), a second surface (332), a first electrode (335), and a second electrode (336).
  • the first surface (331) faces the first main surface (101) of the mounting board (10) in the thickness direction (D1) of the mounting board (10).
  • the second surface (332) faces the second main surface (102) of the mounting board (10) in the thickness direction (D1) of the mounting board (10).
  • the first electrode (335) is provided on the first surface (331) and is electrically connected to the first electronic component (201).
  • the second electrode (336) is provided on the second surface (332) and is electrically connected to the second electronic component (202).
  • the shield electrode (337) is arranged between the coil (330) of the first chip inductor (33A) and the coil (330) of the second chip inductor (33B) in the second direction (D2).
  • the second electronic component (202) is viewed in a plan view from the thickness direction (D1) of the mounting substrate (10). It overlaps with the first electronic component (201).
  • the first electronic component (201) is a filter (4B).
  • the second electronic component (202) is an IC chip (27).
  • the material of the mounting substrate (10) and the material of the chip inductor (33) are different in any one of the first to twelfth aspects.
  • the thickness and the line width change depending on the manufacturing method, and the inductance value changes, so that it is possible to increase the variation in characteristics.
  • the communication device (300) according to the fourteenth aspect includes a high frequency module (100; 100a to 100g) according to any one of the first to thirteenth aspects, and a signal processing circuit (301).
  • the signal processing circuit (301) is connected to a high frequency module (100; 100a to 100g).

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Abstract

La présente invention permet de réduire la taille et de supprimer la dégradation des propriétés due à la longueur du câblage. Un module haute fréquence (100) est pourvu d'un substrat de montage (10), d'un premier composant électronique (201), d'un second composant électronique (202), d'une borne de connexion externe (8), et d'une ou plusieurs bobines d'induction de puce (33). Le substrat de montage (10) a une première surface principale (101) et une seconde surface principale (102) opposées l'une à l'autre. Le premier composant électronique (201) est monté sur la première surface principale (101) du substrat de montage (10). Le second composant électronique (202), contrairement au premier composant électronique (201), est monté sur la seconde surface principale (102) du substrat de montage (10). La borne de connexion externe (8) est disposée sur la seconde surface principale (102) du substrat de montage (10). La bobine d'induction de puce (33) est contenue dans le substrat de montage (10). Le premier composant électronique (201) chevauche la bobine d'induction de puce (33) dans une vue en plan depuis une direction d'épaisseur (D1) du substrat de montage (10).
PCT/JP2021/044707 2020-12-09 2021-12-06 Module haute fréquence et appareil de communication WO2022124262A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024009554A1 (fr) * 2022-07-06 2024-01-11 株式会社村田製作所 Substrat et module

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JPH02164096A (ja) * 1988-12-19 1990-06-25 Matsushita Electric Ind Co Ltd 多層電子回路基板とその製造方法
JPH10335142A (ja) * 1997-05-29 1998-12-18 Citizen Electron Co Ltd チップインダクタとその製造方法
JP2002171073A (ja) * 2000-09-19 2002-06-14 Ngk Spark Plug Co Ltd 配線基板
JP2005210074A (ja) * 2003-12-26 2005-08-04 Tdk Corp 多層基板及びパワーアンプモジュール
JP2008135781A (ja) * 2005-12-14 2008-06-12 Shinko Electric Ind Co Ltd チップ内蔵基板の製造方法
JP2010239344A (ja) * 2009-03-31 2010-10-21 Fujikura Ltd 無線回路モジュール
JP2013150349A (ja) * 2013-04-02 2013-08-01 Taiyo Yuden Co Ltd 回路基板
JP2020170944A (ja) * 2019-04-03 2020-10-15 株式会社村田製作所 高周波モジュール及び通信装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02164096A (ja) * 1988-12-19 1990-06-25 Matsushita Electric Ind Co Ltd 多層電子回路基板とその製造方法
JPH10335142A (ja) * 1997-05-29 1998-12-18 Citizen Electron Co Ltd チップインダクタとその製造方法
JP2002171073A (ja) * 2000-09-19 2002-06-14 Ngk Spark Plug Co Ltd 配線基板
JP2005210074A (ja) * 2003-12-26 2005-08-04 Tdk Corp 多層基板及びパワーアンプモジュール
JP2008135781A (ja) * 2005-12-14 2008-06-12 Shinko Electric Ind Co Ltd チップ内蔵基板の製造方法
JP2010239344A (ja) * 2009-03-31 2010-10-21 Fujikura Ltd 無線回路モジュール
JP2013150349A (ja) * 2013-04-02 2013-08-01 Taiyo Yuden Co Ltd 回路基板
JP2020170944A (ja) * 2019-04-03 2020-10-15 株式会社村田製作所 高周波モジュール及び通信装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024009554A1 (fr) * 2022-07-06 2024-01-11 株式会社村田製作所 Substrat et module

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