WO2022121382A1 - 带侧壁互连结构的半导体装置及其制造方法及电子设备 - Google Patents

带侧壁互连结构的半导体装置及其制造方法及电子设备 Download PDF

Info

Publication number
WO2022121382A1
WO2022121382A1 PCT/CN2021/115008 CN2021115008W WO2022121382A1 WO 2022121382 A1 WO2022121382 A1 WO 2022121382A1 CN 2021115008 W CN2021115008 W CN 2021115008W WO 2022121382 A1 WO2022121382 A1 WO 2022121382A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
source
layers
drain
channel
Prior art date
Application number
PCT/CN2021/115008
Other languages
English (en)
French (fr)
Inventor
朱慧珑
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US18/250,128 priority Critical patent/US20230402392A1/en
Priority to EP21902090.6A priority patent/EP4261883A1/en
Publication of WO2022121382A1 publication Critical patent/WO2022121382A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly, to semiconductor devices having sidewall interconnect structures, methods of fabricating the same, and electronic equipment including such semiconductor devices.
  • an object of the present disclosure is, at least in part, to provide a semiconductor device with a sidewall interconnect structure, a method of fabricating the same, and an electronic device including the semiconductor device.
  • a semiconductor device including a plurality of device stacks, each device stack including stacked multilayer semiconductor devices, each semiconductor device including a vertically stacked first source /drain layer, a channel layer and a second source/drain layer and a gate electrode surrounding the channel layer; an interconnect structure disposed between the plurality of device stacks.
  • the interconnect structure may include an electrical isolation layer and conductive structures in the electrical isolation layer. At least one of the respective first source/drain layers, second source/drain layers, and gate electrodes of at least a portion of the semiconductor devices laterally contacts and is thus electrically connected to conductive structures at corresponding heights in the interconnect structure.
  • a method of fabricating a semiconductor device comprising: disposing a stack on a substrate, the stack including one or more device layers, each device layer including a sequentially stacked first a source/drain layer, a channel defining layer, and a second source/drain layer; patterning the stack into pillars for defining an active region; forming a channel layer based on the channel defining layer, the channel layer is opposite to The first source/drain layer and the second source/drain layer are relatively recessed in the lateral direction; a gate electrode is formed in the recess of the channel layer relative to the first source/drain layer and the second source/drain layer; the pillar is formed An interconnect structure is formed around it, and the interconnect structure includes an electrical isolation layer and conductive structures in the electrical isolation layer.
  • the method also includes controlling the height of the conductive structure in the interconnect structure such that at least one of the respective first source/drain layer, second source/drain layer and gate electrode of at least a portion of the semiconductor device is within the corresponding height of the conductive structure laterally in contact and thus electrically connected.
  • an electronic apparatus including the above-described semiconductor device.
  • sidewall interconnect structures laterally adjacent thereto may be provided. This can reduce photolithography steps in the manufacturing process and reduce manufacturing costs.
  • the manufacturing process steps can be shared among the stacked vertical type semiconductor devices, so that the manufacturing cost can be reduced.
  • the three-dimensional configuration allows more space for interconnections between devices, and thus can have low resistance and high bandwidth.
  • the semiconductor device can have lead-out terminals, so that the fabrication of the semiconductor device can be separated from the fabrication of the metallization stack, resulting in a field programmable gate array (FPGA)-like chip.
  • FPGA field programmable gate array
  • FIGS. 1 to 33 schematically illustrate some stages in a flow of manufacturing a semiconductor device, particularly an interconnect structure therein, in accordance with an embodiment of the present disclosure
  • FIGS. 34 to 36 schematically illustrate some stages in a flow of manufacturing a semiconductor device, particularly an interconnect structure therein, in accordance with another embodiment of the present disclosure, wherein,
  • Figures 2(a) (wherein the positions of the AA' and BB' lines are shown), 2(b), 3(a), 4(a), 5(a), 12, 16(a) (wherein the The position of CC' line and DD' line is shown), 17(a) is a top view,
  • Figures 1, 2(c), 5(b), 6 to 11, 13 to 15, 34 to 36 are cross-sectional views along line AA',
  • Figures 3(b), 4(b), and 5(c) are cross-sectional views along line BB',
  • Figures 16(b), 17(b), 18(a), 19, 20(a), 21 to 27, 28(a), 31(b), 32(a), 33 are cross-sections taken along line CC' picture
  • 16(c), 17(c), 18(b), 20(b), 28(b), 29, 30, 31(a), 32(b) are cross-sectional views taken along line DD'.
  • a layer/element when referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element.
  • a layer/element when a layer/element is “on” another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under” the other layer/element.
  • a semiconductor device with a sidewall interconnect structure is provided.
  • sidewall interconnect structure it is meant that such interconnect structure is formed laterally (eg, in a direction approximately parallel to the surface of the substrate) of the device to be interconnected, and thus can pass through the sidewall of the device Interconnects with devices (components in which interconnections are required, such as source/drain layers or source/drain regions formed therein, gate electrodes, etc.).
  • the device can be a vertical type device, so its source/drain layers and gate electrodes can be at different heights (relative to the substrate). Due to the difference in height of components to be interconnected, conductive structures interconnected therewith may be formed on the sidewalls of these components, respectively.
  • a vertical device may have an active region disposed vertically on the substrate (eg, in a direction substantially perpendicular to the surface of the substrate), eg, including vertically stacked first source/drain layers, a channel layer and a second source/drain layer.
  • the channel layer can be vertical nanosheets or nanowires.
  • Source/drain regions may be formed in the first source/drain layer and the second source/drain layer, and a channel region may be formed in the channel layer.
  • the channel layer may include a single crystal semiconductor material.
  • the source/drain layers may also include single crystal semiconductor materials. For example, they can all be formed by epitaxial growth.
  • the device may further include a gate electrode disposed on the periphery of the channel layer, and the gate electrode may surround the periphery of the channel layer. Accordingly, devices according to embodiments of the present disclosure may be gate-around devices. According to an embodiment of the present disclosure, the gate electrode may be self-aligned to the channel layer. For example, at least a portion of the gate electrode near the channel layer can be substantially coplanar with the channel layer, eg, the portion of the gate electrode and the upper and/or lower surface of the channel layer are substantially coplanar with each other.
  • the first source/drain layer, the second source/drain layer, and the gate electrode may be at different heights. Therefore, interconnection with vertical devices can be achieved through conductive structures at different heights in the interconnect structure.
  • Devices can be stacked on top of each other to form a device stack to increase integration density.
  • Multiple device stacks can be provided on the substrate.
  • Interconnect structures may be formed between the device stacks to electrically connect devices within or between the device stacks that require interconnection to each other. More specifically, where the interconnect structure is adjacent to a component to be electrically connected, (the sidewall of) the conductive structure in the interconnection structure is exposed, and (the sidewall of the component) is also exposed, so that both can be are in contact with each other and are thus electrically connected.
  • An observable interface can exist between the interconnect structure and the device.
  • interconnect structures may surround the device stacks. Of course, part of the device stack may only have interconnect structures at the sidewalls where electrical connections are required.
  • device stacks can be arranged in an array.
  • the interconnect structures may include conductive structures such as interconnect lines and vias disposed in electrical isolation layers (eg, dielectric layers).
  • the interconnect structure may include alternate layers of interconnect lines and vias.
  • the interconnection layer is provided with interconnection lines to realize interconnection within the same layer, and the via hole layer is provided with via holes to realize interconnection between different layers.
  • the interconnect lines may include body portions extending within respective interconnect line layers and a barrier layer surrounding the body portions.
  • Such a semiconductor device can be fabricated as follows. For example, a stack of one or more device layers may be provided on the substrate, each device layer may include a first source/drain layer, a channel defining layer, and a second source/drain layer stacked in sequence. Between adjacent device layers and/or between the device layers and the substrate, sacrificial layers may be provided as required.
  • the stack can be formed by epitaxial growth, so the layers can be of single crystal semiconductor material.
  • the stack can be patterned into pillars for defining active regions.
  • the pillars can be arranged in an array.
  • the channel layer may be formed based on the channel defining layer.
  • the channel-defining layer can be relatively recessed laterally by selective etching and additionally grown on the sidewalls of the channel-defining layer (may be a single crystal semiconductor material due to epitaxial growth).
  • the channel layer can also be formed by the (relatively concave) channel defining layer itself.
  • a gate electrode may be formed around the channel layer. Since the channel layer is relatively recessed in the lateral direction, the gate electrode can be self-aligned to the channel layer.
  • the sacrificial layer can be replaced with a device isolation layer.
  • the sacrificial layer has etch selectivity with respect to other layers in the stack, the sacrificial layer can be removed by selective etching, and by filling, for example, a dielectric material in the voids left by the removal of the sacrificial layer.
  • a device isolation layer is formed.
  • the cylinder can be held on at least one side by a support material.
  • the sacrificial layer has no or low etch selectivity relative to other layers in the stack (eg, the channel-defining layer), then protection needs to be formed against the other layers, such as the channel-defining layer, before replacing the sacrificial layer Floor.
  • the channel defining layer may be relatively recessed in the lateral direction by selective etching.
  • the sacrificial layer is also relatively recessed in the lateral direction due to less or no etch selectivity.
  • a filling layer may be formed to eliminate such concavity of the sacrificial layer, and a protective layer (hereinafter also referred to as a position maintaining layer) may be formed in the concavity of the channel defining layer.
  • the filling layer filling only the concavity of the sacrificial layer and not filling the concavity of the channel defining layer can be formed by designing the thickness of each layer. This will be described in further detail below.
  • Source/drain layers and gate electrodes may be exposed at the sidewalls of the pillars.
  • interconnect structures may be formed to interconnect the source/drain layers and gate electrodes exposed at the sidewalls of the pillars.
  • Conductive structures in interconnect structures can be formed in layers to connect to devices at different heights.
  • interconnect lines may be formed around the pillars (eg, on a substrate or a portion of an interconnect structure that has already been formed).
  • Dielectric material may be filled to bury interconnect lines, and vias may be formed in the filled dielectric material. By repeating such operations a plurality of times, an interconnect structure including multi-layer interconnect lines and multi-layer via holes is formed. The height of interconnect lines and vias can be controlled by the formation height of the dielectric material.
  • the present disclosure may be presented in various forms, some examples of which are described below.
  • the selection of various materials takes into account etch selectivity in addition to their function (eg, semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, and conductive materials for forming interconnects and vias).
  • the desired etch selectivity may or may not be indicated. It should be clear to those skilled in the art that when it is mentioned below that a certain material layer is etched, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then such etching Can be selective, and the material layer can have etch selectivity relative to other layers exposed to the same etch recipe.
  • FIG. 1 through 33 schematically illustrate some stages in a flow of fabricating a semiconductor device, particularly an interconnect structure therein, in accordance with an embodiment of the present disclosure.
  • the substrate 1001 may be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • SiGe substrates SiGe substrates
  • the following description takes a bulk Si substrate such as a silicon wafer as an example.
  • a sacrificial layer 1003 1 for defining an isolation layer, a first source/drain layer 1005 1 for defining a lower source/drain region, a trench for defining a channel portion may be formed by, for example, epitaxial growth A channel defining layer 1007 1 , a second source/drain layer 1009 1 for defining upper source/drain regions.
  • the first source/drain layer 1005 1 , the channel defining layer 1007 1 , and the second source/drain layer 1009 1 will then define the active regions of the device, which may be referred to as "device layers", designated L1 in the figure.
  • the sacrificial layer 10031 may then be replaced with an isolation layer for isolating the device from the substrate, the thickness of which may correspond to the thickness of the isolation layer desired to be formed, eg, about 10 nm-20 nm. Depending on the circuit design, the sacrificial layer 1003 1 may not be provided.
  • the first source/drain layer 1005 1 and the second source/drain layer 1009 1 may then be doped (or doped in-situ during growth) to form source/drain regions, the thickness of which may be, for example, about 20 nm-50 nm.
  • the channel defining layer 10071 may define a gate length, and its thickness may correspond to the desired gate length, eg, about 15 nm-100 nm.
  • Each layer grown on the substrate 1001 may be a single crystal semiconductor layer, and adjacent layers may have etching selectivity.
  • the sacrificial layer 1003 1 may include SiGe (the atomic percentage of Ge is, for example, about 10%-30%, preferably 15%)
  • the first source/drain layer 1005 1 may include Si
  • the channel defining layer 1007 1 may include SiGe (The atomic percentage of Ge is, for example, about 10%-30%, preferably 15%)
  • the second source/drain layer 1009 1 may include Si.
  • the device layers L2 and L3 can be sequentially arranged on the device layer L1 by epitaxial growth, and the device layers are separated by sacrificial layers 1003 2 and 1003 3 for defining isolation layers, respectively. Depending on the circuit design, an isolation layer may not be provided between some device layers.
  • the device layer L2 may have a first source/drain layer 1005 2 , a channel defining layer 1007 2 and a second source/drain layer 1009 2
  • the device layer L3 may have a first source/drain layer 1005 3 , a channel defining layer layer 1007 3 and second source/drain layer 1009 3 .
  • Corresponding layers in each device layer may have the same or similar thicknesses and/or materials, or may have different thicknesses and/or materials.
  • the thickness of the channel-defining layer in the different device layers can be varied so that the electrical properties of the resulting device can be tuned.
  • the respective device layers L1, L2 and L3 have the same configuration.
  • a hard mask layer 1011 may be provided to facilitate patterning.
  • the hard mask layer 1011 may include nitride (eg, silicon nitride) with a thickness of about 50nm-200nm.
  • active regions can be defined in these device layers.
  • a photoresist 1013 may be formed on the hard mask layer 1011 and patterned into the shape of an active region by photolithography.
  • the photoresist 1013 is patterned in an array along the x- and y-directions, each element of the array being approximately rectangular (to define the active area of an individual device, will be columnar ), such as a rectangle with the short side in the x direction and the long side in the y direction.
  • the present disclosure is not limited thereto.
  • the photoresist 1013 can be patterned into various suitable shapes.
  • the elements in the array can be zigzag or zigzag.
  • FIG. 2( a ) for the sake of convenience, description is given with reference to the situation shown in FIG. 2( a ) as an example.
  • the photoresist 1013 thus patterned can be used as an etching mask to sequentially etch each layer on the substrate 1001 by selective etching such as reactive ion etching (RIE).
  • RIE reactive ion etching
  • the RIE may proceed in a generally vertical direction (eg, a direction perpendicular to the substrate surface) and may stop at the surface of the substrate 1001 .
  • an array of columns is left on the substrate 1001, as shown in Figure 2(c).
  • Each pillar respectively defines active regions of multiple (in this example, three) vertical devices stacked on top of each other.
  • Each cylinder can be rectangular as shown in Fig. 2(a), or zigzag or zigzag as shown in Fig. 2(b) in top view.
  • the photoresist 1013 can be removed.
  • a shielding material may be formed around the pillars.
  • one or more sides of the active region may be exposed to process the active region, while the other side or sides of the active region are masked by the masking material.
  • the masking material can also support the elongated column during fabrication, especially during the process of replacing the sacrificial layer with an isolation layer, to prevent it from collapsing.
  • a masking material (see 1017 in Figure 4(a)) may be formed on the substrate 1001, eg, by deposition.
  • the masking material 1017 may comprise SiC in view of etch selectivity (eg, relative to the hard mask layer 1011 such as nitride and a subsequently formed position maintaining layer such as oxide (eg silicon oxide)).
  • the deposited masking material 1017 may be planarized such as by chemical mechanical polishing (CMP), which may stop at the hard mask layer 1011.
  • CMP chemical mechanical polishing
  • a photoresist 1015 may be formed on the hard mask layer 1011 and the masking material 1017 and patterned to expose at least opposite sides of each pillar in the y-direction.
  • the photoresist 1015 may include openings extending along the x-direction between the pillars.
  • the photoresist 1015 thus patterned can be used as an etching mask, and the masking material 1017 can be etched by selective etching such as RIE.
  • the RIE may proceed in a substantially vertical direction and may stop at the surface of the substrate 1001 .
  • the sidewalls in the y-direction of each pillar are exposed (see Figure 3(b)), while the sidewalls in the x-direction are at least partially (depending on the size of the opening in the photoresist 1015 in the y-direction) ) are masked by masking material 1017 (see Fig. 4(a)).
  • the photoresist 1015 can be removed.
  • a gap (which may be referred to as a "gate gap") for forming the gate stack may be defined based on the channel defining layer. For example, as shown in FIGS. 4( a ) and 4 ( b ), the sidewalls exposed by the channel defining layers 1007 1 , 1007 2 , 1007 3 may be selectively etched to make them (relative to the upper and lower source/drain) layer) is relatively concave. To achieve good etch control, atomic layer etching (ALE) can be employed here.
  • ALE atomic layer etching
  • a gap (ie, gate gap) is defined between the upper and lower source/drain layers, which is originally occupied by the channel defining layer, thereby self-aligning to channel defining layer.
  • the gate gaps on opposite sides of the channel-defining layer in the y-direction may have approximately the same dimension (the height in the vertical direction corresponds to the thickness of the channel-defining layer, and the widths in the y-direction may be approximately equal to each other).
  • the etching degree of the etching formula for each channel defining layer 1007 1 , 1007 2 , and 1007 3 can be substantially the same, so that the sidewalls of each channel defining layer 1007 1 , 1007 2 , and 1007 3 can be vertically oriented after etching. The directions are still substantially aligned or substantially coplanar.
  • the sacrificial layers 1003 1 , 1003 2 , 1003 3 which are the same as the channel-defining layer and are SiGe, can also be etched so as to be relatively recessed, thereby forming corresponding gaps (which may be referred to as “isolation gaps”).
  • a first position maintaining layer 1019 (also referred to as a "sacrificial gate”) may be filled therein in order to avoid the subsequent processing of remaining material therein and affecting the formation of the gate stack.
  • a first position retention layer 1019 eg, oxide
  • etch-back eg, RIE
  • the isolation gap is also filled by the first position maintaining layer 1019.
  • a masking material can be formed first and patterned to expose the two sides to be processed.
  • a masking material may be formed on the substrate 1001 by a process such as deposition and then planarization.
  • the masking material formed here may include the same material as the previous masking material 1017 such as SiC, and thus may be integrally shown as 1017 ′ with the previous masking material 1017 . In this way, masking material 1017' surrounds each pillar.
  • photoresist 1021 can be formed and patterned to expose one side of each pillar in the x-direction.
  • photoresist 1021 may include openings extending along the y-direction between pairs of adjacent pillars.
  • the photoresist 1021 thus patterned can be used as an etching mask, and the masking material 1017' can be etched by selective etching such as RIE.
  • the RIE may proceed in a substantially vertical direction and may stop at the surface of the substrate 1001 .
  • each pillar in the x-direction is exposed, while the sidewalls in the y-direction are at least partially (depending on the size of the opening in the photoresist 1021 in the x-direction) and the x-direction
  • the other side wall is masked by masking material 1017'. Afterwards, the photoresist 1021 may be removed.
  • FIG. 6 Similar processing to Figures 4(a) and 4(b) can be performed for the currently exposed sidewalls of each pillar to define the gate gap.
  • the exposed sidewalls of the channel defining layers 1007 1 , 1007 2 , and 1007 3 may be selectively etched to be relatively recessed (relative to the upper and lower source/drain layers).
  • ALE may be employed.
  • a gate gap that is self-aligned to the channel defining layer is formed.
  • a position retention layer can be formed to fill these gate gaps.
  • the sacrificial layers 1003 1 , 1003 2 , and 1003 3 are also relatively concave, so as to form isolation gaps.
  • the position maintaining layer will also fill in the isolation gap, which will affect subsequent replacement of the sacrificial layer.
  • the isolation gap may be filled first.
  • the filling layer 1023 may be formed by epitaxial growth.
  • the growth thickness of the filling layer 1023 may be greater than half of the thickness of each sacrificial layer 1003 1 , 1003 2 , 1003 3 , so that each isolation gap can be completely filled.
  • the filling layer 1023 should not fill up the gate gap (where the position retention layer or sacrificial gate should be formed).
  • the thickness of the channel defining layer should be larger than that of the sacrificial layer (the growth thickness of the filling layer 1023 may be less than half of the thickness of the channel defining layer) as mentioned above.
  • the etching depth of the channel defining layer is preferably greater than half the thickness of the sacrificial layer (the growth thickness of the filling layer 1023 may be smaller than the etching depth of the channel defining layer). Therefore, the filling layer 1023 can fill the isolation gaps but not the gate gaps, as shown in FIG. 6 .
  • the material of the fill layer 1023 can have similar or substantially the same etch selectivity as the material of the sacrificial layer so that it can be subsequently removed together with the same etch recipe.
  • the filling layer 1023 may include SiGe, and the atomic percentage of Ge is, for example, about 10%-40%.
  • a certain thickness of the filling layer 1023 may be removed by selective etching.
  • the removal thickness may be substantially equal to or slightly greater than the growth thickness of the filling layer 1023 .
  • the filling layer 1023 may be removed from the gate gap and left in the isolation gap.
  • ALE can be used for good control of removal thickness.
  • the second position maintaining layer 1019' may be formed as described above.
  • the material of the second position maintaining layer 1019' can have similar or substantially the same etch selectivity as the material of the first position maintaining layer 1019 so that it can be subsequently removed together with the same etch recipe.
  • the second position maintaining layer 1019' may include oxide.
  • the first position maintaining layer 1019 and the second position maintaining layer 1019' are formed in different steps. This helps to control the y-direction length of the subsequently grown channel layer and the y-direction end topography.
  • the first position maintaining layer 1019 and the second position maintaining layer 1019' may also be formed in the same step, especially when the channel defining layer itself is used to form the channel layer.
  • the opposite sides of each channel defining layer in the y-direction and one side in the x-direction (the other side in the x-direction may be masked by a masking material) may be selectively etched to be relatively recessed, And a position maintaining layer is formed in the gap thus obtained.
  • each channel defining layer is surrounded by a masking material, a position maintaining layer, and a source/drain layer, while the sidewalls of the filling layer 1023 are exposed.
  • the filling layer 1023 and the sacrificial layer exposed due to its removal can be removed by selective etching. Etching can be stopped at masking material 1017'. In this way, the sacrificial layer is removed between the device layers (while the device layers are still retained by the masking material 1017').
  • the voids left by the removal of the sacrificial layer it can be filled by processes such as deposition (eg, chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.) followed by etchback (eg, RIE) dielectric material to form the isolation layer.
  • Suitable dielectric materials such as oxides, nitrides, SiC, or combinations thereof, can be selected for various purposes such as optimizing isolation reliability, leakage current or capacitance, etc.
  • the device layers can be isolated from each other.
  • the filled dielectric material may include SiC, and thus is shown integrally with the masking material 1017' as 1017".
  • a channel layer may be formed.
  • the position maintaining layer 1019' may be removed by selective etching.
  • the position maintaining layer 1019 can remain because it is covered by the masking material 1017".
  • the gate gap occupied by the position maintaining layer 1019' is released.
  • a semiconductor layer can be formed by selective epitaxial growth. The semiconductor layer can grow along the surface of the channel defining layer and the source/drain layer.
  • channel layer 1025 the part of the semiconductor layer located on the sidewall of the channel defining layer is shown separately and It is called the channel layer 1025 (the channel part will be mainly formed in this part), and the part of the semiconductor layer on the surface of the source/drain layer may be shown integrally with the source/drain layer and called the source/drain layer Drain layer (where source/drain regions will be formed) (see dashed line in Figure 10).
  • Channel layer 1025 may be formed on one sidewall of the channel defining layer in the x-direction (the side originally covered by position maintaining layer 1019'
  • the channel layers 1025 in each device layer may be substantially aligned vertically or substantially coplanar.
  • the channel defining layer and the source/drain layer may be etched back to a certain thickness.
  • the growth thickness of the semiconductor layer may be selected to be approximately equal to the thickness of the source/drain layers etched back, so that the height of the gate gap after the growth of the semiconductor layer may be substantially the same as the thickness of the channel defining layer.
  • the material of the channel layer 1025 can be selected to achieve desired device performance.
  • the channel layer 1025 may include the same material as the source/drain layer, such as Si, or may include a different material than the source/drain layer, such as SiGe.
  • a channel layer 1025 is additionally grown. This helps to control the thickness of the channel layer 1025, and the subsequent selective etching is also easier to control. Thus, double precise control of channel layer thickness and gate length can be obtained without resorting to photolithography and selective ALE.
  • the present disclosure is not limited thereto.
  • the channel portion may be formed directly using the channel defining layer.
  • another masking material 1027 may be formed on the substrate 1001 by a process such as deposition followed by planarization.
  • Another masking material 1027 may fill the gaps between the masking materials 1017" on the substrate 1001.
  • the other masking material 1027 may include an etch relative to the masking material 1017" Selective material, such as oxide.
  • the masking material 1017" may be selectively etched such as RIE. The RIE may proceed in a substantially vertical direction and may stop at the substrate 1001 .
  • the remainder of the masking material 1017" may be removed except for the portion of the masking material 1017" that is below the hard mask layer (forming an isolation layer and shown as 1017"').
  • the channel defining layer Exposed on the other side in the x-direction (although the masking material 1017" is also removed on the other two sides in the y-direction, due to the presence of the position maintaining layer 1019, the opposite sides of the channel layer 1025 in the y-direction can be obscured).
  • a gate gap can also be defined.
  • the channel defining layers 1007 1 , 1007 2 , and 1007 3 may be selectively etched.
  • ALE can be employed.
  • the etching of the channel defining layer may stop at the channel layer 1025, thereby leaving the channel layer 1025 between the upper and lower source/drain layers.
  • a gate gap is formed.
  • the gate gaps on opposite sides of the channel layer 1025 in the x-direction may have approximately the same dimension (the height in the vertical direction corresponds to the thickness of the channel defining layer, and the widths in the x-direction may be approximately equal to each other).
  • the channel portion In the case of forming the channel portion using the channel defining layers 1007 1 , 1007 2 , 1007 3 themselves without additionally growing the channel layer 1025 , around the channel defining layers 1007 1 , 1007 2 , 1007 3 can be similarly A gate gap is formed.
  • the channel defining layers 1007 1 , 1007 2 , 1007 3 may be left with a residual portion like the channel layer 1025 by selective etching such as ALE.
  • a third position-keeping layer 1027" may be similarly formed.
  • the third position-keeping layer 1027" may be formed by depositing and then etching back (eg, RIE) an oxide. .
  • the RIE may proceed in a substantially vertical direction and may stop at the surface of the substrate 1001 .
  • a plurality of pillars arranged in an array are formed on a substrate 1001.
  • a plurality of device layers are stacked in each pillar, and each device layer may include a first source/drain layer and a second source/drain layer and a channel layer therebetween.
  • a gate gap is formed around the channel layer, and the gate gap is occupied by the position maintaining layer. The gate gap is self-aligned to the channel layer.
  • the device layers are isolated from each other by isolation layers.
  • each source/drain layer is exposed to the outside.
  • the source/drain layers may be doped through these exposed sidewalls to form source/drain regions.
  • the hard mask layer 1011 is used as a mask during the etch-back process when the third position maintaining layer 1027" is formed.
  • the source/drain layers are formed in each of the x-direction and the y-direction. Opposite sidewalls in one direction are all exposed so that doping can proceed through each of these sidewalls.
  • a third position retention layer 1027′′ is formed During the etch-back process at the same time, a photoresist 1029 may be additionally formed, and the photoresist 1029 may be communicated to shield the opposite sidewalls of each pillar in the y-direction.
  • the formed third position maintaining layer 1027′′ in addition to occupying the gate gap, also shields the opposite sidewalls of the pillars in the y-direction. In this way, doping can pass through the sides of the source/drain layers in the x-direction It is possible to suppress the change in doping characteristics due to the difference in the respective widths of the gate gaps on the opposite sides in the x-direction and the gate gaps on the opposite sides in the y-direction.
  • a dopant source layer may be formed on the surface of each pillar by, for example, deposition.
  • the dopant source layer may be formed in a substantially conformal fashion.
  • the description is given by taking the example of forming two types of devices (n-type and p-type), so that n-type doping and p-type doping are required.
  • the n-type dopant source layer 1031 may be formed first and patterned to cover the pillars in which the n-type devices are to be formed. Then, a p-type dopant source layer 1035 may be formed.
  • a diffusion barrier layer 1033 may be formed therebetween.
  • the diffusion barrier layer 1033 may be formed on the n-type dopant source layer 1031 and may be patterned together with the n-type dopant source layer 1031 .
  • the n-type dopant source layer 1031 may include an n-type dopant, such as P or As doped oxide, the concentration of the dopant may be about 0.1%-10%, and the thickness may be about 1 nm-10 nm.
  • the p-type dopant source layer 1035 may include a p-type dopant, such as a B-doped oxide, the concentration of the dopant may be about 0.1%-10%, and the thickness may be about 1 nm-10 nm.
  • the diffusion barrier layer 1033 may include nitride and have a thickness of about 2nm-10nm.
  • source/drain regions may be formed in the source/drain layers by driving dopants from the dopant source layer into the source/drain layers by, for example, an annealing process.
  • n-type source/drain regions S/D 1 and p-type source/drain regions S/D 2 are shown.
  • the substrate 1001 may also be doped.
  • the position maintaining layer can prevent dopants from directly entering the channel layer 1025 .
  • the n-type dopant source layer 1031 , the p-type dopant source layer 1035 and the diffusion barrier layer 1033 may be removed.
  • the source/drain layers in each pillar are doped to the same conductivity type.
  • the present disclosure is not limited thereto.
  • the source/drain layers in the different device layers in each pillar can be doped to different conductivity types.
  • the surfaces of the source/drain layers may be silicided to reduce contact resistance.
  • a metal such as NiPt can be formed on the surface of each pillar and annealed to react with Si in the source/drain layers to form a metal silicide such as NiPtSi. Afterwards, unreacted metals can be removed.
  • a replacement gate process may be performed to replace the position retaining layer with the gate stack.
  • the position maintaining layers 1019, 1027" may be removed by selective etching, thereby releasing the gate gap.
  • the gate dielectric layer 1037 may be formed in a substantially conformal manner, eg, by deposition, ALD.
  • a gate conductor layer can be formed by, for example, deposition and ALD.
  • the gate conductor layer 1039 1 of the n-type device is formed as an example for description.
  • the deposited gate conductor layer 1039 1 can be filled with Fill the gate gap.
  • the portion of the gate conductor layer 1039 1 outside the gate gap can be removed by etching back such as RIE, so that the gate conductor layer 1039 1 can remain in the gate gap. Then, the n-type can be covered with, for example, photoresist The p-type device is exposed, and the gate conductor layer 1039 1 formed in the gate gap of the p-type device can be removed by selective etching to release its gate gap. It can be formed in the gate gap of the p-type device in a similar manner The gate conductor layer 1039 2 of the p-type device.
  • the gate dielectric layer 1037 may include a high-k gate dielectric such as HfO 2 , and the gate conductor layers 1039 1 and 1039 2 may include metal gate conductors with corresponding work functions.
  • the n-type devices and The p-type devices have the same gate dielectric layer 1037, but the present disclosure is not limited thereto. For example, they may have different gate dielectric layers.
  • the order of forming the gate conductor layers may be interchanged.
  • Each vertical type device may include a channel layer 1025 and first and second source/drain layers on upper and lower sides of the channel layer 1025 .
  • a gate stack (a stack of gate dielectric layers and gate conductor layers) may surround and be self-aligned to the channel layer 1025 .
  • Each pillar may be referred to as a device stack. Between the device stacks, the substrate 1001 is relatively concave, which becomes a groove.
  • interconnect structures can be formed laterally adjacent to each device for interconnecting the devices in each device stack to each other.
  • the interconnect structure laterally adjoins the device and contacts the sidewalls of the components in the device that need to be electrically connected, it may be referred to as a sidewall interconnect structure.
  • conductive structures at different heights may interface with devices on different sides in order to avoid undesired electrical shorts when forming interconnect structures.
  • a first component of the device that requires electrical connection at a certain height may interface with a conductive structure in the interconnect structure on a first side, while a first component that requires electrical connection vertically adjacent to the first component
  • the two components may interface with the conductive structures in the interconnect structure on a second side different from the first side (eg, opposite the first side).
  • the sidewall of the first part on the second side may be covered by the isolation layer, and the sidewall of the second part on the first side may be covered by the isolation layer to avoid short circuits.
  • a photoresist 1041 may be formed on the substrate 1001 and patterned to mask one side of each device stack ( Figure 16 (a) the upper side in the y-direction), while the other side (the lower side in the y-direction in FIG. 16(a)) of each device stack is exposed.
  • the gate conductor layer On the exposed side of each device stack, the gate conductor layer may be relatively recessed to a certain depth, eg, about 5nm-20nm, by selective etching to release some of the gate gap. In these gate gaps, self-aligned isolation layers can then be formed. Afterwards, the photoresist 1041 may be removed.
  • a photoresist 1043 can be formed on the substrate 1001 and patterned to mask one side of each device stack ( Figure 17 (a) the lower side in the y-direction), while the other side (upper side in the y-direction in FIG. 17(a) ) of each device stack is exposed.
  • the source/drain layers can be relatively recessed by selective etching to a depth, for example, about 5nm-20nm (which can be the same depth as the previously released gate gap for subsequent filling can have roughly the same thickness) to free up some space. In these spaces, self-aligned isolation layers can then be formed. Afterwards, the photoresist 1043 may be removed.
  • isolation layers may be formed.
  • isolation layers 1045 can be filled in these recesses by a process of deposition followed by etch back.
  • the isolation layer 1045 may include a dielectric material such as SiC in consideration of etch selectivity with a subsequently formed interlayer dielectric layer.
  • the isolation layers 1045 in different device layers may be substantially aligned or substantially coplanar in the vertical direction.
  • the interconnect structure can be performed.
  • the conductive structures can be formed first, and then filled with the dielectric Material.
  • the bottommost is the first source/drain layer or source/drain region of the device layer L1.
  • Conductive structures for the first source/drain layer may be formed first.
  • an electrical isolation layer with a certain thickness can be formed in the grooves between the device stacks first, so that the The conductive structures formed on the electrical isolation layer can be at a height corresponding to the first source/drain layer so as to abut laterally therewith.
  • the electrical isolation layers so formed should expose the sidewalls of the various device stacks to avoid interfering with electrical contact with the sidewall interconnect structures.
  • the preliminary isolation layer 1047 may be formed by depositing a dielectric material such as an oxide.
  • the preliminary isolation layer 1047 may be formed to have a thicker laterally extending portion and a thinner vertically extending portion. For example, this can be achieved by high density plasma (HDP) deposition.
  • the thickness of the thicker portion of the preparatory isolation layer 1047 may be about 20 nm-150 nm.
  • the preparatory isolation layer 1047 may be isotropically etched to a thickness that removes the vertically extending portion of the preparatory isolation layer 1047, but leaves its lateral extension.
  • the thickness of the remaining portion may be about 15 nm to 100 nm. Therefore, the preparatory isolation layer 1047 can be left in the grooves between the isolation devices (a part of which is also left on the top of the device stacks, which will not affect the subsequent process) to form the electrical isolation layer 1047'.
  • conductive structures can be fabricated on the electrical isolation layer 1047'.
  • a conductive barrier layer 1049 and a conductive body layer 1051 may be sequentially formed in a substantially conformal manner by deposition.
  • the conductive barrier layer 1049 can prevent the conductive body layer 1051 from diffusing to the surroundings, and for example, can include conductive nitrides such as TiN, TaN, and the like.
  • the conductive body layer 1051 may be used to achieve electrical connection between devices, and may include metals such as tungsten (W), cobalt (Co), rubidium (Ru), copper (Cu), aluminum (Al), nickel (Ni), and the like, for example.
  • the formed conductive barrier layer 1049 and conductive body layer 1051 can be in contact with and connected to the first source/drain layer of the lowermost device in each device stack.
  • the conductive barrier layer 1049 and conductive body layer 1051 can then be patterned into conductive structures for the first source/drain layers of the lowermost devices in each device stack.
  • the portion of the conductive barrier layer 1049 and the conductive body layer 1051 at the bottom of the trench is to be left, so a mask can be formed to cover this portion.
  • This form of masking can be performed, for example, by the method described above in connection with Figures 19 to 20(b).
  • the mask layer 1053 and the patterning auxiliary layer 1055 may be sequentially formed by deposition in a substantially conformal manner.
  • the mask layer 1053 may include oxide, and the thickness may be about 1 nm-5 nm; considering the convenience of local modification (changing the etching selectivity), the patterning auxiliary layer 1055 may include polysilicon or non-woven fabrics. Crystalline silicon, the thickness can be about 5nm-20nm.
  • Impurities such as B may be implanted in the horizontally extending portion 1055a of the patterning auxiliary layer 1055 by ion implantation in the vertical direction and annealed at, for example, about 550° C. to about 900° C.
  • the undoped portion of the patterning assistant layer 1055 may be removed by selective etching, such as wet etching using TMAH, thereby leaving the doped portion 1055a thereof.
  • the doped portion 1055a can be used as an etching mask, and the mask layer 1053 can be selectively etched to obtain a mask in a desired form.
  • ALE can be used.
  • the doped portion 1055a may be removed by selective etching such as RIE.
  • the conductive barrier layer 1049 and the conductive body layer 1051 can be etched isotropically by using the mask layer 1053 as an etch mask, so that they can be left at the bottom of the groove (and part of each device the top surface of the stack, which will be removed in a subsequent process).
  • ALE can be employed to achieve good etch control.
  • the mask layer 1053 may be removed by selective etching such as RIE.
  • the doped portion 1055a is removed before patterning the conductive pattern.
  • the present disclosure is not limited thereto.
  • the doped portion 1055a may be removed after patterning the conductive pattern.
  • a barrier layer may be formed on its top surface.
  • a conductive barrier layer 1057 may be formed by deposition in a substantially conformal manner.
  • Conductive barrier layer 1057 may comprise the same or different materials as conductive barrier layer 1049 .
  • a masking layer 1059 such as an oxide, can then be formed using, for example, the methods described above in connection with FIGS. 22-24, and the conductive barrier layer 1057 can be isotropically etched using the masking layer 1059 so that it can remain in the trenches Bottom (and part left on the top surface of each device stack and will be removed in a subsequent process).
  • the conductive body layer 1051 wrapped by the conductive barrier layers 1049, 1057 may be patterned. Pattern positioning can be aided based on alignment marks of device layer L1.
  • a mask layer 1061 for patterning conductive structures may be formed within the trenches.
  • the photoresist can be thinned for exposure by spin coating and etched back, leaving the photoresist in the grooves, and then patterning the photoresist with the help of the alignment marks of the device layer L1 (eg, photolithography or electron beam exposure, etc.) to form the mask layer 1061 .
  • the minimum gap Wt of each opening in the mask layer 1061 may remain substantially uniform. This aids in the consistency of subsequent processes. To ensure this consistency, a portion of the conductive structures defined by the photoresist thus patterned may be dummy conductive structures.
  • the mask layer 1061 can be used as an etching mask, and the mask layer 1059, the conductive barrier layer 1057, the conductive body layer 1051, and the conductive barrier layer 1049 can be selectively etched, such as RIE, in sequence.
  • the RIE can proceed in a generally vertical direction and can stop at the electrical isolation layer 1047" (or can enter the electrical isolation layer 1047' slightly to ensure severing of the conductive layers).
  • a source/drain layer is formed at a height corresponding to laterally extending conductive structures, and at least a portion of these conductive structures are in contact with and thus electrically connected to the first source/drain layer of the lowermost layer in each device stack.
  • residues from previous processes at the top surface of each device stack may be removed. After that, the mask layer 1061 may be removed.
  • a conductive barrier layer may be formed on the sidewall of the conductive body layer 1051 .
  • conductive barrier layers 1063 may be sequentially formed in a substantially conformal manner by deposition, and the lateral extension thereof may be removed by anisotropic etching, such as vertical RIE, while leaving its The vertically extending portions are thus formed in the form of sidewalls and remain on the sidewalls of the conductive body layer 1051 .
  • the conductive barrier layer 1063 may comprise the same or different material as the conductive barrier layers 1049 , 1057 . To maintain consistency, conductive barrier layers 1049, 1057, and 1063 may be of the same material and substantially the same film thickness.
  • the conductive barrier layer 1063 in the form of a spacer only needs to cover the conductive body layer 1051 .
  • a dielectric layer 1065 eg, oxide
  • the dielectric layer 1065 may be formed by deposition and then etch back.
  • the thickness of the deposited dielectric layer 1065 can be greater than Wt/2 so that the gaps between the conductive structures can be completely filled.
  • the conductive structures may include some dummy patterns (ie, interconnect lines and/or vias that do not make real electrical connections) so that a minimum gap is achieved Substantially uniformity can be maintained as described above.
  • the thickness of the deposited film may be greater than half of the minimum gap.
  • atomic layer deposition ALD may be used for its deposition, and ALE may be used for its etch back.
  • the portion of conductive barrier layer 1063 exposed by dielectric layer 1065 may then be removed by selective etching such as RIE.
  • the conductive body layer 1051 is encapsulated by the conductive barrier layers 1049 , 1057 , 1063 .
  • the conductive structure thus formed has an interface or boundary between the device stack (eg, components that need to be connected, such as source/drain regions, gate electrodes, etc.) due to factors such as different materials, dislocation of upper and lower or front and rear positions, and the like.
  • the dielectric layer 1065 also forms part of the electrical isolation layer and is referred to below as the electrical isolation layer.
  • a layer of conductive structure is formed above.
  • the multilayer conductive structures may be formed one by one in the same or similar manner.
  • conductive structures may be formed, eg, for the gate conductor layer of the lowermost device in each device stack.
  • the conductive structure to be formed for the gate conductor layer should be located at a height corresponding to the gate conductor layer.
  • the top surface of the electrical isolation layer 1065 may be raised to the level with the gate conductor by depositing and then etching back a dielectric material such as an oxide, for example, as described above in connection with FIGS. 19 to 20(b). The corresponding height of the layer.
  • the raised electrical isolation layer is designated 1065' in the figure. It should be noted that although the electrical isolation layer 1065' is shown as a single body, an interface or boundary may exist between successively formed layers. Here, the residue on the top surface of each device stack can also be thickened (this thickening is not shown in the figures for convenience only).
  • the height of the top surface of the electrical isolation layer 1065' may be such that: on the one hand, the exposed sidewalls of the first source/drain layer in the trench are shielded to avoid the subsequent conductive formation on the top surface of the electrical isolation layer 1065'.
  • the structure is in contact with the first source/drain layer; on the other hand, the sidewalls of the gate conductor layer can be exposed in the trench, so that a conductive structure subsequently formed on the top surface of the electrical isolation layer 1065' can be in contact with the gate conductor layer .
  • vias 1067 may be formed by, for example, etching holes and filling the holes with a conductive barrier layer such as a conductive nitride and a conductive material such as a metal. Vias 1067 can realize electrical connection between the upper and lower layers. One or more of the vias adjacent to the sidewalls of the device stack may be in direct contact with the first source/drain layer.
  • a conductive structure may be formed on the electrical isolation layer 1065' as described above in connection with Figures 21 to 28(b). Then, the height of the electrical isolation layer 1065' is further raised.
  • the height of the top surface of the electrical isolation layer 1065' can be such that: on the one hand, the sidewalls of the gate conductor layer exposed in the trench are shielded, so as to avoid the conductive structure and the gate formed on the top surface of the electrical isolation layer 1065' later.
  • the sidewalls of the second source/drain layer may be exposed in the trench, so that a conductive structure subsequently formed on the top surface of the electrical isolation layer 1065' may be in contact with the second source/drain layer .
  • vias may be formed in the electrical isolation layer 1065'.
  • a conductive structure can be formed layer by layer, thereby forming an interconnect structure.
  • corresponding conductive structures are formed at corresponding heights to realize the required interconnection.
  • the electrical isolation layers between the conductive structures in the interconnect structure are shown as 1065". At least a portion of the aforementioned interfaces or boundaries in the various layers may be substantially coplanar, eg are substantially aligned in the vertical direction.
  • an interlayer dielectric layer (here shown integrally with the electrical isolation layer as 1065"') may be formed by, for example, depositing and planarizing a dielectric material such as an oxide, and the interlayer dielectric layer 1065 "' to form interconnect structures 1067 such as interconnect lines or vias.
  • the interconnect structure 1067 may be in contact and electrically connected to the interconnect structure previously formed in the trench.
  • isolation layers are provided between adjacent device layers.
  • the present disclosure is not limited thereto.
  • some of the device layers may be directly contiguous, especially in the case of complementary metal oxide semiconductor (CMOS) processes.
  • CMOS complementary metal oxide semiconductor
  • 34 to 36 schematically illustrate some stages in a flow of fabricating a semiconductor device, particularly an interconnect structure therein, in accordance with another embodiment of the present disclosure.
  • each source/drain layer can be doped in-situ during growth, so that there is no need to use a dopant source layer for diffusion doping.
  • the source/drain layers in device layers L1, L2 may be doped p-type, while the source/drain layers in device layer L3 may be doped n-type.
  • the sacrificial layer 1003 3 is not provided between the device layers L2 and L3 so that they are directly adjacent.
  • an isolation layer can be formed by the same process as described above, and a channel layer 1025 can be formed, as shown in FIG. 35 .
  • Fig. 36 shows the situation after the position maintaining layer 1027" is formed around the channel layer 1025.
  • the semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. Accordingly, the present disclosure also provides an electronic apparatus including the above-described semiconductor device. Electronic devices may also include components such as display screens and wireless transceivers. Such electronic devices are, for example, smartphones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, power banks, and the like.
  • a method of fabricating a system on a chip is also provided.
  • the method may include the methods described above.
  • a variety of devices can be integrated on a chip, at least some of which are fabricated according to the methods of the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Geometry (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

公开了一种带侧壁互连结构的半导体装置及其制造方法及包括这种半导体装置的电子设备。根据实施例，半导体装置可以包括：多个器件叠层，每一器件叠层包括堆叠的多层半导体器件，每个半导体器件包括在竖直方向上叠置的第一源/漏层、沟道层和第二源/漏层以及围绕沟道层的栅电极；设置在所述多个器件叠层之间的互连结构。互连结构可以包括电隔离层以及电隔离层中的导电结构。至少一部分半导体器件各自的第一源/漏层、第二源/漏层和栅电极中至少之一与互连结构中相应高度处的导电结构在横向上相接触并因此电连接。

Description

带侧壁互连结构的半导体装置及其制造方法及电子设备
相关申请的引用
本申请要求于2020年12月11日递交的题为“带侧壁互连结构的半导体装置及其制造方法及电子设备”的中国专利申请202011463249.8的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及具有侧壁互连结构的半导体装置及其制造方法及包括这种半导体装置的电子设备。
背景技术
随着半导体器件的不断小型化，越来越难以制造高密度的互连结构，因为在横向上难以缩减尺寸。另外，为增加集成度，可以堆叠多层器件。期望能够以灵活的方式为这种堆叠器件设置互连。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种带侧壁互连结构的半导体装置及其制造方法及包括这种半导体装置的电子设备。
根据本公开的一个方面，提供了一种半导体装置，包括多个器件叠层，每一器件叠层包括堆叠的多层半导体器件，每个半导体器件包括在竖直方向上叠置的第一源/漏层、沟道层和第二源/漏层以及围绕沟道层的栅电极；设置在所述多个器件叠层之间的互连结构。互连结构可以包括电隔离层以及电隔离层中的导电结构。至少一部分半导体器件各自的第一源/漏层、第二源/漏层和栅电极中至少之一与互连结构中相应高度处的导电结构在横向上相接触并因此电连接。
根据本公开的另一方面，提供了一种制造半导体装置的方法，包括：在衬底上设置叠层，所述叠层包括一个或多个器件层，每一器件层包括依次叠置的第一源/漏层、沟道限定层和第二源/漏层；将所述叠层构图为用于限定有源区 的柱体；基于沟道限定层形成沟道层，沟道层相对于第一源/漏层和第二源/漏层在横向上相对凹入；在沟道层相对于第一源/漏层和第二源/漏层的凹入中形成栅电极；在柱体周围形成互连结构，互连结构包括电隔离层以及电隔离层中的导电结构。该方法还包括控制互连结构中的导电结构的高度，使得至少一部分半导体器件各自的第一源/漏层、第二源/漏层和栅电极中至少之一与相应高度处的导电结构在横向上相接触并因此电连接。
根据本公开的另一方面，提供了一种电子设备，包括上述半导体装置。
根据本公开的实施例，对于竖直型半导体器件的阵列，可以设置与之横向上邻接的侧壁互连结构。这可以减少制造工艺中的光刻步骤并降低制造成本。制造工艺步骤在叠置的竖直型半导体器件之间可以共享，从而可以降低制造成本。另外，三维构造使得器件之间的互连可以由更多空间，并因此可以具有低电阻和高带宽。由于侧壁互连结构的存在，半导体装置可以具有引出端子，因此可以将半导体装置的制造与金属化叠层的制造相分离，从而可以得到类似现场可编程门阵列(FPGA)的芯片。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至33示意性示出了根据本公开实施例的制造半导体装置特别是其中的互连结构的流程中的一些阶段；
图34至36示意性示出了根据本公开另一实施例的制造半导体装置特别是其中的互连结构的流程中的一些阶段，其中，
图2(a)(其中示出了AA′线、BB′线的位置)、2(b)、3(a)、4(a)、5(a)、12、16(a)(其中示出了CC′线、DD′线的位置)、17(a)是俯视图，
图1、2(c)、5(b)、6至11、13至15、34至36是沿AA′线的截面图，
图3(b)、4(b)、5(c)是沿BB′线的截面图，
图16(b)、17(b)、18(a)、19、20(a)、21至27、28(a)、31(b)、32(a)、33是沿CC′线的截面图，
图16(c)、17(c)、18(b)、20(b)、28(b)、29、30、31(a)、32(b)是沿DD′线 的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种带有侧壁互连结构的半导体装置。在此，所谓“侧壁”互连结构，是指这种互连结构形成在需要互连的器件的侧向(例如，大致平行于衬底表面的方向)，并因此可以通过器件的侧壁与器件(中需要互连的部件，如源/漏层或其中形成的源/漏区、栅电极等)相互连接。器件可以是竖直型器件，因此其源/漏层和栅电极可以处于(相对于衬底)不同高度。由于需要互连的部件在高度上的差异，可以在这些部件的侧壁上分别形成与之互连的导电结构。
例如，竖直型器件可以具有在衬底上竖直(例如，沿大致垂直于衬底表面的方向)设置的有源区，例如包括在竖直方向上叠置的第一源/漏层、沟道层和第二源/漏层。沟道层可以是竖直纳米片或纳米线。在第一源/漏层和第二源/漏层中可以形成源/漏区，且沟道区可以形成在沟道层中。沟道层可以包括单晶半导体材料。当然，源/漏层也可以包括单晶半导体材料。例如，它们都可 以通过外延生长来形成。
器件还可以包括设置在沟道层外周的栅电极，栅电极可以围绕沟道层的外周。因此，根据本公开实施例的器件可以是围栅器件。根据本公开的实施例，栅电极可以自对准于沟道层。例如，栅电极的至少靠近沟道层一侧的部分可以与沟道层实质上共面，例如栅电极的所述部分与沟道层的上表面和/或下表面彼此实质上共面。
于是，第一源/漏层、第二源/漏层以及栅电极可以处于不同的高度。因此，可以通过互连结构中不同高度处的导电结构，实现与竖直型器件的互连。
器件可以彼此叠置从而形成器件叠层，以增加集成密度。可以在衬底上设置多个器件叠层。互连结构可以在这些器件叠层之间形成，从而将这些器件叠层内或之间需要互连的器件彼此电连接。更具体地，在互连结构与需要电连接的部件相邻接之处，互连结构中的导电结构(的侧壁)露出，且所述部件(的侧壁)也露出，从而两者可以彼此接触并因此电连接。互连结构与器件之间可以存在可观察的界面。为实现各个方向上的互连，互连结构可以环绕各器件叠层。当然，部分器件叠层可以仅在需要电连接的侧壁处存在互连结构即可。为方便布局，器件叠层可以排列成阵列。
互连结构可以包括设置在电隔离层(例如，电介质层)中的导电结构如互连线和过孔。例如，互连结构可以包括交替设置的互连线层与过孔层。互连线层中设置有互连线以实现同一层内的互连，过孔层中设置有过孔以实现不同层之间的互连。互连线可以包括在相应互连线层内延伸的主体部分以及包围主体部分的阻挡层。
这种半导体装置可以如下制作。例如，可以在衬底上设置一个或多个器件层的叠层，每一器件层可以包括依次叠置的第一源/漏层、沟道限定层和第二源/漏层。在相邻的器件层之间和/或器件层与衬底之间，可以根据需要设置牺牲层。该叠层可以通过外延生长来形成，因此各层可以是单晶半导体材料。
可以将该叠层构图为用于限定有源区的柱体。例如，柱体可以排列成阵列。可以基于沟道限定层来形成沟道层。例如，可以通过选择性刻蚀使沟道限定层在横向上相对凹入，并在沟道限定层的侧壁上另外生长沟道层(由于外延生长，可以是单晶半导体材料)。或者，也可以通过(相对凹入的)沟道限定层本身 来形成沟道层。
可以围绕沟道层形成栅电极。由于沟道层在横向上相对凹入，因此栅电极可以自对准于沟道层。
在设置了牺牲层的情况下，可以将牺牲层替换为器件隔离层。在牺牲层相对于叠层中的其他层具有刻蚀选择性的情况下，可以通过选择性刻蚀，去除牺牲层，并在由于牺牲层的去除而留下的空隙中通过填充例如电介质材料而形成器件隔离层。在替换时，可以通过支撑材料来至少在一侧保持柱体。
如果牺牲层相对于叠层中的其他层(例如，沟道限定层)不具有刻蚀选择性或者刻蚀选择性不大，则在替换牺牲层之前需要针对其他层如沟道限定层形成保护层。例如，可以通过选择性刻蚀，使沟道限定层在横向上相对凹入。由于刻蚀选择性较小或甚至没有，牺牲层也会在横向上相对凹入。可以形成填充层来消除牺牲层的这种凹入，并在沟道限定层的凹入中形成保护层(下面也称作位置保持层)。可以通过设计各层的厚度，来形成仅填充牺牲层的凹入而不填充沟道限定层的凹入的填充层。这将在以下进一步详细描述。
源/漏层和栅电极可以在柱体的侧壁处露出。在柱体周围，可以形成互连结构，从而与在柱体的侧壁处露出的源/漏层和栅电极互连。
互连结构中的导电结构可以分层形成，以便与不同高度处的器件相连。例如，可以在柱体周围(例如，衬底或者已经形成的部分互连结构上)形成互连线。可以填充电介质材料以掩埋互连线，并在填充的电介质材料中形成过孔。通过多次重复这样的操作，形成包括多层互连线和多层过孔的互连结构。可以通过电介质材料的形成高度，来控制互连线和过孔所在的高度。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离，导电材料用于形成互连线和过孔)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至33示意性示出了根据本公开实施例的制造半导体装置特别是其中的互连结构的流程中的一些阶段。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。以下以体Si衬底如硅晶片为例进行描述。
在衬底1001上，可以通过例如外延生长，形成用于限定隔离层的牺牲层1003 1、用于限定下源/漏区的第一源/漏层1005 1、用于限定沟道部的沟道限定层1007 1、用于限定上源/漏区的第二源/漏层1009 1。第一源/漏层1005 1、沟道限定层1007 1和第二源/漏层1009 1随后将限定器件的有源区，可以将它们称作“器件层”，图中标示为L1。
牺牲层1003 1随后可以被替换为用于将器件与衬底隔离的隔离层，其厚度可以对应于希望形成的隔离层的厚度，例如为约10nm-20nm。根据电路设计，也可以不设置牺牲层1003 1。第一源/漏层1005 1和第二源/漏层1009 1随后可以通过掺杂(或者在生长时原位掺杂)而形成源/漏区，其厚度例如可以为约20nm-50nm。沟道限定层1007 1可以限定栅长，其厚度可以对应于希望形成的栅长，例如为约15nm-100nm。考虑以下将牺牲层1003 1替换为隔离层的工艺，在此沟道限定层1007 1的厚度应大于牺牲层1003 1的厚度，这将在以下进一步详细说明。
衬底1001上所生长的各层可以是单晶的半导体层，且相邻的层之间可以具有刻蚀选择性。例如，牺牲层1003 1可以包括SiGe(Ge的原子百分比例如为约10％-30％，优选为15％)，第一源/漏层1005 1可以包括Si，沟道限定层1007 1可以包括SiGe(Ge的原子百分比例如为约10％-30％，优选为15％)，第二源/漏层1009 1可以包括Si。
为增加集成密度，可以设置多个器件层。例如，可以通过外延生长，在器件层L1上依次设置器件层L2和L3，各器件层之间分别通过用于限定隔离层的牺牲层1003 2、1003 3间隔开。根据电路设计，某些器件层之间也可以不设置隔离层。类似地，器件层L2可以具有第一源/漏层1005 2、沟道限定层1007 2和第二源/漏层1009 2，器件层L3可以具有第一源/漏层1005 3、沟道限定层1007 3和第二源/漏层1009 3。各器件层中相应的层可以具有相同或相似的厚度和/或 材料，也可以具有不同的厚度和/或材料。特别是，不同器件层中沟道限定层的厚度可以不同，从而可以调节所得到的器件的电气特性。在此，仅为方便描述起见，假设各器件层L1、L2和L3具有相同的配置。
在衬底1001上形成的这些层上，可以设置硬掩模层1011，以方便构图。例如，硬掩模层1011可以包括氮化物(例如，氮化硅)，厚度为约50nm-200nm。
接下来，可以在这些器件层中限定有源区。
例如，如图2(a)所示，可以在硬掩模层1011上形成光刻胶1013，并通过光刻将其构图为有源区的形状。在图2(a)的示例中，光刻胶1013被构图为沿x方向和y方向布置的阵列形式，阵列中每一元素呈大致矩形(用以限定单独器件的有源区，将呈柱状)，例如短边沿x方向、长边沿y方向的矩形。当然，本公开不限于此。光刻胶1013可以构图为各种合适的形状。例如，如图2(b)所示，为避免柱状有源区在制造中坍塌，阵列中的元素可以呈曲折形或之字形。以下，为方便起见，参照图2(a)所示的情形为例描述。
可以如此构图的光刻胶1013作为刻蚀掩模，通过选择性刻蚀如反应离子刻蚀(RIE)，来依次刻蚀衬底1001上的各层。RIE可以沿大致竖直的方向(例如，垂直于衬底表面的方向)进行，并可以停止于衬底1001的表面。于是，在衬底1001上留下了一系列柱体的阵列，如图2(c)所示。每一柱体分别限定了彼此叠置的多个(在该示例中，三个)竖直器件的有源区。各柱体在顶视图中可以呈如图2(a)所示的矩形，或者如图2(b)所示的曲折形或之字形。之后，可以去除光刻胶1013。
可以这些有源区为基础，进行下述的器件制作。考虑到以下工艺的需要，例如对沟道层形貌的控制等，可以在柱体周围形成遮蔽材料。在制作过程中可以暴露有源区的一侧或多侧以对有源区进行处理，同时有源区的另外一侧或多侧被遮蔽材料所遮蔽。遮蔽材料也可以在制作过程中支撑细长柱体，特别是在将牺牲层替换为隔离层的处理中，以防止其坍塌。
例如，如图3(a)和3(b)所示，可以通过例如淀积在衬底1001上形成遮蔽材料(参见图4(a)中的1017)。考虑到刻蚀选择性(例如，相对于例如氮化物的硬掩模层1011以及随后形成的例如氧化物(例如，氧化硅)的位置保持层)，遮蔽材料1017可以包括SiC。可以对淀积的遮蔽材料1017进行平坦化如化学 机械抛光(CMP)，CMP可以停止于硬掩模层1011。于是，各柱体被遮蔽材料1017所围绕。
在此，为控制随后形成的沟道层在y方向上的长度以及y方向上端部的形貌，可以先对有源区在y方向上的相对两侧进行处理。于是，需要露出这两侧。为此，可以在硬掩模层1011以及遮蔽材料1017上形成光刻胶1015，并将其构图为至少能够露出各柱体在y方向上的相对两侧。例如，光刻胶1015中可以包括在各柱体之间沿着x方向延伸的开口。可以如此构图的光刻胶1015作为刻蚀掩模，通过选择性刻蚀如RIE对遮蔽材料1017进行刻蚀。RIE可以沿大致竖直的方向进行，并可以停止于衬底1001的表面。于是，各柱体在y方向上的侧壁被露出(参见图3(b))，同时在x方向上的侧壁至少部分地(取决于光刻胶1015中的开口在y方向上的尺寸)由遮蔽材料1017遮蔽(参见图4(a))。之后，可以去除光刻胶1015。
为形成自对准的栅堆叠，可以基于沟道限定层来限定用于形成栅堆叠的间隙(可以称为“栅间隙”)。例如，如图4(a)和4(b)所示，可以对沟道限定层1007 1、1007 2、1007 3露出的侧壁进行选择性刻蚀，使其(相对于上下的源/漏层)相对凹入。为实现良好的刻蚀控制，在此可以采用原子层刻蚀(ALE)。于是，对于每一器件层L1、L2、L3，在上、下源/漏层之间限定了一个间隙(即，栅间隙)，该间隙原本被沟道限定层所占据，从而自对准于沟道限定层。沟道限定层在y方向上相对两侧的栅间隙可以具有大致相同的维度(在竖直方向上的高度对应于沟道限定层的厚度，在y方向上的宽度可以彼此大致相等)。
刻蚀配方对于各沟道限定层1007 1、1007 2、1007 3的刻蚀程度可以实质上相同，从而刻蚀之后各沟道限定层1007 1、1007 2、1007 3的侧壁可以在竖直方向上仍然基本对准或者基本共面。另外，与沟道限定层同为SiGe的牺牲层1003 1、1003 2、1003 3也可以被刻蚀从而相对凹入，并因此形成相应的间隙(可以称为“隔离间隙”)。
在所形成的栅间隙中，为避免后继处理在其中残留材料而影响栅堆叠的形成，可以在其中填充第一位置保持层1019(也可以称为“牺牲栅”)。例如，可以通过淀积然后回蚀(例如，RIE)的方式，在这些栅间隙中填充例如氧化物的第一位置保持层1019。类似地，隔离间隙也会被第一位置保持层1019填 充。
然后，可以对有源区在x方向上的相对两侧进行处理。同样地，首先可以形成遮蔽材料，并将遮蔽材料构图为露出要处理的这两侧。例如，如图5(a)、5(b)和5(c)所示，可以通过例如淀积然后平坦化的工艺在衬底1001上形成遮蔽材料。考虑到后继刻蚀工艺的方便，在此形成的遮蔽材料可以与之前的遮蔽材料1017包括相同的材料如SiC，并因此可以与之前的遮蔽材料1017被一体示出为1017′。这样，遮蔽材料1017′围绕各柱体。
在露出x方向上的相对两侧时，考虑到替换隔离层时所需的支撑功能，可以对这两侧分别进行处理。
例如，可以形成光刻胶1021，并将其构图为能够露出各柱体在x方向上的一侧。例如，光刻胶1021可以包括在各对相邻柱体之间沿着y方向延伸的开口。可以如此构图的光刻胶1021作为刻蚀掩模，通过选择性刻蚀如RIE对遮蔽材料1017′进行刻蚀。RIE可以沿大致竖直的方向进行，并可以停止于衬底1001的表面。于是，各柱体在x方向上的一个侧壁被露出，同时在y方向上的侧壁至少部分地(取决于光刻胶1021中的开口在x方向上的尺寸)以及在x方向上的另一侧壁由遮蔽材料1017′遮蔽。之后，可以去除光刻胶1021。
对于各柱体当前露出的侧壁，可以进行与图4(a)和4(b)类似的处理，以限定栅间隙。例如，如图6所示，可以对沟道限定层1007 1、1007 2、1007 3露出的侧壁进行选择性刻蚀，使其(相对于上下的源/漏层)相对凹入。同样，可以采用ALE。于是，形成了自对准于沟道限定层的栅间隙。之后，可以形成位置保持层来填充这些栅间隙。
在此，同样地牺牲层1003 1、1003 2、1003 3也会相对凹入，从而形成隔离间隙。在以上结合图4(a)和4(b)描述的处理中，位置保持层也会填充在隔离间隙中，这将影响后继对牺牲层的替换。为避免位置保持层填充到隔离间隙中，可以先将隔离间隙填满。
例如，可以通过外延生长，形成填充层1023。填充层1023的生长厚度可以大于各牺牲层1003 1、1003 2、1003 3的厚度的一半，从而可以完全填满各隔离间隙。另外，填充层1023不应填满栅间隙(其中应当形成位置保持层或者说牺牲栅)。为此，一方面如上所述沟道限定层的厚度应大于牺牲层的厚度(填 充层1023的生长厚度可以小于沟道限定层的厚度的一半)。另一方面，形成栅间隙时沟道限定层的刻蚀深度优选大于牺牲层的厚度的一半(填充层1023的生长厚度可以小于沟道限定层的刻蚀深度)。于是，可以使得填充层1023可以填满各隔离间隙，而不会填满各栅间隙，如图6所示。
填充层1023的材料可以与牺牲层的材料具有相似或基本相同的刻蚀选择性，以便随后可以被相同的刻蚀配方一起去除。例如，填充层1023可以包括SiGe，Ge的原子百分比例如为约10％-40％。
之后，如图7所示，可以通过选择性刻蚀，去除一定厚度的填充层1023。例如，去除厚度可以基本上等于或略大于填充层1023的生长厚度。于是，填充层1023可以从栅间隙中去除，而留于隔离间隙中。为良好地控制去除厚度，可以采用ALE。
然后，如图8所示，可以如上所述形成第二位置保持层1019′。第二位置保持层1019′的材料可以与第一位置保持层1019的材料具有相似或基本相同的刻蚀选择性，以便随后可以被相同的刻蚀配方一起去除。例如，第二位置保持层1019′可以包括氧化物。
在上述实施例中，第一位置保持层1019与第二位置保持层1019′在不同的步骤中形成。这有助于控制随后生长的沟道层在y方向上的长度以及y方向上端部的形貌。但是，本公开不限于此。第一位置保持层1019与第二位置保持层1019′也可以在相同的步骤中形成，特别是在利用沟道限定层自身来形成沟道层的情况下。例如，可以对各沟道限定层在y方向上的相对两侧以及x方向上的一侧(x方向上的另一侧可以被遮蔽材料遮蔽)进行选择性刻蚀以使其相对凹入，并在由此得到的间隙中形成位置保持层。
当前，各沟道限定层被遮蔽材料、位置保持层、源/漏层围绕，而填充层1023的侧壁外露。可以通过选择性刻蚀，去除填充层1023以及由于其去除而露出的牺牲层。刻蚀可以停止于遮蔽材料1017′。这样，在各器件层之间去除了牺牲层(同时各器件层仍然被遮蔽材料1017′所保持)。在由于牺牲层的去除而留下的空隙中，可以通过例如淀积(例如，化学气相淀积(CVD)、原子层淀积(ALD)等)然后回蚀(例如，RIE)的工艺，填充电介质材料以形成隔离层。可以出于各种目的例如优化隔离的可靠性、漏电流或电容等，选择合适 的电介质材料，例如氧化物、氮化物、SiC或其组合。于是，各器件层之间可以彼此隔离。在此，仅为方便描述起见，填充的电介质材料可以包括SiC，并因此与遮蔽材料1017′被一体示出为1017″。
接下来，可以形成沟道层。
例如，如图9所示，可以通过选择性刻蚀，去除位置保持层1019′。在此，位置保持层1019由于被遮蔽材料1017″覆盖，可以保留。于是，位置保持层1019′所占据的栅间隙被释放。在释放的栅间隙中，可以通过选择性外延生长，形成半导体层。该半导体层可以沿着沟道限定层和源/漏层的表面生长。在以下，仅为图示和描述方便起见，单独示出该半导体层位于沟道限定层的侧壁上的部分并将之称作沟道层1025(沟道部将主要形成在这一部分中)，而该半导体层位于源/漏层表面上的部分可以与源/漏层一体示出并将之称作源/漏层(其中将形成源/漏区)(参见图10中的虚线)。沟道层1025可以形成在沟道限定层在x方向上的一个侧壁(原本被位置保持层1019′覆盖的侧壁)上。各器件层中的沟道层1025可以在竖直方向上实质上对准或者实质上共面。
在实施例中，为使沟道层1025两侧具有实质上相同的栅长，在生长半导体层之前，可以将沟道限定层和源/漏层回蚀一定的厚度。半导体层的生长厚度可以选择为与源/漏层被回蚀的厚度大致相等，于是在生长半导体层之后栅间隙的高度可以与沟道限定层的厚度实质上相同。可以选择沟道层1025的材料，以实现期望的器件性能。例如，沟道层1025可以包括与源/漏层相同的材料如Si，或者可以包括与源/漏层不同的材料如SiGe。
在该实施例中，另外生长沟道层1025。这有助于控制沟道层1025的厚度，且后继的选择性刻蚀也比较容易控制。于是，可以获得沟道层厚度和栅长的双重精确控制，而不需要借助光刻和选择性ALE。但是，本公开不限于此。例如，可以直接利用沟道限定层来形成沟道部。
接下来，可以对各柱体在x方向上的另一侧进行处理。
例如，如图10所示，可以通过例如淀积然后平坦化的处理，在衬底1001上形成另一遮蔽材料1027。另一遮蔽材料1027可以填充衬底1001上遮蔽材料1017″之间的间隙。为了去除遮蔽材料1017″而露出需要处理的一侧，另一遮蔽材料1027可以包括相对于遮蔽材料1017″具有刻蚀选择性的材料，例如 氧化物。之后，可以对遮蔽材料1017″进行选择性刻蚀如RIE。RIE可以沿大致竖直的方向进行，并可以停止于衬底1001。于是，除了遮蔽材料1017″处于硬掩模层之下的部分可以留下(形成隔离层，并示出为1017″′)，遮蔽材料1017″的其余部分可以被去除。这样，沟道限定层在x方向上的另一侧露出(尽管在y方向上的另外两侧上遮蔽材料1017″也被去除，但是由于位置保持层1019的存在，沟道层1025在y方向上的相对两侧可以被遮蔽)。
在x方向上当前露出的这一侧，也可以限定栅间隙。例如，如图11所示，可以对沟道限定层1007 1、1007 2、1007 3进行选择性刻蚀。同样地，可以采用ALE。在此，对沟道限定层的刻蚀可以停止于沟道层1025，从而留下沟道层1025在上、下源/漏层之间。于是，形成了栅间隙。沟道层1025在x方向上相对两侧的栅间隙可以具有大致相同的维度(在竖直方向上的高度对应于沟道限定层的厚度，在x方向上的宽度可以彼此大致相等)。
在不另外生长沟道层1025，而是利用沟道限定层1007 1、1007 2、1007 3本身形成沟道部的情况下，可以在沟道限定层1007 1、1007 2、1007 3周围类似地形成栅间隙。例如，沟道限定层1007 1、1007 2、1007 3可以通过选择性刻蚀如ALE而留下如同沟道层1025一样的残留部分。
同样，在如此形成的栅间隙中，可以类似地形成第三位置保持层1027″。例如，可以通过淀积然后回蚀(例如，RIE)氧化物的方式，来形成第三位置保持层1027″。RIE可以沿大致竖直的方向进行，并可以停止于衬底1001的表面。
如图11所示，在衬底1001上形成有排列为阵列的多个柱体(例如，如图2(a)或2(b)所示的形式)。每个柱体中叠置了多个器件层，每一器件层可以包括第一源/漏层和第二源/漏层以及它们之间的沟道层。沟道层四周形成有栅间隙，栅间隙被位置保持层所占据。栅间隙自对准于沟道层。各器件层之间通过隔离层彼此隔离。
当前，各源/漏层的侧壁暴露于外。可以通过这些露出的侧壁对源/漏层进行掺杂，以形成源/漏区。
在图11所示的实施例中，在形成第三位置保持层1027″时的回蚀过程中，硬掩模层1011作为掩模。于是，各源/漏层在x方向和y方向中每一个方向上 的相对侧壁均暴露于外，从而掺杂可以通过这些侧壁中的每一个进行。根据本公开的另一实施例，如图12所示，在形成第三位置保持层1027″时的回蚀过程中，还可以另外形成光刻胶1029，光刻胶1029可以被沟通为遮挡各柱体在y方向上的相对侧壁。于是，所形成的第三位置保持层1027″除了占据栅间隙之外，还遮挡各柱体在y方向上的相对侧壁。这样，掺杂可以通过各源/漏层在x方向上的侧壁进行，从而可以抑制由于x方向上相对两侧的栅间隙与y方向上相对两侧的栅间隙各自的宽度不同而造成的掺杂特性变化。
为进行掺杂，如图13所示，可以通过例如淀积，在各柱体的表面上形成掺杂剂源层。掺杂剂源层可以大致共形的方式形成。在此，以形成两种类型(n型和p型)的器件为例进行描述，因此需要进行n型掺杂和p型掺杂。例如，可以先形成n型掺杂剂源层1031，并将其构图为覆盖要在其中形成n型器件的柱体。然后，可以形成p型掺杂剂源层1035。为避免n型掺杂剂源层1031与p型掺杂剂源层1035之间的相互扩散，可以在它们之间形成扩散阻挡层1033。例如，扩散阻挡层1033可以形成在n型掺杂剂源层1031上，并可以与n型掺杂剂源层1031一起构图。n型掺杂剂源层1031可以包括n型掺杂剂，例如P或As掺杂的氧化物，掺杂剂的浓度可以为约0.1％-10％，厚度可以为约1nm-10nm。类似地，p型掺杂剂源层1035可以包括p型掺杂剂，例如B掺杂的氧化物，掺杂剂的浓度可以为约0.1％-10％，厚度可以为约1nm-10nm。扩散阻挡层1033可以包括氮化物，厚度为约2nm-10nm。
然后，如图14所示，可以通过例如退火处理将掺杂剂从掺杂剂源层驱入到源/漏层中，从而在源/漏层中形成源/漏区。在此，示出了n型源/漏区S/D 1以及p型源/漏区S/D 2。衬底1001也可能被掺杂。位置保持层可以防止掺杂剂直接进入沟道层1025中。当然，沟道层1025靠近源/漏层的端部可能存在经由源/漏层而进入的少量掺杂剂。之后，可以去除n型掺杂剂源层1031、p型掺杂剂源层1035以及扩散阻挡层1033。
在该示例中，每一柱体中的源/漏层均被掺杂为相同导电类型。但是，本公开不限于此。例如，通过掺杂剂源层的适当设计，每一柱体中不同器件层中的源/漏层可以被掺杂为不同导电类型。
在实施例中，可以对源/漏层的表面进行硅化处理，以降低接触电阻。例 如，可以在各柱体的表面形成金属如NiPt，并进行退火，使其与源/漏层中的Si发生反应，从而生成金属硅化物如NiPtSi。之后，可以去除未反应的金属。
之后，可以进行替代栅工艺，以将位置保持层替换为栅堆叠。例如，如图15所示，可以通过选择性刻蚀，去除位置保持层1019、1027″，从而释放栅间隙。可以通过例如淀积、ALD，以大致共形的方式，形成栅介质层1037。在栅介质层1037上，可以通过例如淀积、ALD，形成栅导体层。在此，以先形成n型器件的栅导体层1039 1为例进行描述。淀积的栅导体层1039 1可以填满栅间隙。可以通过回蚀如RIE，去除栅导体层1039 1在栅间隙之外的部分，从而栅导体层1039 1可以留于栅间隙中。然后，可以利用例如光刻胶，覆盖n型器件，而露出p型器件。可以通过选择性刻蚀，去除p型器件的栅间隙中形成的栅导体层1039 1，以释放其栅间隙。可以类似的方式在p型器件的栅间隙中形成p型器件的栅导体层1039 2。栅介质层1037可以包括高k栅介质如HfO 2，栅导体层1039 1、1039 2可以包括具有相应功函数的金属栅导体。在此，n型器件和p型器件具有相同的栅介质层1037，但是本公开不限于此。例如，它们可以具有不同的栅介质层。另外，形成栅导体层的顺序可以交换。
这样，在各柱体的每一器件层中，形成了竖直型器件。各竖直型器件可以包括沟道层1025以及位于沟道层1025上下侧的第一源/漏层和第二源/漏层。栅堆叠(栅介质层与栅导体层的叠层)可以围绕并自对准于沟道层1025。每一柱体可以称作器件叠层。在器件叠层之间，衬底1001相对凹入，成为槽。
当前，各器件需要电连接的部件如栅导体层(也可称为栅电极)、源/漏区(或其表面上形成的硅化物)的侧壁暴露于外。于是，可以形成与各器件横向邻接的互连结构，用以将各器件叠层中的器件彼此互连。在此，由于互连结构与器件在横向上邻接，并与器件中需要电连接的部件的侧壁相接触，因此可以称作侧壁互连结构。
另外，在形成互连结构时，为了避免不期望的电短路，不同高度处的导电结构可以在不同侧与器件相接。例如，器件在某一高度处需要电连接的第一部件可以在第一侧与互连结构中的导电结构相接，而在竖直方向上与该第一部件相邻的需要电连接的第二部件可以在不同于第一侧(例如，与第一侧相对)的第二侧与互连结构中的导电结构相接。另外，第一部件在第二侧的侧壁可以被 隔离层覆盖，第二部件在第一侧的侧壁可以被隔离层覆盖，以避免短路。
下面将描述形成这种隔离层的实施例。
例如，如图16(a)、16(b)和16(c)所示，可以在衬底1001上形成光刻胶1041，并将其构图为遮蔽每个器件叠层的一侧(图16(a)中y方向上的上侧)，而露出每个器件叠层的另一侧(图16(a)中y方向上的下侧)。在每个器件叠层露出的这一侧，可以通过选择性刻蚀，使栅导体层相对凹入一定深度，例如约5nm-20nm，以释放一些栅间隙。在这些栅间隙中，随后可以形成自对准的隔离层。之后，可以去除光刻胶1041。
然后，如图17(a)、17(b)和17(c)所示，可以在衬底1001上形成光刻胶1043，并将其构图为遮蔽每个器件叠层的一侧(图17(a)中y方向上的下侧)，而露出每个器件叠层的另一侧(图17(a)中y方向上的上侧)。在每个器件叠层露出的这一侧，可以通过选择性刻蚀，使源/漏层相对凹入一定深度，例如约5nm-20nm(可以与之前释放的栅间隙的深度相同，以便随后填充的隔离层可以具有大致相同的厚度)，以释放一些空间。在这些空间中，随后可以形成自对准的隔离层。之后，可以去除光刻胶1043。
于是，在各器件叠层中，源/漏层在一侧相对突出，而栅导体层在另一侧相对突出。在各自的相对凹入中，可以形成隔离层。例如，如图18(a)和18(b)所示，可以通过淀积然后回蚀的处理，在这些凹入中填充隔离层1045。考虑到与随后形成的层间电介质层的刻蚀选择性，隔离层1045可以包括介质材料如SiC。不同器件层中的隔离层1045可以在竖直方向上实质上对准或者说实质上共面。
接下来，可以进行互连结构的制作。在制作互连结构中的互连线时，为避免常规工艺中刻蚀槽，然后在槽中填充导电材料如金属的困难，根据本公开的实施例，可以先形成导电结构，然后再填充电介质材料。
对于当前的器件叠层，最下方是器件层L1的第一源/漏层或者说源/漏区。可以首先形成针对该第一源/漏层的导电结构。
考虑到与衬底1001之间的电隔离以及与第一源/漏层之间高度上的匹配，可以先在各器件叠层之间的槽中形成一定厚度的电隔离层，这样随后在该电隔离层上形成的导电结构能够处于与第一源/漏层相对应的高度，以便与之横向 邻接。另外，希望这样形成的电隔离层应该露出各器件叠层的侧壁，避免影响与侧壁互连结构之间的电接触。
例如，可以下述方式形成这样的电隔离层。如图19所示，可以通过淀积电介质材料如氧化物，形成预备隔离层1047。为形成如上所述的电隔离层，预备隔离层1047可以形成为其横向延伸部分较厚，而竖直延伸部分较薄。例如，这可以通过高密度等离子体(HDP)淀积来实现。在此，预备隔离层1047较厚部分的厚度可以为约20nm-150nm。
然后，如图20(a)和20(b)所示，可以对预备隔离层1047进行各向同性刻蚀，刻蚀的厚度可以去除预备隔离层1047的竖直延伸部分，但留下其横向延伸部分。例如，留下部分的厚度可以为约15nm-100nm。于是，预备隔离层1047可以留于各隔离器件之间的槽中(也有一部分留于各器件叠层的顶部，这不会影响后继工艺的进行)，形成电隔离层1047′。
接下来，可以在电隔离层1047′上制作导电结构。
例如，如图21所示，可以通过淀积，以大致共形的方式，依次形成导电阻挡层1049和导电主体层1051。导电阻挡层1049可以防止导电主体层1051向周围的扩散，例如可以包括导电氮化物如TiN、TaN等。导电主体层1051可以用于实现器件间的电连接，例如可以包括金属如钨(W)、钴(Co)、铷(Ru)、铜(Cu)、铝(Al)、镍(Ni)等。所形成的导电阻挡层1049和导电主体层1051可以与各器件叠层中最下层器件的第一源/漏层相接触并连接。
然后，可以将导电阻挡层1049和导电主体层1051构图为针对各器件叠层中最下层器件的第一源/漏层的导电结构。在该示例中，要留下导电阻挡层1049和导电主体层1051位于槽底部的部分，因此可以形成覆盖该部分的掩模。
这种形式的掩模例如可以通过以上结合图19至20(b)描述的方法进行。
或者，如图22所示，可以通过淀积，以大致共形的方式，依次形成掩模层1053和构图辅助层1055。例如，考虑到刻蚀选择性，掩模层1053可以包括氧化物，厚度可以为约1nm-5nm；考虑到局部改性(改变刻蚀选择性)的方便，构图辅助层1055可以包括多晶硅或非晶硅，厚度可以为约5nm-20nm。可以通过沿竖直方向的离子注入，在构图辅助层1055的水平延伸部分1055a中注入杂质如B并在例如约550℃-约900℃下退火，以改变其(相对于竖 直延伸部分的)刻蚀选择性。然后，如图23所示，可以通过选择性刻蚀如利用TMAH的湿法腐蚀，去除构图辅助层1055的未掺杂部分，从而留下其掺杂部分1055a。可以掺杂部分1055a为刻蚀掩模，对掩模层1053进行选择性刻蚀，得到所需形式的掩模。为良好地控制刻蚀量，可以采用ALE。之后，可以通过选择性刻蚀如RIE，去除掺杂部分1055a。
如图24所示，可以掩模层1053作为刻蚀掩模，对导电阻挡层1049和导电主体层1051进行各向同性刻蚀，从而它们可以留于槽的底部(还有部分留于各器件叠层的顶面，在随后的工艺中将会被去除)。在此，可以采用ALE，以实现良好的刻蚀控制。之后，可以通过选择性刻蚀如RIE，去除掩模层1053。
在该示例中，在构图导电图案之前，去除了掺杂部分1055a。但是，本公开不限于此。例如，可以在构图导电图案之后，再去除掺杂部分1055a。
导电主体层1051的顶表面目前暴露于外。为防止其扩散，可以在其顶表面上形成阻挡层。例如，如图25所示，可以通过淀积，以大致共形的方式，形成导电阻挡层1057。导电阻挡层1057可以与导电阻挡层1049包括相同或不同的材料。然后，可以利用例如以上结合图22至24描述的方法，形成例如氧化物的掩模层1059，并利用掩模层1059对导电阻挡层1057进行各向同性刻蚀，使其可以留于槽的底部(还有部分留于各器件叠层的顶面，在随后的工艺中将会被去除)。
接下来，可以对被导电阻挡层1049、1057包裹的导电主体层1051进行构图。可以基于器件层L1的对准标记来帮助图案定位。例如，如图26所示，可以在槽内形成用于构图导电结构的掩模层1061。例如，可以通过旋涂并回蚀光刻胶，以减薄光刻胶以便于曝光，并使光刻胶留于槽中，然后在器件层L1的对准标记的帮助下对光刻胶构图(例如，光刻或电子束曝光等)，来形成掩模层1061。掩模层1061中各开口的最小间隙Wt可以保持基本上一致。这有助于后继工艺的一致性。为保证这种一致性，由如此构图的光刻胶限定的导电结构中有一部分可以是虚设导电结构。
可以掩模层1061作为刻蚀掩模，依次对掩模层1059、导电阻挡层1057、导电主体层1051和导电阻挡层1049进行选择性刻蚀如RIE。RIE可以沿大致竖直的方向进行，并可以停止于电隔离层1047″(或者可以稍微进入电隔离层 1047′，以确保切断各导电层)。这样，在槽的底部与器件层L1的第一源/漏层相对应的高度处形成了横向延伸的导电结构，这些导电结构中的至少一部分与各器件叠层中最下层的第一源/漏层相接触并因此电连接。另外，由于刻蚀步骤，之前的工艺在各器件叠层的顶面处的残留物可以被去除。之后，可以去除掩模层1061。
由于这种刻蚀，导电主体层1051的部分侧壁暴露于外。为防止扩散，可以在导电主体层1051的侧壁上形成导电阻挡层。例如，如图27所示，可以通过淀积，以大致共形的方式，依次形成导电阻挡层1063，并通过各向异性刻蚀如竖直方向的RIE，去除其横向延伸部分而留下其竖直延伸部分，从而形成为侧墙形式并留于导电主体层1051的侧壁上。导电阻挡层1063可以包括与导电阻挡层1049、1057相同或不同的材料。为保持一致性，导电阻挡层1049、1057和1063可以具有相同的材料以及实质上相同的膜厚。
侧墙形式的导电阻挡层1063只要能覆盖导电主体层1051即可。为此，如图28(a)和28(b)所示，可以在槽内特别是导电结构的间隙之间填充电介质层1065(例如，氧化物)。电介质层1065可以通过淀积然后回蚀的方式形成。淀积的电介质层1065的厚度可以大于Wt/2，从而可以完全填满导电结构之间的间隙。
由于电介质层1065处于槽内部，难以对其进行平坦化处理如CMP。为确保电介质层1065的顶面具有一定的平坦度以方便后继的光刻，导电结构可以包括一些虚设图案(即，并不实现真正电连接的互连线和/或过孔)，使得最小间隙如上所述能够保持基本上一致。另外，淀积的膜厚可以大于该最小间隙的一半。为更好地控制电介质层1065的平坦性，其淀积可以采用原子层淀积(ALD)，其回蚀可以采用ALE。
然后，可以通过选择性刻蚀如RIE，去除电介质层1065露出的导电阻挡层1063部分。这样，导电主体层1051被导电阻挡层1049、1057、1063所包封。由此形成的导电结构与器件叠层(例如，需要连接的部件，如源/漏区、栅电极等)之间由于材料不同、上下或前后位置的错位等因素而具有界面或边界。另外，电介质层1065与器件叠层(例如，其中的层间电介质层)之间也可以具有界面或边界。电介质层1065也形成电隔离层的一部分，且在以下被 称作电隔离层。
以上形成了一层导电结构。可以按相同或类似的方式，逐一形成多层导电结构。
接下来，可以形成例如针对各器件叠层中最下方器件的栅导体层的导电结构。所要形成的针对栅导体层的导电结构应该位于与栅导体层相应的高度处。为此，如图29所示，可以通过例如以上结合图19至20(b)所述的方法，淀积然后回蚀电介质材料例如氧化物，将电隔离层1065的顶面抬升至与栅导体层相应的高度。抬升后的电隔离层在图中被标示为1065′。需要指出的是，尽管在此将电隔离层1065′示出为一体，但是先后形成的层之间可以存在界面或边界。在此，各器件叠层顶面上的残留物也可以增厚(图中仅为方便起见，没有示出这种增厚)。
在此，电隔离层1065′的顶面高度可以使得：一方面，第一源/漏层在槽中露出的侧壁被遮挡，以避免随后在电隔离层1065′的顶面上形成的导电结构与第一源/漏层相接触；另一方面，栅导体层的侧壁可以在槽中露出，从而随后在电隔离层1065′的顶面上形成的导电结构可以与栅导体层相接触。
如图30所示，在电隔离层1065′中，可以通过例如刻蚀孔并向孔中填充导电阻挡层如导电氮化物以及导电材料如金属，来形成过孔1067。过孔1067可以实现上下两层之间的电连接。这些过孔中邻近器件叠层的侧壁的一个或多个过孔可以与第一源/漏层直接接触。
另外，如图31(a)和31(b)所示，可以如以上结合图21至28(b)所述，可以在电隔离层1065′上形成导电结构。然后，进一步抬升电隔离层1065′的高度。在此，电隔离层1065′的顶面高度可以使得：一方面，栅导体层在槽中露出的侧壁被遮挡，以避免随后在电隔离层1065′的顶面上形成的导电结构与栅导体层相接触；另一方面，第二源/漏层的侧壁可以在槽中露出，从而随后在电隔离层1065′的顶面上形成的导电结构可以与第二源/漏层相接触。类似地，可以在电隔离层1065′形成过孔。
以这种方式，如图32(a)和32(b)所示，可以逐层形成导电结构，从而形成互连结构。在此，针对每一器件层中的第一源/漏层、栅导体层和第二源/漏层，均在相应高度处形成了相应的导电结构，以实现所需的互连。在图32(a)和32(b) 中，将互连结构中导电结构之间的电隔离层示出为1065″。各层中的上述界面或边界中至少一部分可以实质上共面，例如在竖直方向上实质上对准。
之后，可以制作互连结构的引出端子。例如，如图33所示，可以通过例如淀积并平坦化电介质材料如氧化物来形成层间电介质层(在此与电隔离层一体示出为1065″′)，并在层间电介质层1065″′中形成互连结构1067如互连线或过孔。互连结构1067与之前在槽中形成的互连结构可以相接触并电连接。
在以上实施例中，在相邻的器件层之间均设置了隔离层。但是，本公开不限于此。例如，部分器件层之间可以直接邻接，特别是在互补金属氧化物半导体(CMOS)工艺的情况下。
图34至36示意性示出了根据本公开另一实施例的制造半导体装置特别是其中的互连结构的流程中的一些阶段。
如图34所示，可以如以上结合图1所述，在衬底1001上设置各材料层。与以上实施例的不同之处在于，各源/漏层可以在生长时原位掺杂，从而无需使用掺杂剂源层进行扩散掺杂。在该示例中，器件层L1、L2中的源/漏层可以被掺杂为p型，而器件层L3中的源/漏层可以被掺杂为n型。另一不同之处在于，器件层L2与L3之间并未设置牺牲层1003 3，从而它们直接邻接。
接着，可以按上述相同的工艺来形成隔离层，并形成沟道层1025，如图35所示。图36示出了在沟道层1025周围形成位置保持层1027″之后的情形。如图36所示，器件层L2与L3之间并没有隔离层1017″′，而是直接相邻，也即，随后形成的p型器件和n型器件彼此直接接触且因此电连接，构成CMOS结构。
之后，可以按照以上描述的方式完成器件制作。
根据本公开实施例的半导体装置可以应用于各种电子设备。因此，本公开还提供了一种包括上述半导体装置的电子设备。电子设备还可以包括显示屏幕以及无线收发器等部件。这种电子设备例如智能电话、个人计算机(PC)、平板电脑、人工智能设备、可穿戴设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (39)

  1. 一种半导体装置，包括：
    多个器件叠层，每一器件叠层包括堆叠的多层半导体器件，每个所述半导体器件包括在竖直方向上叠置的第一源/漏层、沟道层和第二源/漏层以及围绕沟道层的栅电极；
    设置在所述多个器件叠层之间的互连结构，
    其中，所述互连结构包括：
    电隔离层；以及
    所述电隔离层中的导电结构，
    其中，至少一部分所述半导体器件各自的第一源/漏层、第二源/漏层和栅电极中至少之一与所述互连结构中相应高度处的导电结构在横向上相接触并因此电连接。
  2. 根据权利要求1所述的半导体装置，还包括至少一对在竖直方向上相邻的半导体器件之间的器件隔离层。
  3. 根据权利要求1或2所述的半导体装置，其中，所述沟道层包括单晶半导体材料。
  4. 根据权利要求1或2所述的半导体装置，其中，所述第一源/漏层和所述第二/源漏层包括单晶半导体材料。
  5. 根据权利要求2所述的半导体装置，其中，所述器件隔离层在所述器件叠层中具有实质上均匀的厚度，且小于所述沟道层的厚度。
  6. 根据权利要求2所述的半导体装置，其中，不同器件叠层中相应高度处的器件隔离层实质上共面。
  7. 根据权利要求2所述的半导体装置，其中，所述器件隔离层包括氧化物、氮化物、SiC或其组合。
  8. 根据权利要求2所述的半导体装置，其中，所述器件隔离层与所述电隔离层之间存在界面。
  9. 根据权利要求1或2所述的半导体装置，其中，同一器件叠层中各半导体器件的沟道层实质上共面。
  10. 根据权利要求1或2所述的半导体装置，其中，至少一个或多个器件叠层中各半导体器件的第一源/漏层和第二源/漏层在俯视图中实质上呈矩形或之字形。
  11. 根据权利要求1或2所述的半导体装置，其中，至少一部分器件叠层中的每个半导体器件各自的栅电极在第一侧的侧壁被第一侧壁隔离层覆盖，而第一源/漏层和第二源/漏层在不同于第一侧的第二侧的侧壁被第二侧壁隔离层覆盖。
  12. 根据权利要求11所述的半导体装置，其中，同一器件叠层中的第一侧壁隔离层实质上共面，第二侧壁隔离层实质上共面。
  13. 根据权利要求11所述的半导体装置，其中，所述第一侧壁隔离层与所述电隔离层之间以及所述第二侧壁隔离层与所述电隔离层之间存在界面。
  14. 根据权利要求11所述的半导体装置，其中，所述栅电极在第二侧与所述互连结构中的相应导电结构相接，所述第一源/漏层和第二源/漏层在第一侧与所述互连结构中的相应导电结构相接。
  15. 根据权利要求1或2所述的半导体装置，其中，所述导电结构包括互连线和过孔中至少之一。
  16. 根据权利要求15所述的半导体装置，其中，所述导电结构包括交替设置的互连线层和过孔层，其中在所述互连线层中设置互连线，在所述过孔层中设置过孔。
  17. 根据权利要求1或2所述的半导体装置，其中，所述导电结构包含金属元素W、Co、Ru、Cu、Al、Ti、Ni、Ta中至少之一。
  18. 根据权利要求1或2所述的半导体装置，其中，所述互连结构环绕至少一部分所述半导体器件。
  19. 根据权利要求1所述的半导体装置，其中，所述互连结构中的导电结构与所述器件叠层之间存在界面。
  20. 根据权利要求1所述的半导体装置，其中，所述互连结构中的电隔离层与所述器件叠层之间存在界面。
  21. 根据权利要求8、13、19或20所述的半导体装置，其中，不同高度处的所述界面中的至少一部分实质上共面。
  22. 根据权利要求1或2所述的半导体装置，其中，所述互连结构中包括虚设导电结构，同一层中的导电结构与导电结构、导电结构与虚设导电结构以及虚设导电结构与虚设导电结构之间的最小间隙在该层中保持实质上一致。
  23. 根据权利要求1所述的半导体装置，其中，至少一对在竖直方向上相邻的半导体器件具有不同的导电类型，并因此形成互补金属氧化物半导体
    CMOS配置。
  24. 一种制造半导体装置的方法，包括：
    在衬底上设置叠层，所述叠层包括一个或多个器件层，每一器件层包括依次叠置的第一源/漏层、沟道限定层和第二源/漏层；
    将所述叠层构图为用于限定有源区的柱体；
    基于所述沟道限定层形成沟道层，所述沟道层相对于所述第一源/漏层和第二源/漏层在横向上相对凹入；
    在所述沟道层相对于所述第一源/漏层和第二源/漏层的凹入中形成栅电极；
    在所述柱体周围形成互连结构，所述互连结构包括电隔离层以及所述电隔离层中的导电结构，
    其中，该方法还包括控制所述互连结构中的导电结构的高度，使得至少一部分所述半导体器件各自的第一源/漏层、第二源/漏层和栅电极中至少之一与相应高度处的导电结构在横向上相接触并因此电连接。
  25. 根据权利要求24所述的方法，其中，所述叠层还包括在所述器件层与所述衬底之间和/或在至少一对相邻的器件层之间的牺牲层，
    该方法还包括：在形成所述柱体之后，保持所述柱体的一侧，以将所述牺牲层替换为器件隔离层。
  26. 根据权利要求24或25所述的方法，其中，所述叠层通过外延生长来设置。
  27. 根据权利要求24或25所述的方法，其中，所述叠层中相邻的两层之间相对于彼此具有刻蚀选择性。
  28. 根据权利要求25所述的方法，其中，将所述牺牲层替换为器件隔离层包括：
    通过选择性刻蚀，使得所述沟道限定层与所述牺牲层相对横向凹入；
    在所述牺牲层的横向凹入中形成填充层，而在所述沟道限定层的横向凹入中形成位置保持层；
    通过选择性刻蚀，去除所述填充层以及由于所述填充层的去除而露出的牺牲层；
    在由于所述填充层以及牺牲层的去除而得到的空隙中形成所述器件隔离层。
  29. 根据权利要求28所述的方法，其中，形成所述填充层包括：
    通过外延生长，形成填充层，所述填充层的生长厚度大于所述牺牲层的厚度的一半，但小于所述沟道限定层的厚度的一半且小于所述沟道限定层的横向凹入深度；
    选择性刻蚀一定厚度的所述填充层。
  30. 根据权利要求28所述的方法，其中，形成所述沟道层包括：
    去除所述位置保持层，在所述沟道限定层的侧壁上外延生长所述沟道层。
  31. 根据权利要求30所述的方法，其中，在外延生长所述沟道层之前，该方法还包括：
    回蚀一定厚度的第一源/漏层、第二源/漏层和沟道限定层，所述厚度与所述沟道层的生长厚度实质上相等。
  32. 根据权利要求30所述的方法，还包括：从所述柱体的所述一侧，通过选择性刻蚀去除所述沟道限定层。
  33. 根据权利要求24所述的方法，还包括：
    遮蔽所述柱体的第一侧，通过选择性刻蚀使所述栅电极相对横向凹入，以形成第一侧壁隔离间隙；
    遮蔽所述柱体的不同于所述第一侧的第二侧，通过选择性刻蚀使所述第一源/漏层和第二源/漏层相对横向凹入，以形成第二侧壁隔离间隙；
    在所述第一侧壁隔离间隙和第二侧壁隔离间隙中填充侧壁隔离层。
  34. 根据权利要求24所述的方法，其中，形成所述互连结构包括：
    交替形成互连线层和过孔层，其中，在所述互连线层中设置互连线，在所述过孔层中设置过孔。
  35. 根据权利要求34所述的方法，其中，形成所述互连线层和过孔层包 括：
    在所述柱体周围第一高度处形成互连线，其中所述第一高度使得所述互连线与相应半导体器件的栅电极、第一源/漏层或第二源/漏层处在实质上相同的高度；
    在所述柱体周围填充电介质材料，以掩埋所述互连线，其中所述电介质材料的顶面处于第二高度，所述第二高度使得随后在所述电介质材料上形成的互连线与相应半导体器件的栅电极、第一源/漏层或第二源/漏层处在实质上相同的高度；以及
    在所述电介质材料中形成过孔。
  36. 根据权利要求35所述的方法，其中，形成所述互连线包括：
    形成导电材料层；
    将所述导电材料层构图为在面内延伸的若干线条图案，其中，至少一些线条图案形成所述互连线，
    其中，各线条图案之间的最小间隙保持实质上一致。
  37. 根据权利要求36所述的方法，还包括：
    形成围绕所述线条图案的导电阻挡层。
  38. 一种电子设备，包括如权利要求1至23中任一项所述的半导体装置。
  39. 根据权利要求38所述的电子设备，其中，所述电子设备包括智能电话、个人计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
PCT/CN2021/115008 2020-12-11 2021-08-27 带侧壁互连结构的半导体装置及其制造方法及电子设备 WO2022121382A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US18/250,128 US20230402392A1 (en) 2020-12-11 2021-08-27 Semiconductor apparatus with sidewall interconnection structure, method of manufacturing semiconductor apparatus with sidewall interconnection structure, and electronic device
EP21902090.6A EP4261883A1 (en) 2020-12-11 2021-08-27 Semiconductor apparatus having side wall interconnection structure and manufacturing method for semiconductor apparatus, and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011463249.8A CN112582377B (zh) 2020-12-11 2020-12-11 带侧壁互连结构的半导体装置及其制造方法及电子设备
CN202011463249.8 2020-12-11

Publications (1)

Publication Number Publication Date
WO2022121382A1 true WO2022121382A1 (zh) 2022-06-16

Family

ID=75131834

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/115008 WO2022121382A1 (zh) 2020-12-11 2021-08-27 带侧壁互连结构的半导体装置及其制造方法及电子设备

Country Status (4)

Country Link
US (1) US20230402392A1 (zh)
EP (1) EP4261883A1 (zh)
CN (1) CN112582377B (zh)
WO (1) WO2022121382A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220189853A1 (en) * 2020-12-11 2022-06-16 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device with sidewall interconnection structure and method for manufacturing the same, and electronic apparatus

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112582375B (zh) * 2020-12-11 2023-11-10 中国科学院微电子研究所 带侧壁互连结构的半导体装置及其制造方法及电子设备
CN112582377B (zh) * 2020-12-11 2023-11-17 中国科学院微电子研究所 带侧壁互连结构的半导体装置及其制造方法及电子设备
CN112582374B (zh) * 2020-12-11 2023-11-07 中国科学院微电子研究所 带侧壁互连结构的半导体装置及其制造方法及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120146131A1 (en) * 2010-12-14 2012-06-14 Hynix Semiconductor Inc. Vertical semiconductor device and method of manufacturing the same
CN106252352A (zh) * 2016-09-30 2016-12-21 中国科学院微电子研究所 半导体设置及其制造方法及包括该设置的电子设备
CN106653731A (zh) * 2015-10-27 2017-05-10 晟碟信息科技（上海）有限公司 半导体装置中的侧壁桥互连体
CN111540748A (zh) * 2020-04-03 2020-08-14 长江存储科技有限责任公司 三维存储器结构及其制备方法
CN112582377A (zh) * 2020-12-11 2021-03-30 中国科学院微电子研究所 带侧壁互连结构的半导体装置及其制造方法及电子设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106992182B (zh) * 2017-04-24 2020-06-09 中国科学院微电子研究所 存储器件及其制造方法及包括该存储器件的电子设备
CN109192721A (zh) * 2018-09-05 2019-01-11 中国科学院微电子研究所 一种半导体器件及其制造方法
CN109300874B (zh) * 2018-10-08 2020-06-30 中国科学院微电子研究所 并联结构及其制造方法及包括该并联结构的电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120146131A1 (en) * 2010-12-14 2012-06-14 Hynix Semiconductor Inc. Vertical semiconductor device and method of manufacturing the same
CN106653731A (zh) * 2015-10-27 2017-05-10 晟碟信息科技（上海）有限公司 半导体装置中的侧壁桥互连体
CN106252352A (zh) * 2016-09-30 2016-12-21 中国科学院微电子研究所 半导体设置及其制造方法及包括该设置的电子设备
CN111540748A (zh) * 2020-04-03 2020-08-14 长江存储科技有限责任公司 三维存储器结构及其制备方法
CN112582377A (zh) * 2020-12-11 2021-03-30 中国科学院微电子研究所 带侧壁互连结构的半导体装置及其制造方法及电子设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220189853A1 (en) * 2020-12-11 2022-06-16 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device with sidewall interconnection structure and method for manufacturing the same, and electronic apparatus
US11961787B2 (en) * 2020-12-11 2024-04-16 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device with sidewall interconnection structure and method for manufacturing the same, and electronic apparatus

Also Published As

Publication number Publication date
US20230402392A1 (en) 2023-12-14
CN112582377B (zh) 2023-11-17
EP4261883A1 (en) 2023-10-18
CN112582377A (zh) 2021-03-30

Similar Documents

Publication Publication Date Title
US20210384351A1 (en) Semiconductor device integrating backside power grid and related integrated circuit and fabrication method
WO2022121382A1 (zh) 带侧壁互连结构的半导体装置及其制造方法及电子设备
US9202922B2 (en) Semiconductor device
CN112992857B (zh) 侧壁互连结构中带散热管道的半导体装置及其制造方法及电子设备
CN112582375B (zh) 带侧壁互连结构的半导体装置及其制造方法及电子设备
CN112582374B (zh) 带侧壁互连结构的半导体装置及其制造方法及电子设备
CN112582376B (zh) 带侧壁互连结构的半导体装置及其制造方法及电子设备
US20230005839A1 (en) Metalized laminate and manufacturing method therefor, and electronic device comprising metalized laminate
CN115188728A (zh) 金属化叠层及其制造方法及包括金属化叠层的电子设备
TWI731390B (zh) 互連結構、電路及包括該互連結構或電路的電子設備
WO2019157775A1 (zh) 互连结构及其制造方法、包括互连结构的电子设备
TWI763591B (zh) 具有銅錳襯層的半導體元件及其製備方法
TWI786847B (zh) 具有銅錳襯層的半導體元件及其製備方法
TWI751896B (zh) 半導體元件及其形成方法
CN114792687A (zh) 栅极结构上具有碳衬垫的半导体元件及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21902090

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2021902090

Country of ref document: EP

Effective date: 20230711