WO2022120647A1 - 显示面板及其驱动方法、显示装置 - Google Patents

显示面板及其驱动方法、显示装置 Download PDF

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Publication number
WO2022120647A1
WO2022120647A1 PCT/CN2020/134972 CN2020134972W WO2022120647A1 WO 2022120647 A1 WO2022120647 A1 WO 2022120647A1 CN 2020134972 W CN2020134972 W CN 2020134972W WO 2022120647 A1 WO2022120647 A1 WO 2022120647A1
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WIPO (PCT)
Prior art keywords
circuit
sub
display
driving
display panel
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PCT/CN2020/134972
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English (en)
French (fr)
Inventor
袁丽君
丛宁
王灿
牛晋飞
玄明花
张粲
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/134972 priority Critical patent/WO2022120647A1/zh
Priority to US17/761,161 priority patent/US11842684B2/en
Priority to CN202080003272.0A priority patent/CN115066719A/zh
Publication of WO2022120647A1 publication Critical patent/WO2022120647A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/30—Transforming light or analogous information into electric information
    • H04N5/33—Transforming infrared radiation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/011—Arrangements for interaction with the human body, e.g. for user immersion in virtual reality
    • G06F3/013—Eye tracking input arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/18—Use of optical transmission of display information
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2380/00—Specific applications

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a driving method thereof, and a display device.
  • Self-luminous devices have the advantages of high brightness, continuously adjustable luminous color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, and high luminous efficiency.
  • a display panel has a display area.
  • the display panel includes a substrate, a plurality of display units, a driving circuit and a gating circuit.
  • the plurality of display units are disposed on the substrate and located in the display area.
  • the driving circuit is disposed on the substrate and located outside the display area.
  • the gate circuit is disposed on the substrate and located in the display area and outside the plurality of display units.
  • Each display unit includes a plurality of pixel islands, and each pixel island includes a plurality of sub-pixels of the same color.
  • the drive circuit is configured to output a plurality of drive signals.
  • the gating circuit is coupled to the driving circuit, and the gating circuit is also coupled to at least one display unit.
  • the gating circuit is configured to control the drive circuit to conduct with the at least one display unit, so that the at least one display unit drives the at least one display unit according to at least one drive signal from the drive circuit Multiple sub-pixels in multiple pixel islands in the display.
  • the display panel further includes a plurality of control signal lines.
  • the plurality of driving signal lines are disposed on the substrate.
  • the drive circuit includes: a plurality of drive signal output terminals.
  • the plurality of driving signal output terminals are configured to output the plurality of driving signals.
  • the gating circuit includes: a plurality of gating sub-circuits.
  • a gating sub-circuit is coupled with at least one control signal line, one display unit and at least one driving signal output terminal.
  • the gating subcircuit is configured to transmit at least one drive signal received at the at least one drive signal output to each pixel in the display unit in response to a control signal transmitted by the at least one control signal line Multiple subpixels in an island.
  • the display unit includes at least one row of sub-pixels.
  • the gating sub-circuit includes: at least one switching sub-circuit.
  • a switch sub-circuit is coupled to a control signal line, a driving signal output terminal and a row of sub-pixels in the display unit.
  • the switch sub-circuit is configured to transmit the drive signal received at the drive signal output terminal to a row of sub-pixels to which the switch sub-circuit is coupled in response to the control signal transmitted by the control signal line.
  • the plurality of display units are arranged in an array.
  • the switch sub-circuits respectively coupled to the sub-pixels of the same row are coupled to the same driving signal output terminal.
  • At least one switch sub-circuit in the gating sub-circuit is coupled to the same control signal line.
  • the switching subcircuit includes: a gate transistor.
  • the control electrode of the pass transistor is coupled to the control signal line, the first electrode of the pass transistor is coupled to the driving signal output end, and the second electrode of the pass transistor is coupled to the display unit A row of sub-pixels in is coupled.
  • different gating sub-circuits are coupled to different control signal lines.
  • the display panel further includes: a plurality of input signal lines.
  • the plurality of input signal lines are disposed on the substrate.
  • the driving circuit includes: a plurality of driving sub-circuits. Each driving sub-circuit is coupled to an input signal line, and the driving sub-circuit includes a plurality of driving signal output terminals.
  • the driving sub-circuit is configured to output a plurality of driving signals from a plurality of driving signal output terminals of the driving sub-circuit according to the input signal transmitted by the input signal line.
  • the driver subcircuit includes a plurality of cascaded shift registers.
  • the output end of each stage of the shift register is a drive signal output end.
  • the input terminal of the first stage shift register is coupled to an input signal line; the output terminal of each stage shift register except the last stage shift register is coupled to the input terminal of the next stage shift register.
  • the display panel further includes: a plurality of data lines.
  • the plurality of data lines are disposed on the substrate.
  • the subpixels include pixel circuits.
  • the pixel circuit includes a data writing sub-circuit; the data writing sub-circuit is coupled to the gating circuit and a data line.
  • the data writing subcircuit is configured to write the data signal transmitted by the data line in response to a drive signal from the gating circuit.
  • the subpixels comprise light emitting devices.
  • the light-emitting device includes a light-emitting layer; the light-emitting layers of the light-emitting device in a plurality of sub-pixels in one pixel island have no gaps.
  • the display panel further includes an optical film.
  • the optical film is disposed on a side of the plurality of display units away from the substrate.
  • the optical film is configured to refract light emitted by each sub-pixel in each pixel island in the display unit in the display panel to disperse it to a plurality of pixel regions.
  • a display device in another aspect, includes: the display panel according to any one of the above embodiments.
  • the display device further includes a processing device.
  • the processing device is configured to output at least one control signal to the gating circuit in the display panel according to the information of the to-be-displayed area of the display panel, so as to control the driving circuit in the display panel and the display panel at least one display unit corresponding to the to-be-displayed area in the display panel is turned on; and, according to the information of the to-be-displayed area of the display panel, output at least one input signal to the drive circuit in the display panel, so that the drive circuit The circuit outputs at least one driving signal to at least one display unit corresponding to the area to be displayed.
  • the display device further includes an information collection device.
  • the information collection device is configured to collect user sight line information.
  • the processing device is further configured to acquire the user's sight line information, and determine the information of the to-be-displayed area of the display panel according to the user's sight line information.
  • a method for driving a display panel includes: outputting at least one input signal to a driving circuit in the display panel according to the information of the to-be-displayed area of the display panel, so that the driving circuit responds to the at least one input signal to a At least one display unit corresponding to the to-be-displayed area outputs at least one drive signal; according to the information of the to-be-displayed area of the display panel, outputs at least one control signal to the gating circuit in the display panel, so that the selection
  • the turn-on circuit controls the drive circuit to conduct conduction with at least one display unit corresponding to the to-be-displayed area among the plurality of display units according to the at least one control signal, so that the at least one display unit receives data from the drive circuit
  • the at least one driving signal drives at least one display unit corresponding to the to-be-displayed area to display.
  • the driving method further includes: acquiring user sight line information; and determining information of the area to be displayed on the display panel according to the user sight line information.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • FIG. 2 is a structural diagram of a display panel according to some embodiments.
  • FIG. 3 is a structural diagram of a sub-pixel according to some embodiments.
  • FIG. 4 is a structural diagram of a light emitting device according to some embodiments.
  • FIG. 5 is another structural diagram of a display panel according to some embodiments.
  • FIG. 6 is another structural diagram of a display panel according to some embodiments.
  • FIG. 7 is another structural diagram of a display panel according to some embodiments.
  • FIG. 8 is another structural diagram of a display panel according to some embodiments.
  • FIG. 9 is another structural diagram of a display panel according to some embodiments.
  • 10A is another structural diagram of a display panel according to some embodiments.
  • 10B is a structural diagram of a driving sub-circuit according to some embodiments.
  • FIG. 11 is a structural diagram of a shift register according to some embodiments.
  • FIG. 12 is another structural diagram of a shift register according to some embodiments.
  • FIG. 13 is a driving timing diagram of a shift register according to some embodiments.
  • FIG. 14 is still another structural diagram of a display panel according to some embodiments.
  • FIG. 15 is another structural diagram of a display panel according to some embodiments.
  • FIG. 16 is another structural diagram of a display panel according to some embodiments.
  • FIG. 17 is another structural diagram of a display panel according to some embodiments.
  • 18A is another structural diagram of a display panel according to some embodiments.
  • FIG. 18B is a cross-sectional view of the display panel in FIG. 18A along the A-B direction;
  • FIG. 19 is an optical schematic diagram of an optical film according to some embodiments.
  • FIG. 20 is another structural diagram of a display device according to some embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on detection of [recited condition or event]” or “in response to detection of [recited condition or event]”.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the display device may be any device that displays text or images, whether in motion (eg, video) or stationary (eg, still images).
  • the embodiments of the present disclosure do not specifically limit the specific form of the above-mentioned display device.
  • the display device may be a micro display device; for example, the micro display device may include a head-mounted display device; for example, the head-mounted display device may include a VR (Virtual Reality, virtual reality) display device or an AR (Augmented Reality, augmented reality) display device. ) display device, etc.
  • the display device 200 includes the display panel 100 .
  • the display panel 100 has a display area (Active Area, AA) and a peripheral area S.
  • the peripheral area S is located at least on the outer side of the AA area.
  • the display panel includes a plurality of sub-pixels located in the AA area.
  • at least one sub-pixel P includes a pixel circuit 110 and a light emitting device L.
  • the pixel circuit 110 is coupled to the light emitting device L.
  • the pixel circuit 110 is configured to drive the light emitting device L to emit light.
  • the pixel circuits are arranged in an array.
  • the embodiments of the present disclosure do not limit the specific structure of the pixel circuit, and can be designed according to actual conditions.
  • the pixel circuit is composed of electronic devices such as transistors (for example, thin film transistors (Thin Film Transistor, TFT)), capacitors (Capacitance, C for short).
  • the pixel circuit may include two transistors and one capacitor to form a 2T1C structure; of course, the pixel circuit may also include more than two transistors and at least one capacitor, such as seven transistors and one capacitor, to form a 7T1C structure.
  • the light-emitting device may adopt a current-driven light-emitting device including LED (Light Emitting Diode, Light Emitting Diode), OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) or Quantum Light Emitting Diode (QLED). device.
  • LED Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • QLED Quantum Light Emitting Diode
  • the light-emitting device L includes a cathode 1202 and an anode 1201 , and a light-emitting functional layer 1203 between the cathode 1202 and the anode 1201 .
  • the light-emitting functional layer 1203 may include, for example, a light-emitting layer E, a hole transport layer (HTL) located between the light-emitting layer E and the anode 1201 , an electron transport layer (Election Layer) located between the light-emitting layer E and the cathode 1202 Transporting Layer, ETL).
  • a hole injection layer Hole Injection Layer, HIL
  • an electron injection layer may be provided between the electron transport layer ETL and the cathode 1202 (Election Injection Layer, EIL).
  • the anode may be formed of, for example, a transparent conductive material having a high work function
  • the electrode material may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO) oxide Zinc (ZnO), indium oxide (In 2 O 3 ), aluminum zinc (AZO), carbon nanotubes, etc.
  • the cathode can be formed of a material with high conductivity and low work function, for example, and the electrode material can include magnesium aluminum alloy (MgAl ) and alloys such as lithium aluminum alloy (LiAl), or simple metals such as magnesium (Mg), aluminum (Al), lithium (Li), and silver (Ag).
  • the material of the light-emitting layer can be selected according to the color of the emitted light.
  • the material of the light-emitting layer includes a fluorescent light-emitting material or a phosphorescent light-emitting material.
  • a doping system may be adopted for the light-emitting layer, that is, a doping material is mixed into a host light-emitting material to obtain a usable light-emitting material.
  • metal compound materials derivatives of anthracene, aromatic diamine-based compounds, triphenylamine compounds, aromatic triamine-based compounds, biphenylenediamine derivatives, triarylamine polymers, and the like can be used as the host light-emitting material.
  • Embodiments of the present disclosure provide a display panel.
  • the display panel 100 includes a substrate 10 , a plurality of display units 20 , a driving circuit 30 and a gate circuit 40 .
  • a plurality of display units 20 , driving circuits 30 and gate circuits 40 are all disposed on the substrate 10 .
  • the substrate 10 may include: a rigid substrate such as glass (or referred to as a rigid substrate), or a flexible substrate such as PI (Polyimide, polyimide); Films such as buffer layers on flexible substrates.
  • a rigid substrate such as glass (or referred to as a rigid substrate)
  • a flexible substrate such as PI (Polyimide, polyimide)
  • Films such as buffer layers on flexible substrates.
  • the substrate 10 may be a silicon-based substrate.
  • each display unit 20 includes a plurality of pixel islands 21 .
  • Each pixel island 21 includes a plurality of sub-pixels P of the same color.
  • the colors of the plurality of pixel islands 21 in the display unit 20 are different from each other. It can be understood that a plurality of display units 20 are located in the AA area.
  • a plurality of pixel islands can be arranged in an array; for example, the pixel islands 21 arranged in a row along the X direction (horizontal direction) in FIG. ) arranged in a row of pixel islands 21 are referred to as the same row of pixel islands.
  • a plurality of sub-pixels may be arranged in an array.
  • the sub-pixels P arranged in a row along the X direction in FIG. 5 are referred to as sub-pixels in the same row
  • the sub-pixels P arranged in a row in the Y direction in FIG. 5 are referred to as sub-pixels in the same column.
  • the number of sub-pixels in the pixel island can be designed according to the actual situation, for example, according to the size of the area mapped on the display panel by the user's line of sight.
  • Arrangement (as shown in FIG. 5 ), or, a plurality of sub-pixels in a pixel island are arranged in an array of 5 rows and 5 columns, which is not specifically limited herein.
  • the plurality of sub-pixels include first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels; correspondingly, the plurality of pixel islands include first-color pixel islands, second-color pixel islands, and third-color pixels island.
  • the first color, the second color and the third color are three primary colors; for example, the first color, the second color and the third color are red, green and blue, respectively; that is, the plurality of sub-pixels include red sub-pixels, green Subpixels and blue subpixels; the plurality of pixel islands include red pixel islands, green pixel islands, and blue pixel islands.
  • a display unit includes a red pixel island, a green pixel island and a blue pixel island.
  • the subpixel includes a light emitting device including a light emitting layer.
  • the light-emitting layers of the light-emitting devices in the plurality of sub-pixels in one pixel island are free of gaps.
  • the light-emitting layers of the light-emitting devices in a plurality of sub-pixels in one pixel island are connected in an integrated structure.
  • each opening of the mask may correspond to the light-emitting layers of all light-emitting devices in one pixel island, that is, , the light-emitting layers in the pixel island are formed by co-evaporation through the same opening of the mask; that is, the light-emitting layers in the light-emitting devices in the pixel island can be co-evaporated through the same opening of the mask.
  • the distance between adjacent sub-pixels is relatively small. It is formed by vapor deposition through an opening of the mask plate, resulting in relatively high requirements for the mask plate, and the preparation process is difficult due to the limitation of the mask plate.
  • the light-emitting layers of the light-emitting devices in multiple sub-pixels can be formed by evaporation through the same opening of the mask, and the requirements for the mask are relatively low, and the low PPI (
  • the mask of the light-emitting layer in the display panel of 400PPI makes the light-emitting layer of the display panel with high PPI (for example, 1000PPI to 10000PPI).
  • a display panel with a higher number of pixels In this way, while realizing a high PPI display panel, the difficulty of preparing the mask plate and the difficulty of the evaporation process can also be reduced.
  • each pixel island has the same size, and the number and size of sub-pixels in each pixel island are also the same.
  • the size of the pixel island is related to the size of the sub-pixels it contains; for example, the size of the pixel island is approximately equal to the size of n sub-pixels, where n is the number of sub-pixels in the pixel island.
  • the driving circuit 30 is located outside the AA area, that is, the driving circuit 30 is located in the peripheral area S.
  • the gate circuit 40 is located in the AA area, and the gate circuit 40 is located outside the plurality of display units 20 .
  • the gating circuit 40 is coupled to the driving circuit 30 , and the gating circuit 40 is also coupled to at least one display unit 20 .
  • the drive circuit 30 is configured to output a plurality of drive signals.
  • the driving signal may be a gate driving signal.
  • the gating circuit 40 is configured to control the driving circuit 30 to conduct with the at least one display unit 20 , so that the at least one display unit 20 drives a plurality of pixel islands in the at least one display unit 20 according to at least one driving signal from the driving circuit 30 A plurality of sub-pixels P in 21 are displayed.
  • the gating circuit 40 controls at least one display unit 20 of the plurality of display units 20 to conduct with the driving circuit 30, and the driving circuit 30 transmits at least one driving signal to the at least one display unit 20 that is conducting with it, so that the display
  • the plurality of sub-pixels P in the plurality of pixel islands 21 in the unit 20 receive the driving signal, that is, the pixel circuits 110 in the plurality of sub-pixels P generate a driving current according to the received driving signal, and drive the light-emitting device L to emit light, so that the plurality of sub-pixels P emit light.
  • At least one of the display units 20 displays.
  • some display units (one or more display units) of the plurality of display units in the display panel are displayed, and the rest of the display units are not displayed, that is, a partial area in the display panel is displayed, and the remaining areas are not displayed. to display.
  • the conduction state of each display unit and the driving circuit can be independently controlled, and each display unit in the display panel can be individually controlled to be in a display state or a non-display state, so as to realize independent driving of multiple display units, and realize Independent control of the display of multiple display units.
  • the display panel provided by the embodiments of the present disclosure can realize partitioned display , thereby reducing the display power consumption.
  • the display panel (or display screen) can be divided into multiple sub-display screens according to multiple display units, one display unit corresponds to one sub-display screen, and the display area of the display unit corresponds to the display area of the sub-display screen, thus, In the case where some display units in the multiple display units are displaying, some sub-displays in the display panel are displayed, and the remaining sub-displays are not displayed, so as to realize split-screen display; in the case where all the multiple display units are displayed , all sub-displays in the display panel are displayed to achieve full-screen display.
  • embodiments of the present disclosure provide a display panel, wherein a gating circuit in the display panel controls a driving circuit to conduct with at least one display unit, so that the at least one display unit drives at least one display unit according to at least one driving signal from the driving circuit A plurality of sub-pixels in a plurality of pixel islands in the display unit are displayed.
  • the conduction state of each display unit and the driving circuit can be independently controlled, and each display unit in the display panel can be individually controlled to be in a display state or a non-display state, so as to realize independent control of multiple display units.
  • the display panel provided by the embodiments of the present disclosure can implement partitioned display, thereby reducing display power consumption.
  • the display panel 100 further includes a plurality of control signal lines CL.
  • a plurality of control signal lines CL are provided on the substrate 10 .
  • the control signal lines are configured to carry control signals; for example, one control signal line may carry one control signal.
  • the driving circuit 30 includes a plurality of driving signal output terminals OUT.
  • the plurality of driving signal output terminals OUT are configured to output a plurality of driving signals.
  • the gating circuit 40 includes a plurality of gating sub-circuits 41 .
  • a gate sub-circuit 41 is coupled to at least one control signal line CL, one display unit 20 and at least one driving signal output terminal OUT. Exemplarily, the number of gating sub-circuits is the same as the number of display units.
  • the position of the gating sub-circuit can be designed according to the actual situation, which is not limited here.
  • the gating sub-circuit may be located in the peripheral area; for example, the gating sub-circuit may be located in the area outside the display unit to which it is coupled; for example, the gating sub-circuit may be located in the area between two adjacent display units.
  • the gating subcircuit is configured to transmit at least one drive signal received at the at least one drive signal output to a plurality of subpixels in each pixel island in the display unit in response to a control signal transmitted by the at least one control signal line. It can be understood that under the control of the control signal, the gating sub-circuit is turned on, and the display unit to which it is coupled is connected to the driving circuit, so that the driving signal output by the driving circuit can be transmitted to the display unit, and each pixel in the display unit is turned on.
  • the sub-pixels in the island perform display under the control of the driving signal, that is, the pixel circuits in the sub-pixels provide the driving current to the light-emitting device under the control of the driving signal to drive the light-emitting device to emit light.
  • the driving signal that is, the pixel circuits in the sub-pixels provide the driving current to the light-emitting device under the control of the driving signal to drive the light-emitting device to emit light.
  • the conduction or non-conduction of the display unit and the driving circuit can be controlled.
  • the cells are not displayed, so that the display panel realizes partition display, so that the power consumption of the display panel can be reduced.
  • the display unit includes at least one row of sub-pixels.
  • the display unit 20 includes three pixel islands sequentially arranged in a row direction (eg, the X direction in FIG. 5 ), and the three pixel islands respectively include red sub-pixels, green sub-pixels and blue sub-pixels.
  • a row of sub-pixels in the display unit includes a row of red sub-pixels in a pixel island, a row of green sub-pixels in a pixel island and a row of blue sub-pixels in a pixel island, the row of red sub-pixels, a row of green sub-pixels and a row of blue sub-pixels.
  • the color sub-pixels are included in the same row of sub-pixels.
  • the gating sub-circuit 41 includes at least one switching sub-circuit 411 .
  • a switch sub-circuit 411 is coupled to a control signal line CL, a driving signal output terminal OUT and a row of sub-pixels in the display unit 20 .
  • the number of switch sub-circuits is the same as the number of rows of sub-pixels included in the display unit; for example, in the case where the display unit 20 includes two rows of sub-pixels P, referring to FIG.
  • the gating sub-circuit 41 includes two switching sub-circuits 411; for example, in the case that the display unit includes three rows of sub-pixels, the gating sub-circuit to which the display unit is coupled includes three switching sub-circuits.
  • the switch sub-circuit is configured to transmit the drive signal received at the drive signal output terminal to a row of sub-pixels to which the switch sub-circuit is coupled in response to the control signal transmitted by the control signal line. It can be understood that, under the control of the control signal, the switch sub-circuit is turned on, and a row of sub-circuits is connected to one driving signal output terminal of the driving circuit, so that a row of sub-pixels receives the driving signal from the driving signal output terminal, and a row of sub-pixels receives the driving signal from the driving signal output terminal. Under the control of the driving signal, the pixel circuit in the device drives the light-emitting device to emit light, so that a row of sub-pixels realizes display.
  • each row of subpixels in the display unit can receive a driving signal, so that the subpixels in each pixel island in the display unit can display.
  • multiple rows of sub-pixels in the display unit may be driven row by row and displayed row by row.
  • the switch sub-circuit 411 includes a gate transistor MK.
  • the control electrode of the switching transistor MK is coupled to the control signal line CL
  • the first electrode of the gate transistor MK is coupled to the driving signal output terminal OUT
  • the second electrode of the gate transistor MK is coupled to a row of sub-pixels P in the display unit 20 catch.
  • the gate transistor MK is turned on in response to the control signal transmitted by the control signal line CL, and transmits the driving signal received at the driving signal output terminal OUT to a row of sub-pixels P, so as to drive a row of sub-pixels. Pixel P is displayed.
  • the plurality of display units are arranged in an array.
  • the switch sub-circuits respectively coupled to the sub-pixels of the same row are coupled to the same driving signal output terminal.
  • sub-pixels with the same row number in each pixel island are sub-pixels in the same row.
  • the ith row of subpixels in each pixel island in each display unit are subpixels in the same row, and are the ith row of subpixels in the display unit, and i is a positive integer.
  • the drive circuit outputs the drive signal to the display unit line by line, and by controlling the on or off of the switch sub-circuit, so that the display unit in each line of the display unit that is connected to the drive circuit is displayed, and each line of the display unit can be controlled. At least one column of display units in the display unit is displayed, so as to realize the partition driving of the display unit.
  • At least one switch sub-circuit in the gating sub-circuit is coupled to the same control signal line.
  • the wiring design of the display panel can be simplified.
  • at least one switch sub-circuit in the gating sub-circuits receives the same control signal, and the at least one switching sub-circuit in the gating sub-circuit can be turned on or off at the same time.
  • different gating sub-circuits are coupled to different control signal lines.
  • different gating sub-circuits receive different control signals, so that the display unit and the driving circuit are turned on at different times, and the display panel is controlled to realize partition display.
  • the display panel 100 further includes a plurality of input signal lines STV.
  • a plurality of input signal lines STV are provided on the substrate 10 .
  • the input signal line is configured to transmit the input signal.
  • the driving circuit 30 includes a plurality of driving sub-circuits 31 .
  • Each driving sub-circuit 31 is coupled to an input signal line STV.
  • the driving sub-circuit 31 includes a plurality of driving signal output terminals OUT.
  • the driving sub-circuit 31 is configured to output a plurality of driving signals from the plurality of driving signal output terminals OUT of the driving sub-circuit 31 according to the input signal transmitted by the input signal line STV. It can be understood that, according to different input signals, different driving sub-circuits can be controlled to output driving signals, so as to control different display units to display.
  • each drive subcircuit may provide drive signals to a row of display cells.
  • the gating sub-circuit coupled to each display unit in the row of display units is in an off state, that is, each display unit in the row of display units is connected to
  • the driving sub-circuit is not turned on.
  • the driving sub-circuit that provides the driving signal to the display unit of the row may not work, and there is no input signal transmission on the input signal line coupled to the non-working driving sub-circuit.
  • each sub-pixel in the display panel when the display panel is in a full-screen display state, each sub-pixel in the display panel can be driven row by row in sequence; when the display panel is in a partial display state, each sub-pixel in the display panel can be driven row by row in sequence. In sequence, each sub-pixel in the display unit to be displayed is driven.
  • a driving circuit 30 may be provided on one side of the two opposite outer sides of the AA area, and the display panel 100 outputs the driving signal from one side through the driving circuit 30, so that the The area of the peripheral region S simplifies the circuit design of the display panel 100 .
  • two driving circuits 30 may be respectively disposed on opposite outer sides of the AA area. In this case, the display panel 100 may be driven by both sides simultaneously. The driving signal is output from both sides, which can reduce the voltage drop generated by the driving signal during the transmission process, thereby improving the uniformity of display; side output drive signal.
  • the driving sub-circuit 31 includes a plurality of cascaded shift registers RS (eg, the first stage shift register RS(1) in FIG. 10B , the second stage shift register RS(1) in FIG. Bit register RS(2), third-stage shift register RS(3)).
  • the output terminal Oput of each stage of the shift register is a driving signal output terminal OUT. It can be understood that, the output terminal Oput of each stage of the shift register RS is configured to output a driving signal.
  • the input end of the first-stage shift register is coupled to an input signal line.
  • the output terminal of each shift register except the last stage shift register is coupled to the input terminal of the next stage shift register.
  • the input terminal IN of the first-stage shift register RS(1) is coupled to the input signal line STV; the output terminal Oput of the first-stage shift register RS(1) is connected to the second-stage shift register RS
  • the input terminal IN of (2) is coupled; the output terminal Oput of the second stage shift register RS(2) is coupled with the input terminal IN of the third stage shift register RS(3), and so on, until the last stage
  • the input terminal of the shift register is coupled to the output terminal of the previous stage shift register of the last stage shift register.
  • each shift register in each driving sub-circuit outputs a driving signal to a row of sub-pixels in the display unit to which the driving sub-circuit is coupled.
  • the driving sub-circuit 31 includes three shift registers RS( 1 ), RS( 2 ) and RS that are cascaded in sequence (3).
  • Figure 6, Figure 7, Figure 8, Figure 9 and Figure 10A only show schematic diagrams of the connection between the pixel island and each circuit.
  • the actual circuit connection is not limited to this, and can be designed according to the actual situation. Here Not limited.
  • the first clock signal terminals of two adjacent cascaded shift registers are respectively coupled to different clock signal lines, and the second clock signal terminals are respectively coupled to different clock signal lines.
  • the first clock signal terminal CLK1 in the odd-numbered stage shift register is coupled to the first clock signal line CLKA
  • the second clock signal terminal CLK2 in the odd-numbered stage shift register is coupled to the second clock signal line CLKB
  • the first clock signal terminal CLK1 in the even-numbered stage shift register is coupled to the second clock signal line CLKB
  • the second clock signal terminal CLK2 in the even-numbered stage shift register is coupled to the first clock signal line CLKA.
  • the signal transmitted by the first clock signal line CLKA and the signal transmitted by the second clock signal line CLKB have a certain phase difference; for example, the signal transmitted by the first clock signal line CLKA and the signal transmitted by the second clock signal line CLKB are mutually Invert the signal.
  • the shift register RS includes an input sub-circuit 121 and an output sub-circuit 122 .
  • the input sub-circuit 121 is coupled to the input signal terminal IN and the pull-up node PU.
  • the output sub-circuit 122 is coupled to the pull-up node PU, the first clock signal terminal CLK1 and the output terminal Oput.
  • the input subcircuit 121 is configured to transmit the input signal to the pull-up node PU in response to the input signal received at the input signal terminal IN.
  • the output subcircuit 122 is configured to transmit the first clock signal received at the first clock signal terminal CLK1 to the output terminal Oput in response to the voltage of the pull-up node PU. It can be understood that the signal output by the output terminal Oput is the driving signal.
  • the input sub-circuit 121 includes a first transistor M1.
  • the control electrode and the first electrode of the first transistor M1 are respectively coupled to the input signal terminal IN, and the second electrode of the first transistor M1 is coupled to the pull-up node PU.
  • the output sub-circuit 122 includes a second transistor M2 and a first capacitor C1.
  • the control electrode of the second transistor M2 is coupled to the pull-up node PU, the first electrode of the second transistor M2 is coupled to the first clock signal terminal CLK1, and the second electrode of the second transistor M2 is coupled to the output terminal Oput.
  • the first pole of the first capacitor C1 is coupled to the pull-up node PU, and the second pole of the first capacitor C2 is coupled to the output terminal Oput.
  • the shift register RS further includes a pull-down control sub-circuit 123 .
  • the pull-down control sub-circuit 123 is coupled to the second clock signal terminal CLK2, the pull-up node PU, the pull-down node PD and the voltage terminal VGL.
  • the pull-down control sub-circuit 123 is configured to transmit the second clock signal to the pull-down node PD in response to the second clock signal received at the second clock signal terminal CLK2; and, in response to the voltage of the pull-up node PU, to the voltage terminal
  • the voltage of VGL is transferred to the pull-down node PD.
  • the voltage terminal VGL is configured to transmit a DC low level signal.
  • the pull-down control sub-circuit 123 includes a third transistor M3 and a fourth transistor M4.
  • the control electrode and the first electrode of the third transistor M3 are respectively coupled to the second clock signal terminal CLK2, and the second electrode of the third transistor M3 is coupled to the pull-down node PD.
  • the control electrode of the fourth transistor M4 is coupled to the pull-up node PU, the first electrode of the fourth transistor M4 is coupled to the voltage terminal VGL, and the second electrode of the fourth transistor M4 is coupled to the pull-down node PD.
  • the shift register RS further includes a first noise reduction sub-circuit 124 .
  • the first noise reduction sub-circuit 124 is coupled to the voltage terminal VGL, the reset signal terminal Rst and the pull-up node PU.
  • the first noise reduction sub-circuit 124 is configured to transmit the voltage of the voltage terminal VGL to the pull-up node PU in response to the reset signal received at the reset signal terminal Rst. In this way, the pull-up node can be denoised during the inactive output stage of the shift register to avoid signal interference.
  • the first noise reduction sub-circuit 124 includes a fifth transistor M5.
  • the control electrode of the fifth transistor M5 is coupled to the reset signal end Rst, the first electrode of the fifth transistor M5 is coupled to the voltage end VGL, and the second electrode of the fifth transistor M5 is coupled to the pull-up node PU.
  • the shift register RS further includes a second noise reduction sub-circuit 125 .
  • the second noise reduction sub-circuit 125 is coupled to the pull-down node PD, the voltage terminal VGL and the pull-up node PU.
  • the second noise reduction subcircuit 125 is configured to transmit the voltage of the voltage terminal VGL to the pull-up node PU in response to the voltage of the pull-down node PD. In this way, the pull-up node can be denoised during the inactive output stage of the shift register to avoid signal interference.
  • the second noise reduction sub-circuit 125 includes a sixth transistor M6.
  • the control electrode of the sixth transistor M6 is coupled to the pull-down node PD, the first electrode of the sixth transistor M6 is coupled to the voltage terminal VGL, and the second electrode of the sixth transistor M6 is coupled to the pull-up node PU.
  • the shift register RS further includes a third noise reduction sub-circuit 126 .
  • the third noise reduction sub-circuit 126 is coupled to the pull-down node PD, the voltage terminal VGL and the output terminal Oput.
  • the third noise reduction subcircuit is configured 126 to transmit the voltage of the voltage terminal VGL to the output terminal Oput in response to the voltage of the pull-down node PD. In this way, noise reduction can be performed on the output end in the ineffective output stage of the shift register to avoid signal interference.
  • the third noise reduction sub-circuit 126 includes a seventh transistor M7.
  • the control electrode of the seventh transistor M7 is coupled to the pull-down node PD, the first electrode of the seventh transistor M7 is coupled to the voltage terminal VGL, and the second electrode of the seventh transistor M7 is coupled to the output end Oput.
  • the shift register RS further includes a first voltage regulator sub-circuit 127 .
  • the first voltage regulator sub-circuit 127 is coupled to the pull-down node PD, the voltage terminal VGL and the output terminal Oput.
  • the first voltage regulator sub-circuit 127 is configured to transmit the voltage of the voltage terminal VGL to the pull-down node PD to control the voltage of the pull-down node PD in response to the signal received at the output terminal Oput.
  • the first voltage regulator sub-circuit 127 transmits the voltage of the voltage terminal VGL to the pull-down node PD, and controls the voltage of the pull-down node PD. Keep stable (for example, the voltage of the pull-down node PD is kept at a low level voltage), so that the output terminal Oput can be output stably.
  • the first voltage regulator sub-circuit 127 includes an eighth transistor M8.
  • the control electrode of the eighth transistor M8 is coupled to the output terminal Oput, the first electrode of the eighth transistor M8 is coupled to the voltage terminal VGL, and the second electrode of the eighth transistor M8 is coupled to the pull-down node PD.
  • the shift register RS further includes a second voltage regulator sub-circuit 128 .
  • the second voltage regulator sub-circuit 128 is coupled to the voltage terminal VGL and the pull-down node PD.
  • the second voltage regulator sub-circuit 128 is configured to control the voltage of the pull-down node PD according to the voltage of the voltage terminal VGL and the voltage of the pull-down node PD.
  • the second voltage regulator sub-circuit 128 may control the voltage of the pull-down node PD, for example, control the voltage of the pull-down node PD to be at a high level. voltage, so that the voltage of the pull-down node PD remains stable, so as to ensure that the shift register can work normally.
  • the second voltage regulator sub-circuit 128 includes a second capacitor C2.
  • the first pole of the second capacitor C2 is coupled to the voltage terminal VGL, and the second pole of the second capacitor C2 is coupled to the pull-down node PD.
  • each transistor in the shift register is an N-type transistor.
  • the input sub-circuit 121 transmits the input signal to the pull-up node PU in response to the input signal received at the input terminal IN, and the pull-up Node PU charging.
  • the output sub-circuit 122 transmits the first clock signal received at the first clock signal terminal CLK1 to the output terminal OUT.
  • the first transistor M1 in the input sub-circuit 121 is turned on to transmit the input signal to the pull-up node PU, so that the voltage of the pull-up node PU is a high-level voltage , the first capacitor C1 in the output sub-circuit 122 is charged, and the second transistor M2 in the output sub-circuit 122 responds to the voltage of the high-level pull-up node PU, and transmits the low-level first clock signal to the output terminal Oput, at this time, the driving signal output by the output terminal Oput is a low-level signal.
  • the pull-down control sub-circuit 123 transmits the second clock signal to the pull-down node PD in response to the second clock signal received at the second clock signal terminal CLK2; and, in response to the voltage of the pull-up node PU, changes the voltage of the voltage terminal VGL to transmitted to the pull-down node PD.
  • the third transistor M3 in the pull-down control sub-circuit 123 is turned on to transmit the second clock signal to the pull-down node PD;
  • the fourth transistor M4 responds to The high-level voltage of the pull-up node PU is turned on, and the fourth transistor M4 is turned on to transmit the low-level voltage of the voltage terminal VGL to the pull-down node PD, because the width to length ratio of the channel of the fourth transistor M4 is larger than that of the third transistor The width to length ratio of the channel of M3, therefore, the voltage of the pull-down node PD is a low level voltage.
  • first noise reduction sub-circuit 124, the second noise reduction sub-circuit 125 and the third noise reduction sub-circuit 126 are all inactive, that is, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all turned off.
  • the first voltage regulator sub-circuit 127 also does not work, that is, the eighth transistor M8 is turned off.
  • the output sub-circuit 122 will receive the first clock signal received at the first clock signal terminal CLK1
  • the clock signal is transmitted to the output terminal Oput.
  • the first transistor M1 in the input sub-circuit 121 is turned off under the control of the low-level input signal. Due to the bootstrapping effect of the first capacitor C1, the voltage of the pull-up node PU is still a high level voltage.
  • the second transistor M2 in the output sub-circuit 122 transmits the low-level first clock signal to the output terminal OUT in response to the high-level voltage of the pull-up node PU. At this time, the driving signal output by the output terminal Oput is high. level signal.
  • the pull-down control sub-circuit 123 transmits the voltage of the voltage terminal VGL to the pull-down node PD in response to the voltage of the pull-up node PU.
  • the third transistor M3 in the pull-down control sub-circuit 123 is controlled by the low-level second clock signal, and the third transistor M3 is turned off; the fourth transistor M4 is pulled up by the high-level voltage of the node PU, the fourth The transistor M4 is turned on, and transmits the low-level voltage of the voltage terminal VGL to the pull-down node PD, so the pull-down node PD is at a low-level potential, so that the voltage of the pull-down node PD is a low-level voltage.
  • the first voltage regulator sub-circuit 127 transfers the voltage of the voltage terminal VGL to the pull-down node PD in response to the signal received at the output terminal Oput.
  • the eighth transistor M8 in the first voltage regulator sub-circuit 127 transmits the low-level voltage of the voltage terminal VGL to the pull-down node PD in response to the high-level signal received at the output terminal Oput.
  • the voltage of the pull-down node PD is a low-level voltage.
  • the first noise reduction sub-circuit 124 transmits the voltage of the voltage terminal VGL to the pull-up in response to the reset signal received at the reset signal terminal Rst Node PU.
  • the fifth transistor M5 in the first noise reduction sub-circuit 124 transmits the low-level voltage of the voltage terminal VGL to the pull-up node PU in response to the high-level reset signal.
  • the pull-down control subcircuit 123 transmits the second clock signal to the pull-down node PD in response to the second clock signal received at the second clock signal terminal CLK2.
  • the third transistor M3 in the pull-down control sub-circuit 123 is turned on, and transmits the high-level second clock signal to the pull-down node PD, so that the pull-down The voltage of the node PD is a high-level voltage; the fourth transistor M4 is turned off under the control of the low-level voltage of the pull-up node PU, and at this time, the voltage of the pull-down node PD is a high-level voltage.
  • the second noise reduction sub-circuit 125 transmits the voltage of the voltage terminal VGL to the pull-up node PU in response to the voltage of the pull-down node PD.
  • the sixth transistor M6 in the second noise reduction sub-circuit 125 transmits the low-level voltage of the voltage terminal VGL to the pull-up node PU in response to the high-level voltage of the pull-down node PD.
  • the voltage of the pull-up node PU is a low-level voltage.
  • the second transistor M2 in the output sub-circuit 122 is turned off and does not output the first clock signal.
  • the third noise reduction sub-circuit 127 transmits the voltage of the voltage terminal VGL to the output terminal Oput in response to the voltage of the pull-down node PD.
  • the eighth transistor M8 in the third noise reduction sub-circuit 127 transmits the low-level voltage of the voltage terminal VGL to the output terminal Oput in response to the high-level voltage of the pull-down node PD, so that the output terminal Oput outputs a low-level voltage
  • the level signal that is, the drive signal is a low level signal.
  • the third transistor M3 in the pull-down control sub-circuit 123 is controlled by the second clock signal of low level, the third transistor M3
  • the voltage of the pull-up node PU is the low-level voltage of the previous stage
  • the fourth transistor M4 is turned off under the control of the low-level voltage of the pull-up node PU.
  • the third transistor M3 will not transmit the second clock signal to the pull-down node PD
  • the fourth transistor M4 will not transmit the voltage of the voltage terminal VGL to the pull-down node PD, at this time, the voltage of the pull-down node PD is unstable .
  • the second voltage regulator sub-circuit 128 controls the voltage of the pull-down node PD according to the voltage of the pull-down node PD and the voltage of the voltage terminal VGL.
  • the low-level voltage of VGL controls the voltage of the pull-down node PD to be a high-level voltage.
  • the fifth transistor M5 in the first noise reduction sub-circuit 124 is in an off state under the control of the reset signal of low level.
  • the second noise reduction sub-circuit 125 transmits the voltage of the voltage terminal VGL to the pull-up node PU in response to the voltage of the pull-down node PD.
  • the sixth transistor M6 in the second noise reduction sub-circuit 125 transmits the low-level voltage of the voltage terminal VGL to the pull-up node PU in response to the high-level voltage of the pull-down node PD.
  • the voltage of the pull-up node PU is a low-level voltage.
  • the second transistor M2 in the output sub-circuit 122 is turned off and does not output the first clock signal.
  • the third noise reduction sub-circuit 127 transmits the voltage of the voltage terminal VGL to the output terminal Oput in response to the voltage of the pull-down node PD.
  • the eighth transistor M8 in the third noise reduction sub-circuit 127 transmits the low-level voltage of the voltage terminal VGL to the output terminal Oput in response to the high-level voltage of the pull-down node PD, so that the output terminal Oput outputs a low-level voltage
  • the level signal that is, the drive signal is a low level signal.
  • the output terminal of each stage shift register is coupled to the reset signal terminal of the previous stage shift register.
  • the output terminal Oput of the shift register RS(2) of the second stage is coupled to the reset signal terminal Rst of the shift register of the previous stage, that is, the shift register RS(1) of the first stage. connected; the output terminal Oput of the third-stage shift register RS(3) is coupled to the reset signal terminal Rst of the upper-stage shift register, ie, the second-stage shift register RS(2).
  • the reset signal terminal of the last-stage shift register in the driving sub-circuit can be coupled to the reset signal line in the display panel, so as to reset the last-stage shift register.
  • the display panel 100 includes a plurality of data lines DL.
  • a plurality of data lines DL are disposed on the substrate 10 .
  • the extension direction of the plurality of data lines is parallel to the column direction of the sub-pixel arrangement, parallel to the column direction of the pixel island 21 arrangement, and parallel to the column direction of the display unit 20 arrangement; for example, referring to FIG.
  • the line extends in the Y direction. It will be appreciated that the data lines are configured to transmit data signals.
  • the sub-pixel P includes a pixel circuit 110 .
  • the pixel circuit 110 includes a data writing subcircuit 111 .
  • the data writing sub-circuit 111 is coupled to the gate circuit 40 and a data line DL.
  • the gating circuit 40 includes the gating sub-circuit 41
  • the data writing sub-circuit 111 in the pixel circuit 110 in each sub-pixel in one display unit 20 is coupled to one gating sub-circuit 41;
  • the gating sub-circuit 41 includes the switching sub-circuit 411
  • the data writing sub-circuit 111 in the pixel circuit 110 in a row of sub-pixels in one display unit 20 is coupled with one switching sub-circuit 411; in the switching sub-circuit
  • 411 includes a gate transistor MK
  • the second pole of the gate transistor MK is coupled to the data writing sub-circuit 111 .
  • the gating circuit 40 is coupled to the driving circuit 30 , and the gating circuit 40 can transmit the driving signal from the driving circuit 30 .
  • the data writing sub-circuit 111 is configured to write the data signal transmitted by the data line DL in response to a driving signal from the gate circuit 40 .
  • the gating circuit controls the data writing sub-circuit to form a conductive path with the driving circuit. Exemplarily, a column of sub-pixels in a column of display units is coupled to the same data line.
  • the pixel circuit includes a light-emitting driving sub-circuit 112, and the light-emitting driving sub-circuit 112 is coupled to the data writing sub-circuit 111 and the first power supply voltage terminal VDD.
  • the light-emitting driving sub-circuit 112 is configured to output driving current.
  • the light-emitting driving sub-circuit 112 is also coupled to the light-emitting device L, and the light-emitting driving sub-circuit 112 can transmit the driving circuit to the light-emitting device L to drive the light-emitting device L to emit light.
  • the light-emitting driving sub-circuit 112 includes a driving transistor MD and a storage capacitor Cst.
  • the data writing sub-circuit 111 includes a data writing transistor MA.
  • the control electrode of the data writing transistor MA is coupled to the gate circuit 40, the first electrode of the data writing transistor MA is coupled to the data line DL, the second electrode of the data writing transistor MA is coupled to the light-emitting driving sub-circuit 112,
  • the second electrode of the data writing transistor MA is coupled to the driving transistor MD in the light-emitting driving sub-circuit 112; for example, the second electrode of the data writing transistor MA is coupled to the control electrode of the driving transistor MD.
  • the switch sub-circuit 411 includes the gate transistor MK
  • the control electrode of the data writing transistor MA is coupled to the second electrode of the gate transistor MK.
  • the control electrode (gate) of the data writing transistor MA is used to receive the driving signal (ie, the gate driving signal). Under the control of the driving signal, the data writing transistor MA is turned on. At this time, the data A signal is written to the gate of the drive transistor MD through the transistor M1.
  • the first electrode of the driving transistor MD receives the first power supply voltage of the first power supply voltage terminal VDD.
  • the driving transistor MD When the voltage difference between the control electrode and the first electrode of the driving transistor MD meets the turn-on condition of the driving transistor MD, the driving transistor MD generates a driving and transmit the driving current to the light emitting device L to drive the light emitting device L to emit light.
  • one pole (eg, anode) of the light emitting device L receives the driving current from the pixel circuit, and the other pole (eg, cathode) of the light emitting device L is coupled to the second power supply voltage terminal VSS.
  • the first power supply voltage at the first power supply voltage terminal and the second power supply voltage at the second power supply voltage terminal are both DC voltages; for example, the first power supply voltage is a DC high voltage, and the second power supply voltage is a DC low voltage.
  • the transistors used in each circuit may be thin film transistors (Thin Film Transistor, TFT), field effect transistors (Field effect transistors, etc.) Effect Transistor, FET), Complementary Metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor, CMOS), or other switching devices with the same characteristics, which are not limited in the embodiments of the present disclosure.
  • TFT Thin Film Transistor
  • FET Field effect transistors
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • the control electrode of each transistor described herein is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure Diodes can be indistinguishable in structure. Exemplarily, when the transistor is a P-type transistor, the first electrode of the transistor is the source electrode, and the second electrode is the drain electrode; exemplarily, when the transistor is an N-type transistor, the first electrode of the transistor is the drain electrode, The second pole is the source pole.
  • each node described in the text does not represent an actual component, but represents a confluence of related electrical connections in the circuit diagram, that is, These nodes are nodes that are equivalent to the junctions of the relevant electrical connections in the circuit diagram.
  • each circuit described herein includes: a driving circuit, a driving sub-circuit in the driving circuit, a shift register in the driving sub-circuit, a gating circuit, and a gating in the gating circuit
  • the specific implementations of the sub-circuit, the switching sub-circuit in the gating sub-circuit, the pixel circuit, the data writing sub-circuit in the pixel circuit, and the light-emitting driving sub-circuit are not limited to the above-described modes, and can be any implementation used.
  • the method such as the conventional connection method well known to those skilled in the art, only needs to ensure that the corresponding functions are realized.
  • the above examples do not limit the scope of protection of the present disclosure. In practical applications, the skilled person can choose to use or not apply one or more of the above circuits according to the situation, and the various combinations and modifications of the above circuits do not depart from the principles of the present disclosure, and will not be repeated here.
  • the display panel 100 further includes: an optical film 50 .
  • the optical film 50 is disposed on the side of the plurality of display units 20 away from the substrate 10 , that is, along the direction perpendicular to the plane where the display panel 100 is located (eg, the Z direction in FIG. 18B ), the optical film 50 is compared with the plurality of display units. 20 is remote from the substrate 10 .
  • the optical film 50 is configured to refract light emitted from each sub-pixel P in each pixel island 21 in the display unit 20 in the display panel 100 to disperse to a plurality of pixel regions H (refer to FIG. 19 ).
  • a pixel area refers to an area where a pixel is located; the light emitted by the pixel is composed of light emitted by sub-pixels with different colors, and the sub-pixels with different colors come from different pixel islands.
  • the red light emitted by the red sub-pixels in the display unit is refracted by the optical film to disperse into multiple pixel areas; the green light emitted by the green sub-pixels in the display unit is refracted through the optical film to disperse into multiple pixel areas; the display unit The blue light emitted by the blue sub-pixels is refracted by the optical film to disperse to multiple pixel areas.
  • the size of the pixel area is the same as the size of the sub-pixels, which can increase the design space of the circuit for driving the sub-pixels to emit light, and can also conveniently improve the PPI of the display panel.
  • light of different colors emitted by sub-pixels of different colors is refracted by the optical film, then arranged at intervals in a direction parallel to the plane of the display panel and converged to the same pixel area to realize grayscale display.
  • the size of the pixel area is approximately n times the size of the sub-pixels, and n represents the number of sub-pixels that converge to the same pixel area.
  • the optical film includes a microlens film.
  • the light emitted by each sub-pixel in the display unit is refracted by the microlens film and dispersed to a plurality of pixel areas.
  • the microlens film includes a plurality of microlenses arranged in sequence, for example, one microlens corresponds to one sub-pixel position, or, for example, one microlens corresponds to one pixel island position, the microlens can Light emitted by the pixels is refracted to a plurality of pixel regions.
  • the optical film can be designed according to the actual situation, so that the light refracted by the optical film is dispersed to a plurality of designated pixel areas.
  • a plurality of pixel regions H are included in the to-be-displayed region T; for example, the to-be-displayed region may be an area where a user views a display device (or a display panel).
  • the display device further includes a processing device 210 .
  • the processing device 210 is coupled to the display panel 100 .
  • the processing device includes a timing controller (Timing Controller, TCON).
  • the processing device is configured to output at least one control signal to the gating circuit in the display panel according to the information of the to-be-displayed area of the display panel to control the drive circuit in the display panel and at least one display corresponding to the to-be-displayed area in the display panel
  • the unit is turned on; and, according to the information of the to-be-displayed area of the display panel, output at least one input signal to the drive circuit in the display panel, so that the drive circuit outputs at least one input signal to at least one display unit corresponding to the to-be-displayed area in the display panel A drive signal to display the area to be displayed.
  • the at least one display unit is at least one display unit corresponding to the area to be displayed.
  • the processing device outputs at least one control signal to the gating circuit according to the information of the area to be displayed on the display panel, and the control signal received by the gating circuit (for example, the gating sub-circuit in the gating circuit) controls the At least one display unit corresponding to the to-be-displayed area and the driving circuit are turned on, so that the at least one display unit corresponding to the to-be-displayed area can receive the driving signal from the driving circuit.
  • the control signal received by the gating circuit for example, the gating sub-circuit in the gating circuit
  • the processing device outputs at least one input signal to the drive circuit according to the information of the area to be displayed on the display panel, so that the drive circuit (for example, a drive sub-circuit in the drive circuit) that conducts at least one display unit corresponding to the area to be displayed is turned on.
  • An input signal is received, and at least one driving signal is output.
  • at least one display unit corresponding to the area to be displayed can receive the drive signal, so that the at least one display unit that receives the drive signal performs display, so that the area to be displayed can be displayed.
  • the display panel realizes partition driving and partition display, which saves the power consumption of the display device.
  • the display device 200 further includes an information collection device 220 .
  • the information collection device 220 is coupled to the processing device 210 .
  • the information collection device is configured to collect user sight line information.
  • the processing device is further configured to acquire the user's sight line information, and determine the information of the to-be-displayed area of the display panel according to the user's sight line information.
  • the information collection device may use any device with a sight line collection function, such as a camera, an eye tracker, and the like.
  • the information collection device collects the user's line of sight information, and sends the user's line of sight information to the processing device.
  • the processing device acquires the user's sight line information, and determines the information of the to-be-displayed area of the display panel according to the user's sight line information.
  • the information of the area to be displayed includes the position and size of the area to be displayed.
  • at least one display unit corresponding to the to-be-displayed area can be obtained.
  • the information of the area to be displayed can be obtained, the display unit corresponding to the area to be displayed can be determined, and the display unit can be driven to display the area to be displayed.
  • the display area of the display device is adjusted so that the display device is in a partial display state or a full-screen display state, so that the power consumption of the display device can be reduced while meeting the user's usage requirements.
  • the display device further includes a driver chip.
  • the driver chip is a driver IC, for example, the driver IC includes a source driver.
  • the driving chip is configured to provide driving signals to the respective sub-pixels in the display panel; for example, the driving signals include data signals.
  • Embodiments of the present disclosure provide a driving method of a display panel.
  • the display panel is the display panel in any of the above embodiments.
  • the driving method includes:
  • At least one input signal is output to the drive circuit in the display panel, so that the drive circuit responds to the at least one input signal and outputs at least one drive signal to at least one display unit corresponding to the area to be displayed .
  • the driving sub-circuit receives the input signal and outputs the driving signal.
  • the driving sub-circuit includes a shift register
  • the shift register outputs the driving signal.
  • input signals are output to the driving sub-circuits in the driving circuits coupled to the display unit corresponding to the area to be displayed, and no input signals are output to the driving sub-circuits coupled to the remaining display units to reduce power consumption.
  • At least one control signal is output to the gating circuit in the display panel, so that the gating circuit controls the driving circuit corresponding to the area to be displayed among the plurality of display units according to the at least one control signal
  • the at least one display unit is turned on, so that the at least one display unit receives at least one driving signal from the driving circuit, and drives the at least one display unit corresponding to the area to be displayed to display.
  • the gating circuit includes a plurality of gating sub-circuits
  • at least one gating sub-circuit receives at least one control signal to conduct at least one display unit with the driving circuit.
  • the switching sub-circuit in the gating sub-circuit receives a control signal to conduct each row of sub-pixels in the display unit with the driving circuit.
  • the control signal is output to the gating sub-circuit in the gating circuit coupled to the display unit corresponding to the area to be displayed, and the control signal is not output to the gating sub-circuits coupled to the remaining display units, so as to reduce the output of the control signal. power consumption.
  • the display panel at least one display unit corresponding to the area to be displayed is displayed, and the rest of the display units are not displayed, so that the area to be displayed is in a display state, and the rest of the area is in a non-display state, that is, some areas of the display panel are displayed , some areas are not displayed, the partition control of the display unit is realized, and the power consumption of the display panel is reduced.
  • the driving method further includes: acquiring user sight line information; and determining information about a to-be-displayed area of the display panel according to the user sight line information. In this way, the display of the display panel can meet the actual viewing situation of the user, and the user experience effect can be improved.

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Abstract

一种显示面板（100）及其驱动方法、显示装置（200），其中，显示面板（100），具有显示区（AA），包括：衬底（10）、多个显示单元（20）、驱动电路（30）和选通电路（40）。多个显示单元（20）在衬底（10）上且在显示区（AA）内。驱动电路（30）在衬底（10）上且在显示区（AA）外。选通电路（40）在衬底（10）上且在显示区（AA）内及多个显示单元（20）的外侧。每个显示单元（20）包括多个像素岛（21），每个像素岛（21）包括多个颜色相同的子像素（P）。驱动电路（30）被配置为输出多个驱动信号。选通电路（40）与驱动电路（30）耦接，还与至少一个显示单元（20）耦接。选通电路（40）被配置为控制驱动电路（30）与至少一个显示单元（20）导通，以使至少一个显示单元（20）根据来自驱动电路（30）的至少一个驱动信号，驱动至少一个显示单元（20）中的多个像素岛（21）中的多个子像素（P）显示。

Description

显示面板及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其驱动方法、显示装置。
背景技术
自发光器件具有亮度高、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高等优点，而广泛应用于各种具有高分辨率彩色屏幕的终端显示产品。
发明内容
一方面，提供一种显示面板。所述显示面板具有显示区。所述显示面板包括衬底、多个显示单元、驱动电路和选通电路。所述多个显示单元设置于所述衬底上且位于所述显示区内。所述驱动电路设置于所述衬底上且位于所述显示区外。所述选通电路设置于所述衬底上，及位于所述显示区内且位于所述多个显示单元的外侧。每个显示单元包括多个像素岛，每个像素岛包括多个颜色相同的子像素。所述驱动电路被配置为输出多个驱动信号。所述选通电路与所述驱动电路耦接，所述选通电路还与至少一个显示单元耦接。所述选通电路被配置为控制所述驱动电路与所述至少一个显示单元导通，以使所述至少一个显示单元根据来自所述驱动电路的至少一个驱动信号，驱动所述至少一个显示单元中的多个像素岛中的多个子像素显示。
在一些实施例中，所述显示面板还包括多条控制信号线。所述多条驱动信号线设置于所述衬底上。所述驱动电路包括：多个驱动信号输出端。所述多个驱动信号输出端被配置为输出所述多个驱动信号。所述选通电路包括：多个选通子电路。一个选通子电路与至少一条控制信号线、一个显示单元和至少一个驱动信号输出端耦接。所述选通子电路被配置为响应于所述至少一条控制信号线传输的控制信号，将在所述至少一个驱动信号输出端处接收的至少一个驱动信号传输至所述显示单元中的各像素岛中的多个子像素。
在一些实施例中，所述显示单元包括至少一行子像素。所述选通子电路包括：至少一个开关子电路。一个开关子电路与一条控制信号线、一个驱动信号输出端和所述显示单元中的一行子像素耦接。所述开关子电路被配置为响应于所述控制信号线传输的控制信号，将在所述驱动信号输出端处接收的驱动信号传输至所述开关子电路所耦接的一行子像素。
在一些实施例中，所述多个显示单元呈阵列排布。在一行显示单元中的 各个显示单元中，相同行的子像素各自所耦接的开关子电路与同一个驱动信号输出端耦接。
在一些实施例中，所述选通子电路中的至少一个开关子电路与同一条控制信号线耦接。
在一些实施例中，所述开关子电路包括：选通晶体管。所述选通晶体管的控制极与所述控制信号线耦接，所述选通晶体管的第一极与所述驱动信号输出端耦接，所述选通晶体管的第二极与所述显示单元中的一行子像素耦接。
在一些实施例中，不同的选通子电路耦接的控制信号线不同。
在一些实施例中，所述显示面板还包括：多条输入信号线。所述多条输入信号线设置于所述衬底上。所述驱动电路包括：多个驱动子电路。每个驱动子电路与一条输入信号线耦接，所述驱动子电路包括多个驱动信号输出端。所述驱动子电路被配置为根据所述输入信号线传输的输入信号，从所述驱动子电路的多个驱动信号输出端输出多个驱动信号。
在一些实施例中，所述驱动子电路包括多个级联的移位寄存器。每一级移位寄存器的输出端为一个驱动信号输出端。第一级移位寄存器的输入端与一条输入信号线耦接；除最后一级移位寄存器之外的每一级移位寄存器的输出端与其下一级移位寄存器的输入端耦接。
在一些实施例中，所述显示面板还包括：多条数据线。所述多条数据线设置于所述衬底上。所述子像素包括像素电路。所述像素电路包括数据写入子电路；所述数据写入子电路与所述选通电路和一条数据线耦接。所述数据写入子电路被配置为响应于来自所述选通电路的一个驱动信号，写入所述数据线传输的数据信号。
在一些实施例中，所述子像素包括发光器件。所述发光器件包括发光层；一个像素岛中的多个子像素中的发光器件的发光层无间隙。
在一些实施例中，所述显示面板还包括光学膜。所述光学膜设置于所述多个显示单元远离所述衬底的一侧。所述光学膜被配置为将所述显示面板中的显示单元中的各像素岛中各子像素发出的光折射，以分散至多个像素区域。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
在一些实施例中，所述显示装置还包括处理装置。所述处理装置被配置为根据所述显示面板的待显示区域的信息，向所述显示面板中的选通电路输出至少一个控制信号，以控制所述显示面板中的驱动电路和所述显示面板中与所述待显示区域对应的至少一个显示单元导通；及，根据所述显示面板的 待显示区域的信息，向所述显示面板中的驱动电路输出至少一个输入信号，以使所述驱动电路向与所述待显示区域对应的至少一个显示单元输出至少一个驱动信号。
在一些实施例中，所述显示装置还包括信息采集装置。所述信息采集装置被配置为采集用户视线信息。所述处理装置还被配置为获取所述用户视线信息，根据所述用户视线信息，确定所述显示面板的待显示区域的信息。
又一方面，提供一种如上述任一实施例所述的显示面板的驱动方法。所述驱动方法包括：根据所述显示面板的待显示区域的信息，向所述显示面板中的驱动电路输出至少一个输入信号，以使所述驱动电路响应于所述至少一个输入信号，向与所述待显示区域对应的至少一个显示单元输出至少一个驱动信号；根据所述显示面板的待显示区域的信息，向所述显示面板中的选通电路输出至少一个控制信号，以使所述选通电路根据所述至少一个控制信号，控制所述驱动电路与多个显示单元中的与所述待显示区域对应的至少一个显示单元导通，使所述至少一个显示单元接收来自所述驱动电路的至少一个驱动信号，驱动与所述待显示区域对应的至少一个显示单元显示。
在一些实施例中，所述驱动方法还包括：获取用户视线信息；根据所述用户视线信息，确定所述显示面板的待显示区域的信息。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的一种结构图；
图2为根据一些实施例的显示面板的一种结构图；
图3为根据一些实施例的子像素的一种结构图；
图4为根据一些实施例的发光器件的一种结构图；
图5为根据一些实施例的显示面板的另一种结构图；
图6为根据一些实施例的显示面板的又一种结构图；
图7为根据一些实施例的显示面板的又一种结构图；
图8为根据一些实施例的显示面板的又一种结构图；
图9为根据一些实施例的显示面板的又一种结构图；
图10A为根据一些实施例的显示面板的又一种结构图；
图10B为根据一些实施例的驱动子电路的一种结构图；
图11为根据一些实施例的移位寄存器的一种结构图；
图12为根据一些实施例的移位寄存器的另一种结构图；
图13为根据一些实施例的移位寄存器的一种驱动时序图；
图14为根据一些实施例的显示面板的又一种结构图；
图15为根据一些实施例的显示面板的又一种结构图；
图16为根据一些实施例的显示面板的又一种结构图；
图17为根据一些实施例的显示面板的又一种结构图；
图18A为根据一些实施例的显示面板的又一种结构图；
图18B为图18A中的显示面板沿A-B方向的一种剖视图；
图19为根据一些实施例的光学膜的一种光学示意图；
图20为根据一些实施例的显示装置的另一种结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。 例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供一种显示装置。示例性地，该显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。本公开的实施例对上述显示装置的具体形式不做特殊限制。示例性地，显示装置可以是微型显示装置；例如微型显示装置可以包括头戴式显示装置；例如头戴式显示装置可以包括VR(Virtual Reality，虚拟现实)显示装置或AR(Augmented Reality，增强现实)显示装置等。
在一些实施例中，如图1所示，显示装置200包括显示面板100。如图2所示，显示面板100具有显示区(Active Area，AA)和周边区S。其中，周边区S至少位于AA区外一侧。
在一些实施例中，显示面板包括位于AA区中的多个子像素。如图3所示，至少一个子像素P(例如，每个子像素P)包括像素电路110和发光器件L。其中，像素电路110与发光器件L耦接。像素电路110被配置为驱动发光器件L发光。示例性地，像素电路呈阵列排布。
需要说明的是，本公开的实施例对像素电路的具体结构不作限定，可以根据实际情况进行设计。示例性地，像素电路由晶体管(例如薄膜晶体管(Thin Film Transistor，TFT))、电容器(Capacitance，简称C)等电子器件组成。例如，像素电路可以包括两个晶体管和一个电容器，构成2T1C结构；当然，像素电路还可以包括两个以上的晶体管和至少一个电容器，例如七个晶体管和一个电容器，构成7T1C结构。
示例性地，发光器件可以采用包括LED(发光二极管，Light Emitting Diode)、OLED(有机电致发光二极管，Organic Light Emitting Diode)或者量子点发光二极管(Quantum Light Emitting Diode，QLED)等电流驱动型发光器件。例如，如图4所示，发光器件L包括阴极1202和阳极1201，以及位于阴极1202和阳极1201之间的发光功能层1203。其中，发光功能层1203例如可以包括发光层E、位于发光层E和阳极1201之间的空穴传输层(Hole Transporting Layer，HTL)、位于发光层E和阴极1202之间的电子传输层(Election Transporting Layer，ETL)。当然，根据需要在一些实施例中，还可以在空穴传输层HTL和阳极之间设置空穴注入层(Hole Injection Layer，HIL)，可以在电子传输层ETL和阴极1202之间设置电子注入层(Election Injection Layer，EIL)。
示例性地，阳极例如可由具有高功函数的透明导电材料形成，其电极材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In 2O 3)、氧化铝锌(AZO)和碳纳米管等；阴极例如可由高导电性和低功函数的材料形成，其电极材料可以包括镁铝合金(MgAl)和锂铝合金(LiAl)等合金或者镁(Mg)、铝(Al)、锂(Li)和银(Ag)等金属单质。发光层的材料可以根据其发射光颜色的不同进行选择。例如，发光层的材料包括荧光发光材料或磷光发光材料。例如，在本公开至少一个实施例中，发光层可以采用掺杂体系，即在主体发光材料中混入掺杂材料来得到可用的发光材料。例如，主体发光材料可以采用金属化合物材料、蒽的衍生物、芳香族二胺类化合物、三苯胺化合物、芳香族三胺类化合物、联苯二胺衍生物和三芳胺聚合物等。
本公开的实施例提供一种显示面板。如图2所示，显示面板100包括衬 底10、多个显示单元20、驱动电路30和选通电路40。多个显示单元20、驱动电路30和选通电路40均设置于衬底10上。
示例性地，衬底10可以包括：玻璃等刚性衬底(或称为硬质衬底)，或者PI(Polyimide，聚酰亚胺)等柔性衬底；还可以包括：设置在刚性衬底或柔性衬底上的缓冲层等薄膜。示例性地，衬底10可以是硅基衬底。
其中，如图5所示，每个显示单元20包括多个像素岛21。每个像素岛21包括多个颜色相同的子像素P。例如，显示单元20中的多个像素岛21的颜色各不相同。可以理解的是，多个显示单元20位于AA区中。
示例性地，多个像素岛可以呈阵列排布；例如，沿图5中X方向(水平方向)排列成一排的像素岛21称为同一行像素岛，沿图5中Y方向(竖直方向)排列成一排的像素岛21称为同一列像素岛。示例性地，多个子像素可以呈阵列排布。例如，沿图5中X方向排列成一排的子像素P称为同一行子像素，沿图5中Y方向排列成一排的子像素P称为同一列子像素。
需要说明的是，可以根据实际情况，例如根据用户视线范围映射在显示面板上的区域的大小，设计像素岛中子像素的数量，例如，一个像素岛中的多个子像素呈3行3列阵列排布(如图5所示)，或者，一个像素岛中的多个子像素呈5行5列阵列排布，具体在此不作限定。
示例性地，多个子像素包括第一颜色子像素、第二颜色子像素和第三颜色子像素；相应地，多个像素岛包括第一颜色像素岛、第二颜色像素岛和第三颜色像素岛。例如，第一颜色、第二颜色和第三颜色为三基色；例如，第一颜色、第二颜色和第三颜色分别为红色、绿色和蓝色；即，多个子像素包括红色子像素、绿色子像素和蓝色子像素；多个像素岛包括红色像素岛、绿色像素岛和蓝色像素岛。示例性地，一个显示单元包括一个红色像素岛、一个绿色像素岛和一个蓝色像素岛。
在一些实施例中，子像素包括发光器件，发光器件包括发光层。一个像素岛中的多个子像素中的发光器件的发光层无间隙。例如，一个像素岛中的多个子像素中的发光器件的发光层连为一体结构。
示例性地，像素岛中的多个子像素中的发光器件的发光层连接为一体结构。例如，在工艺上形成发光层的过程中，掩膜板(例如FMM(Fine Metal Mask，精细金属掩膜版))的每个开孔可以对应一个像素岛中的所有发光器件的发光层，即，像素岛中的发光层经掩膜板的同一开孔共同蒸镀而成；也就是说，像素岛中各发光器件中的发光层可以经掩膜板的同一开孔共同蒸镀而成。
对于高像素密度(Pixels Per Inch，PPI)的显示面板，相邻子像素的间隔 距离较小，在工艺通过掩膜板蒸镀形成发光层的过程中，每个子像素中的发光器件的发光层经过掩膜板的一个开孔蒸镀形成，导致对掩膜板的要求相对较高，受掩膜板的限制，制备过程难度较大。在此情况下，本公开的实施例可以将多个子像素中的发光器件的发光层经过掩膜板的同一开孔蒸镀形成，对掩膜板的要求相对较低，可以通过制备低PPI(例如400PPI)显示面板中的发光层的掩膜板制作出高PPI(例如1000PPI～10000PPI)显示面板中的发光层，这样，可通过每英寸开孔数目较少的掩膜板可制作出每英寸像素数目较多的显示面板。这样，可以在实现高PPI显示面板的同时，还可以降低掩膜板的制备难度及蒸镀工艺难度。
示例性地，各像素岛尺寸相同，且各像素岛中子像素的数量及尺寸也相同。示例性地，像素岛的尺寸与其所包含的子像素的尺寸有关；例如，像素岛的尺寸近似等于n个子像素的尺寸，n为像素岛中的子像素的数量。
其中，驱动电路30位于AA区外，即，驱动电路30位于周边区S。选通电路40位于AA区内，且选通电路40位于多个显示单元20的外侧。选通电路40与驱动电路30耦接，选通电路40还与至少一个显示单元20耦接。驱动电路30被配置为输出多个驱动信号。示例性地，驱动信号可以为栅极驱动信号。
选通电路40被配置为控制驱动电路30与至少一个显示单元20导通，以使至少一个显示单元20根据来自驱动电路30的至少一个驱动信号，驱动至少一个显示单元20中的多个像素岛21中的多个子像素P显示。
可以理解的是，选通电路40控制多个显示单元20中的至少一个显示单元20与驱动电路30导通，驱动电路30向与其导通的至少一个显示单元20传输至少一个驱动信号，使得显示单元20中的多个像素岛21中的多个子像素P接收驱动信号，即，多个子像素P中的像素电路110根据接收到的驱动信号，生成驱动电流，驱动发光器件L发光，使得多个显示单元20中的至少一个显示单元20进行显示。在此情况下，显示面板中的多个显示单元中的部分显示单元(一个或者多个显示单元)进行显示，其余显示单元不进行显示，即，显示面板中的局部区域进行显示，其余区域不进行显示。这样，通过选通电路，可以单独控制每个显示单元与驱动电路的导通状态，单独控制显示面板中的每个显示单元处于显示状态或者非显示状态，实现对多个显示单元独立驱动，实现对多个显示单元的显示的独立控制。因此，相比于显示面板中的所有子像素均与驱动电路连接，即所有子像素全部被驱动，使得显示面板只能进行全屏显示的情况，本公开的实施例提供的显示面板可以实现分区 显示，从而降低了显示功耗。
示例性地，显示面板(或显示屏)可以根据多个显示单元划分为多个子显示屏，一个显示单元对应于一个子显示屏，显示单元的显示区域对应于子显示屏的显示区域，这样，在多个显示单元中的部分显示单元进行显示的情况下，显示面板中的部分子显示屏进行显示，其余子显示屏不显示，实现分屏显示；在多个显示单元全部进行显示的情况下，显示面板中的所有子显示屏进行显示，实现全屏显示。
因此，本公开的实施例提供一种显示面板，显示面板中的选通电路控制驱动电路与至少一个显示单元导通，以使至少一个显示单元根据来自驱动电路的至少一个驱动信号，驱动至少一个显示单元中的多个像素岛中的多个子像素显示。在此情况下，通过选通电路，可以单独控制每个显示单元与驱动电路的导通状态，单独控制显示面板中的每个显示单元处于显示状态或者非显示状态，实现对多个显示单元独立驱动，实现对多个显示单元的显示的独立控制。因此，相比于只能进行全屏显示的显示面板，本公开的实施例提供的显示面板可以实现分区显示，从而降低了显示功耗。
在一些实施例中，如图6所示，显示面板100还包括多条控制信号线CL。多条控制信号线CL设置于衬底10上。可以理解的是，控制信号线被配置为传输控制信号；例如，一条控制信号线可以传输一个控制信号。如图6所示，驱动电路30包括多个驱动信号输出端OUT。多个驱动信号输出端OUT被配置为输出多个驱动信号。选通电路40包括多个选通子电路41。一个选通子电路41与至少一条控制信号线CL、一个显示单元20和至少一个驱动信号输出端OUT耦接。示例性地，选通子电路的数量与显示单元的数量相同。
需要说明的是，可以根据实际情况，设计选通子电路的位置，在此不做限定。例如，选通子电路可以位于周边区；例如，选通子电路可以位于其所耦接的显示单元以外的区域；例如，选通子电路位于相邻两个显示单元之间的区域。
选通子电路被配置为响应于至少一条控制信号线传输的控制信号，将在至少一个驱动信号输出端处接收的至少一个驱动信号传输至显示单元中的各像素岛中的多个子像素。可以理解的是，在控制信号的控制下，选通子电路开启，将其所耦接的显示单元与驱动电路导通，使得驱动电路输出的驱动信号可以传输至显示单元，显示单元中各像素岛中的多个子像素在驱动信号的控制下进行显示，即，多个子像素中的像素电路在驱动信号的控制下，向发光器件提供驱动电流，驱动发光器件发光。在此情况下，通过控制选通子电 路的开启或关断，可以控制显示单元与驱动电路的导通或不导通，与驱动电路导通的显示单元显示，与驱动电路不导通的显示单元不显示，使得显示面板实现分区显示，从而可以降低显示面板的功耗。
在一些实施例中，显示单元包括至少一行子像素。例如，参考图5，显示单元20包括沿行方向(例如图5中X方向)依次排列的三个像素岛，三个像素岛分别包括红色子像素、绿色子像素和蓝色子像素。显示单元中的一行子像素包括一个像素岛中的一行红色子像素、一个像素岛中一行绿色子像素和一个像素岛中一行蓝色子像素，该一行红色子像素、一行绿色子像素和一行蓝色子像素包含于同一行子像素中。
如图7所示，选通子电路41包括至少一个开关子电路411。一个开关子电路411与一条控制信号线CL、一个驱动信号输出端OUT和显示单元20中的一行子像素耦接。示例性地，开关子电路的数量与显示单元中所包含的子像素的行数相同；例如，在显示单元20包含两行子像素P的情况下，参考图7，该显示单元20耦接的选通子电路41包括两个开关子电路411；例如，在显示单元包含三行子像素的情况下，该显示单元耦接的选通子电路包括三个开关子电路。
开关子电路被配置为响应于控制信号线传输的控制信号，将在驱动信号输出端处接收的驱动信号传输至开关子电路所耦接的一行子像素。可以理解的是，在控制信号的控制下，开关子电路开启，将一行子电路与驱动电路的一个驱动信号输出端导通，使得一行子像素接收来自该驱动信号输出端的驱动信号，一行子像素中的像素电路在驱动信号的控制下，驱动发光器件发光，使得一行子像素实现显示。在显示单元中的每行子像素所耦接的开关子电路开启的情况下，显示单元中的每行子像素均可以接收驱动信号，使得显示单元中各像素岛中的子像素均实现显示。示例性地，显示单元中的多行子像素可以是逐行驱动，逐行显示。
示例性地，如图8所示，开关子电路411包括选通晶体管MK。开关晶体管MK的控制极与控制信号线CL耦接，选通晶体管MK的第一极与驱动信号输出端OUT耦接，选通晶体管MK的第二极与显示单元20中的一行子像素P耦接。可以理解的是，选通晶体管MK响应于控制信号线CL传输的控制信号，选通晶体管MK导通，将在驱动信号输出端OUT处接收的驱动信号传输至一行子像素P，以驱动一行子像素P进行显示。
示例性地，多个显示单元呈阵列排布。在一行显示单元中的各个显示单元中，相同行的子像素各自所耦接的开关子电路与同一个驱动信号输出端耦 接。
需要说明的是，一行显示单元中，每个像素岛中的行数相同的子像素为相同行的子像素。例如，一行显示单元中，各个显示单元中的每个像素岛中的第i行子像素为相同行的子像素，且为显示单元中的第i行子像素，i为正整数。
可以理解的是，驱动电路向显示单元逐行输出驱动信号，通过控制开关子电路的开启或关断，使得每行显示单元中与驱动电路导通的显示单元进行显示，可以控制每行显示单元中的至少一列显示单元进行显示，实现对显示单元的分区驱动。
示例性地，选通子电路中的至少一个开关子电路与同一条控制信号线耦接。在此情况下，可以简化显示面板的布线设计。示例性地，选通子电路中的至少一个开关子电路接收相同的控制信号，选通子电路中的至少一个开关子电路可以同时开启或关断。
在一些实施例中，不同的选通子电路耦接的控制信号线不同。在此情况下，不同的选通子电路接收不同的控制信号，使得显示单元与驱动电路在不同时刻导通，控制显示面板实现分区显示。
在一些实施例中，如图9所示，显示面板100还包括多条输入信号线STV。多条输入信号线STV设置于衬底10上。其中，输入信号线被配置为传输输入信号。
如图9所示，驱动电路30包括多个驱动子电路31。每个驱动子电路31与一条输入信号线STV耦接。驱动子电路31包括多个驱动信号输出端OUT。驱动子电路31被配置为根据输入信号线STV传输的输入信号，从驱动子电路31的多个驱动信号输出端OUT输出多个驱动信号。可以理解的是，根据不同的输入信号，可以控制不同的驱动子电路输出驱动信号，以控制不同的显示单元进行显示。
示例性地，每个驱动子电路可以向一行显示单元提供驱动信号。在一行显示单元不进行显示的情况下，即，该一行显示单元中的每个显示单元所耦接的选通子电路处于关断状态，也即，该一行显示单元中的每个显示单元与驱动子电路不导通，此时，该给该一行显示单元提供驱动信号的驱动子电路可以不工作，不工作的驱动子电路所耦接的输入信号线上无输入信号传输。在此情况下，给需要进行待显示的显示单元提供驱动信号的驱动子电路所耦接的输入信号线上有输入信号传输，这些驱动子电路工作，其他驱动子电路可以不工作，这样可以减少显示面板的功耗。
示例性地，在显示面板处于全屏显示状态下，显示面板中的各个子像素可以采用逐行依次驱动；在显示面板进行局部显示状态下，显示面板中的各个子像素可以按照逐行依次驱动的顺序，驱动待显示的显示单元中的各个子像素。
示例性地，沿子像素排列的行方向上，在AA区的相对两外侧中的一侧可以设置一个驱动电路30，显示面板100通过驱动电路30，从单侧输出驱动信号，这样，可以减小周边区S的面积，简化显示面板100的电路设计。示例性地，沿子像素排列的行方向上，在AA区的相对两外侧可以分别设置两个驱动电路30，在此情况下，显示面板100可以采用双侧同时驱动，两个驱动电路30，同时从两侧输出驱动信号，这样可以降低驱动信号在传输过程中产生的压降，从而提高显示的均匀性；或者，显示面板100可以采用双侧交叉驱动，通过两个驱动电路30，交替从两侧输出驱动信号。
在一些实施例中，如图10A和图10B所示，驱动子电路31包括多个级联的移位寄存器RS(例如图10B中的第一级移位寄存器RS(1)、第二级移位寄存器RS(2)、第三级移位寄存器RS(3)……)。每一级移位寄存器的输出端Oput为一个驱动信号输出端OUT。可以理解的是，每一级移位寄存器RS的输出端Oput被配置为输出驱动信号。
其中，第一级移位寄存器的输入端与一条输入信号线耦接。除最后一级移位寄存器之外的每一级移位寄存器的输出端与其下一级移位寄存器的输入端耦接。例如，参考图10B，第一级移位寄存器RS(1)的输入端IN与输入信号线STV耦接；第一级移位寄存器RS(1)的输出端Oput与第二级移位寄存器RS(2)的输入端IN耦接；第二级移位寄存器RS(2)的输出端Oput与第三级移位寄存器RS(3)的输入端IN耦接，以此类推，直至最后一级移位寄存器的输入端与该最后一级移位寄存器的前一级移位寄存器的输出端耦接。
可以理解的是，移位寄存器的数量与显示单元中子像素的行数相同。每个驱动子电路中的每个移位寄存器向该驱动子电路所耦接的显示单元中的一行子像素输出驱动信号。例如，参考图10A，在显示单元20中的多个子像素P呈三行子像素的情况下，驱动子电路31包括依次级联的三个移位寄存器RS(1)、RS(2)和RS(3)。
需要说明的是，图6、图7、图8、图9和图10A仅示出了像素岛与各个电路连接的示意图，实际的电路连接情况不限于此，可以根据实际情况进行设计，在此不作限定。
示例性地，相邻的两个级联的移位寄存器的第一时钟信号端分别耦接不 同的时钟信号线，第二时钟信号端分别耦接不同的时钟信号线。例如，参考图10B，奇数级移位寄存器中的第一时钟信号端CLK1与第一时钟信号线CLKA耦接，奇数级移位寄存器中的第二时钟信号端CLK2与第二时钟信号线CLKB耦接；偶数级移位寄存器中的第一时钟信号端CLK1与第二时钟信号线CLKB耦接，偶数级移位寄存器中的第二时钟信号端CLK2与第一时钟信号线CLKA耦接。其中，第一时钟信号线CLKA传输的信号与第二时钟信号线CLKB传输的信号具有一定的相位差；例如，第一时钟信号线CLKA传输的信号与第二时钟信号线CLKB传输的信号互为反转信号。
示例性地，如图11所示，移位寄存器RS包括输入子电路121和输出子电路122。输入子电路121与输入信号端IN和上拉节点PU耦接。输出子电路122与上拉节点PU、第一时钟信号端CLK1和输出端Oput耦接。输入子电路121被配置为响应于在输入信号端IN处接收的输入信号，将输入信号传输至上拉节点PU。输出子电路122被配置为响应于上拉节点PU的电压，将在第一时钟信号端CLK1处接收的第一时钟信号传输至输出端Oput。可以理解的是，输出端Oput输出的信号为驱动信号。
例如，如图12所示，输入子电路121包括第一晶体管M1。第一晶体管M1的控制极和第一极分别与输入信号端IN耦接，第一晶体管M1的第二极与上拉节点PU耦接。例如，如图12所示，输出子电路122包括第二晶体管M2和第一电容器C1。第二晶体管M2的控制极与上拉节点PU耦接，第二晶体管M2的第一极与第一时钟信号端CLK1耦接，第二晶体管M2的第二极与输出端Oput耦接。第一电容器C1的第一极与上拉节点PU耦接，第一电容器C2的第二极与输出端Oput耦接。
示例性地，如图11所示，移位寄存器RS还包括下拉控制子电路123。下拉控制子电路123与第二时钟信号端CLK2、上拉节点PU、下拉节点PD和电压端VGL耦接。下拉控制子电路123被配置为响应于在第二时钟信号端CLK2处接收的第二时钟信号，将第二时钟信号传输至下拉节点PD；及，响应于上拉节点PU的电压，将电压端VGL的电压传输至下拉节点PD。示例性地，电压端VGL被配置为传输直流低电平信号。
例如，如图12所示，下拉控制子电路123包括第三晶体管M3和第四晶体管M4。第三晶体管M3的控制极和第一极分别与第二时钟信号端CLK2耦接，第三晶体管M3的第二极与下拉节点PD耦接。第四晶体管M4的控制极与上拉节点PU耦接，第四晶体管M4的第一极与电压端VGL耦接，第四晶体管M4的第二极与下拉节点PD耦接。
示例性地，如图11所示，移位寄存器RS还包括第一降噪子电路124。第一降噪子电路124与电压端VGL、复位信号端Rst和上拉节点PU耦接。第一降噪子电路124被配置为响应于在复位信号端Rst处接收的复位信号，将电压端VGL的电压传输至上拉节点PU。这样，可以在移位寄存器的非有效输出阶段，对上拉节点进行降噪，避免信号干扰。
例如，如图12所示，第一降噪子电路124包括第五晶体管M5。第五晶体管M5的控制极与复位信号端Rst耦接，第五晶体管M5的第一极与电压端VGL耦接，第五晶体管M5的第二极与上拉节点PU耦接。
示例性地，如图11所示，移位寄存器RS还包括第二降噪子电路125。第二降噪子电路125与下拉节点PD、电压端VGL和上拉节点PU耦接。第二降噪子电路125被配置为响应于下拉节点PD的电压，将电压端VGL的电压传输至上拉节点PU。这样，可以在移位寄存器的非有效输出阶段，对上拉节点进行降噪，避免信号干扰。
例如，如图12所示，第二降噪子电路125包括第六晶体管M6。第六晶体管M6的控制极与下拉节点PD耦接，第六晶体管M6的第一极与电压端VGL耦接，第六晶体管M6的第二极与上拉节点PU耦接。
示例性地，如图11所示，移位寄存器RS还包括第三降噪子电路126。第三降噪子电路126与下拉节点PD、电压端VGL和输出端Oput耦接。第三降噪子电路被126配置为响应于下拉节点PD的电压，将电压端VGL的电压传输至输出端Oput。这样，可以在移位寄存器的非有效输出阶段，对输出端进行降噪，避免信号干扰。
例如，如图12所示，第三降噪子电路126包括第七晶体管M7。第七晶体管M7的控制极与下拉节点PD耦接，第七晶体管M7的第一极与电压端VGL耦接，第七晶体管M7的第二极与输出端Oput耦接。
示例性地，如图11所示，移位寄存器RS还包括第一稳压子电路127。第一稳压子电路127与下拉节点PD、电压端VGL和输出端Oput耦接。第一稳压子电路127被配置为响应于在输出端Oput处接收的信号，将电压端VGL的电压传输至下拉节点PD，控制下拉节点PD的电压。示例性地，在输出端Oput输出的信号为有效信号(例如高电平信号)的情况下，第一稳压子电路127将电压端VGL的电压传输至下拉节点PD，控制下拉节点PD的电压保持稳定(例如下拉节点PD的电压保持低电平的电压)，从而使得输出端Oput可以稳定输出。
例如，如图12所示，第一稳压子电路127包括第八晶体管M8。第八晶 体管M8的控制极与输出端Oput耦接，第八晶体管M8的第一极与电压端VGL耦接，第八晶体管M8的第二极与下拉节点PD耦接。
示例性地，如图11所示，移位寄存器RS还包括第二稳压子电路128。第二稳压子电路128与电压端VGL和下拉节点PD耦接。第二稳压子电路128被配置为根据电压端VGL的电压和下拉节点PD电压，控制下拉节点PD的电压。示例性地，在下拉节点PD无信号输入的情况下，下拉节点PD的电压不稳定，第二稳压子电路128可以控制下拉节点PD的电压，例如控制下拉节点PD的电压为高电平的电压，使得下拉节点PD的电压保持稳定，以保证移位寄存器可以正常工作。
例如，如图12所示，第二稳压子电路128包括第二电容器C2。第二电容器C2的第一极与电压端VGL耦接，第二电容器C2的第二极与下拉节点PD耦接。
示例性地，移位寄存器中的各个晶体管为N型晶体管。例如，在一个移位寄存器RS工作的第一阶段(参考图13中的Q1)，输入子电路121响应于在输入端IN处接收的输入信号，将输入信号传输至上拉节点PU，对上拉节点PU充电。在上拉节点PU的电压的控制下，输出子电路122将在第一时钟信号端CLK1处接收的第一时钟信号传输至输出端OUT。例如，输入子电路121中的第一晶体管M1响应于高电平的输入信号，第一晶体管M1导通，将输入信号传输至上拉节点PU，使得上拉节点PU的电压为高电平的电压，对输出子电路122中的第一电容器C1充电，输出子电路122中的第二晶体管M2响应于高电平的上拉节点PU的电压，将低电平的第一时钟信号传输至输出端Oput，此时，输出端Oput输出的驱动信号为低电平信号。
下拉控制子电路123响应于在第二时钟信号端CLK2处接收的第二时钟信号，将第二时钟信号传输至下拉节点PD；及，响应于上拉节点PU的电压，将电压端VGL的电压传输至下拉节点PD。例如，下拉控制子电路123中的第三晶体管M3在高电平的第二时钟信号的控制下，第三晶体管M3导通，将第二时钟信号传输至下拉节点PD；第四晶体管M4响应于上拉节点PU的高电平的电压，第四晶体管M4导通，将电压端VGL的低电平的电压传输至下拉节点PD，由于第四晶体管M4的沟道的宽长比大于第三晶体管M3的沟道的宽长比，因此，下拉节点PD的电压为低电平的电压。
此外，第一降噪子电路124、第二降噪子电路125和第三降噪子电路126均不工作，即，第五晶体管M5、第六晶体管M6和第七晶体管M7均截止。第一稳压子电路127也不工作，即，第八晶体管M8截止。
例如，在一个移位寄存器RS工作的第二阶段(参考图13中的Q2)，在上拉节点PU的电压的控制下，输出子电路122将在第一时钟信号端CLK1处接收的第一时钟信号传输至输出端Oput。例如，输入子电路121中的第一晶体管M1在低电平的输入信号的控制下截止。由于第一电容器C1的自举作用，使得上拉节点PU的电压仍为高电平的电压。输出子电路122中的第二晶体管M2响应于高电平的上拉节点PU的电压，将低电平的第一时钟信号传输至输出端OUT，此时，输出端Oput输出的驱动信号为高电平信号。
下拉控制子电路123响应于上拉节点PU的电压，将电压端VGL的电压传输至下拉节点PD。例如，下拉控制子电路123中的第三晶体管M3在低电平的第二时钟信号的控制下，第三晶体管M3截止；第四晶体管M4在上拉节点PU的高电平的电压，第四晶体管M4导通，将电压端VGL的低电平的电压传输至下拉节点PD，因此下拉节点PD为低电平电位，使得下拉节点PD的电压为低电平的电压。
第一稳压子电路127响应于在输出端Oput处接收的信号，将电压端VGL的电压传输至下拉节点PD。例如，第一稳压子电路127中的第八晶体管M8响应于在输出端Oput处接收的高电平的信号，将电压端VGL的低电平的电压传输至下拉节点PD。此时，下拉节点PD的电压为低电平的电压。
此外，第一降噪子电路、第二降噪子电路和第三降噪子电路均不工作。
例如，在一个移位寄存器RS工作的第三阶段(参考图13中的Q3)，第一降噪子电路124响应于复位信号端Rst处接收的复位信号，将电压端VGL的电压传输至上拉节点PU。例如，第一降噪子电路124中的第五晶体管M5响应于高电平的复位信号，将电压端VGL的低电平的电压传输至上拉节点PU。
下拉控制子电路123响应于在第二时钟信号端CLK2处接收的第二时钟信号，将第二时钟信号传输至下拉节点PD。例如，下拉控制子电路123中的第三晶体管M3在高电平的第二时钟信号的控制下，第三晶体管M3导通，将高电平的第二时钟信号传输至下拉节点PD，使得下拉节点PD的电压为高电平的电压；第四晶体管M4在上拉节点PU的低电平的电压的控制下截止，此时，下拉节点PD的电压为高电平的电压。
第二降噪子电路125响应于下拉节点PD的电压，将电压端VGL的电压传输至上拉节点PU。例如，第二降噪子电路125中的第六晶体管M6响应于下拉节点PD的高电平的电压，将电压端VGL的低电平的电压传输至上拉节点PU。此时，上拉节点PU的电压为低电平电压。在此情况下，输出子电路122中的第二晶体管M2在上拉节点PU的低电平的电压的控制下，第二晶体 管M2截止，不会将第一时钟信号输出。此时，第三降噪子电路127响应于下拉节点PD的电压，将电压端VGL的电压传输至输出端Oput。例如，第三降噪子电路127中的第八晶体管M8响应于下拉节点PD的高电平的电压，将电压端VGL的低电平的电压传输至输出端Oput，使得输出端Oput输出的低电平信号，即，驱动信号为低电平信号。
例如，在一个移位寄存器RS工作的第四阶段(参考图13中的Q4)，下拉控制子电路123中的第三晶体管M3在低电平的第二时钟信号的控制下，第三晶体管M3截止；并且，上拉节点PU的电压为上一阶段的低电平的电压，第四晶体管M4在上拉节点PU的低电平的电压的控制下截止。在此情况下，第三晶体管M3不会将第二时钟信号传输至下拉节点PD，第四晶体管M4不会将电压端VGL的电压传输至下拉节点PD，此时，下拉节点PD的电压不稳定。第二稳压子电路128根据下拉节点PD的电压和电压端VGL的电压，控制下拉节点PD的电压，例如，由于第二稳压子电路128中的第二电容器C2的存储作用，根据电压端VGL的低电平的电压，控制下拉节点PD的电压为高电平的电压。
第一降噪子电路124中的第五晶体管M5在低电平的复位信号的控制下处于截止状态。第二降噪子电路125响应于下拉节点PD的电压，将电压端VGL的电压传输至上拉节点PU。例如，第二降噪子电路125中的第六晶体管M6响应于下拉节点PD的高电平的电压，将电压端VGL的低电平的电压传输至上拉节点PU。此时，上拉节点PU的电压为低电平电压。在此情况下，输出子电路122中的第二晶体管M2在上拉节点PU的低电平的电压的控制下，第二晶体管M2截止，不会将第一时钟信号输出。此时，第三降噪子电路127响应于下拉节点PD的电压，将电压端VGL的电压传输至输出端Oput。例如，第三降噪子电路127中的第八晶体管M8响应于下拉节点PD的高电平的电压，将电压端VGL的低电平的电压传输至输出端Oput，使得输出端Oput输出的低电平信号，即，驱动信号为低电平信号。
在一些实施例中，在驱动子电路中，除了第一级移位寄存器，每一级移位寄存器的输出端与其上一级移位寄存器的复位信号端耦接。参考图10B，在驱动子电路31中，第二级移位寄存器RS(2)的输出端Oput与其上一级移位寄存器，即第一级移位寄存器RS(1)的复位信号端Rst耦接；第三级移位寄存器RS(3)的输出端Oput与其上一级移位寄存器，即第二级移位寄存器RS(2)的复位信号端Rst耦接。可以理解的是，在每一级移位寄存器输出有效信号的阶段，对其上一级移位寄存器进行复位。示例性地，驱动子电路中的最后一 级移位寄存器的复位信号端可以与显示面板中的复位信号线耦接，以对最后一级移位寄存器进行复位。
在一些实施例中，如图14所示，显示面板100包括多条数据线DL。多条数据线DL设置于衬底10上。示例性地，多条数据线的延伸方向，与子像素排列的列方向平行，与像素岛21排列的列方向平行，与显示单元20排列的列方向平行；例如，参考图14，多条数据线沿Y方向延伸。可以理解的是，数据线被配置为传输数据信号。
如图15所示，子像素P包括像素电路110。像素电路110包括数据写入子电路111。数据写入子电路111与选通电路40和一条数据线DL耦接。示例性地，在选通电路40包括选通子电路41的情况下，一个显示单元20中各个子像素中的像素电路110中的数据写入子电路111与一个选通子电路41耦接；在选通子电路41包括开关子电路411的情况下，一个显示单元20中的一行子像素中的像素电路110中的数据写入子电路111与一个开关子电路411耦接；在开关子电路411包括选通晶体管MK的情况下，选通晶体管MK的第二极与数据写入子电路111耦接。其中，选通电路40与驱动电路30耦接，选通电路40可以传输来自驱动电路30的驱动信号。数据写入子电路111被配置为响应于来自选通电路40的一个驱动信号，写入数据线DL传输的数据信号。选通电路控制数据写入子电路与驱动电路形成导电通路。示例性地，一列显示单元中的一列子像素与同一条数据线耦接。
示例性地，如图12所示，像素电路包括发光驱动子电路112，发光驱动子电路112与数据写入子电路111和第一电源电压端VDD耦接发光驱动子电路112被配置为输出驱动电流。发光驱动子电路112还与发光器件L耦接，发光驱动子电路112可以将驱动电路传输至发光器件L，以驱动发光器件L发光。例如，参考图16，发光驱动子电路112包括驱动晶体管MD和存储电容器Cst。
示例性地，参考图16，数据写入子电路111包括数据写入晶体管MA。数据写入晶体管MA的控制极与选通电路40耦接，数据写入晶体管MA的第一极与数据线DL耦接，数据写入晶体管MA的第二极与发光驱动子电路112耦接，例如数据写入晶体管MA的第二极与发光驱动子电路112中的驱动晶体管MD耦接；例如，数据写入晶体管MA的第二极与驱动晶体管MD的控制极耦接。示例性地，参考图17，在开关子电路411包括选通晶体管MK的情况下，数据写入晶体管MA的控制极与选通晶体管MK的第二极耦接。
例如，参考图16，数据写入晶体管MA的控制极(栅极)用于接收驱动 信号(即栅极驱动信号)，在驱动信号的控制下，数据写入晶体管MA导通，此时，数据信号通过该晶体管M1写入至驱动晶体管MD的控制极。驱动晶体管MD的第一极接收第一电源电压端VDD的第一电源电压，在驱动晶体管MD的控制极和第一极的电压差值符合驱动晶体管MD的开启条件时，驱动晶体管MD产生的驱动电流，并将该驱动电流传输至发光器件L，以驱动发光器件L进行发光。示例性地，发光器件L的一极(例如阳极)接收来自像素电路的驱动电流，发光器件L的另一极(例如阴极)与第二电源电压端VSS耦接。例如，第一电源电压端的第一电源电压和第二电源电压端的第二电源电压均为直流电压；例如，第一电源电压为直流高电压，第二电源电压为直流低电压。
需要说明的是，本公开的实施例提供的各个电路(例如包括驱动电路、选通电路和像素电路等)中所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，TFT)、场效应晶体管(Field Effect Transistor，FET)、互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)或其他特性相同的开关器件，本公开的实施例对此并不设限。例如，在显示面板的衬底为硅基衬底的情况下，晶体管可以采用CMOS管。
在一些实施例中，文中描述的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的电路中，文中描述的各个节点(例如包括上拉节点和下拉节点等)并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
在本公开的实施例提供的电路中，例如文中描述的各个电路包括：驱动电路、驱动电路中的驱动子电路、驱动子电路中的移位寄存器、选通电路、选通电路中的选通子电路、选通子电路中的开关子电路、像素电路、像素电路中的数据写入子电路和发光驱动子电路等的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例并不能限制本公开的保 护范围。在实际应用中，技术人员可以根据情况选择使用或不适用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
需要说明的是，为了描述方便，本公开的实施例将一些信号端、一些信号端传输的信号、以及一些信号端所耦接的信号线均采用相同符号表示，但各自的属性不相同。
在一些实施例中，如图18A和图18B所示，显示面板100还包括：光学膜50。光学膜50设置于多个显示单元20远离衬底10的一侧，即，沿垂直于显示面板100所在平面的方向(例如图18B中的Z方向)，光学膜50相比于多个显示单元20远离衬底10。光学膜50被配置为将显示面板100中的显示单元20中的各像素岛21中各子像素P发出的光折射，以分散至多个像素区域H(参考图19)。
其中，一个像素区域指的是一个像素所在的区域；该像素发出的光由颜色不同的子像素发出的光构成，颜色不同的子像素来自不同的像素岛。例如，显示单元中的红色子像素发出的红色光经过光学膜折射，以分散至多个像素区域；显示单元中的绿色子像素发出的绿色光经过光学膜折射，以分散至多个像素区域；显示单元中的蓝色子像素发出的蓝色光经过光学膜折射，以分散至多个像素区域。例如，不同颜色的子像素发出的不同颜色的光经过光学膜折射后，在垂直于显示面板所在平面的方向上互相叠加，并汇聚至同一像素区域，以实现灰阶显示。在此情况下，像素区域的尺寸与子像素的尺寸相同，可以增大用于驱动子像素发光的电路的设计空间，也可以方便提高显示面板的PPI。或者，例如，不同颜色的子像素发出的不同颜色的光经光学膜折射后，在平行于显示面板所在平面的方向上间隔排布并汇聚至同一像素区域，以实现灰阶显示。在此情况下，像素区域的尺寸约为n倍子像素的尺寸，n表示汇聚至同一像素区域中子像素的个数。
示例性地，光学膜包括微透镜膜。显示单元中各子像素发出的光经过微透镜膜折射，分散至多个像素区域。示例性地，微透镜膜包括多个依次排布的微透镜，例如一个微透镜与一个子像素位置对应，或者，例如一个微透镜与一个像素岛位置对应，微透镜可以将与之对应的子像素发出的光折射至多个像素区域。
需要说明的是，可以根据实际情况，对光学膜进行设计，使得经过光学膜折射后的光分散至指定的多个像素区域。例如，参考图19，多个像素区域H包含于待显示区域T中；例如，待显示区域可以为用户观看显示装置(或 显示面板)的区域。
在本公开提供的显示装置中，如图20所示，显示装置还包括处理装置210。示例性地，处理装置210与显示面板100耦接。示例性地，处理装置包括时序控制器(Timing Controller，TCON)。
处理装置被配置为根据显示面板的待显示区域的信息，向显示面板中的选通电路输出至少一个控制信号，以控制显示面板中的驱动电路和显示面板中与待显示区域对应的至少一个显示单元导通；及，根据显示面板的待显示区域的信息，向显示面板中的驱动电路输出至少一个输入信号，以使驱动电路向与显示面板中与待显示区域对应的至少一个显示单元输出至少一个驱动信号，使待显示区域显示。
其中，至少一个显示单元进行显示的显示区域(例如多个像素区域)与待显示区域相同或对应，则该至少一个显示单元为与待显示区域对应的至少一个显示单元。
在此情况下，处理装置根据显示面板的待显示区域的信息，向选通电路输出至少一个控制信号，选通电路(例如选通电路中的选通子电路)接收到的控制信号，控制与待显示区域对应的至少一个显示单元和驱动电路导通，使得与待显示区域对应的至少一个显示单元可以接收来自驱动电路的驱动信号。并且，处理装置根据显示面板的待显示区域的信息，向驱动电路输出至少一个输入信号，使得与待显示区域对应的至少一个显示单元相导通的驱动电路(例如驱动电路中的驱动子电路)接收到输入信号，输出至少一个驱动信号。这样，与待显示区域对应的至少一个显示单元可以接收到驱动信号，使得接收到驱动信号的至少一个显示单元进行显示，从而使得待显示区域实现显示。在此情况下，显示面板实现分区驱动，分区显示，节省了显示装置的功耗。
在一些实施例中，如图20所示，显示装置200还包括信息采集装置220。例如，信息采集装置220与处理装置210耦接。其中，信息采集装置被配置为采集用户视线信息。处理装置还被配置为获取用户视线信息，根据用户视线信息，确定显示面板的待显示区域的信息。
示例性地，信息采集装置可以采用任何具有视线采集功能的器件，例如摄像头、眼球追踪仪等。
可以理解的是，信息采集装置采集用户视线信息，并将用户视线信息发送至处理装置。处理装置获取用户视线信息，并根据用户视线信息，确定显示面板的待显示区域的信息。例如，待显示区域的信息包括该待显示区域的 位置和大小。例如，根据待显示区域的信息，可以得到与该待显示区域对应的至少一个显示单元。
因此，可以根据用户实际观看显示装置的情况，获得待显示区域的信息，确定与该待显示区域对应的显示单元，并驱动显示单元使得待显示区域进行显示，这样，可以根据用户实际观看情况进行调节显示装置的显示区域，使得显示装置处于局部显示状态或者全屏显示状态，从而在满足用户的使用要求的同时，还可以显示装置的降低功耗。
示例性地，显示装置还包括驱动芯片。例如，驱动芯片为驱动IC，例如，驱动IC包括源极驱动器。例如，驱动芯片被配置为向显示面板中的各个子像素提供驱动信号；例如驱动信号包括数据信号。
本公开的实施例提供一种显示面板的驱动方法。该显示面板为上述任一实施例中的显示面板。其中，驱动方法包括：
根据显示面板的待显示区域的信息，向显示面板中的驱动电路输出至少一个输入信号，以使驱动电路响应于至少一个输入信号，向与待显示区域对应的至少一个显示单元输出至少一个驱动信号。
示例性地，在驱动电路包括驱动子电路的情况下，驱动子电路接收输入信号，输出驱动信号。示例性地，在驱动子电路包括移位寄存器的情况下，移位寄存器输出驱动信号。示例性地，向与待显示区域对应的显示单元所耦接的驱动电路中的驱动子电路输出输入信号，不向其余的显示单元所耦接的驱动子电路输出输入信号，以降低功耗。
根据显示面板的待显示区域的信息，向显示面板中的选通电路输出至少一个控制信号，以使选通电路根据至少一个控制信号，控制驱动电路与多个显示单元中的与待显示区域对应的至少一个显示单元导通，使至少一个显示单元接收来自驱动电路的至少一个驱动信号，驱动与待显示区域对应的至少一个显示单元显示。
示例性地，在选通电路包括多个选通子电路的情况下，至少一个选通子电路接收至少一个控制信号，将至少一个显示单元与驱动电路导通。示例性地，在选通子电路包括开关子电路的情况下，选通子电路中的开关子电路接收控制信号，以将显示单元中的各行子像素与驱动电路导通。示例性地，向与待显示区域对应的显示单元所耦接的选通电路中的选通子电路输出控制信号，不向其余的显示单元所耦接的选通子电路输出控制信号，以降低功耗。
在此情况下，在显示面板中，与待显示区域对应的至少一个显示单元显示，其余显示单元不显示，使得待显示区域处于显示状态，其余区域处于非 显示状态，即，显示面板部分区域显示，部分区域不显示，实现了对显示单元的分区控制，降低了显示面板的功耗。
在一些实施例中，驱动方法还包括：获取用户视线信息；根据用户视线信息，确定显示面板的待显示区域的信息。这样，可以使得显示面板的显示满足用户的实际观看情况，提高用户体验效果。
需要说明的是，上述显示面板的驱动方法的有益效果和上述一些实施例所述的显示面板和显示装置的有益效果相同，可以参考对应部分的描述，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种显示面板，具有显示区；所述显示面板包括：
    衬底，
    多个显示单元，设置于所述衬底上且位于所述显示区内，每个显示单元包括多个像素岛，每个像素岛包括多个颜色相同的子像素；
    驱动电路，设置于所述衬底上且位于所述显示区外；所述驱动电路被配置为输出多个驱动信号；
    选通电路，设置于所述衬底上，及位于所述显示区内且位于所述多个显示单元的外侧；所述选通电路与所述驱动电路耦接，所述选通电路还与至少一个显示单元耦接；所述选通电路被配置为，控制所述驱动电路与所述至少一个显示单元导通，以使所述至少一个显示单元根据来自所述驱动电路的至少一个驱动信号，驱动所述至少一个显示单元中的多个像素岛中的多个子像素显示。
  2. 根据权利要求1所述的显示面板，还包括：
    多条控制信号线，设置于所述衬底上；
    所述驱动电路包括：多个驱动信号输出端；所述多个驱动信号输出端被配置为输出所述多个驱动信号；
    所述选通电路包括：多个选通子电路；一个选通子电路与至少一条控制信号线、一个显示单元和至少一个驱动信号输出端耦接；
    所述选通子电路被配置为，响应于所述至少一条控制信号线传输的控制信号，将在所述至少一个驱动信号输出端处接收的至少一个驱动信号传输至所述显示单元中的各像素岛中的多个子像素。
  3. 根据权利要求2所述的显示面板，其中，所述显示单元包括至少一行子像素；
    所述选通子电路包括：
    至少一个开关子电路；一个开关子电路与一条控制信号线、一个驱动信号输出端和所述显示单元中的一行子像素耦接；所述开关子电路被配置为，响应于所述控制信号线传输的控制信号，将在所述驱动信号输出端处接收的驱动信号传输至所述开关子电路所耦接的一行子像素。
  4. 根据权利要求3所述的显示面板，其中，所述多个显示单元呈阵列排布；
    在一行显示单元中的各个显示单元中，相同行的子像素各自所耦接的开关子电路与同一个驱动信号输出端耦接。
  5. 根据权利要求3或4所述的显示面板，其中，所述选通子电路中的至少一个开关子电路与同一条控制信号线耦接。
  6. 根据权利要求3～5中任一项所述的显示面板，其中，所述开关子电路包括：
    选通晶体管；所述选通晶体管的控制极与所述控制信号线耦接，所述选通晶体管的第一极与所述驱动信号输出端耦接，所述选通晶体管的第二极与所述显示单元中的一行子像素耦接。
  7. 根据权利要求2～6中任一项所述的显示面板，其中，不同的选通子电路耦接的控制信号线不同。
  8. 根据权利要求2～7中任一项所述的显示面板，还包括：
    多条输入信号线，设置于所述衬底上；
    所述驱动电路包括：
    多个驱动子电路，每个驱动子电路与一条输入信号线耦接，所述驱动子电路包括多个驱动信号输出端；
    所述驱动子电路被配置为，根据所述输入信号线传输的输入信号，从所述驱动子电路的多个驱动信号输出端输出多个驱动信号。
  9. 根据权利要求8所述的显示面板，其中，所述驱动子电路包括多个级联的移位寄存器；每一级移位寄存器的输出端为一个驱动信号输出端；
    第一级移位寄存器的输入端与一条输入信号线耦接；
    除最后一级移位寄存器之外的每一级移位寄存器的输出端与其下一级移位寄存器的输入端耦接。
  10. 根据权利要求1～9中任一项所述的显示面板，还包括：
    多条数据线，设置于所述衬底上；
    所述子像素包括像素电路；
    所述像素电路包括数据写入子电路；所述数据写入子电路与所述选通电路和一条数据线耦接；所述数据写入子电路被配置为，响应于来自所述选通电路的一个驱动信号，写入所述数据线传输的数据信号。
  11. 根据权利要求1～10中任一项所述的显示面板，其中，所述子像素包括发光器件；所述发光器件包括发光层；一个像素岛中的多个子像素中的发光器件的发光层无间隙。
  12. 根据权利要求1～11中任一项所述的显示面板，还包括：
    光学膜，设置于所述多个显示单元远离所述衬底的一侧；所述光学膜被配置为将所述显示面板中的显示单元中的各像素岛中各子像素发出的光折 射，以分散至多个像素区域。
  13. 一种显示装置，包括：如权利要求1～12中任一项所述的显示面板。
  14. 根据权利要求13所述的显示装置，还包括：
    处理装置；所述处理装置被配置为根据所述显示面板的待显示区域的信息，向所述显示面板中的选通电路输出至少一个控制信号，以控制所述显示面板中的驱动电路和所述显示面板中与所述待显示区域对应的至少一个显示单元导通；及，根据所述显示面板的待显示区域的信息，向所述显示面板中的驱动电路输出至少一个输入信号，以使所述驱动电路向与所述待显示区域对应的至少一个显示单元输出至少一个驱动信号。
  15. 根据权利要求14所述的显示装置，还包括：
    信息采集装置，被配置为采集用户视线信息；
    所述处理装置还被配置为，获取所述用户视线信息，根据所述用户视线信息，确定所述显示面板的待显示区域的信息。
  16. 一种如权利要求1～12中任一项所述的显示面板的驱动方法，包括：
    根据所述显示面板的待显示区域的信息，向所述显示面板中的驱动电路输出至少一个输入信号，以使所述驱动电路响应于所述至少一个输入信号，向与所述待显示区域对应的至少一个显示单元输出至少一个驱动信号；
    根据所述显示面板的待显示区域的信息，向所述显示面板中的选通电路输出至少一个控制信号，以使所述选通电路根据所述至少一个控制信号，控制所述驱动电路与多个显示单元中的与所述待显示区域对应的至少一个显示单元导通，使所述至少一个显示单元接收来自所述驱动电路的至少一个驱动信号，驱动与所述待显示区域对应的至少一个显示单元显示。
  17. 根据权利要求16所述的驱动方法，还包括：
    获取用户视线信息；
    根据所述用户视线信息，确定所述显示面板的待显示区域的信息。
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