WO2022116894A1 - 太阳电池及电池组件 - Google Patents

太阳电池及电池组件 Download PDF

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WO2022116894A1
WO2022116894A1 PCT/CN2021/133236 CN2021133236W WO2022116894A1 WO 2022116894 A1 WO2022116894 A1 WO 2022116894A1 CN 2021133236 W CN2021133236 W CN 2021133236W WO 2022116894 A1 WO2022116894 A1 WO 2022116894A1
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layer
base layer
inversion layer
solar cell
inversion
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PCT/CN2021/133236
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English (en)
French (fr)
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吴兆
徐琛
李子峰
解俊杰
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隆基绿能科技股份有限公司
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Priority claimed from CN202011395240.8A external-priority patent/CN112786729B/zh
Priority claimed from CN202011555929.2A external-priority patent/CN112786719B/zh
Application filed by 隆基绿能科技股份有限公司 filed Critical 隆基绿能科技股份有限公司
Publication of WO2022116894A1 publication Critical patent/WO2022116894A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present disclosure relates to the field of photovoltaic technology, and in particular, to a solar cell and a battery assembly.
  • PN junction solar cells have the characteristics of forward conduction and reverse cut-off.
  • the entire PN junction solar cell string connected in series with the PN junction solar cell will have an abnormality.
  • the output current is greatly affected, and it is easy to cause damage to the battery components.
  • the present disclosure provides a solar cell and a battery assembly, aiming at solving the problems that the power of the assembly drops a lot and the diode generates serious heat when a parallel bypass diode is set in a PN junction solar cell string.
  • a solar cell including a PN junction; the PN junction is formed by a base layer and an inversion layer; the base layer and the inversion layer have different doping types;
  • the light facing side of the backlight side extends into the layer;
  • One of the base layer and the inversion layer on the light-facing side is a non-degenerate semiconductor
  • the weakly degenerate or degenerate semiconductor is set such that the energy level difference between the Fermi level and the bottom of the conduction band of the n-type semiconductor or the top of the valence band of the p-type semiconductor is less than 2k B ⁇ T m .
  • the PN junction in the embodiment of the present disclosure exists as a general PN junction when a forward voltage is applied, and is used to separate carriers. When a reverse voltage is applied, the PN junction will exist as a tunnel junction and will be reverse biased, a tunnel current will be formed in the PN junction, and reverse conduction will occur, and when a forward voltage is applied, it will return to the normal PN knot exists.
  • a reverse voltage will be applied to the PN junction, that is, the PN junction will exist as a tunnel junction in an abnormal situation, and will not be broken down and will not affect the PN junction solar cell.
  • the battery string formed by the solar cell does not need parallel bypass diodes, the packaging loss is small, and the size of the junction box can be reduced; on the other hand, in the event of an abnormality, the rest of the battery string All solar cells allow normal current to pass through, but the output current of abnormal solar cells is affected, with less current loss, less heat generation, higher reliability and long-term stability, and less component power drop.
  • a side junction box can be used for the battery assembly formed by the above-mentioned solar cells, the back plate does not need to be opened, the process is simple, and the cost is low.
  • the matrix layer and the inversion layer located on the light-facing side are non-degenerate semiconductors, with better light absorption performance and lower recombination.
  • the material of the inversion layer is selected from: at least one of III-V compound semiconductors, oxide semiconductors, amorphous silicon, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide;
  • the material of the base layer is selected from at least one of crystalline silicon, III-V compound semiconductor, oxide semiconductor, amorphous silicon, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide.
  • the inversion layer is located on the backlight side, wherein, when the following materials are used as the inversion layer,
  • the doping concentration of the III-V compound semiconductor is 10 17 cm -3 -10 21 cm -3 ;
  • Donor defect or acceptor defect concentration of the oxide semiconductor is 10 16 cm -3 -10 21 cm -3 ;
  • the doping concentration of the inversion layer is 10 15 cm -3 -10 18 cm - 3 .
  • the base layer is located on the backlight side, wherein, when the following materials are used as the base layer,
  • the doping concentration of crystalline silicon is 10 16 cm -3 -10 20 cm -3 ;
  • the doping concentration of the III-V compound semiconductor is 10 17 cm -3 -10 21 cm -3 ;
  • Donor defect or acceptor defect concentration of the oxide semiconductor is 10 16 cm -3 -10 21 cm -3 ;
  • the doping concentration of the base layer is 10 15 cm -3 -10 18 cm -3 .
  • the inversion layer is located on the entire backlight surface of the base layer; the base layer is crystalline silicon, and the doping concentration of the crystalline silicon is 10 13 cm -3 -10 16 cm -3 ; or,
  • the inversion layer is located in a local area of the backlight surface of the base layer, the base layer is crystalline silicon, and the doping concentration of the crystalline silicon is 10 13 cm -3 -10 20 cm -3 .
  • the inversion layer is located in a local area of the backlight surface of the base layer, the base layer is crystalline silicon, and the doping concentration of the crystalline silicon near the inversion layer in the local area larger than the opposite side.
  • the material of the inversion layer is selected from III-V compound semiconductors, and a buffer layer is further provided between the base layer and the inversion layer; the buffer layer has a thickness of 0.1-50 nm, and the The material of the buffer layer is selected from one of germanium crystal, silicon germanium compound, and III-V compound.
  • the material of the inversion layer is an oxide semiconductor, and a silicon oxide layer is further provided between the base layer and the inversion layer; the thickness of the silicon oxide layer is 0.1-10 nm.
  • the material of the inversion layer is selected from at least one of amorphous silicon, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide, and there is also a gap between the base layer and the inversion layer.
  • a passivation layer is provided; the thickness of the passivation layer is 0.1-10 nm, and the material of the passivation layer is selected from: intrinsic amorphous silicon, nanocrystalline silicon or silicon oxide.
  • the III-V compound semiconductor is selected from: at least one of GaAs, InAs, InP, GaP, AlP, and AlAs;
  • the oxide semiconductor is selected from: a first material or a doping compound of the first material and the second material; the first material is selected from: titanium oxide, zinc oxide, tin oxide, nickel oxide, copper oxide, oxide At least one of tungsten, molybdenum oxide, and vanadium oxide; the second material is selected from at least one of halogen group elements, transition metal elements, alkali metal elements, rare earth elements, group III elements, group IV elements, and group V elements A sort of.
  • the projected area of the inversion layer on the backlight surface of the base layer accounts for the backlight of the base layer. 50% to 95% of the total surface area.
  • a battery assembly comprising: any of the aforementioned solar cells.
  • the above-mentioned battery assembly has the same or similar beneficial effects as the aforementioned solar cells.
  • a solar cell including a PN junction, the PN junction is formed by a base layer and an inversion layer, the base layer and the inversion layer have different doping types; the The inversion layer has a first heavily doped region, the first heavily doped region extends from a side of the inversion layer away from the base layer into the inversion layer, the first heavily doped region the same doping type as the inversion layer;
  • the thickness difference between the inversion layer and the first heavily doped region is 1-100 nm;
  • the first heavily doped region forms a weakly degenerate or degenerate semiconductor
  • the rest of the inversion layer and the base layer are non-degenerate semiconductors
  • the weakly degenerate or degenerate semiconductor The semiconductor is set such that the energy level difference between the Fermi level and the bottom of the conduction band of the n-type semiconductor or the top of the conduction band of the p-type semiconductor is less than 2k B ⁇ T m .
  • the first heavily doped region extends from the side of the inversion layer away from the base layer into the inversion layer, and along the direction away from the base layer, the thickness difference between the inversion layer and the first heavily doped region is 1-100 nm, the distance between the first heavily doped region and the interface of the pn junction is 1-100 nm, which can reduce the recombination at the interface and reduce the non-local transition current of carriers.
  • the PN junction in the embodiment of the present disclosure exists as a general PN junction when a forward voltage is applied, and is used to separate carriers.
  • the base layer, the inversion layer, and the first heavily doped region form a heavily doped junction.
  • the heavily doped junction When a reverse voltage is applied, the heavily doped junction will exist as a tunnel junction, and a tunnel current will be formed in the PN junction, which will conduct reverse conduction. , and was not reversely broken down, and in the case of applying a forward voltage, it returned to the existence of a general PN junction. In the case of an abnormality, the heavily doped junction will exist as a tunnel junction, will not be broken down, and will not affect the output of the entire solar cell string connected in series with the solar cell.
  • the battery string does not need a parallel bypass diode, the packaging loss is small, and the size of the junction box can be reduced; on the other hand, when an abnormality occurs, the rest of the solar cells in the battery string allow normal current to pass through, only the output of the abnormal solar cell The current is affected, the loss of current is less, the heat generation is less, the hot spot effect is minimized, and the reliability and long-term stability are higher, and the power drop of the components is also less.
  • the back plate of the battery module formed by the above-mentioned solar cells does not need to be perforated, the process is simple, and the cost is low.
  • a battery assembly comprising: any of the aforementioned solar cells.
  • the above-mentioned battery assembly has the same or similar beneficial effects as the aforementioned solar cells.
  • FIG. 1 shows a schematic structural diagram of a first solar cell in an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a second type of solar cell in an embodiment of the present disclosure
  • FIG. 3 shows a schematic structural diagram of a third type of solar cell in an embodiment of the present disclosure
  • FIG. 4 shows a schematic structural diagram of a fourth solar cell in an embodiment of the present disclosure
  • FIG. 5 shows a schematic structural diagram of a fifth solar cell in an embodiment of the present disclosure
  • FIG. 6 shows a schematic structural diagram of a battery assembly in an embodiment of the present disclosure
  • FIG. 7 shows a schematic circuit diagram of a battery assembly in an embodiment of the present disclosure
  • FIG. 8 shows a schematic structural diagram of a sixth solar cell in an embodiment of the present disclosure
  • FIG. 9 shows a schematic structural diagram of a seventh solar cell in an embodiment of the present disclosure.
  • FIG. 10 shows a schematic structural diagram of an eighth solar cell in an embodiment of the present disclosure.
  • FIG. 11 shows a schematic structural diagram of a ninth solar cell in an embodiment of the present disclosure.
  • the bypass diode During normal operation, the bypass diode is in a reverse cut-off state.
  • the battery string where the abnormal solar cells are located to protect the damaged solar cells.
  • the bypass diode when the bypass diode is forward biased and turned on, the output power of the battery string where the abnormal solar cell is located is limited, and the output power of the battery string where the abnormal solar cell is located will not be used as the output power of the battery module.
  • the turned-on bypass diode needs to pass a large current, and the environment where the diode is located has poor heat dissipation, which makes the bypass diode and the junction box generate serious heat, which is likely to cause serious electrical safety hazards and even fire.
  • FIG. 1 shows a schematic structural diagram of a first type of solar cell in an embodiment of the present disclosure.
  • the solar cell includes: a PN junction.
  • the PN junction consists of a base layer 1 and an inversion layer 2.
  • the doping types of the base layer 1 and the inversion layer 2 are different, that is, the doping type of one of the base layer 1 and the inversion layer 2 is P type, and the other is P type.
  • the doping type is N-type, and there is no specific limitation as to which doping type of the two is P-type. For example, if the doping type of the base layer 1 in FIG. 1 is N-type, then the doping type of the inversion layer 2 is P-type.
  • the inversion layer 2 is disposed on the back light side or the light facing side of the base layer 1 . As shown in FIG. 1 , the inversion layer 2 is disposed on the backlight surface of the base layer 1 . Referring to FIG. 2 , FIG. 2 shows a schematic structural diagram of a second type of solar cell in an embodiment of the present disclosure. In FIG. 2 , the inversion layer 2 is disposed on the light-facing surface of the base layer 1 .
  • Tm represents room temperature.
  • weakly degenerate or degenerate semiconductors are formed in at least part of the base layer 1 and the inversion layer 2 on one side of the backlight. That is, at room temperature Tm , at least a partial region of one of the base layer 1 and the inversion layer 2 located on the backlight side has a higher doping concentration, forming a weakly degenerate or degenerate semiconductor.
  • the size of at least part of the region is not specifically limited.
  • a weakly degenerate or degenerate semiconductor is formed in a region near the PN junction in one of the base layer 1 and the inversion layer 2 located on the backlight side, and both the base layer 1 and the inversion layer 2 can form a tunnel junction .
  • the light-facing surface of the base layer 1 and the inversion layer 2 located on the backlight side is the interface between the base layer 1 and the inversion layer 2 located on the backlight side, and the interface with the other.
  • Part of the region extends from the light-facing layer of the base layer 1 and the inversion layer 2 on one side of the backlight, and the extending depth is not specifically limited.
  • the base layer 1 and the inversion layer 2 on the light-facing side have a lower doping concentration and are non-degenerate semiconductors.
  • the doping concentration on the light-facing side is lower, the light absorption performance is better, and the recombination is lower.
  • a weakly degenerate or degenerate semiconductor is formed in the base layer 1 and the inversion layer 2 on the back light side, and the energy level difference between the Fermi level and the bottom of the conduction band of the n-type semiconductor or the top of the valence band of the p-type semiconductor is less than 2k B ⁇ T m , in this formula, k B is the Boltzmann constant, and the value of k B is 1.380649 ⁇ 10 -23 J/K.
  • the PN junction formed by the above-mentioned base layer 1 and the inversion layer 2 exists as a general PN junction when a forward voltage is applied, and is used for carrier separation.
  • the PN junction In the case of applying reverse voltage, the PN junction will exist as a tunnel junction and will be reverse biased. A tunnel current will be formed in the PN junction, and reverse conduction will not be reversed. When a forward voltage is applied Then, it reverts to the existence of a general PN junction. In the case of an abnormality, a reverse voltage will be applied to the PN junction, that is, the PN junction will exist as a tunnel junction in an abnormal situation, and will not be broken down and will not affect the PN junction solar cell.
  • the battery string formed by the solar cell does not need parallel bypass diodes, the packaging loss is small, and the size of the junction box can be reduced; on the other hand, in the event of an abnormality, the rest of the battery string All solar cells allow normal current to pass through, but the output current of abnormal solar cells is affected, with less current loss, less heat generation, higher reliability and long-term stability, and less component power drop.
  • each string consists of 20 solar cells connected in series. If a certain solar cell in a battery string is abnormal, in the prior art, the abnormal solar cell is in a reverse bias state, and the current of the remaining solar cells in the battery string where the abnormal solar cell is located is not allowed to pass, and the output power loss is approximately is 1/3.
  • the PN junction in the solar cell will exist as a tunnel junction, which will be reverse biased and then conduct reversely. The current of the solar cell can pass through the solar cell, which exists only as a resistor in the string, and the output power loss is roughly 1/60.
  • the inversion layer 2 is provided on the backlight surface of the base layer 1 .
  • the doping concentration in at least part of the inversion layer 2 is relatively high, forming a weakly degenerate or degenerate semiconductor.
  • a region in the inversion layer 2 where a weakly degenerate or degenerate semiconductor is formed extends from the light-facing surface of the inversion layer 2 into the layer.
  • the base layer 1 is located on the light-facing side.
  • the base layer 1 has a low doping concentration and is a non-degenerate semiconductor.
  • the energy level difference between the Fermi level and the bottom of the conduction band of the n-type semiconductor or the top of the valence band of the p-type semiconductor is less than 2k B ⁇ T m .
  • the inversion layer 2 is disposed on the light-facing surface of the base layer 1 .
  • the doping concentration in at least part of the base layer 1 is relatively high, forming a weakly degenerate or degenerate semiconductor.
  • the regions in the base layer 1 where weakly degenerate or degenerate semiconductors are formed extend from the light-facing side of the base layer 1 into the layer.
  • the inversion layer 2 has a lower doping concentration and is a non-degenerate semiconductor.
  • the energy level difference between the Fermi level and the bottom of the conduction band of the n-type semiconductor or the top of the valence band of the p-type semiconductor is less than 2k B ⁇ T m .
  • the material of the inversion layer 2 is selected from at least one of III-V compound semiconductors, oxide semiconductors, amorphous silicon, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide.
  • the material of the base layer 1 is selected from at least one of crystalline silicon, III-V compound semiconductor, oxide semiconductor, amorphous silicon, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide.
  • III-V compound semiconductors, oxide semiconductors, amorphous silicon, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide are direct bandgap semiconductors with high tunneling efficiency, and then the PN junctions formed by the above-mentioned materials are used as When the tunnel junction exists, higher photoelectric conversion efficiency and larger reverse tunnel current can be achieved.
  • the doping concentration of the III-V compound semiconductors is 10 17 cm -3 -10 21 cm -3 , which is close to a degenerate state.
  • the concentration of donor defects or acceptor defects of the oxide semiconductor is 10 16 cm ⁇ 3 to 10 21 cm ⁇ 3 .
  • the doping concentration of the inversion layer 2 is 10 15 cm ⁇ 3 ⁇ 10 18 cm -3 .
  • the inversion layer 2 of the above-mentioned material is easy to conduct reverse conduction when a reverse voltage is applied to the PN junction, and has high tunneling efficiency.
  • the base layer 1 is located on the backlight side, that is, when the inversion layer 2 is located on the light-facing surface of the base layer 1, and the material of the base layer 1 is selected from crystalline silicon, the doping concentration of crystalline silicon is 10 16 cm -3 -10 20 cm -3 , which is close to a degenerate state.
  • the doping concentration of the III-V compound semiconductors is 10 17 cm -3 -10 21 cm -3 .
  • the concentration of donor defects or acceptor defects of the oxide semiconductor is 10 16 cm ⁇ 3 to 10 21 cm ⁇ 3 .
  • the doping concentration of the base layer 1 is 10 15 cm -3 -10 18 cm -3
  • the base layer 1 and the inversion layer 2 of the above-mentioned materials are easy to conduct reverse conduction when a reverse voltage is applied to the PN junction, and the tunneling efficiency is high.
  • the PN junction in the embodiment of the present disclosure when the solar cell is abnormal, through testing, the PN junction in the solar cell will exist as a tunnel junction, and will be reverse biased and then conduct reversely, and a tunnel current will be formed in the PN junction. Its own photo-generated current decreases, and the current of other solar cells connected in series with the solar cell can pass through the solar cell.
  • the solar cell only exists in the battery string as a resistor, and its heating power is very weak compared with the prior art, so there is no need for parallel connection.
  • the package loss is small, which can reduce the size of the junction box; at the same time, in the event of an abnormality, the rest of the solar cells in the battery string allow normal current to pass through, only the output current of the abnormal solar cell is affected, and the loss of Less current, less heat generation, higher reliability and long-term stability, and less component power drop.
  • the tunnel current can continue to increase, the PN junction is not broken down, and the reverse bias state is removed, that is, the solar cell returns to normal operation, and the PN junction can return to normal operation. That is, the normal PN junction is restored.
  • the above-mentioned PN junction reduces the recombination and parasitic absorption of the body region, the extended space charge region extends the forbidden band width of the interface region, and suppresses the spontaneous interface tunneling recombination under normal conditions.
  • the above-mentioned III-V compound semiconductors, oxide semiconductors, amorphous silicon, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide are all direct bandgap semiconductors with high tunneling efficiency, and then the PN junction formed by the above materials is When present as a tunnel junction, higher photoelectric conversion efficiency and larger reverse tunnel current can be achieved.
  • the III-V compound semiconductor is selected from: GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), GaP (gallium phosphide), AlP (aluminum phosphide), AlAs (arsenic at least one of aluminum oxide).
  • the oxide semiconductor specifically refers to a transition metal oxide semiconductor, and is specifically selected from: a first material or a doping compound of the first material and the second material.
  • the first material is selected from at least one of titanium oxide, zinc oxide, tin oxide, nickel oxide, copper oxide, tungsten oxide, molybdenum oxide, and vanadium oxide.
  • the second material is selected from at least one of halogen group elements, transition metal elements, alkali metal elements, rare earth elements, group III elements, group IV elements, and group V elements.
  • the inversion layer 2 is disposed on the backlight surface or the light-facing surface of the base layer 1 by one of three ways of epitaxy, deposition and doping.
  • the inversion layer 2 obtained by epitaxial growth has a steep doped element diffusion interface at the interface to reduce the width of one side of the space charge region, improve the tunneling recombination probability in the reverse state, and have fewer epitaxial interface defects, ensuring the The steep space charge region and band change response on the epitaxial side ensures low reverse conduction resistance, so epitaxial growth can be the preferred process.
  • precise doping processes such as ion implantation or rapid thermal diffusion can also be used, and post-deposition crystallization processes can also be used.
  • the inversion layer 2 is disposed on the entire backlight surface of the base layer 1 , thereby facilitating the transmission and collection of minority carriers.
  • the doping concentration of the crystalline silicon is 10 13 cm -3 -10 16 cm -3 , which can reduce the bulk Zone recombination and parasitic absorption.
  • the first electrode 4 is arranged on the backlight surface of the inversion layer 2
  • the second electrode 3 is arranged on the light-directing surface of the base layer 1 .
  • the inversion layer 2 when the inversion layer 2 is arranged on the entire light-facing surface of the base layer 1 , the first electrode 4 is arranged on the backlight surface of the base layer 1 , and the second electrode 3 is arranged on the inversion surface.
  • FIG. 3 shows a schematic structural diagram of a third type of solar cell in an embodiment of the present disclosure.
  • the inversion layer 2 is located in a local area of the backlight surface of the base layer 1, that is to say, the inversion layer 2 does not cover the entire backlight surface of the base layer 1.
  • the material of the base layer 1 is selected from crystalline silicon
  • the doping of crystalline silicon The impurity concentration was 10 13 cm -3 -10 20 cm -3 .
  • the solar cell also includes: a first electrode 4 and a second electrode 3, the first electrode 4 is arranged on the back light surface of the inversion layer 2, and the second electrode 3 is arranged on the back light surface of the base layer 1 outside the inversion layer 2.
  • the electrode does not block the light surface at all, which is beneficial to improve the output power of the solar cell.
  • the inversion layer 2 is located in a local area of the backlight surface of the base layer 1 , the base layer 1 is crystalline silicon, and the crystalline silicon in the local area of the base layer 1 is doped on the side close to the inversion layer 2 .
  • the impurity concentration is greater than the opposite side. That is, the inversion layer 2 is located in a local area of the backlight surface of the base layer 1 , the base layer 1 is crystalline silicon, and the doping concentration of the crystalline silicon in the local area of the base layer 1 near the inversion layer 2 is greater than that far from the inversion layer 2 side, which is beneficial to ensure the incident amount of light.
  • the subsequent process temperature needs to be controlled. Too high subsequent process temperature will cause element diffusion or interface layer cracking at the PN junction interface, which will destroy the PN junction interface and lead to decreased efficiency.
  • the projected area of the inversion layer 2 on the backlight surface of the base layer 1 accounts for the base layer 1 .
  • the total area of the backlight surface is 50% to 95%, and the transport and collection effects of minority carriers and majority carriers are good.
  • the inversion layer 2 may be disposed on a local area of the light-facing surface of the base layer 1 , that is, the inversion layer 2 does not cover the entire light-facing surface of the base layer 1 .
  • FIG. 4 shows a schematic structural diagram of a fourth type of solar cell in an embodiment of the present disclosure.
  • the material of the inversion layer 2 is selected from: III-V compound semiconductors, and a buffer layer 5 is further provided between the inversion layer 2 and the base layer 1 . That is, whether the inversion layer 2 is disposed on the light-directing surface of the base layer 1 or the inversion layer 2 is disposed on the backlight surface of the base layer 1 , the buffer layer 5 may be disposed between the inversion layer 2 and the base layer 1 .
  • the buffer layer 5 can play functions such as buffering lattice mismatch and passivating interface defects.
  • the thickness d1 of the buffer layer 5 is 0.1-50 nm, and the buffer layer 5 in the above thickness range has good lattice adaptation effect and good passivation performance.
  • the material of the buffer layer 5 is selected from one of germanium crystal, silicon germanium compound, and III-V compound.
  • the III-V compound in the buffer layer 5 may be: InPSb (Indium Phosphorous Antimony), GaInP (Gallium Indium Phosphorus), and the like.
  • the buffer layer 5 of the above material has good lattice adaptation effect and good passivation performance.
  • the material of the inversion layer 2 is: an oxide semiconductor, and a silicon oxide layer is also arranged between the base layer 1 and the inversion layer 2, that is, whether the inversion layer 2 is arranged on the base layer 1, the light direction or the inversion layer 2 is arranged on the backlight surface of the base layer 1, a silicon oxide layer may be arranged between the inversion layer 2 and the base layer 1, and the silicon oxide layer acts to prevent the mutual diffusion of the doping elements of the two, and The function of passivating interface defects, and the preparation process can use the existing solar cell preparation process, and the preparation efficiency is high.
  • the thickness of the silicon oxide layer is 0.1-10 nm.
  • the material of the inversion layer 2 is selected from: at least one of amorphous silicon, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide, and a passivation is also provided between the base layer and the inversion layer. That is, whether the inversion layer 2 is arranged on the light-facing surface of the base layer 1 or the inversion layer 2 is arranged on the backlight surface of the base layer 1, a passivation can be provided between the inversion layer 2 and the base layer 1.
  • the passivation layer functions to block the interdiffusion of the two doping elements and passivate the interface defects.
  • the thickness of the passivation layer is 0.1-10 nm.
  • the material of the passivation layer is selected from: intrinsic amorphous silicon, nanocrystalline silicon or silicon oxide, the effect of blocking diffusion and passivation is good, and the preparation process can use the existing preparation process of solar cells. efficient.
  • FIG. 5 shows a schematic structural diagram of a fifth solar cell in an embodiment of the present disclosure.
  • the solar cell when the inversion layer 2 is located on the backlight surface of the base layer 1 , the solar cell further includes a front surface field 6 located on the light-facing surface of the base layer 1 .
  • the doping type of 6 is the same as that of the base layer 1 , and the doping concentration of the front surface field 6 is greater than that of the base layer 1 .
  • the front surface field 6 and the base layer 1 form a concentration gradient difference, which is beneficial to improve the photoelectric conversion efficiency.
  • the solar cell further includes a back surface field 7 located on the backlight side of the base layer 1 .
  • the back surface field 7 is doped.
  • the impurity type is the same as that of the base layer 1 , and the doping concentration of the back surface field 7 is greater than that of the base layer 1 .
  • the back surface field 7 and the base layer 1 form a concentration gradient difference, which is beneficial to improve the photoelectric conversion efficiency.
  • the solar cell when the inversion layer 2 is located in a local area of the backlight surface of the base layer 1 , the solar cell further includes a back surface located outside the inversion layer 2 in the backlight surface of the base layer 1 .
  • Field 7 the doping type of the back surface field 7 is the same as that of the base layer 1, and the doping concentration of the back surface field 7 is greater than that of the base layer 1.
  • the back surface field 7 and the base layer 1 form a concentration gradient difference, which is beneficial to improve the photoelectric conversion efficiency.
  • the backlight surface of the base layer 1 is a plane structure or a light trapping structure, and/or the light-facing surface of the base layer 1 is a plane structure or a light trapping structure, and the inversion layer 2 in contact with it is adapted to the surface structure of the base layer 1. .
  • the light-facing surface of the PN junction is provided with at least one of a front passivation layer, a front anti-reflection film layer, a scattering structure layer, and a light concentrating structure layer; and/or, a back surface is provided on the backlight surface of the PN junction.
  • a passivation layer, a backside anti-reflection film layer, a scattering structure layer, and a light concentrating structure layer At least one of a passivation layer, a backside anti-reflection film layer, a scattering structure layer, and a light concentrating structure layer.
  • FIG. 3-FIG. 5, 9 may be a front anti-reflection film layer
  • 8 may be a back passivation layer.
  • Embodiments of the present disclosure also provide a battery assembly, comprising: any of the foregoing solar cells.
  • FIG. 6 shows a schematic structural diagram of a battery assembly in an embodiment of the present disclosure.
  • FIG. 6 may be a top view from the light-facing backlight side of the battery assembly.
  • FIG. 7 shows a schematic circuit diagram of a battery assembly in an embodiment of the present disclosure. Referring to Figure 7, there is no need for parallel bypass diodes in each battery string.
  • the solar cells in the module reference may be made to the above-mentioned related records, and the same or similar beneficial effects can be achieved. In order to avoid repetition, details are not repeated here.
  • the base layer 1 is n-type single crystal silicon, the light-facing surface of the base layer 1 is a textured structure, the backlight surface is a polished structure, and the doping concentration of the base layer 1 is 10 13 cm -3 -10 16 cm -3 .
  • the base layer 1 is provided with a front surface field 6 toward the light surface, and the front surface field 6 is a heavily doped layer, the doping type is the same as that of the base layer 1 , and the doping concentration is higher than that of the base layer 1 .
  • a weakly degenerate or degenerate semiconductor is formed in at least part of the inversion layer 2 , and the base layer 1 is a non-degenerate semiconductor.
  • the light-facing surface of the base layer 1 is provided with a front-facing antireflection film layer 9 .
  • the inversion layer 2 is located on the entire backlight surface side of the base layer 1 and is obtained by epitaxial growth.
  • the inversion layer 2 is GaAs, is p-type doped (Al-doped), and the doping concentration is 10 18 cm -3 -10 20 cm -3 .
  • the inversion layer 2 is in a near degenerate or degenerate state.
  • a buffer layer 5 exists between the inversion layer 2 and the base layer 1 , and the buffer layer 5 is a SiGe buffer layer with a thickness of 2-50 nm, obtained by epitaxial growth.
  • the backside passivation layer 8 is provided on the backside of the inversion layer 2 .
  • the second electrode 3 is printed on the light-facing surface of the device and dried and sintered, and the first electrode 4 is printed on the backlight surface of the device and dried and sintered.
  • the sintering temperature does not exceed 700°C to protect the tunnel junction interface and reduce interface diffusion.
  • the base layer 1 is n-type single crystal silicon, the light-facing surface of the base layer 1 is a textured structure, the backlight surface is a polished structure, and the doping concentration of the base layer 1 is 10 15 cm -3 -10 16 cm -3 .
  • the base layer 1 is provided with a front surface field 6 toward the light surface, and the front surface field 6 is a heavily doped layer, the doping type is the same as that of the base layer 1 , and the doping concentration is higher than that of the base layer 1 .
  • a weakly degenerate or degenerate semiconductor is formed in at least part of the inversion layer 2 , and the base layer 1 is a non-degenerate semiconductor.
  • the light-facing surface of the base layer 1 is provided with a front-facing antireflection film layer 9 .
  • the inversion layer 2 is located on the entire backlight surface side of the base layer 1, and is obtained by vapor deposition.
  • the inversion layer 2 is aluminum-doped zinc oxide, which is p-type doped.
  • a silicon oxide layer 5 exists between the inversion layer 2 and the base layer 1 , and the silicon oxide layer 5 is a silicon oxide layer with a thickness of 1 nm, which is obtained by annealing after deposition and oxidation.
  • the backside passivation layer 8 is provided on the backside of the inversion layer 2 .
  • the second electrode 3 is printed on the light-facing surface of the device and dried and sintered.
  • the first electrode 4 is printed on the backlight surface of the device and dried and sintered.
  • the sintering temperature does not exceed 700°C to protect the tunnel junction interface and prevent oxide layer cracking. Interface defects.
  • the base layer 1 is n-type single crystal silicon, the light-facing surface of the base layer 1 is a textured structure, the backlight surface is a polished structure, and the doping concentration of the base layer 1 is 10 15 cm -3 -10 16 cm -3 .
  • the base layer 1 is provided with a front surface field 6 toward the light surface, and the front surface field 6 is a heavily doped layer, the doping type is the same as that of the base layer 1 , and the doping concentration is higher than that of the base layer 1 .
  • a weakly degenerate or degenerate semiconductor is formed in at least part of the inversion layer 2 , and the base layer 1 is a non-degenerate semiconductor.
  • the light-facing surface of the base layer 1 is provided with a front-facing antireflection film layer 9 .
  • the inversion layer 2 is located on the entire backlight surface side of the base layer 1, and is obtained by vapor deposition.
  • the inversion layer 2 is amorphous silicon, which is p-type doped, and the doping concentration is 10 15 cm -3 -10 18 cm -3 .
  • a passivation layer 5 exists between the inversion layer 2 and the base layer 1 , and the passivation layer 5 is an intrinsic amorphous silicon layer with a thickness of 2 nm, obtained by vapor deposition.
  • the backside passivation layer 8 is provided on the backside of the inversion layer 2 .
  • the second electrode 3 is printed on the light-facing surface of the device and dried and sintered.
  • the first electrode 4 is printed on the backlight surface of the device and dried and sintered.
  • the sintering temperature does not exceed 250°C to protect the tunnel junction interface and prevent amorphous silicon. Crystallization leads to passivation and degradation of tunnel junction performance.
  • the base layer 1 is n-type single crystal silicon
  • the backlight surface of the base layer 1 is a textured structure
  • the light-facing surface is a polished structure
  • the doping concentration of the base layer 1 is 10 16 cm -3 -10 19 cm -3 .
  • a weakly degenerate or degenerate semiconductor is formed in at least part of the base layer 1
  • the inversion layer 2 is a non-degenerate semiconductor.
  • the backside surface of the base layer 1 is provided with a back surface field 7 , which is a heavily doped layer, the doping type is the same as that of the base layer 1 , and the doping concentration is higher than that of the base layer 1 .
  • the back surface field 7 may be a complete layer, or a local area located on the backlight surface of the base layer 1 , for example, only located near the electrode position in the backlight surface of the base layer 1 .
  • the backside passivation layer 8 is provided on the backside of the base layer 1 .
  • the inversion layer 2 is located on the entire light-facing side of the base layer 1 and is obtained by an epitaxy method.
  • the inversion layer 2 is GaAs, is p-type doped (Al-doped), and the doping concentration is 10 15 cm -3 -10 17 cm -3 .
  • a buffer layer 5 exists between the inversion layer 2 and the base layer 1 , and the buffer layer 5 is a GaAs buffer layer with a thickness of 2-50 nm, which is obtained by epitaxy.
  • the light-facing surface of the inversion layer 2 is provided with a front-facing antireflection film layer 9 .
  • the second electrode 3 is printed on the light-facing surface of the device and dried and sintered, and the first electrode 4 is printed on the backlight surface of the device and dried and sintered.
  • the sintering temperature does not exceed 700°C to protect the tunnel junction interface and reduce interface diffusion.
  • the base layer 1 is n-type single crystal silicon
  • the backlight surface of the base layer 1 is a textured structure
  • the light-facing surface is a polished structure
  • the doping concentration of the base layer 1 is 10 16 cm -3 -10 19 cm -3 .
  • a weakly degenerate or degenerate semiconductor is formed in at least part of the base layer 1
  • the inversion layer 2 is a non-degenerate semiconductor.
  • the backside surface of the base layer 1 is provided with a back surface field 7 , which is a heavily doped layer, the doping type is the same as that of the base layer 1 , and the doping concentration is higher than that of the base layer 1 .
  • the back surface field 7 may be a complete layer, or a local area located on the backlight surface of the base layer 1 , for example, only located near the electrode position in the backlight surface of the base layer 1 .
  • the backside passivation layer 8 is provided on the backside of the base layer 1 .
  • the inversion layer 2 is located on the entire light-facing side of the base layer 1, and is obtained by chemical vapor deposition.
  • the inversion layer 2 is molybdenum oxide and is p-type doped.
  • a silicon oxide layer 5 exists between the inversion layer 2 and the base layer 1 , and the silicon oxide layer 5 is a silicon oxide layer with a thickness of 1 nm, which is obtained by depositing molybdenum oxide and then annealing.
  • the light-facing surface of the inversion layer 2 is provided with a front-facing antireflection film layer 9 .
  • the second electrode 3 is printed on the light-facing surface of the device and dried and sintered, and the first electrode 4 is printed on the backlight surface of the device and dried and sintered.
  • the sintering temperature does not exceed 700°C to protect the tunnel junction interface and reduce interface diffusion.
  • the base layer 1 is n-type single crystal silicon
  • the backlight surface of the base layer 1 is a textured structure
  • the light-facing surface is a polished structure
  • the doping concentration of the base layer 1 is 10 16 cm -3 -10 19 cm -3 .
  • a weakly degenerate or degenerate semiconductor is formed in at least part of the base layer 1
  • the inversion layer 2 is a non-degenerate semiconductor.
  • the backside surface of the base layer 1 is provided with a back surface field 7 , which is a heavily doped layer, the doping type is the same as that of the base layer 1 , and the doping concentration is higher than that of the base layer 1 .
  • the back surface field 7 may be a complete layer, or a local area located on the backlight surface of the base layer 1 , for example, only located near the electrode position in the backlight surface of the base layer 1 .
  • the backside passivation layer 8 is provided on the backside of the base layer 1 .
  • the inversion layer 2 is located on the entire light-facing side of the base layer 1, and is obtained by chemical vapor deposition.
  • the inversion layer 2 is hydrogen-containing amorphous silicon, which is p-type doped with a doping concentration of 10 13 cm -3 -10 18 cm -3 .
  • a passivation layer 5 exists between the inversion layer 2 and the base layer 1 , and the passivation layer 5 is an intrinsic hydrogen-containing amorphous silicon layer with a thickness of 2 nm, obtained by chemical vapor deposition.
  • the light-facing surface of the inversion layer 2 is provided with a front-facing antireflection film layer 9 .
  • the second electrode 3 is printed on the light-facing surface of the device and dried and sintered.
  • the first electrode 4 is printed on the backlight surface of the device and dried and sintered.
  • the sintering temperature does not exceed 250°C to prevent the interface passivation failure caused by the crystallization of amorphous silicon. .
  • the base layer 1 is n-type single crystal silicon
  • the light-facing surface of the base layer 1 is a textured structure
  • the backlight surface is a polished structure
  • the doping concentration of the base layer 1 is 10 13 cm -3 -10 20 cm -3 , for conventional doping.
  • a weakly degenerate or degenerate semiconductor is formed in at least part of the inversion layer 2
  • the base layer 1 is a non-degenerate semiconductor. More preferably, the doping concentration is 10 13 cm -3 -10 16 cm -3 .
  • the base layer 1 is provided with a front surface field 6 toward the light surface, and the front surface field 6 is a heavily doped layer, the doping type is the same as that of the base layer 1 , and the doping concentration is higher than that of the base layer 1 .
  • the light-facing surface of the base layer 1 is provided with a front-facing antireflection film layer 9 .
  • the inversion layer 2 is located in a local area of the backlight surface of the base layer 1.
  • the projection of the inversion layer 2 on the backlight surface of the base layer 1 accounts for 50-95% of the backlight surface of the base layer 1.
  • the inversion layer 2 is formed by vapor deposition. method to obtain.
  • the inversion layer 2 is amorphous silicon, which is p-type doped, and the doping concentration is 10 15 cm -3 -10 18 cm -3 .
  • the backside surface of the base layer 1 is provided with a back surface field 7 , which is a heavily doped layer, the doping type is the same as that of the base layer 1 , and the doping concentration is higher than that of the base layer 1 .
  • the backside passivation layer 8 is provided on the backside of the inversion layer 2 .
  • the second electrode 3 is printed on the area of the backlight surface of the device opposite to the inversion layer 2
  • the first electrode 4 is printed on the remaining area of the backlight surface of the device, and dried and sintered
  • the first electrode 4 is printed on the backlight surface of the device and baked Drying and sintering, and the sintering temperature should not exceed 250 °C to protect the tunnel junction interface and prevent the crystallization of amorphous silicon from causing passivation and degradation of tunnel junction performance.
  • FIG. 8 shows a schematic structural diagram of a sixth type of solar cell in an embodiment of the present disclosure.
  • the solar cell includes: a PN junction.
  • the PN junction includes a base layer 1 and an inversion layer 2.
  • the doping types of the base layer 1 and the inversion layer 2 are different, that is, the doping type of one of the base layer 1 and the inversion layer 2 is P type, and the other is the doping type.
  • the doping type is N-type, and there is no specific limitation as to which of the two doping types is P-type. For example, if the doping type of the base layer 1 in FIG. 8 is N-type, the doping type of the inversion layer 2 is P-type.
  • the inversion layer 2 is disposed on the back light side or the light facing side of the base layer 1 . As shown in FIG. 8 , the inversion layer 2 is disposed on the backlight surface of the base layer 1 .
  • FIG. 9 shows a schematic structural diagram of a seventh solar cell in an embodiment of the present disclosure. In FIG. 9 , the inversion layer 2 is disposed on the light-facing surface of the base layer 1 .
  • the inversion layer 2 has a first heavily doped region 3', the first heavily doped region 3' extends from the side of the inversion layer 2 away from the base layer 1 into the inversion layer 2, and the first heavily doped region 3'
  • the depth of inward extension is not particularly limited.
  • the first heavily doped region 3 ′ has the same doping type as the inversion layer 2 .
  • the doping type of the inversion layer 2 is P-type, and the doping type of the first heavily doped region 3 ′ is also P-type.
  • the thickness difference h1 between the inversion layer 2 and the first heavily doped region 3' is 1 nm-100 nm, then the first heavily doped region 3' and the pn junction
  • the distance at the interface is 1nm-100nm, which can reduce the recombination at the interface and reduce the carrier non-local transition current.
  • the thickness difference h1 between the inversion layer 2 and the first heavily doped region 3 ′ may be 1 nm-50 nm.
  • Tm characterizes room temperature, and at room temperature Tm , the first heavily doped region 3' forms a weakly degenerate or degenerate semiconductor. That is to say, under the condition of room temperature Tm , the doping concentration of the first heavily doped region 3' is relatively high, forming a weakly degenerate or degenerate semiconductor.
  • the rest of the inversion layer 2 and the base layer 1 are both non-degenerate semiconductors,
  • the rest of the inversion layer 2 and the base layer 1 are both non-degenerate semiconductors, that is, the rest of the inversion layer 2 and the base layer 1 have lower doping concentrations and are non-degenerate semiconductors.
  • the first heavily doped region 3' forms a weakly degenerate or degenerate semiconductor, which is specifically set as the Fermi level of the first heavily doped region 3' and the bottom of the conduction band of the n-type semiconductor or the top of the valence band of the p-type semiconductor
  • the energy level difference is less than 2k B ⁇ T m , where k B is the Boltzmann constant (Boltzmann constant) in this formula, and the value of k B is 1.380649 ⁇ 10 -23 J/K.
  • the PN junction formed by the above-mentioned base layer 1 and the inversion layer 2 exists as a general PN junction when a forward voltage is applied, and is used for carrier separation.
  • the base layer 1, the inversion layer 2, and the first heavily doped region 3' form a heavily doped junction.
  • the heavily doped junction When a reverse voltage is applied, the heavily doped junction will exist as a tunnel junction, and a tunnel current will be formed in the PN junction. And reverse conduction, and no reverse breakdown, in the case of applying forward voltage, it returns to the general PN junction.
  • the heavily doped junction In the case of an abnormality, the heavily doped junction will exist as a tunnel junction, will not be broken down, and will not affect the output of the entire solar cell string connected in series with the solar cell.
  • the battery string does not need a parallel bypass diode, the packaging loss is small, and the size of the junction box can be reduced; on the other hand, when an abnormality occurs, the rest of the solar cells in the battery string allow normal current to pass through, only the output of the abnormal solar cell The current is affected, the loss of current is less, the heat generation is less, the hot spot effect is minimized, and the reliability and long-term stability are higher, and the power drop of the components is also less.
  • the base layer 1, the inversion layer 2, and the first heavily doped region 3' constitute a heavily doped junction.
  • the doped junction can become a tunnel junction, allowing reverse current to pass.
  • carriers can be avoided or reduced from the first heavily doped region 3' to the base layer 1 A non-local transition occurs, the interface leakage current is reduced, and a higher photoelectric conversion efficiency can be obtained.
  • the inversion layer 2 of the heavily doped junction is n-type
  • the first heavily doped region 3' is an n+ region.
  • the photoexcited electrons flow from the p-type region to the n-type region, and are collected and exported from the n+ region.
  • the device is abnormal, that is, when it is subjected to reverse voltage, the output voltage drops, and the device in series with it works normally, so the electron flow in the device is changed from the n+ region to the p-type region, and the existing conventional pn junction will be at this time. Turn-off occurs and the current cannot pass, but electrons in the embodiments of the present disclosure can flow from the n+ region to the p region by means of the tunneling recombination mechanism, conduct reverse conduction, and are not reversely broken down.
  • the first heavily doped region 3 ′ is disposed in a local region of the inversion layer 2 by means of ion implantation or laser implantation.
  • the projected area of the first heavily doped region 3 ′ on the light-facing surface of the base layer 1 accounts for 5% of the projected area of the inversion layer 2 on the light-facing surface of the base layer 1 .
  • the projection of the first heavily doped region 3' on the light-facing surface of the base layer 1 is a dot-shaped or linear pattern, and the first heavily doped region 3' can also be used as a selective contact structure, which is beneficial to carriers. collection.
  • the material of the base layer 1 is selected from: crystalline silicon, such as monocrystalline silicon or polycrystalline silicon, the doping concentration can be 1 ⁇ 10 13 cm -3 -1 ⁇ 10 16 cm -3 , or, the doping concentration of the base layer 1 can be The impurity concentration may be 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 . It should be noted that, if the doping concentration of the base layer 1 is relatively high, in the case of applying a reverse voltage to the heavily doped junction, the overall resistance of the tunnel junction is relatively small, and the conduction capability is relatively strong.
  • the material of the inversion layer 2 is selected from at least one of crystalline silicon, amorphous silicon, transition metal oxide semiconductor material, and III-V semiconductor material.
  • the material of the inversion layer 2 is crystalline silicon carbide or amorphous silicon carbide.
  • the material of the inversion layer 2 can be a transition metal oxide semiconductor material, such as zinc oxide (aluminum-doped), tin oxide, titanium oxide, molybdenum oxide, and the like.
  • the material of the inversion layer 2 may be a III-V semiconductor material, such as gallium arsenide, indium phosphide, and the like.
  • the doping concentration of the inversion layer 2 is not limited.
  • the material of the first heavily doped region 3 ′ is selected from at least one of crystalline silicon, amorphous silicon, transition metal oxide semiconductor material, and III-V semiconductor material, and the material of the first heavily doped region 3 ′ is selected from: Higher doping concentrations require the formation of weakly degenerate or degenerate semiconductors.
  • the material of the first heavily doped region 3 ′ and the material of the inversion layer 2 may be the same or different.
  • the inversion layer 2 is arranged on the entire area on one side of the base layer 1 , the first electrode 4 is arranged on the first heavily doped region 3 ′, and the second electrode 5 ′ is arranged on the first heavily doped region 3 ′.
  • a double-sided battery is further formed on the base layer 1.
  • the inversion layer 2 is disposed on the entire area of the backlight surface of the base layer 1 , the first electrode 4 is disposed on the first heavily doped region 3 ′, and the second electrode 5 ′ is disposed on the base layer 1 , forming a bifacial cell.
  • the inversion layer 2 is provided on the entire area of the base layer 1 facing the light surface.
  • FIG. 10 shows a schematic structural diagram of an eighth solar cell in an embodiment of the present disclosure.
  • one side of the base layer 1 is divided into a first area and a second area, and the inversion layer 2 is disposed in the first area on one side of the base layer 1 , that is, the inversion layer 2 is only provided in a partial area on one side of the base layer 1 .
  • the solar cell further includes: a second heavily doped region 8 ′, and the second heavily doped region 8 ′ is located in the second region, that is to say, the second heavily doped region 8 ′ and the inversion layer 2 are located on the same side of the base layer 1 , and the second heavily doped region 8 ′ is located in the region where the inversion layer 2 is not provided on one side of the base layer 1 .
  • the second heavily doped region 8 ′ has the same doping type as the base layer 1 , and the doping concentration is higher than that of the base layer.
  • the doping types of the base layer 1 and the second heavily doped region 8 ′ are both N-type, and the doping concentration of the second heavily doped region 8 ′ is greater than that of the base layer 1 .
  • the relative sizes of the first area and the second area are not specifically limited.
  • the area of the area for collecting and/or transporting minority carriers may be larger than the area for collecting and/or transporting majority carriers to facilitate the collection and/or transport of minority carriers.
  • the solar cell shown in FIG. 10 further includes: a first electrode 4 and a second electrode 5 ′, the first electrode 4 is arranged on the first heavily doped region 3 ′, and the second electrode 5 ′ is arranged on the second heavily doped region 8', a single-sided battery is formed.
  • the solar cell shown in FIG. 10 further includes a blocking structure 9 ′, and the blocking structure 9 ′ is located between the second heavily doped region 8 ′ and the inversion layer 2 to avoid leakage.
  • the blocking structure 9' may be an insulating gap, or the blocking structure 9' is formed of a dielectric material, so that not only the insulation effect is good, but also the blocking structure 9' is easy to obtain.
  • the subsequent process temperature needs to be controlled. Too high subsequent process temperature will cause element diffusion or interface layer cracking at the PN junction interface, which will destroy the PN junction interface and lead to decreased efficiency.
  • electrodes are printed on the surface of the PN junction, dried and sintered, and the sintering temperature does not exceed 500 °C to protect the PN junction interface and reduce interface diffusion.
  • the backlight surface of the base layer 1 is a plane structure or a light trapping structure, and/or the light-facing surface of the base layer 1 is a plane structure or a light trapping structure, and the inversion layer 2 in contact with it is adapted to the surface structure of the base layer 1. .
  • the light-facing surface of the PN junction is provided with an upper surface functional layer 6 ′, and the upper surface functional layer 6 ′ can be a front passivation layer, a front anti-reflection film layer, and a scattering structure layer.
  • the upper surface functional layer 6 ′ can be a front passivation layer, a front anti-reflection film layer, and a scattering structure layer.
  • at least one of the light-gathering structure layers; and/or, a lower surface functional layer 7 ′ is provided on the backlight surface of the PN junction, and the lower surface functional layer 7 ′ can be a back passivation layer, a back anti-reflection film layer, a scattering At least one of a structural layer and a light-concentrating structural layer.
  • Embodiments of the present disclosure also provide a battery assembly, comprising: any of the foregoing solar cells.
  • a battery assembly comprising: any of the foregoing solar cells.
  • no parallel bypass diodes are required in each battery string.
  • FIG. 11 shows a schematic structural diagram of a ninth solar cell in an embodiment of the present disclosure.
  • the base layer 1 adopts an n-type single crystal silicon wafer, the doping concentration is 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is 150 ⁇ m.
  • the inversion layer 2 is located on the entire backlight surface of the base layer 1, and is diffused into a p-type layer by using a shallow junction process. The average depth of the inversion layer 2 is 100 nm.
  • a first heavily doped region 3 ′ is provided under the inversion layer 2 by ion implantation or a laser process. The doping concentration of the first heavily doped region 3 ′ is 1 ⁇ 10 18 cm ⁇ 3 . In the direction away from the base layer 1 , the thickness difference between the inversion layer 2 and the first heavily doped region 3 ′ is 10 nm.
  • the base layer 1 is an n-type single crystal silicon wafer, the doping concentration is 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is 150 ⁇ m. Both the light-facing surface and the back-lighting surface of the base layer 1 are suede structures.
  • the inversion layer 2 is located on the entire light-facing surface of the base layer 1, and is diffused into a p-type layer by using a shallow junction process.
  • the average depth of the inversion layer 2 is 700 nm.
  • a laser process is used in the inversion layer 2 to form a first heavily doped region 3'.
  • the doping concentration of the first heavily doped region 3 ′ is 1 ⁇ 10 18 cm ⁇ 3 , and along the direction away from the base layer 1 , the thickness difference between the inversion layer 2 and the first heavily doped region 3 ′ is 50 nm.
  • the base layer 1 adopts an n-type single crystal silicon wafer, the doping concentration is 0.5 ⁇ 10 16 cm ⁇ 3 , and the thickness is 100 ⁇ m.
  • the light-facing surface of the base layer 1 has a textured structure and may have a front surface field.
  • the inversion layer 2 is located in a local area of the backlight surface of the base layer 1, and is diffused into a p-type layer by using a shallow junction process.
  • the average depth of the inversion layer 2 is 100 nm.
  • a second heavily doped region 8' is provided on the backside of the base layer 1, except for the rest of the inversion layer 2, a second heavily doped region 8' is provided.
  • the second heavily doped region 8' is n-type doped, and the doping concentration is higher than that of the base layer 1. concentration.
  • a blocking structure 9' is disposed between the second heavily doped region 8' and the inversion layer 2, and the blocking structure 9' is an insulating gap or a dielectric material.
  • a first heavily doped region 3 ′ is provided under the inversion layer 2 by ion implantation or a laser process.
  • the doping concentration of the first heavily doped region 3 ′ is 1 ⁇ 10 18 cm ⁇ 3 .
  • the thickness difference between the inversion layer 2 and the first heavily doped region 3 ′ is 10 nm.

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Abstract

本公开提供了太阳电池及电池组件，涉及光伏技术领域。太阳电池包括PN结；PN结由基体层以及反型层形成；室温T m下，基体层和反型层中位于背光一侧者至少部分区域形成弱简并或简并半导体，部分区域从基体层和反型层中位于背光一侧者的向光面向层内延伸；基体层和反型层中位于向光一侧者为非简并半导体；弱简并或简并半导体设置为，费米能级与n型半导体的导带底或p型半导体的价带顶的能级差小于2k B×T m。在施加反向电压的情况下PN结会作为隧道结反向偏置，PN结中形成隧道电流，反向导通，由该太阳电池形成的电池串无需并联旁路二极管，封装损失小，接线盒尺寸小；在出现异常时，损失电流少，发热少，具备更高可靠性和长期稳定性。

Description

太阳电池及电池组件
相关申请的交叉引用
本公开要求在2020年12月03日提交中国专利局、申请号为202011395240.8、名称为“太阳电池及电池组件”，以及在2020年12月24日提交中国专利局、申请号为202011555929.2、名称为“太阳电池及电池组件”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及光伏技术领域，特别是涉及一种太阳电池及电池组件。
背景技术
PN结太阳电池具有正向导通反向截止的特性，由PN结太阳电池形成的电池组件在某一个PN结太阳电池出现异常情况下，与该PN结太阳电池串联的整个PN结太阳电池串的输出电流受到很大影响，且容易造成电池组件损坏。
目前，通过为PN结太阳电池串设置并联的旁路二极管，以解决上述问题。然而，旁路二极管导通时组件功率下降多、二极管发热较为严重，容易引起严重的安全隐患。
概述
本公开提供一种太阳电池及电池组件，旨在解决PN结太阳电池串设置并联的旁路二极管导通时，组件功率下降多、二极管发热严重的问题。
根据本公开的第一方面，提供了一种太阳电池，包括PN结；所述PN结由基体层以及反型层形成；所述基体层与所述反型层的掺杂类型不同；
室温T m下，所述基体层和所述反型层中位于背光一侧者至少部分区域形成弱简并或简并半导体，所述部分区域从所述基体层和所述反型层中位于背光一侧者的向光面向层内延伸；
所述基体层和所述反型层中位于向光一侧者为非简并半导体；
所述弱简并或简并半导体设置为，费米能级与n型半导体的导带底或p型半导体的价带顶的能级差小于2k B×T m。本公开实施方式中的PN结，在施 加正向电压的情况下，作为一般的PN结存在，用于分离载流子。在施加反向电压的情况下，PN结会作为隧道结存在，会反向偏置，PN结中形成隧道电流，并反向导通，在施加正向电压的情况下，又恢复为一般的PN结存在。而在出现异常的情况下，就会在PN结上施加反向电压，即，PN结在出现异常的情况，会作为隧道结存在，不会被击穿，不会影响与该PN结太阳电池串联的整个太阳电池串的输出，一方面由该太阳电池形成的电池串无需并联旁路二极管，封装损失小，可以减小接线盒的尺寸；另一方面，在出现异常时，电池串中其余太阳电池均允许正常电流通过，仅是出现异常的太阳电池的输出电流受影响，损失的电流少，发热少，具备更高的可靠性和长期稳定性，组件功率下降也少。可选的，由上述太阳电池形成的电池组件可采用侧面接线盒，背板无需开孔，工艺简单，成本低。而且，基体层和反型层中位于向光一侧者为非简并半导体，吸光性能较好，复合也较低。
可选的，所述反型层的材料选自：III-V化合物半导体、氧化物半导体、非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种；
所述基体层的材料选自：晶体硅、III-V化合物半导体、氧化物半导体、非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种。
可选的，所述反型层的位于背光侧，其中，以下材料作为反型层时，
III-V化合物半导体的掺杂浓度为10 17cm -3-10 21cm -3；
氧化物半导体的施主缺陷或受主缺陷浓度为10 16cm -3-10 21cm -3；
反型层采用非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种的情况下，所述反型层的掺杂浓度为10 15cm -3-10 18cm -3。
可选的，所述基体层位于背光侧，其中，以下材料作为基体层时，
晶体硅的掺杂浓度为10 16cm -3-10 20cm -3；
III-V化合物半导体的掺杂浓度为10 17cm -3-10 21cm -3；
氧化物半导体的施主缺陷或受主缺陷浓度为10 16cm -3-10 21cm -3；
基体层选自非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种的情况下，所述基体层的掺杂浓度为10 15cm -3-10 18cm -3。
可选的，在所述反型层位于所述基体层的整个背光面；所述基体层为晶体硅，晶体硅的掺杂浓度为10 13cm -3-10 16cm -3；或，
所述反型层位于所述基体层的背光面的局部区域，所述基体层为晶体硅， 晶体硅的掺杂浓度为10 13cm -3-10 20cm -3。
可选的，所述反型层位于所述基体层的背光面的局部区域，所述基体层为晶体硅，在所述局部区域所述晶体硅靠近所述反型层一侧的掺杂浓度大于相对的一侧。
可选的，所述反型层的材料选自III-V化合物半导体，所述基体层以及所述反型层之间还设置有缓冲层；所述缓冲层的厚度为0.1-50nm，所述缓冲层的材料选自：锗晶体、硅锗化合物、III-V化合物中的一种。
可选的，所述反型层的材料为氧化物半导体，所述基体层以及所述反型层之间还设置有氧化硅层；所述氧化硅层的厚度为0.1-10nm。
可选的，所述反型层的材料选自：非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种，所述基体层以及所述反型层之间还设置有钝化层；所述钝化层的厚度为0.1-10nm，所述钝化层的材料选自：本征非晶硅、纳米晶硅或氧化硅。
可选的，所述III-V化合物半导体选自：GaAs、InAs、InP、GaP、AlP、AlAs中的至少一种；
所述氧化物半导体选自：第一材料或所述第一材料与第二材料的掺杂化合物；所述第一材料选自：氧化钛、氧化锌、氧化锡、氧化镍、氧化铜、氧化钨、氧化钼、氧化钒中的至少一种；所述第二材料选自：卤族元素、过渡金属元素、碱金属元素、稀土元素、III族元素、IV族元素、V族元素中的至少一种。
可选的，在所述反型层位于所述基体层的背光面的局部区域的情况下，所述反型层在所述基体层的背光面的投影的面积，占所述基体层的背光面的总面积的50％至95％。
根据本公开的第二方面，还提供一种电池组件，包括：任一前述的太阳电池。
上述电池组件，具有与前述太阳电池相同或相似的有益效果。
根据本公开的第三方面，提供了一种太阳电池，包括PN结，所述PN结由基体层以及反型层形成，所述基体层与所述反型层的掺杂类型不同；所述反型层具有第一重掺杂区域，所述第一重掺杂区域从所述反型层远离所述基体层的一侧向所述反型层内延伸，所述第一重掺杂区域与所述反型层的掺杂 类型相同；
沿远离所述基体层的方向，所述反型层与所述第一重掺杂区域的厚度差为1-100nm；
室温T m下，所述第一重掺杂区域形成弱简并或简并半导体，所述反型层的其余部分和所述基体层均为非简并半导体，所述弱简并或简并半导体设置为，费米能级与n型半导体的导带底或p型半导体的导带顶的能级差小于2k B×T m。
本公开实施方式中，第一重掺杂区域从反型层远离基体层的一侧向反型层内延伸，沿远离基体层的方向，反型层与第一重掺杂区域的厚度差为1-100nm，则第一重掺杂区域与pn结界面处的距离为1-100nm，可以减少界面处的复合，并降低载流子非局域跃迁电流。本公开实施方式中的PN结，在施加正向电压的情况下，作为一般的PN结存在，用于分离载流子。基体层、反型层、第一重掺杂区域形成重掺杂结，在施加反向电压的情况下，该重掺杂结会作为隧道结存在，PN结中形成隧道电流，并反向导通，并没有被反向击穿，在施加正向电压的情况下，又恢复为一般的PN结存在。而在出现异常的情况下，该重掺杂结又会作为隧道结存在，不会被击穿，不会影响与该太阳电池串联的整个太阳电池串的输出，一方面由该太阳电池形成的电池串无需并联旁路二极管，封装损失小，可以减小接线盒的尺寸；另一方面，在出现异常时，电池串中其余太阳电池均允许正常电流通过，仅是出现异常的太阳电池的输出电流受影响，损失的电流少，发热少，最大程度上降低了热斑效应，具备更高的可靠性和长期稳定性，组件功率下降也少。可选的，由上述太阳电池形成的电池组件的背板无需开孔，工艺简单，成本低。
根据本公开的第四方面，还提供一种电池组件，包括：任一前述的太阳电池。
上述电池组件，具有与前述太阳电池相同或相似的有益效果。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本公开实施方式的技术方案，下面将对本公开实施方式的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开实施方式中的第一种太阳电池的结构示意图；
图2示出了本公开实施方式中的第二种太阳电池的结构示意图；
图3示出了本公开实施方式中的第三种太阳电池的结构示意图；
图4示出了本公开实施方式中的第四种太阳电池的结构示意图；
图5示出了本公开实施方式中的第五种太阳电池的结构示意图；
图6示出了本公开实施方式中的一种电池组件的结构示意图；
图7示出了本公开实施方式中的一种电池组件的电路示意图；
图8示出了本公开实施方式中的第六种太阳电池的结构示意图；
图9示出了本公开实施方式中的第七种太阳电池的结构示意图；
图10示出了本公开实施方式中的第八种太阳电池的结构示意图；
图11示出了本公开实施方式中的第九种太阳电池的结构示意图。
附图编号说明：
1-基体层，2-反型层，3-第二电极，4-第一电极，5-缓冲层、第一钝化层、第二钝化层中的一种，6-前表面场，7-背表面场，8-背面钝化层，9-正面减反射薄膜层，3'-第一重掺杂区域，5'-第二电极，6'-上表面功能层，7'-下表面功能层，8'-第二重掺杂区域，9'-阻断结构。
具体实施例
下面将结合本公开实施方式中的附图，对本公开实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式是本公开一部分实施方式，而不是全部的实施方式。基于本公开中的实施方式，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施方式，都属于本公开保护的范围。
发明人发现，现有技术中在某一个PN结太阳电池出现异常情况下，电池 串的输出电流受到很大影响，且容易造成电池组件损坏的原因在于：当某一片PN结太阳电池破损、被遮挡等异常情况下，电池串中该片太阳电池输出电流及电压下降，其余太阳电池均正常输出，此时异常太阳电池处于反向偏置状态，但由于其反向截止的特性不允许电池串中其余太阳电池的电流通过，异常太阳电池需要消纳整串电池串的富余输出功率。为了解决这个问题，现有技术中，为电池串并联旁路二极管，在正常运行时，旁路二极管处于反向截止状态，在出现异常时，旁路二极管会正向偏置导通，短路掉异常的太阳电池所在的电池串，以保护受损的太阳电池。但是当旁路二极管正向偏置导通的情况下，异常的太阳电池所在的电池串的输出功率受到限制，异常的太阳电池所在的电池串的输出功率均不会作为电池组件的输出功率，导通的旁路二极管需要通过较大的电流，同时二极管所在环境散热较差，使得旁路二极管及接线盒发热严重，容易引发严重的电气安全隐患，甚至发生火灾。
在本公开实施方式中，参照图1所示，图1示出了本公开实施方式中的第一种太阳电池的结构示意图。该太阳电池包括：PN结。PN结由基体层1以及反型层2组成，基体层1和反型层2的掺杂类型不同，即基体层1以及反型层2两者中一个的掺杂类型为P型，另一个的掺杂类型为N型，至于两者中哪个的掺杂类型是P型不作具体限定。例如，若图1中基体层1的掺杂类型为N型，则，反型层2的掺杂类型即为P型。反型层2设置在基体层1的背光面或向光面。如图1所示，反型层2设置在基体层1的背光面。参照图2所示，图2示出了本公开实施方式中的第二种太阳电池的结构示意图。图2中，反型层2设置在基体层1的向光面。
T m表征室温，室温T m下，基体层1和反型层2中位于背光一侧者至少部分区域形成弱简并或简并半导体。就是说，室温T m情况下，基体层1和反型层2两者中位于背光一侧的一个的至少部分区域掺杂浓度较高，形成弱简并或简并半导体。至少部分区域的大小不作具体限定。具体是在基体层1和反型层2两者中位于背光一侧的一个中靠近PN结的区域形成弱简并或简并半导体，基体层1和反型层2两者即可形成隧道结。基体层1和反型层2中位于背光一侧者的向光面为基体层1和反型层2中位于背光一侧者中，与另一个接触的界面。部分区域从基体层1和反型层2中位于背光一侧者的向光面向层内延伸，延伸的深度不作具体限定。
基体层1和反型层2中位于向光一侧者掺杂浓度较低，为非简并半导体。基体层1和反型层2中位于向光一侧者掺杂浓度较低，吸光性能较好，复合也较低。
基体层1和反型层2中位于背光一侧者中形成弱简并或简并半导体设置为，费米能级与n型半导体的导带底或p型半导体的价带顶的能级差小于2k B×T m，该公式中k B为玻尔兹曼常数(Boltzmann constant)，k B取值为1.380649×10 -23J/K。由上述基体层1和反型层2形成的PN结，在施加正向电压的情况下，作为一般的PN结存在，用于分离载流子。在施加反向电压的情况下，PN结会作为隧道结存在，会反向偏置，PN结中形成隧道电流，并反向导通，并没有被反向击穿，在施加正向电压的情况下，又恢复为一般的PN结存在。而在出现异常的情况下，就会在PN结上施加反向电压，即，PN结在出现异常的情况，会作为隧道结存在，不会被击穿，不会影响与该PN结太阳电池串联的整个太阳电池串的输出，一方面由该太阳电池形成的电池串无需并联旁路二极管，封装损失小，可以减小接线盒的尺寸；另一方面，在出现异常时，电池串中其余太阳电池均允许正常电流通过，仅是出现异常的太阳电池的输出电流受影响，损失的电流少，发热少，具备更高的可靠性和长期稳定性，组件功率下降也少。
例如，若电池组件包括由60个太阳电池形成的3个电池串，每个电池串中由20个太阳电池串联。若1个电池串中的某一个太阳电池出现异常，现有技术中，异常太阳电池处于反向偏置状态，不允许该异常太阳电池所在电池串中其余太阳电池的电流通过，输出功率损失大致为1/3。而本公开中，当该太阳电池出现异常时，该太阳电池中的PN结会作为隧道结存在，会反向偏置进而反向导通，PN结中形成隧道电流，与该太阳电池串联的其他太阳电池的电流可以通过该太阳电池，该太阳电池仅作为电阻存在于电池串中，输出功率损失大致为1/60。
如，参照图1所示，反型层2设置在基体层1的背光面。反型层2中至少部分区域掺杂浓度较高，形成弱简并或简并半导体。反型层2中形成弱简并或简并半导体的区域从反型层2的向光面向层内延伸。基体层1和反型层2两者中位于向光一侧的就是基体层1。基体层1掺杂浓度较低，为非简并半导体。反型层2中形成弱简并或简并半导体的区域，费米能级与n型半导体的 导带底或p型半导体的价带顶的能级差小于2k B×T m。
再例如，参照图2所示，反型层2设置在基体层1的向光面。基体层1中至少部分区域掺杂浓度较高，形成弱简并或简并半导体。基体层1中形成弱简并或简并半导体的区域从基体层1的向光面向层内延伸。反型层2掺杂浓度较低，为非简并半导体。反基体层1中形成弱简并或简并半导体的区域，费米能级与n型半导体的导带底或p型半导体的价带顶的能级差小于2k B×T m。
可选的，反型层2的材料选自：III-V化合物半导体、氧化物半导体、非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种。基体层1的材料选自：晶体硅、III-V化合物半导体、氧化物半导体、非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种。上述的III-V化合物半导体、氧化物半导体、非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅均为遂穿效率高的直接带隙半导体，进而上述材料形成的PN结在作为隧道结存在时，可以实现更高的光电转换效率和较大的反向隧道电流。
可选的，在反型层2位于基体层1的背光面的情况下，在反型层2的材料选自III-V化合物半导体的情况下，III-V化合物半导体的掺杂浓度为10 17cm -3-10 21cm -3，即接近简并态。在反型层2的材料选自氧化物半导体的情况下，氧化物半导体的施主缺陷或受主缺陷浓度为10 16cm -3-10 21cm -3。在反型层2的材料选自非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种的情况下，反型层2的掺杂浓度为10 15cm -3-10 18cm -3。上述材料的反型层2，在PN结施加反向电压的情况下，易于反向导通，而且遂穿效率高。
可选的，基体层1位于背光侧，即在反型层2位于基体层1的向光面的情况下，在基体层1的材料选自晶体硅的情况下，晶体硅的掺杂浓度为10 16cm -3-10 20cm -3，接近简并态。在基体层1的材料选自III-V化合物半导体的情况下，III-V化合物半导体的掺杂浓度为10 17cm -3-10 21cm -3。在基体层1的材料选自氧化物半导体的情况下，氧化物半导体的施主缺陷或受主缺陷浓度为10 16cm -3-10 21cm -3。在基体层1的材料选自非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种的情况下，基体层1的掺杂浓度为10 15cm -3-10 18cm -3，上述材料的基体层1和反型层2，在PN结施加反向电压的情况下，易于反向导通，而且遂穿效率高。
本公开实施例中的PN结，当该太阳电池出现异常时，通过测试，该太阳 电池中的PN结会作为隧道结存在，会反向偏置进而反向导通，PN结中形成隧道电流，其自身光生电流下降，与该太阳电池串联的其他太阳电池的电流可以通过该太阳电池，该太阳电池仅作为电阻存在于电池串中，其发热功率与现有技术相比十分微弱，进而无需并联旁路二极管，封装损失小，可以减小接线盒的尺寸；同时，在出现异常时，电池串中其余太阳电池均允许正常电流通过，仅是出现异常的太阳电池的输出电流受影响，损失的电流少，发热少，具备更高的可靠性和长期稳定性，组件功率下降也少。当反向电压继续增大时，隧道电流可以持续增加，该PN结并没有被击穿，表现为解除反向偏置状态时，即太阳电池恢复正常运行状态，PN结可以恢复正常工作状态，即又恢复为一般的PN结存在。而且，上述PN结降低了体区复合与寄生性吸收，延伸的空间电荷区扩展了界面区域的禁带宽度，抑制了正常情况下自发的界面隧穿复合。同时，上述的III-V化合物半导体、氧化物半导体、非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅均为遂穿效率高的直接带隙半导体，进而上述材料形成的PN结在作为隧道结存在时，可以实现更高的光电转换效率和较大的反向隧道电流。
可选的，III-V化合物半导体选自：GaAs(砷化镓)、InAs(砷化锢)、InP(磷化铟)、GaP(磷化镓)、AlP(磷化铝)、AlAs(砷化铝)中的至少一种。
可选的，氧化物半导体具体指过渡金属氧化物半导体，具体选自：第一材料或该第一材料与第二材料的掺杂化合物。该第一材料选自：氧化钛、氧化锌、氧化锡、氧化镍、氧化铜、氧化钨、氧化钼、氧化钒中的至少一种。该第二材料选自：卤族元素、过渡金属元素、碱金属元素、稀土元素、III族元素、IV族元素、V族元素中的至少一种。
可选的，反型层2通过外延、沉积、掺杂三种方式中的一种方式，设置在基体层1的背光面或向光面。外延生长得到的反型层2在界面处具备陡峭的掺杂元素扩散界面，以缩减空间电荷区一侧的宽度，提高反向状态下隧穿复合几率，且外延界面缺陷较少，保证了在外延侧陡峭的空间电荷区以及能带变化响应，确保较低的反向导通电阻，因此，外延生长可以为优选工艺。除外延外，还可采用精确的掺杂工艺如离子注入或快速热扩散等工艺，还可以采用沉积后晶化的工艺。
可选的，参照图1所示，反型层2设置在基体层1的整个背光面，进而利于少数载流子的传输和收集。在反型层2设置在基体层1的整个背光面且基体层1的材料选自晶体硅的情况下，晶体硅的掺杂浓度为10 13cm -3-10 16cm -3，可以降低体区复合和寄生性吸收。第一电极4设置在反型层2的背光面，第二电极3设置在基体层1的向光面。
可选的，参照图2所示，在反型层2设置在基体层1的整个向光面的情况下，第一电极4设置在基体层1的背光面，第二电极3设置在反型层2的向光面。
可选的，参照图3所示，图3示出了本公开实施方式中的第三种太阳电池的结构示意图。反型层2位于基体层1的背光面的局部区域，也就是说反型层2并没有覆盖基体层1的全部背光面，基体层1的材料选自晶体硅的情况下，晶体硅的掺杂浓度为10 13cm -3-10 20cm -3。太阳电池还包括：第一电极4和第二电极3，第一电极4设置在反型层2的背光面上，第二电极3设置在基体层1的背光面中反型层2之外的区域，进而，电极完全不遮挡向光面，利于提升太阳电池的输出功率。
可选的，参照图3所示，反型层2位于基体层1的背光面的局部区域，基体层1为晶体硅，在基体层1局部区域的晶体硅靠近反型层2一侧的掺杂浓度大于相对的一侧。即，反型层2位于基体层1的背光面的局部区域，基体层1为晶体硅，在基体层1局部区域的晶体硅靠近反型层2一侧的掺杂浓度大于远离反型层2的一侧，利于保证光的入射量。
需要说明的是，PN结形成后，需控制后续工艺温度，过高的后续工艺温度会导致PN结界面发生元素扩散或界面层裂解，破坏PN结界面，导致效率下降。
可选的，参照图3所示，在反型层2设置在基体层1的背光面的局部区域的情况下，反型层2在基体层1的背光面的投影的面积，占基体层1的背光面的总面积的50％至95％，对少数载流子和多数载流子的运输和收集效果均较好。
可选的，反型层2可以设置在基体层1的向光面的局部区域，也就是说反型层2并没有覆盖基体层1的全部向光面。
图4示出了本公开实施方式中的第四种太阳电池的结构示意图。可选的， 参照图2或图4所示，在反型层2的材料选自：III-V化合物半导体，反型层2和基体层1之间还设置有缓冲层5。即，无论是反型层2设置在基体层1的向光面，还是反型层2设置在基体层1的背光面，反型层2和基体层1之间均可以设置有缓冲层5。缓冲层5可以起到缓冲晶格失配、钝化界面缺陷等功能。缓冲层5的厚度d1为0.1-50nm，上述厚度范围的缓冲层5晶格适配效果好，且钝化性能好。
可选的，缓冲层5的材料选自：锗晶体、硅锗化合物、III-V化合物中的一种。缓冲层5中的III-V化合物可以为：InPSb(铟磷锑)、GaInP(镓铟磷)等。上述材料的缓冲层5的晶格适配效果好，且钝化性能好。
可选的，在反型层2的材料为：氧化物半导体，基体层1以及反型层2之间还设置有氧化硅层，即，无论是反型层2设置在基体层1的向光面，还是反型层2设置在基体层1的背光面，反型层2和基体层1之间均可以设置有氧化硅层，氧化硅层起到阻挡两者的掺杂元素相互扩散，和钝化界面缺陷的功能，而且制备工艺使用已有的太阳电池的制备工艺即可，制备效率高。氧化硅层的厚度为0.1-10nm。
可选的，在反型层2的材料选自：非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种，基体层以及反型层之间还设置有钝化层，即，无论是反型层2设置在基体层1的向光面，还是反型层2设置在基体层1的背光面，反型层2和基体层1之间均可以设置有钝化层，钝化层起到阻挡两者的掺杂元素相互扩散，和钝化界面缺陷的功能。钝化层的厚度为0.1-10nm。
可选的，钝化层的材料选自：本征非晶硅、纳米晶硅或氧化硅，阻挡扩散和钝化的效果好，而且制备工艺使用已有的太阳电池的制备工艺即可，制备效率高。
图5示出了本公开实施方式中的第五种太阳电池的结构示意图。可选的，参照图4、图5所示，在反型层2位于基体层1的背光面的情况下，太阳电池还包括位于基体层1的向光面的前表面场6，前表面场6的掺杂类型与基体层1的掺杂类型相同，前表面场6的掺杂浓度大于基体层1的掺杂浓度。前表面场6与基体层1形成浓度梯度差，利于提升光电转换效率。
可选的，参照图2所示，在反型层2位于基体层1的向光面的情况下，太阳电池还包括位于基体层1的背光面的背表面场7，背表面场7的掺杂类型 与基体层1的掺杂类型相同，背表面场7的掺杂浓度大于基体层1的掺杂浓度。背表面场7与基体层1形成浓度梯度差，利于提升光电转换效率。
可选的，参照图3所示，在反型层2位于基体层1的背光面的局部区域的情况下，太阳电池还包括位于基体层1的背光面中反型层2之外的背表面场7，背表面场7的掺杂类型与基体层1的掺杂类型相同，背表面场7的掺杂浓度大于基体层1的掺杂浓度。背表面场7与基体层1形成浓度梯度差，利于提升光电转换效率。
可选的，基体层1的背光面为平面结构或陷光结构，和/或，基体层1的向光面为平面结构或陷光结构，与其接触的反型层2适应基体层1表面结构。
可选的，PN结的向光面设置有正面钝化层、正面减反射薄膜层、散射结构层、聚光结构层中的至少一种；和/或，在PN结的背光面设置有背面钝化层、背面减反射薄膜层、散射结构层、聚光结构层中的至少一种。例如，图2、图3-图5中，9可以为正面减反射薄膜层，8可以为背面钝化层。
本公开实施方式还提供了一种电池组件，包括：任一前述太阳电池。图6示出了本公开实施方式中的一种电池组件的结构示意图。图6可以为从电池组件的向光面向背光面看的俯视图。图7示出了本公开实施方式中的一种电池组件的电路示意图。参照图7所示，每个电池串中无需并联旁路二极管。该组件中的太阳电池具体可以参照前述有关记载，并能达到相同或相似的有益效果，为了避免重复，此处不再赘述。
下面以具体实施例对本公开作进一步阐述。
实施例1
参照图4所示，基体层1为n型单晶硅，基体层1的向光面为绒面结构，背光面为抛光结构，基体层1的掺杂浓度10 13cm -3-10 16cm -3。基体层1向光面具备前表面场6，前表面场6为重掺层，掺杂类型与基体层1相同，掺杂浓度比基体层1高。反型层2中至少部分区域形成弱简并或简并半导体，基体层1为非简并半导体。
基体层1的向光面具备向正面减反射薄膜层9。反型层2位于基体层1的整个背光面侧，采用外延生长的方式获得。反型层2为GaAs，为p型掺杂(掺Al)，掺杂浓度为10 18cm -3-10 20cm -3。反型层2处于接近简并态或简并态。反型层2与基体层1之间存在缓冲层5，缓冲层5为SiGe缓冲层，厚度2-50nm， 采用外延生长的方式获得。反型层2背光面侧具备背面钝化层8。
在器件的向光表面印刷第二电极3并烘干、烧结，在器件背光面印刷第一电极4并烘干、烧结，烧结温度不超过700℃，以保护隧道结界面，减少界面扩散。
实施例2
参照图4所示，基体层1为n型单晶硅，基体层1的向光面为绒面结构，背光面为抛光结构，基体层1的掺杂浓度10 15cm -3-10 16cm -3。基体层1向光面具备前表面场6，前表面场6为重掺层，掺杂类型与基体层1相同，掺杂浓度比基体层1高。反型层2中至少部分区域形成弱简并或简并半导体，基体层1为非简并半导体。
基体层1的向光面具备向正面减反射薄膜层9。反型层2位于基体层1的整个背光面侧，采用气相沉积的方法获得。反型层2为掺铝氧化锌，为p型掺杂。反型层2与基体层1之间存在氧化硅层5，氧化硅层5为氧化硅层，厚度1nm，采用沉积氧化后退火的方式获得。反型层2背光面侧具备背面钝化层8。
在器件的向光表面印刷第二电极3并烘干、烧结，在器件背光面印刷第一电极4并烘干、烧结，烧结温度不超过700℃，以保护隧道结界面，防止氧化层裂解产生界面缺陷。
实施例3
参照图4所示，基体层1为n型单晶硅，基体层1的向光面为绒面结构，背光面为抛光结构，基体层1的掺杂浓度10 15cm -3-10 16cm -3。基体层1向光面具备前表面场6，前表面场6为重掺层，掺杂类型与基体层1相同，掺杂浓度比基体层1高。反型层2中至少部分区域形成弱简并或简并半导体，基体层1为非简并半导体。
基体层1的向光面具备向正面减反射薄膜层9。反型层2位于基体层1的整个背光面侧，采用气相沉积的方法获得。反型层2为非晶硅，为p型掺杂，掺杂浓度为10 15cm -3-10 18cm -3。反型层2与基体层1之间存在钝化层5，钝化层5为本征非晶硅层，厚度2nm，采用气相沉积的方式获得。反型层2背光面侧具备背面钝化层8。
在器件的向光表面印刷第二电极3并烘干、烧结，在器件背光面印刷第 一电极4并烘干、烧结，烧结温度不超过250℃，以保护隧道结界面，以防止非晶硅晶化导致钝化及隧道结性能下降。
实施例4
参照图2所示，基体层1为n型单晶硅，基体层1的背光面为绒面结构，向光面为抛光结构，基体层1的掺杂浓度10 16cm -3-10 19cm -3。基体层1中至少部分区域形成弱简并或简并半导体，反型层2为非简并半导体。基体层1背光面具备背表面场7，背表面场7为重掺层，掺杂类型与基体层1相同，掺杂浓度比基体层1高。背表面场7可以为完整的一层，或在位于基体层1背光面的局部区域，例如，仅位于基体层1背光面中电极位置附近。基体层1背光面侧具备背面钝化层8。
反型层2位于基体层1的整个向光面侧，采用外延的方法获得。反型层2为GaAs，为p型掺杂(掺Al)，掺杂浓度为10 15cm -3-10 17cm -3。反型层2与基体层1之间存在缓冲层5，缓冲层5为GaAs缓冲层，厚度2-50nm，采用外延的方式获得。反型层2的向光面具备向正面减反射薄膜层9。
在器件的向光表面印刷第二电极3并烘干、烧结，在器件背光面印刷第一电极4并烘干、烧结，烧结温度不超过700℃，以保护隧道结界面，减少界面扩散。
实施例5
参照图2所示，基体层1为n型单晶硅，基体层1的背光面为绒面结构，向光面为抛光结构，基体层1的掺杂浓度10 16cm -3-10 19cm -3。基体层1中至少部分区域形成弱简并或简并半导体，反型层2为非简并半导体。基体层1背光面具备背表面场7，背表面场7为重掺层，掺杂类型与基体层1相同，掺杂浓度比基体层1高。背表面场7可以为完整的一层，或在位于基体层1背光面的局部区域，例如，仅位于基体层1背光面中电极位置附近。基体层1背光面侧具备背面钝化层8。
反型层2位于基体层1的整个向光面侧，采用化学气相沉积的方法获得。反型层2为氧化钼，为p型掺杂。反型层2与基体层1之间存在氧化硅层5，氧化硅层5为氧化硅层，厚度1nm，采用沉积氧化钼后退火的方式获得。反型层2的向光面具备向正面减反射薄膜层9。
在器件的向光表面印刷第二电极3并烘干、烧结，在器件背光面印刷第 一电极4并烘干、烧结，烧结温度不超过700℃，以保护隧道结界面，减少界面扩散。
实施例6
参照图2所示，基体层1为n型单晶硅，基体层1的背光面为绒面结构，向光面为抛光结构，基体层1的掺杂浓度10 16cm -3-10 19cm -3。基体层1中至少部分区域形成弱简并或简并半导体，反型层2为非简并半导体。基体层1背光面具备背表面场7，背表面场7为重掺层，掺杂类型与基体层1相同，掺杂浓度比基体层1高。背表面场7可以为完整的一层，或在位于基体层1背光面的局部区域，例如，仅位于基体层1背光面中电极位置附近。基体层1背光面侧具备背面钝化层8。
反型层2位于基体层1的整个向光面侧，采用化学气相沉积的方法获得。反型层2为含氢非晶硅，为p型掺杂，掺杂浓度10 13cm -3-10 18cm -3。反型层2与基体层1之间存在钝化层5，钝化层5为本征含氢非晶硅层，厚度2nm，采用化学气相沉积的方式获得。反型层2的向光面具备向正面减反射薄膜层9。
在器件的向光表面印刷第二电极3并烘干、烧结，在器件背光面印刷第一电极4并烘干、烧结，烧结温度不超过250℃，防止非晶硅晶化造成界面钝化失效。
实施例7
参照图3所示，基体层1为n型单晶硅，基体层1的向光面为绒面结构，背光面为抛光结构，基体层1的掺杂浓度10 13cm -3-10 20cm -3，为常规掺杂。反型层2中至少部分区域形成弱简并或简并半导体，基体层1为非简并半导体。更优的，掺杂浓度为10 13cm -3-10 16cm -3。基体层1向光面具备前表面场6，前表面场6为重掺层，掺杂类型与基体层1相同，掺杂浓度比基体层1高。
基体层1的向光面具备向正面减反射薄膜层9。反型层2位于基体层1的背光面的局部区域，反型层2在基体层1的背光面的投影，占基体层1的背光面的50-95％，反型层2采用气相沉积的方法获得。反型层2为非晶硅，为p型掺杂，掺杂浓度为10 15cm -3-10 18cm -3。基体层1背光面具备背表面场7，背表面场7为重掺层，掺杂类型与基体层1相同，掺杂浓度比基体层1高。反型层2背光面侧具备背面钝化层8。
在器件的背光表面与反型层2相对的区域印刷第二电极3，在器件的背光 面的其余区域印刷第一电极4，并烘干、烧结，在器件背光面印刷第一电极4并烘干、烧结，烧结温度不超过250℃，以保护隧道结界面，以防止非晶硅晶化导致钝化及隧道结性能下降。
在本公开实施方式中，参照图8所示，图8示出了本公开实施方式中的第六种太阳电池的结构示意图。该太阳电池包括：PN结。PN结包括基体层1以及反型层2，基体层1和反型层2的掺杂类型不同，即基体层1以及反型层2两者中一个的掺杂类型为P型，另一个的掺杂类型为N型，至于两者中那个的掺杂类型是P型不作具体限定。例如，若图8中基体层1的掺杂类型为N型，则，反型层2的掺杂类型即为P型。反型层2设置在基体层1的背光面或向光面。如图8所示，反型层2设置在基体层1的背光面。参照图9所示，图9示出了本公开实施方式中的第七种太阳电池的结构示意图。图9中，反型层2设置在基体层1的向光面。
反型层2具有第一重掺杂区域3'，第一重掺杂区域3'从反型层2远离基体层1的一侧向反型层2内延伸，第一重掺杂区域3'向内延伸的深度不作具体限定。第一重掺杂区域3'与反型层2的掺杂类型相同。如，反型层2的掺杂类型为P型，第一重掺杂区域3'的掺杂类型也为P型。
参照图8所示，沿远离基体层1的方向，反型层2与第一重掺杂区域3'的厚度差h1为1nm-100nm，则，则第一重掺杂区域3'与pn结界面处的距离为1nm-100nm，可以减少界面处的复合，并降低载流子非局域跃迁电流。更优地，反型层2与第一重掺杂区域3'的厚度差h1可以为1nm-50nm。
T m表征室温，室温T m下，第一重掺杂区域3'形成弱简并或简并半导体。就是说，室温T m情况下，第一重掺杂区域3'掺杂浓度较高，形成弱简并或简并半导体。反型层2的其余部分和基体层1均为非简并半导体，
反型层2的其余部分和基体层1均为非简并半导体，即，反型层2的其余部分和基体层1掺杂浓度较低，为非简并半导体。
第一重掺杂区域3'形成弱简并或简并半导体，具体设置为，第一重掺杂区域3'的费米能级与n型半导体的导带底或p型半导体的价带顶的能级差小于2k B×T m，该公式中k B为玻尔兹曼常数(Boltzmann constant)，k B取值为1.380649×10 -23J/K。由上述基体层1和反型层2形成的PN结，在施加正向电压的情况下，作为一般的PN结存在，用于分离载流子。基体层1、反型层 2、第一重掺杂区域3'形成重掺杂结，在施加反向电压的情况下，该重掺杂结会作为隧道结存在，PN结中形成隧道电流，并反向导通，并没有被反向击穿，在施加正向电压的情况下，又恢复为一般的PN结存在。而在出现异常的情况下，该重掺杂结又会作为隧道结存在，不会被击穿，不会影响与该太阳电池串联的整个太阳电池串的输出，一方面由该太阳电池形成的电池串无需并联旁路二极管，封装损失小，可以减小接线盒的尺寸；另一方面，在出现异常时，电池串中其余太阳电池均允许正常电流通过，仅是出现异常的太阳电池的输出电流受影响，损失的电流少，发热少，最大程度上降低了热斑效应，具备更高的可靠性和长期稳定性，组件功率下降也少。
更为具体的，在存在第一重掺杂区域3'的位置，基体层1、反型层2、第一重掺杂区域3'构成重掺杂结，当承受反向电压时，该重掺杂结可以成为隧道结，使得反向电流可以通过。正常工作时，即在施加正向电压的情况下，重掺杂结中由于较薄的反型层2的存在，可以避免或减少载流子由第一重掺杂区域3'向基体层1发生非局域跃迁，降低界面漏电电流，可以获得较高的光电转换效率。
例如，以p型硅基体层1为例，重掺杂结的反型层2为n型，第一重掺杂区域3'为n+区域，正常工作时，即在施加正向电压的情况下，光激发电子由p型区域流向n型区域，再由n+区域收集并导出。当该器件异常时，即承受反向电压时，输出电压下降，与其串联的器件正常工作，因此该器件内电子流向改为由n+区域向p型区域，现有的常规pn结在此时会发生截止，不能通过该电流，但是本公开实施例中的电子可以依靠隧穿复合机制由n+区域流向p区，反向导通，并没有被反向击穿。
可选的，第一重掺杂区域3'通过离子注入或激光注入的方式，设置在反型层2的局部区域内。
可选的，参照图8或图9所示，第一重掺杂区域3'在基体层1的向光面的投影面积，占反型层2在基体层1的向光面的投影面积的1％-50％，由上述尺寸比例形成的重掺杂结，在施加反向电压的情况下，该重掺杂结作为隧道结存在，更易于反向导通。
可选的，第一重掺杂区域3'在基体层1的向光面的投影为点状或线状图案，第一重掺杂区域3'还可以作为选择性接触结构，利于载流子的收集。
可选的，基体层1的材料选自：晶体硅，如单晶硅或多晶硅，掺杂浓度可以为1×10 13cm -3-1×10 16cm -3，或者，基体层1的掺杂浓度可以为1×10 16cm -3-1×10 18cm -3。需要说明的是，基体层1的掺杂浓度若较高，在重掺杂结施加反向电压的情况下，隧道结的整体电阻较小，导通能力较强。
可选的，反型层2的材料选自：晶体硅、非晶硅、过渡金属氧化物半导体材料、III-V半导体材料中的至少一种。例如，反型层2的材料是晶体碳化硅、非晶碳化硅材料。反型层2的材料可以是过渡金属氧化物半导体材料，如氧化锌(掺铝)、氧化锡、氧化钛、氧化钼等。反型层2的材料可以是III-V半导体材料，如砷化镓、磷化铟等。反型层2的掺杂浓度不限。
可选的，第一重掺杂区域3'的材料选自：晶体硅、非晶硅、过渡金属氧化物半导体材料、III-V半导体材料中的至少一种，第一重掺杂区域3的掺杂浓度较高，需要形成弱简并或简并半导体。
需要说明的是，第一重掺杂区域3'的材料与反型层2的材料可以相同或不同。
可选的，参照图8或图9所示，反型层2设置在基体层1一侧的整个区域，第一电极4设置在第一重掺杂区域3'上，第二电极5'设置在基体层1上，进而形成双面电池。例如，参照图1所示，反型层2设置在基体层1背光面的整个区域，第一电极4设置在第一重掺杂区域3'上，第二电极5'设置在基体层1上，形成双面电池。再例如，参照图9所示，反型层2设置在基体层1向光面的整个区域上。
图10示出了本公开实施方式中的第八种太阳电池的结构示意图。可选的，参照图10所示，基体层1的一侧区分为第一区域和第二区域，反型层2设置在基体层1的一侧的第一区域内，也就是说反型层2只是设置在基体层1的一侧的局部区域内。太阳电池还包括：第二重掺杂区域8'，第二重掺杂区域8'位于第二区域内，就是说第二重掺杂区域8'与反型层2位于基体层1的同一侧，且第二重掺杂区域8'位于基体层1一侧未设置反型层2的区域内。第二重掺杂区域8'与基体层1的掺杂类型相同，且掺杂浓度大于基体层，第二重掺杂区域8'与基体层1形成浓度梯度差，利于提升光电转换效率。例如，图10中基体层1与第二重掺杂区域8'的掺杂类型均为N型，第二重掺杂区域8'的掺杂浓度大于基体层1的掺杂浓度。
需要说明的是，上述第一区域和第二区域的相对大小不作具体限定。例如，用于收集和/或传输少数载流子的区域面积可以大于用于收集和/或传输多数载流子的区域的面积，以利于少数载流子的收集和/或传输。
图10所示的太阳电池还包括：第一电极4和第二电极5'，第一电极4设置在第一重掺杂区域3'上，第二电极5'设置在第二重掺杂区域8'上，形成单面电池。
可选的，图10所示的太阳电池还包括：阻断结构9'，阻断结构9'位于第二重掺杂区域8'与反型层2之间，以避免漏电。
可选的，上述阻断结构9'可以为绝缘间隙，或，阻断结构9'由电介质材料形成，进而不仅绝缘效果好，而且阻断结构9'易于获得。
需要说明的是，PN结形成后，需控制后续工艺温度，过高的后续工艺温度会导致PN结界面发生元素扩散或界面层裂解，破坏PN结界面，导致效率下降。例如，PN结表面印刷电极并烘干、烧结，烧结温度不超过500℃，以保护PN结界面，减少界面扩散。
可选的，基体层1的背光面为平面结构或陷光结构，和/或，基体层1的向光面为平面结构或陷光结构，与其接触的反型层2适应基体层1表面结构。
可选的，参照图9或图10所示，PN结的向光面设置有上表面功能层6'，上表面功能层6'可以为正面钝化层、正面减反射薄膜层、散射结构层、聚光结构层中的至少一种；和/或，在PN结的背光面设置有下表面功能层7'，下表面功能层7'可以为背面钝化层、背面减反射薄膜层、散射结构层、聚光结构层中的至少一种。
本公开实施方式还提供了一种电池组件，包括：任一前述太阳电池。该电池组件中，每个电池串中无需并联旁路二极管。该电池组件中的太阳电池具体可以参照前述有关记载，并能达到相同或相似的有益效果，为了避免重复，此处不再赘述。
下面以具体实施例对本公开作进一步阐述。
实施例8
参照图11所示，图11示出了本公开实施方式中的第九种太阳电池的结构示意图。图11中基体层1采用n型单晶硅片，掺杂浓度为1×10 16cm -3，厚度为150um。反型层2位于基体层1的整个背光面，采用浅结工艺，扩散成p 型层，反型层2的平均深度为100nm。在反型层2下采用离子注入或激光工艺，设置第一重掺杂区域3'。第一重掺杂区域3'掺杂浓度为1×10 18cm -3。沿远离基体层1的方向，反型层2与第一重掺杂区域3'的厚度差为10nm。
实施例9
参照图9所示，基体层1采用n型单晶硅片，掺杂浓度为1×10 16cm - 3，厚度为150um。基体层1的向光面及背光面均为绒面结构。
反型层2位于基体层1的整个向光面，采用浅结工艺，扩散成p型层。反型层2平均深度700nm。
在反型层2中采用激光工艺，设置第一重掺杂区域3'。第一重掺杂区域3'掺杂浓度为1×10 18cm -3，沿远离基体层1的方向，反型层2与第一重掺杂区域3'的厚度差为50nm。
实施例10
参照图10所示，基体层1采用n型单晶硅片，掺杂浓度为0.5×10 16cm - 3，厚度为100um。基体层1向光面为绒面结构，可以具备前表面场。
反型层2位于基体层1背光面局部区域，采用浅结工艺，扩散成p型层。反型层2平均深度100nm。
在基体层1背光面，除反型层2的其余区域，设置第二重掺杂区域8'，第二重掺杂区域8'为n型掺杂，掺杂浓度高于基体层1掺杂浓度。第二重掺杂区域8'与反型层2之间设置阻断结构9'，阻断结构9'为绝缘间隙或电介质材料。
在反型层2下采用离子注入或激光工艺，设置第一重掺杂区域3'。第一重掺杂区域3'掺杂浓度为1×10 18cm -3。沿远离基体层1的方向，反型层2与第一重掺杂区域3'的厚度差为10nm。
上面结合附图对本公开的实施方式进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本公开的保护之内。

Claims (21)

  1. 一种太阳电池，其特征在于，包括PN结；所述PN结由基体层以及反型层形成；所述基体层与所述反型层的掺杂类型不同；
    室温T m下，所述基体层和所述反型层中位于背光一侧者至少部分区域形成弱简并或简并半导体，所述部分区域从所述基体层和所述反型层中位于背光一侧者的向光面向层内延伸；
    所述基体层和所述反型层中位于向光一侧者为非简并半导体；
    所述弱简并或简并半导体设置为，费米能级与n型半导体的导带底或p型半导体的价带顶的能级差小于2k B×T m。
  2. 根据权利要求1所述的太阳电池，其特征在于，所述反型层的材料选自：III-V化合物半导体、氧化物半导体、非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种；
    所述基体层的材料选自：晶体硅、III-V化合物半导体、氧化物半导体、非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种。
  3. 根据权利要求2所述的太阳电池，其特征在于，所述反型层的位于背光侧，其中，以下材料作为反型层时，
    III-V化合物半导体的掺杂浓度为10 17cm -3-10 21cm -3；
    氧化物半导体的施主缺陷或受主缺陷浓度为10 16cm -3-10 21cm -3；
    反型层采用非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种的情况下，所述反型层的掺杂浓度为10 15cm -3-10 18cm -3。
  4. 根据权利要求2所述的太阳电池，其特征在于，所述基体层位于背光侧，其中，以下材料作为基体层时，
    晶体硅的的掺杂浓度为10 16cm -3-10 20cm -3；
    III-V化合物半导体的掺杂浓度为10 17cm -3-10 21cm -3；
    氧化物半导体的施主缺陷或受主缺陷浓度为10 16cm -3-10 21cm -3；
    基体层选自非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种的情况下，所述基体层的掺杂浓度为10 15cm -3-10 18cm -3。
  5. 根据权利要求1-4中任一所述的太阳电池，其特征在于，在所述反型层位于所述基体层的整个背光面；所述基体层为晶体硅，晶体硅的掺杂浓度为10 13cm -3-10 16cm -3；或，
    所述反型层位于所述基体层的背光面的局部区域，所述基体层为晶体硅，晶体硅的掺杂浓度为10 13cm -3-10 20cm -3。
  6. 根据权利要求5所述的太阳电池，其特征在于，所述反型层位于所述基体层的背光面的局部区域，所述基体层为晶体硅，在所述局部区域所述晶体硅靠近所述反型层一侧的掺杂浓度大于相对的一侧。
  7. 根据权利要求1-4中任一所述的太阳电池，其特征在于，所述反型层的材料选自III-V化合物半导体，所述基体层以及所述反型层之间还设置有缓冲层；所述缓冲层的厚度为0.1-50nm，所述缓冲层的材料选自：锗晶体、硅锗化合物、III-V化合物中的一种。
  8. 根据权利要求1-4中任一所述的太阳电池，所述反型层的材料为氧化物半导体，所述基体层以及所述反型层之间还设置有氧化硅层；所述氧化硅层的厚度为0.1-10nm。
  9. 根据权利要求1-4中任一所述的太阳电池，所述反型层的材料选自：非晶硅、非晶碳化硅、纳米晶硅、纳米晶碳化硅中的至少一种，所述基体层以及所述反型层之间还设置有钝化层；所述钝化层的厚度为0.1-10nm，所述钝化层的材料选自：本征非晶硅、纳米晶硅或氧化硅。
  10. 根据权利要求2-4中任一所述的太阳电池，其特征在于，所述III-V化合物半导体选自：GaAs、InAs、InP、GaP、AlP、AlAs中的至少一种；
    所述氧化物半导体选自：第一材料或所述第一材料与第二材料的掺杂化合物；所述第一材料选自：氧化钛、氧化锌、氧化锡、氧化镍、氧化铜、氧化钨、氧化钼、氧化钒中的至少一种；所述第二材料选自：卤族元素、过渡金属元素、碱金属元素、稀土元素、III族元素、IV族元素、V族元素中的至少一种。
  11. 根据权利要求1-4中任一所述的太阳电池，其特征在于，在所述反型层位于所述基体层的背光面的局部区域的情况下，所述反型层在所述基体层的背光面的投影的面积，占所述基体层的背光面的总面积的50％至95％。
  12. 一种电池组件，其特征在于，包括：权利要求1至权利要求11中任一所述的太阳电池。
  13. 一种太阳电池，其特征在于，包括PN结，所述PN结由基体层以及反型层形成，所述基体层与所述反型层的掺杂类型不同；
    所述反型层具有第一重掺杂区域，所述第一重掺杂区域从所述反型层远离所述基体层的一侧向所述反型层内延伸，所述第一重掺杂区域与所述反型层的掺杂类型相同；
    沿远离所述基体层的方向，所述反型层与所述第一重掺杂区域的厚度差为1-100nm；
    室温T m下，所述第一重掺杂区域形成弱简并或简并半导体，所述反型层的其余部分和所述基体层均为非简并半导体，所述弱简并或简并半导体设置为，费米能级与n型半导体的导带底或p型半导体的导带顶的能级差小于2k B×T m。
  14. 根据权利要求13所述的太阳电池，其特征在于，所述第一重掺杂区域在所述基体层的向光面的投影面积，占所述反型层在所述基体层的向光面的投影面积的1％-50％。
  15. 根据权利要求13所述的太阳电池，其特征在于，所述第一重掺杂区域在所述基体层的向光面的投影为点状或线状图案。
  16. 根据权利要求13所述的太阳电池，其特征在于，所述基体层的材料选自：晶体硅；
    所述反型层的材料选自：晶体硅、非晶硅、过渡金属氧化物半导体材料、III-V半导体材料中的至少一种；
    所述第一重掺杂区域的材料选自：晶体硅、非晶硅、过渡金属氧化物半导体材料、III-V半导体材料中的至少一种。
  17. 根据权利要求13-16中任一所述的太阳电池，其特征在于，所述反型层设置在所述基体层一侧的整个区域；
    所述太阳电池还包括：第一电极和第二电极，所述第一电极设置在所述第一重掺杂区域上，所述第二电极设置在所述基体层上。
  18. 根据权利要求13-16中任一所述的太阳电池，其特征在于，
    所述基体层的一侧区分为第一区域和第二区域；
    所述反型层设置在所述基体层的一侧的第一区域内；
    所述太阳电池还包括：第二重掺杂区域，所述第二重掺杂区域位于所述第二区域内；
    所述第二重掺杂区域与所述基体层的掺杂类型相同，且掺杂浓度大于所 述基体层；
    所述太阳电池还包括：第一电极和第二电极，所述第一电极设置在所述第一重掺杂区域上，所述第二电极设置在所述第二重掺杂区域上。
  19. 根据权利要求18所述的太阳电池，其特征在于，所述太阳电池还包括阻断结构，所述阻断结构位于第二重掺杂区域与所述反型层之间。
  20. 根据权利要求19所述的太阳电池，其特征在于，所述阻断结构为绝缘间隙，或，所述阻断结构由电介质材料形成。
  21. 一种电池组件，其特征在于，包括：权利要求13至权利要求20中任一所述的太阳电池。
PCT/CN2021/133236 2020-12-03 2021-11-25 太阳电池及电池组件 WO2022116894A1 (zh)

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CN112786729A (zh) * 2020-12-03 2021-05-11 隆基绿能科技股份有限公司 太阳电池及电池组件
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JP2001237438A (ja) * 2000-02-25 2001-08-31 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
CN104300015A (zh) * 2014-10-13 2015-01-21 北京工业大学 AlGaAs/GaInAs/Ge连续光谱太阳能电池
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