WO2022116307A1 - 一种静电保护电路和显示面板 - Google Patents

一种静电保护电路和显示面板 Download PDF

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Publication number
WO2022116307A1
WO2022116307A1 PCT/CN2020/138065 CN2020138065W WO2022116307A1 WO 2022116307 A1 WO2022116307 A1 WO 2022116307A1 CN 2020138065 W CN2020138065 W CN 2020138065W WO 2022116307 A1 WO2022116307 A1 WO 2022116307A1
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Prior art keywords
thin film
field effect
effect transistor
film field
voltage
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PCT/CN2020/138065
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English (en)
French (fr)
Inventor
李育智
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Tcl华星光电技术有限公司
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Priority to US17/259,181 priority Critical patent/US11776457B2/en
Publication of WO2022116307A1 publication Critical patent/WO2022116307A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present invention relates to the field of display technology. More specifically, it relates to an electrostatic discharge protection circuit and a display panel.
  • Oxide semiconductors represented by IGZO indium gallium zinc oxide, indium gallium zinc oxide
  • TFT Thin Film Transistor, thin film field effect transistor
  • a-Si TFT amorphous silicon thin film field effect transistor
  • oxide TFT has higher mobility and lower leakage current I off .
  • oxide TFT As switch It has a stronger ability to maintain charge, which is conducive to the improvement of display quality.
  • Oxide TFT-based GOA Gate Driver on Array, array substrate row driver
  • oxide TFT has high mobility, TFT can achieve a smaller layout area (layout area), which is helpful for making narrow-bezel panels.
  • the low current of the oxide leakage current state also makes it difficult to release the charge in the GOA signal line.
  • ESD Electro-Static Discharge, electrostatic discharge
  • the anti-static breakdown capability of the panel is an important indicator to measure the reliability of the panel.
  • the existing design scheme is generally that the GOA signal line is connected to the Common line (common electrode line) through an electrostatic protection circuit, and the accumulated charge in the GOA signal line is led to the Common line.
  • the purpose of dispersing the charge is achieved, avoiding the accumulation of too much charge in a single signal line, and generating a large voltage difference with other signal lines to generate static electricity.
  • the electrostatic protection circuit In order to disperse the charge in time and avoid the signal line with a large load, the electrostatic protection circuit needs to have a small leakage current under low voltage (the upper limit is the maximum voltage difference between the GOA signal line and the Common line), and under high voltage (the lower limit is The maximum voltage difference between the GOA signal line and the Common line) has a large leakage current.
  • the purpose of the present application is to provide an electrostatic discharge protection circuit and a display panel in view of the problems in the prior art, so as to reduce the load influence on the row driving signal lines of the array substrate and improve the reliability of the display panel.
  • an electrostatic protection circuit comprising:
  • the first voltage reference unit is used to divide the voltage between the row driving signal line and the common electrode line of the array substrate once;
  • the second voltage reference unit is used to divide the voltage between the row driving signal line and the common electrode line of the array substrate twice;
  • the charge discharge unit adjusts the charge distribution between the row driving signal lines and the common electrode lines of the array substrate based on the reference voltages provided by the first voltage reference unit and the second voltage reference unit;
  • the first voltage reference unit, the second voltage reference unit and the charge discharge unit are respectively connected between the row driving signal line and the common electrode line of the array substrate;
  • the potential midpoint of the first voltage reference unit is connected to the potential midpoint of the second voltage reference unit;
  • At least two reference voltage output terminals of the second voltage reference unit are connected to the reference voltage input terminal of the charge discharge unit.
  • the present application also provides a display panel, comprising: the electrostatic protection circuit as described above.
  • the electrostatic protection circuit described in this solution has a larger leakage current than ordinary electrostatic protection circuits, and can drive the signal lines of the array substrate row in time.
  • the accumulated electrostatic charge is released to avoid the phenomenon of cross-line electrostatic protection in the circuit; in the case of low voltage (U ⁇ 20V), the load of the array substrate row driving signal line is not affected, and the reliability of the display panel is improved.
  • Fig. 1 shows the schematic diagram in the prior art
  • FIG. 2 shows a schematic diagram of an example of the electrostatic protection circuit described in this scheme
  • FIG. 3 shows a schematic diagram of another example of the electrostatic protection circuit described in this scheme
  • FIG. 4 shows a comparison diagram of experimental data of the electrostatic protection circuit of the present scheme and the electrostatic protection circuit of the prior art in the ability to discharge charges under low voltage conditions;
  • FIG. 5 is a graph showing the comparison of experimental data of the electrostatic protection circuit of the present solution and the electrostatic protection circuit of the prior art on the ability to discharge charges under high voltage conditions.
  • a first voltage reference unit 101, a first voltage divider module; 102, a second voltage divider module;
  • the second voltage reference unit 201, the third voltage dividing module; 202, the fourth voltage dividing module;
  • T1 the first thin film field effect transistor
  • T2 the second thin film field effect transistor
  • T3 the third thin film field effect transistor
  • T4 the fourth thin film field effect transistor
  • T5 the fifth thin film field effect transistor
  • T6 the sixth thin film field effect transistor
  • T7 the seventh thin film field effect transistor
  • T8 the eighth thin film field effect transistor
  • T9 the ninth thin film field effect transistor
  • T10 the tenth thin film field effect transistor
  • T11 the eleventh thin film field effect transistor
  • T12 the twelfth thin film field effect transistor
  • A the array substrate row driving signal line
  • B the common electrode line
  • the TFT in the electrostatic protection circuit can be connected in the form of a diode pair (diode pair), which is equivalent to increasing the TFT's Channel width to length ratio, so as to achieve the purpose of adjusting the leakage current of the electrostatic protection circuit.
  • the channel width of the TFT is increased in the ESD circuit, the leakage current of the electrostatic protection circuit will increase at both low voltage and high voltage.
  • the GOA signal line has more charge release channels, and the aspect ratio of the TFT in the electrostatic protection circuit can be designed to a relatively small level, or even canceled.
  • Electrostatic protection circuit however, the leakage current I off of oxide TFTs such as IGZO is low, and the charge is difficult to discharge under the off-state condition. Therefore, the electrostatic protection circuit needs a strong ability to discharge the charge. Obviously, the electrostatic protection circuit in the form of diode pair is used. It is necessary to increase the aspect ratio of the TFT and increase the leakage current of the electrostatic protection circuit, but this will also increase the load of the GOA signal line and affect the normal driving of the GOA circuit.
  • this solution is intended to be an electrostatic protection circuit, in which the TFT of a diode pair formed by TFTs is used as the first voltage reference unit 1, and a plurality of thin-film field effect transistors connected in series are used as the second voltage reference unit 2, that is,
  • the width-length ratio of the TFT can be adjusted equivalently by reasonably setting the arrangement of the TFTs in the first voltage reference unit 1, so that the electrostatic protection circuit has a small load under low voltage conditions, which does not affect the normal operation of the GOA circuit. It has a larger charge release capability at higher voltages, avoiding static electricity generated by the GOA input signal line, thereby improving the reliability of the display panel.
  • the electrostatic protection circuit in this solution includes: a first voltage reference unit 1 , a second voltage reference unit 2 and a charge discharge unit 3 .
  • the first voltage reference unit 1, the second voltage reference unit 2 and the charge discharge unit 3 are respectively connected between the array substrate row driving signal line A and the common electrode line B; the first voltage reference unit 1 drives the array substrate row signal line
  • the second voltage reference unit 2 is further used to divide the voltage between the row driving signal line A and the common electrode line B of the array substrate.
  • the charge discharge unit 3 adjusts the charge distribution between the array substrate row driving signal line A and the common electrode line B according to the reference voltage provided by the first voltage reference unit 1 and the second voltage reference unit 2, so as to drive the signal line A in the array substrate row
  • the electrostatic protection circuit has a small leakage current, does not affect the load of the array substrate row driving signal line, and improves the reliability of the display panel;
  • the electrostatic protection circuit can rapidly increase the leakage current, so that the accumulated amount of the array substrate row driving signal line A
  • the static electricity can be released in time to avoid the problem of cross-line electrostatic discharge, and at the same time, it can ensure that the load of the row driving input signal of the array substrate is not affected during normal operation.
  • the midpoint of the potential of the first voltage reference unit 1 is connected to the midpoint of the potential of the second voltage reference unit 2.
  • the second voltage reference The output terminal of the reference voltage in the unit 2 outputs the reference voltage provided to the charge discharge unit 3 .
  • the second voltage reference unit 2 has at least two reference voltage output terminals.
  • the first voltage reference unit 1 may include: a first voltage dividing module 101 and a second voltage dividing module 102 .
  • the two voltage dividing modules are connected in series; the potential midpoint of the first voltage reference unit 1 is located between the two voltage dividing modules.
  • the input end of the first voltage dividing module 101 is connected to the row driving signal line A of the array substrate, and the output end of the first voltage dividing module 101 and the input end of the second voltage dividing module 102 are both connected to the first voltage reference
  • the potential midpoint of the unit 1 is connected, and the output end of the second voltage dividing module 102 is connected to the common electrode line B.
  • the use of the first voltage reference unit 1 enables the electrostatic protection circuit to increase the leakage current under both high and low voltage conditions.
  • the first voltage dividing module 101 may include: a first thin film field effect transistor T1 and a second thin film field effect transistor T2.
  • the first thin film field effect transistor T1 and the second thin film field effect transistor T2 are connected in the form of a diode pair (diode pair), which can equivalently increase the thin film field effect transistor without changing the structure of the thin film field effect transistor.
  • the aspect ratio is increased, thereby increasing the leakage current of the electrostatic protection circuit and improving the charge release capability of the electrostatic protection circuit.
  • the specific connection mode of the two thin film field effect transistors is as follows: the gate of the first thin film field effect transistor T1, the first electrode of the first thin film field effect transistor T1 and the second electrode of the second thin film field effect transistor T2 are all connected to the first thin film field effect transistor T1.
  • the potential midpoint of the voltage reference unit 1 is connected; the second electrode of the first thin film field effect transistor T1, the gate of the second thin film field effect transistor T2 and the first electrode of the second thin film field effect transistor T2 are all connected to the array substrate
  • the row driving signal line A is connected.
  • the first electrode may be a source electrode or a drain electrode; the second electrode may be a source electrode or a drain electrode; and the types of the first electrode and the second electrode are different.
  • the second voltage dividing module 102 may include: a third thin film field effect transistor T3 and a fourth thin film field effect transistor T4.
  • the third thin film field effect transistor T3 and the fourth thin film field effect transistor T4 may also be connected in the form of a diode pair.
  • the specific connection mode of the two thin film field effect transistors is as follows: the gate of the third thin film field effect transistor T3, the first electrode of the third thin film field effect transistor T3 and the second electrode of the fourth thin film field effect transistor T4 are all connected to the common electrode.
  • Line B is connected; the second electrode of the third thin film field effect transistor T3, the gate of the fourth thin film field effect transistor T4 and the first electrode of the fourth thin film field effect transistor T4 are all connected to the potential midpoint of the first voltage reference unit 1 connect.
  • the first electrode may be a source electrode or a drain electrode; the second electrode may be a source electrode or a drain electrode; and the types of the first electrode and the second electrode are different.
  • this solution adds a second voltage reference unit 2 on the basis of the first voltage reference unit 1, which can not only satisfy the situation of low voltage between the row driving signal line A and the common electrode line B of the array substrate, the electrostatic protection circuit It has a small leakage current, and at the same time, the array substrate row driving signal line A has a small load, and the driving operation of the array substrate row driving signal line A is not affected.
  • the second voltage reference unit 2 includes: a third voltage dividing module 201 and a fourth voltage dividing module 202 .
  • the two voltage dividing modules are connected in series; the potential midpoint of the second voltage reference unit 2 is located between the two voltage dividing modules.
  • the voltage dividing input terminal of the third voltage dividing module 201 is connected to the row driving signal line A of the array substrate, and the reference voltage output terminal of the third voltage dividing module 201 is connected to at least one reference voltage input terminal of the charge discharge unit 3.
  • Both the voltage dividing output terminal of the third voltage dividing module 201 and the voltage dividing input terminal of the fourth voltage dividing module 202 are connected to the potential midpoint of the second voltage reference unit 2 .
  • the reference voltage output end of the fourth voltage dividing module 202 is connected to at least one reference voltage input end of the charge discharge unit 3 , and the voltage dividing output end of the fourth voltage dividing module 202 is connected to the common electrode line B.
  • the first voltage reference unit 1 and the second voltage reference unit 2 are used to provide a reference voltage for the charge discharge unit 3 to control the switch state of the charge discharge unit 3, so that the array substrate row drives the signal line A and the common electrode line B charge redistribution between.
  • the second voltage reference unit 2 further divides the voltage between the driving signal line A and the common electrode line B in the row of the array substrate, so as to avoid driving the signal line A and the common electrode line in the row of the array substrate.
  • the charge discharge unit 3 When the voltage between the electrode lines B is low (U ⁇ 20), the charge discharge unit 3 is turned on because the potential is too high, thereby ensuring that the electrostatic protection circuit has a small leakage current under the normal working conditions of the circuit. At the same time, in this way, the problem of increasing the load of the array substrate row driving signal line A in the case of low voltage when the thin film field effect transistors are connected in the form of diode pairs is overcome, and the array substrate row driving signal line A is ensured normal work.
  • the third voltage dividing module 201 is composed of a fifth thin film field effect transistor T5 and a sixth thin film field effect transistor T6.
  • the first electrode of the fifth thin film field effect transistor T5 is connected to the row driving signal line A of the array substrate; the gate of the fifth thin film field effect transistor T5, the second electrode of the fifth thin film field effect transistor T5 and the sixth thin film field effect transistor
  • the first electrode of the effect transistor T6 is connected to the reference voltage output terminal of the third voltage dividing module 201; the gate of the sixth thin film field effect transistor T6 and the second electrode of the sixth thin film field effect transistor T6 are both connected to the second voltage reference
  • the potential midpoint of cell 2 is connected.
  • the first electrode may be a source electrode or a drain electrode; the second electrode may be a source electrode or a drain electrode; and the types of the first electrode and the second electrode are different.
  • the fourth voltage dividing module 202 includes: a seventh thin film field effect transistor T7 and an eighth thin film field effect transistor T8; the gate of the seventh thin film field effect transistor T7 and the The first electrodes of the seventh thin film field effect transistor T7 are all connected to the potential midpoint of the second voltage reference unit 2; the second electrode of the seventh thin film field effect transistor T7, the eighth thin film field effect transistor The gate of the transistor T8 and the first electrode of the eighth thin film field effect transistor T8 are both connected to the reference voltage output end of the fourth voltage dividing module 202; the second electrode of the eighth thin film field effect transistor T8 is connected to The common electrode line B is connected.
  • the first electrode may be a source electrode or a drain electrode; the second electrode may be a source electrode or a drain electrode; and the types of the first electrode and the second electrode are different.
  • the charge discharge unit 3 includes a ninth thin film field effect transistor T9, and the ninth thin film field effect transistor T9 is turned on under the action of the reference voltage provided by the second voltage reference unit 2, Complete the charge release work.
  • the first voltage dividing module 101 and the second voltage dividing module 101 in the first voltage reference unit 1 performs the voltage dividing work, and at the same time, the thin film field effect transistors in the third voltage dividing module 201 and the fourth voltage dividing module 202 in the second voltage reference unit 2 generate the work of the reference voltage based on the change of the current and voltage .
  • the ninth thin film field effect transistor T9 in the charge discharge unit 3 is based on the reference generated by the third voltage dividing module 201 and the fourth voltage dividing module 202 The voltage is turned on and charges are released, until the voltage between the array substrate row driving signal line A and the common electrode line B drops to a low voltage (voltage U ⁇ 20V), the ninth thin film field effect transistor T9 stops releasing charges.
  • the second voltage reference unit 2 is added to divide the voltage, the side of the reference voltage unit in the electrostatic protection circuit is reduced. It has a smaller leakage current, thereby ensuring that the potential of the ninth thin film field effect transistor T9 in the charge discharge unit 3 is lower than the potential of the reference voltage unit side in the electrostatic protection circuit, preventing the potential of the ninth thin film field effect transistor T9 from being too high As a result, the ninth thin film field effect transistor T9 is turned on, thereby ensuring that the electrostatic protection circuit has a small leakage current under normal operating conditions of the circuit.
  • the third voltage dividing module 201 is composed of a fifth thin film field effect transistor T5 , a sixth thin film field effect transistor T6 and a seventh thin film field effect transistor T7 .
  • the first electrode of the fifth thin film field effect transistor T5 is connected to the row driving signal line A of the array substrate; the gate of the fifth thin film field effect transistor T5, the second electrode of the fifth thin film field effect transistor T5 and the sixth thin film field effect transistor
  • the first electrodes of T6 are all connected to the first reference voltage output terminal of the third voltage dividing module 201; the gate of the sixth thin film field effect transistor T6, the second electrode of the sixth thin film field effect transistor T6 and the seventh thin film field
  • the first electrode of the effect transistor T7 is connected to the second reference voltage output terminal of the third voltage dividing module 201; the gate of the seventh thin film field effect transistor T7 and the second electrode of the seventh thin film field effect transistor T7 are both connected to the The potential midpoints of the two voltage reference units 2 are connected.
  • the third voltage dividing module 201
  • the fourth voltage dividing module 202 includes: an eighth thin film field effect transistor T8, a ninth thin film field effect transistor T9 and a tenth thin film field effect transistor T10, and the eighth thin film field effect transistor T10.
  • the first electrode of the transistor T8 and the gate of the eighth thin film field effect transistor T8 are connected to the potential midpoint of the second voltage reference unit 2; the second electrode of the eighth thin film field effect transistor T8, the ninth thin film field effect transistor T9
  • the gate and the first electrode of the ninth thin film field effect transistor T9 are both connected to the first reference voltage output end of the fourth voltage dividing module 202; the second electrode of the ninth thin film field effect transistor T9, the tenth thin film field effect transistor
  • the gate of T10 and the first electrode of the tenth thin film field effect transistor T10 are both connected to the second reference voltage output terminal of the fourth voltage dividing module 202; the second electrode of the tenth thin film field effect transistor T10 is connected to the common electrode Line B is connected.
  • the charge discharge unit 3 includes an eleventh thin film field effect transistor T11 and a twelfth thin film field effect transistor T12 .
  • the gate of the eleventh thin film field effect transistor T11 is connected to the first reference voltage output terminal in the third voltage dividing module 201 and the first reference voltage output terminal in the fourth voltage dividing module 202; the eleventh thin film field
  • the first electrode of the effect transistor T11 is connected to the row driving signal line A of the array substrate;
  • the second electrode of the eleventh thin film field effect transistor T11 is connected to the first electrode of the twelfth thin film field effect transistor T12;
  • the twelfth thin film field effect transistor T12 The gate of the field effect transistor T12 is connected to the second reference voltage output terminal in the third voltage dividing module 201 and the second reference voltage output terminal in the fourth voltage dividing module 202;
  • the second electrode is connected to the common electrode line B.
  • the first voltage dividing module 101 and the second voltage dividing module 101 in the first voltage reference unit 1 performs the voltage dividing work, and at the same time, the thin film field effect transistors in the third voltage dividing module 201 and the fourth voltage dividing module 202 in the second voltage reference unit 2 generate the work of the reference voltage based on the change of the current and voltage .
  • the second voltage reference unit 2 can provide two sets of different reference voltages.
  • the eleventh thin film field effect transistor T11 and the twelfth thin film field effect transistor T12 in the charge discharge unit 3 are respectively turned on based on different reference voltages to perform charge discharge work. Since the eleventh thin film field effect transistor T11 and the twelfth thin film field effect transistor T11 The thin film field effect transistors T12 are all turned on, therefore, the problem of high voltage across a single TFT can be avoided, and the safety of the TFT can be ensured. Until the voltage between the array substrate row driving signal line A and the common electrode line B is reduced to a low voltage (voltage U ⁇ 20V), the eleventh thin film field effect transistor T11 and the twelfth thin film field effect transistor in the charge discharge unit 3 Transistor T12 stops discharging charges.
  • the second voltage reference unit 2 is added to divide the voltage, the side of the reference voltage unit in the electrostatic protection circuit is reduced. It has a smaller leakage current, thereby ensuring that the potential of the ninth thin-film field effect transistor T9 in the charge discharge unit 3 is lower than the potential on the side of the reference voltage unit in the electrostatic protection circuit, preventing any thin film field effect in the charge discharge unit 3
  • the potential of the transistor is too high to cause any one of the thin film field effect transistors to be turned on, thereby ensuring that the electrostatic protection circuit has a small leakage current under the normal working conditions of the circuit.
  • the thin film field effect transistors generally use transistors of the same material. Therefore, in the specific implementation, all the above-mentioned thin film transistors use N-type thin film transistors. It should be noted that the N-type thin film transistor is in an ON state when its gate potential is a high potential, and is in an OFF state when its gate potential is a low potential.
  • the horizontal axis is the voltage between the row driving signal line A and the common electrode line B of the array substrate, and the vertical axis is the leakage current of the electrostatic protection circuit.
  • L1 is the electrostatic protection circuit in the prior art;
  • L2 is the electrostatic protection circuit described in the first example of the solution;
  • L3 is the electrostatic protection circuit described in the second example of the solution.
  • the leakage current of the electrostatic protection circuit described in this solution is different from the leakage current of the electrostatic protection circuit in the prior art.
  • the current is equivalent, and will not increase the load on the row driving signal line A of the array substrate.
  • the horizontal axis is the voltage between the row driving signal line A and the common electrode line B of the array substrate, and the vertical axis is the leakage current of the electrostatic protection circuit.
  • L1 is the electrostatic protection circuit in the prior art;
  • L2 is the electrostatic protection circuit described in the first example of the solution;
  • L3 is the electrostatic protection circuit described in the second example of the solution.
  • the leakage current of the electrostatic protection circuit described in this solution is different from the leakage current of the electrostatic protection circuit in the prior art. Compared with the current, it has a better ability to release charges, and can release the accumulated electrostatic charge of the row driving signal lines of the array substrate in time to avoid the phenomenon of cross-line electrostatic protection in the circuit.
  • this solution further discloses a display panel including the electrostatic protection circuit as described above.
  • the material of the thin film field effect transistor in the display panel is indium gallium zinc oxide IGZO.
  • the display panel can be used for products or components with display functions, such as mobile phones, tablet computers, TV sets, display modules, notebook computers, digital photo frames, navigators, smart watches, fitness wristbands, personal digital assistants, and the like.
  • display functions such as mobile phones, tablet computers, TV sets, display modules, notebook computers, digital photo frames, navigators, smart watches, fitness wristbands, personal digital assistants, and the like.

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Abstract

本方案公开了一种静电保护电路和显示面板，其中静电保护电路包括：第一电压基准单元，用于对阵列基板行驱动信号线和公共电极线之间的电压进行一次分压；第二电压基准单元，用于对阵列基板行驱动信号线和公共电极线之间的电压进行二次分压；电荷释放单元，基于第一电压基准单元和第二电压基准单元提供的基准电压，调整阵列基板行驱动信号线和公共电极线之间电荷分布。

Description

一种静电保护电路和显示面板 技术领域
本发明涉及显示技术领域。更具体地，涉及一种静电放电保护电路和显示面板。
 背景技术
以IGZO (indium gallium zinc oxide，铟镓锌氧)为代表的氧化物半导体是应用于新一代TFT（Thin Film Transistor，薄膜场效应晶体管）技术的沟道层材料，氧化物 TFT由于具备迁移率较高，均匀性好，制备成本低等优点而在大尺寸AMLCD（Active Matrix Liquid Crystal Display，有源矩阵彩色液晶显示器）、AMOLED（Active-matrix organic light emitting diode，有源矩阵有机发光二极体）等显示面板中具有广泛应用前景。相比于a-Si TFT（非晶硅薄膜场效应晶体管），氧化物TFT除具有更高的迁移率外，还有更低的泄漏电流I off，因此，以氧化物TFT为开关的显示像素有更强的保持电荷的能力，有利于显示画质的提升。基于氧化物TFT的GOA(Gate  Driver  on  Array，阵列基板行驱动)电路由于氧化物TFT具有较高的迁移率，TFT可实现更小的layout area（布局面积），有助于制作窄边框面板，但氧化物漏电流态较低的电流也给GOA信号线中电荷的释放造成了困难，相对a-Si产品，氧化物TFT面板的GOA电路信号线发生ESD (Electro-Static Discharge，静电释放)的风险更高。
面板抗静电击穿能力是衡量面板可靠性的一个重要指标，现有的设计方案一般是GOA信号线通过静电保护电路连接Common线（公共电极线），将GOA信号线中的累积电荷导至Common线等其他信号线网络中，达到分散电荷的目的，避免单一信号线中电荷积累过多，与其他信号线产生较大的压差而产生静电。为达到及时分散电荷且避免信号线具有较大的负载，静电保护电路需要在低电压下（上限为GOA信号线与Common线的最大压差）具有较小的泄露电流，高电压下（下限为GOA信号线与Common线的最大压差）具有较大的泄漏电流。
 技术问题
本申请的目的在于，针对现有技术中存在的问题，提供一种静电放电保护电路和显示面板，以降低对阵列基板行驱动信号线的负载影响，提高显示面板的可靠性。
 技术解决方案
为实现上述目的，本申请提供一种静电保护电路，包括：
第一电压基准单元，用于对阵列基板行驱动信号线和公共电极线之间的电压进行一次分压；
第二电压基准单元，用于对阵列基板行驱动信号线和公共电极线之间的电压进行二次分压；
电荷释放单元，基于第一电压基准单元和第二电压基准单元提供的基准电压，调整阵列基板行驱动信号线和公共电极线之间电荷分布；
所述第一电压基准单元、第二电压基准单元和电荷释放单元分别连接在阵列基板行驱动信号线和公共电极线之间；
所述第一电压基准单元的电位中点与所述第二电压基准单元的电位中点连接；
所述第二电压基准单元的至少两个基准电压输出端与所述电荷释放单元的基准电压输入端连接。
本申请还提供了一种显示面板，包括：如上所述的静电保护电路。
 有益效果
本申请的有益效果：本方案所述静电保护电路在高电压（U＞20V）的情况下，相比于普通的静电保护电路具有更大的泄漏电流，能够及时将阵列基板行驱动信号线的累积静电荷释放，避免电路出现跨线静电保护的现象；在低电压（U≤20V）的情况下，不影响阵列基板行驱动信号线的负载，提高了显示面板的可靠性。
 附图说明
为了更加清楚地说明本申请的技术方案，下面对描述实施方案所需的附图做简要说明。
图1示出现有技术中的示意图；
图2示出本方案所述静电保护电路的一个实例的示意图；
图3示出本方案所述静电保护电路的另一个实例的示意图；
图4示出本方案所述静电保护电路和现有技术所述静电保护电路在低电压条件下释放电荷能力的实验数据对比图；
图5示出本方案所述静电保护电路和现有技术所述静电保护电路在高电压条件下释放电荷能力的实验数据对比图。
附图标号
1、第一电压基准单元；101、第一分压模块；102、第二分压模块；
2、第二电压基准单元；201、第三分压模块；202、第四分压模块；
3、电荷释放单元；
T1、第一薄膜场效应晶体管；T2、第二薄膜场效应晶体管；
T3、第三薄膜场效应晶体管；T4、第四薄膜场效应晶体管；
T5、第五薄膜场效应晶体管；T6、第六薄膜场效应晶体管；
T7、第七薄膜场效应晶体管；T8、第八薄膜场效应晶体管；
T9、第九薄膜场效应晶体管；T10、第十薄膜场效应晶体管；
T11、第十一薄膜场效应晶体管；T12、第十二薄膜场效应晶体管；
A、阵列基板行驱动信号线；B、公共电极线。
 本发明的实施方式
下面将参照附图详细描述本申请的具体实施例。本领域技术人员应理解的是，下面通过参照附图描述的实施方式是示例性的，仅用于理解本申请而不意图对本申请进行限制。在下文中，相同的附图标记始终表示相同或相似的元件。另外，诸如“第一”、“第二”等的术语仅用于将一个组件与另一个组件区分开，而不将组件限于上述术语。
经过对现有技术的分析和研究，如图1所示，在不改变TFT具体结构的情况下，可以将静电保护电路中的TFT接成diode对（二极管对）的形式，等效增加TFT的沟道宽长比，从而达到调整静电保护电路的泄漏电流大小的目的。若在ESD电路中增大TFT的沟道宽长，那么，静电保护电路在低电压和高电压下均会增加泄漏电流。现有技术中，由于a-Si产品TFT的泄漏电流I off较高，GOA信号线具有较多的电荷释放通道，静电保护电路中TFT的宽长比可设计至比较小的水平，甚至可以取消静电保护电路；但是，IGZO等氧化物TFT的泄漏电流I off较低，关态条件下电荷难以释放，因此，静电保护电路需要较强的释放电荷的能力，显然采用diode对形式的静电保护电路需要能够增加TFT的宽长比，增加静电保护电路的泄露电流，但这也将提升GOA信号线的负载，影响GOA电路的正常驱动。
因此，本方案意在一种静电保护电路，该电路中将TFT接成的diode对的TFT作为第一电压基准单元1，将多个串联的薄膜场效应晶体管作为第二电压基准单元2，既可以通过合理设置第一电压基准单元1中TFT的布置方式来等效调整TFT的宽长比，使静电保护电路在低压情况下，具有较小的负载，不影响GOA电路正常工作，还可以在较高电压下具有较大的电荷释放能力，避免GOA输入信号线产生静电，进而提升显示面板的可靠性。
以下，结合附图对本方案提出的一种静电保护电路进行详细描述。如图2所示，本方案所述静电保护电路包括：第一电压基准单元1、第二电压基准单元2和电荷释放单元3。第一电压基准单元1、第二电压基准单元2和电荷释放单元3分别连接在阵列基板行驱动信号线A和公共电极线B之间；在第一电压基准单元1对阵列基板行驱动信号线A和公共电极线B之间的电压进行分压的基础上，进一步利用第二电压基准单元2对阵列基板行驱动信号线A和公共电极线B之间的电压进行分压。电荷释放单元3根据第一电压基准单元1和第二电压基准单元2提供的基准电压，调整阵列基板行驱动信号线A和公共电极线B之间电荷分布，从而在阵列基板行驱动信号线A和公共电极线B之间电压较低（例如电压U≤20V）的情况下，静电保护电路具有较小的泄露电流，不影响阵列基板行驱动信号线的负载，提高了显示面板的可靠性；在阵列基板行驱动信号线A和公共电极线B之间电压较高（例如电压U＞20V）的情况下，静电保护电路能够迅速增大泄露电流，从而使阵列基板行驱动信号线A累积的静电能够及时得到释放，避免出现跨线静电释放的问题，同时能够保证正常工作时不影响阵列基板行驱动输入信号的负载。
本方案中，第一电压基准单元1的电位中点与第二电压基准单元2的电位中点连接，通过第一电压基准单元1和第二电压基准单元2的共同作用，利用第二电压基准单元2中的基准电压的输出端，输出提供给电荷释放单元3的基准电压。本方案中，第二电压基准单元2具有至少两个基准电压输出端。
本方案中，第一电压基准单元1可以包括：第一分压模块101和第二分压模块102。两个分压模块采用串联的方式连接；第一电压基准单元1的电位中点位于两个分压模块之间。具体来说，第一分压模块101的输入端与阵列基板行驱动信号线A连接，第一分压模块101的输出端和第二分压模块102的输入端均与所述第一电压基准单元1的电位中点连接，所述第二分压模块102的输出端连接所述公共电极线B。利用第一电压基准单元1使静电保护电路在高、低电压的情况下均能增加泄露电流。
在第一个实例中，如图2所示，第一分压模块101可以包括：第一薄膜场效应晶体管T1和第二薄膜场效应晶体管T2。第一薄膜场效应晶体管T1和第二薄膜场效应晶体管T2接成二极管对（diode对）的形式，这种形式能够在不改变薄膜场效应晶体管结构的情况下，等效增加薄膜场效应晶体管的宽长比，从而在增加静电保护电路的泄漏电流，提升静电保护电路的电荷释放能力。两个薄膜场效应晶体管的具体连接方式为：第一薄膜场效应晶体管T1的栅极、第一薄膜场效应晶体管T1的第一电极和第二薄膜场效应晶体管T2的第二电极均与第一电压基准单元1的电位中点连接；第一薄膜场效应晶体管T1的第二电极、第二薄膜场效应晶体管T2的栅极和第二薄膜场效应晶体管T2的第一电极均与所述阵列基板行驱动信号线A连接。本实例中，第一电极可以为源极或漏极；第二电极可以为源极或漏极；第一电极和第二电极的类型不同。
在第一个实例中，如图2所示，第二分压模块102可以包括：第三薄膜场效应晶体管T3和第四薄膜场效应晶体管T4。第三薄膜场效应晶体管T3和第四薄膜场效应晶体管T4也可以接成二极管对（diode对）的形式。两个薄膜场效应晶体管的具体连接方式为：第三薄膜场效应晶体管T3的栅极、第三薄膜场效应晶体管T3的第一电极和第四薄膜场效应晶体管T4的第二电极均与公共电极线B连接；第三薄膜场效应晶体管T3的第二电极、第四薄膜场效应晶体管T4的栅极和第四薄膜场效应晶体管T4的第一电极均与第一电压基准单元1的电位中点连接。本实例中，第一电极可以为源极或漏极；第二电极可以为源极或漏极；第一电极和第二电极的类型不同。
虽然，将薄膜场效应晶体管以二极管对的形式连接，能够提高静电保护电路的泄漏电流，但是，在阵列基板行驱动信号线A和公共电极线B之间处于低电压情况时，会增大阵列基板行驱动信号线A的负载，影响阵列基板行驱动信号线A的正常驱动工作。为此，本方案在第一电压基准单元1的基础上增加了第二电压基准单元2，既能满足阵列基板行驱动信号线A和公共电极线B之间处于低电压情况时，静电保护电路具有较小的泄漏电流，同时使阵列基板行驱动信号线A具有较小的负载，不影响阵列基板行驱动信号线A的驱动工作。
本方案中，第二电压基准单元2包括：第三分压模块201和第四分压模块202。两个分压模块采用串联的方式连接；第二电压基准单元2的电位中点位于两个分压模块之间。具体来说，第三分压模块201的分压输入端与阵列基板行驱动信号线A连接，第三分压模块201的基准电压输出端与电荷释放单元3的至少一个基准电压输入端连接，第三分压模块201的分压输出端和第四分压模块202的分压输入端均与第二电压基准单元2的电位中点连接。第四分压模块202的基准电压输出端与电荷释放单元3的至少一个基准电压输入端连接，第四分压模块202的分压输出端与公共电极线B连接。本方案中，利用第一电压基准单元1和第二电压基准单元2，为电荷释放单元3提供基准电压，控制电荷释放单元3的开关状态，从而阵列基板行驱动信号线A和公共电极线B之间的电荷重新分布。此外，在第一电压基准单元1的基础上，第二电压基准单元2进一步在阵列基板行驱动信号线A和公共电极线B之间进行分压，避免在阵列基板行驱动信号线A和公共电极线B之间电压较低（U≤20）的情况下，电荷释放单元3由于电位过高而开启，从而保证电路正常工作条件下静电保护电路具有较小的泄露电流。与此同时，通过这种方式，克服由于薄膜场效应晶体管以二极管对的形式连接时，造成在低电压情况下阵列基板行驱动信号线A负载增加的问题，保证阵列基板行驱动信号线A的正常工作。
在第一个实例中，如图2所示，第三分压模块201由第五薄膜场效应晶体管T5和第六薄膜场效应晶体管T6组成。第五薄膜场效应晶体管T5的第一电极与所述阵列基板行驱动信号线A连接；第五薄膜场效应晶体管T5的栅极、第五薄膜场效应晶体管T5的第二电极和第六薄膜场效应晶体管T6的第一电极均与第三分压模块201的基准电压输出端连接；第六薄膜场效应晶体管T6的栅极和第六薄膜场效应晶体管T6的第二电极均与第二电压基准单元2的电位中点连接。本实例中，第一电极可以为源极或漏极；第二电极可以为源极或漏极；第一电极和第二电极的类型不同。
在第一个实例中，如图2所示，第四分压模块202包括：第七薄膜场效应晶体管T7和第八薄膜场效应晶体管T8；所述第七薄膜场效应晶体管T7的栅极和所述第七薄膜场效应晶体管T7的第一电极均与所述第二电压基准单元2的电位中点连接；所述第七薄膜场效应晶体管T7的第二电极、所述第八薄膜场效应晶体管T8的栅极和所述第八薄膜场效应晶体管T8的第一电极均与所述第四分压模块202的基准电压输出端连接；所述第八薄膜场效应晶体管T8的第二电极与所述公共电极线B连接。本实例中，第一电极可以为源极或漏极；第二电极可以为源极或漏极；第一电极和第二电极的类型不同。
在第一个实例中，如图2所示，电荷释放单元3中包含第九薄膜场效应晶体管T9，第九薄膜场效应晶体管T9在第二电压基准单元2提供的基准电压的作用下开启，完成电荷释放工作。
如图2所示，若阵列基板行驱动信号线A和公共电极线B之间处于高电压（电压U＞20V）情况时，第一电压基准单元1中的第一分压模块101和第二分压模块102进行分压工作，与此同时，第二电压基准单元2中第三分压模块201和第四分压模块202中的薄膜场效应晶体管基于电流电压的变化，产生基准电压的工作。根据阵列基板行驱动信号线A和公共电极线B之间的电压值情况，电荷释放单元3中的第九薄膜场效应晶体管T9基于第三分压模块201和第四分压模块202产生的基准电压导通，进行电荷释放，直至阵列基板行驱动信号线A和公共电极线B之间的电压降低为低电压（电压U≤20V），则第九薄膜场效应晶体管T9停止释放电荷。
若阵列基板行驱动信号线A和公共电极线B之间处于低电压（电压U≤20V）情况时，由于增加了第二电压基准单元2进行分压，使得静电保护电路中基准电压单元一侧具有较小的泄露电流，从而保证电荷释放单元3中的第九薄膜场效应晶体管T9的电位低于静电保护电路中基准电压单元一侧的电位，防止第九薄膜场效应晶体管T9的电位过高而导致第九薄膜场效应晶体管T9开启，从而保证电路正常工作条件下静电保护电路具有较小的泄露电流。
在实际静电保护过程中，采用单个薄膜场效应晶体管进行电荷释放时，有可能会存在源漏电极间的高跨压问题，进而导致薄膜场效应晶体管发生损坏。为了克服这个问题，本方案在不改变第一电压基准单元1的情况下，对第二电压基准单元2和电荷释放单元3中的TFT数量进行适当调整。具体如下：
在第二个实例中，如图3所示，第三分压模块201由第五薄膜场效应晶体管T5、第六薄膜场效应晶体管T6和第七薄膜场效应晶体管T7组成。第五薄膜场效应晶体管T5的第一电极与阵列基板行驱动信号线A连接；第五薄膜场效应晶体管T5的栅极、第五薄膜场效应晶体管T5的第二电极和第六薄膜场效应晶体管T6的第一电极均与第三分压模块201的第一个基准电压输出端连接；第六薄膜场效应晶体管T6的栅极、第六薄膜场效应晶体管T6的第二电极和第七薄膜场效应晶体管T7的第一电极均与第三分压模块201的第二个基准电压输出端连接；第七薄膜场效应晶体管T7的栅极和第七薄膜场效应晶体管T7的第二电极均与第二电压基准单元2的电位中点连接。本实例中，第一电极可以为源极或漏极；第二电极可以为源极或漏极；第一电极和第二电极的类型不同。
在第二个实例中，如图3所示，第四分压模块202包括：第八薄膜场效应晶体管T8、第九薄膜场效应晶体管T9和第十薄膜场效应晶体管T10，第八薄膜场效应晶体管T8的第一电极和第八薄膜场效应晶体管T8的栅极与第二电压基准单元2的电位中点连接；第八薄膜场效应晶体管T8的第二电极、第九薄膜场效应晶体管T9的栅极和第九薄膜场效应晶体管T9的第一电极均与第四分压模块202的第一个基准电压输出端连接；第九薄膜场效应晶体管T9的第二电极、第十薄膜场效应晶体管T10的栅极和所述第十薄膜场效应晶体管T10的第一电极均与第四分压模块202的第二个基准电压输出端连接；第十薄膜场效应晶体管T10的第二电极与公共电极线B连接。
在第二个实例中，如图3所示，电荷释放单元3中包含第十一薄膜场效应晶体管T11和第十二薄膜场效应晶体管T12。第十一薄膜场效应晶体管T11的栅极与第三分压模块201中的第一个基准电压输出端和第四分压模块202中的第一个基准电压输出端连接；第十一薄膜场效应晶体管T11的第一电极与阵列基板行驱动信号线A连接；第十一薄膜场效应晶体管T11的第二电极和所述第十二薄膜场效应晶体管T12的第一电极连接；第十二薄膜场效应晶体管T12的栅极与第三分压模块201中的第二个基准电压输出端和第四分压模块202中的第二个基准电压输出端连接；第十二薄膜场效应晶体管T12的第二电极与所述公共电极线B连接。
如图3所示，若阵列基板行驱动信号线A和公共电极线B之间处于高电压（电压U＞20V）情况时，第一电压基准单元1中的第一分压模块101和第二分压模块102进行分压工作，于此同时，第二电压基准单元2中第三分压模块201和第四分压模块202中的薄膜场效应晶体管基于电流电压的变化，产生基准电压的工作。本实施例中，第二电压基准单元2能够提供两组不同的基准电压。电荷释放单元3中的第十一薄膜场效应晶体管T11和第十二薄膜场效应晶体管T12分别基于不同的基准电压导通，进行电荷释放工作，由于第十一薄膜场效应晶体管T11和第十二薄膜场效应晶体管T12均导通，因此，可以避免单个TFT时出现的高跨压问题，保证TFT的安全。直至阵列基板行驱动信号线A和公共电极线B之间的电压降低为低电压（电压U≤20V），则电荷释放单元3中的第十一薄膜场效应晶体管T11和第十二薄膜场效应晶体管T12停止释放电荷。
若阵列基板行驱动信号线A和公共电极线B之间处于低电压（电压U≤20V）情况时，由于增加了第二电压基准单元2进行分压，使得静电保护电路中基准电压单元一侧具有较小的泄露电流，从而保证电荷释放单元3中的第九薄膜场效应晶体管T9的电位低于静电保护电路中基准电压单元一侧的电位，防止电荷释放单元3中的任意一个薄膜场效应晶体管的电位过高而导致任意一个薄膜场效应晶体管开启，从而保证电路正常工作条件下静电保护电路具有较小的泄露电流。
本方案中，为了降低制作工艺难度，薄膜场效应晶体管一般均采用相同材质的晶体管。因此，在具体实施时，上述全部薄膜晶体管均采用N型薄膜晶体管。需要说明的是，N型薄膜晶体管在其栅极电位为高电位时处于导通状态，在其栅极电位为低电位时处于截止状态。
本方案在相同条件下，分别对现有技术中的静电保护电路、第一个实例所述静电保护电路和第二个实例所述静电保护电路进行实验验证。
如图4所示，横轴为阵列基板行驱动信号线A和公共电极线B之间的电压，纵轴为静电保护电路的泄漏电流。L1为现有技术中的静电保护电路；L2为本方案第一个实例所述静电保护电路；L3为本方案第二个实例所述静电保护电路。
当阵列基板行驱动信号线A和公共电极线B之间的电压处于低电压（电压U≤20V）情况时，本方案所述静电保护电路的泄漏电流与现有技术中的静电保护电路的泄露电流相当，且不会对阵列基板行驱动信号线A造成负载增加的影响。
如图5所示，横轴为阵列基板行驱动信号线A和公共电极线B之间的电压，纵轴为静电保护电路的泄漏电流。L1为现有技术中的静电保护电路；L2为本方案第一个实例所述静电保护电路；L3为本方案第二个实例所述静电保护电路。
当阵列基板行驱动信号线A和公共电极线B之间的电压处于高电压（电压U＞20V）情况时，本方案所述静电保护电路的泄漏电流与现有技术中的静电保护电路的泄露电流相比，具有更加的释放电荷能力，能够及时将阵列基板行驱动信号线的累积静电荷释放，避免电路出现跨线静电保护的现象。
在上述描述的静电保护电路的基础上，本方案进一步公开了一种显示面板，包括如上所述的静电保护电路。该显示面板中薄膜场效应晶体管的材料采用铟镓锌氧IGZO。该显示面板可以用于手机、平板电脑、电视机、显示模块、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等具有显示功能的产品或部件。该显示面板的实施可以参见上述显示基板的实施例，重复之处不再赘述。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1. 一种静电保护电路，其特征在于，包括：
    第一电压基准单元，用于对阵列基板行驱动信号线和公共电极线之间的电压进行一次分压；
    第二电压基准单元，用于对阵列基板行驱动信号线和公共电极线之间的电压进行二次分压；
    电荷释放单元，基于第一电压基准单元和第二电压基准单元提供的基准电压，调整阵列基板行驱动信号线和公共电极线之间电荷分布；
    所述第一电压基准单元、第二电压基准单元和电荷释放单元分别连接在阵列基板行驱动信号线和公共电极线之间；
    所述第一电压基准单元的电位中点与所述第二电压基准单元的电位中点连接；
    所述第二电压基准单元的至少两个基准电压输出端与所述电荷释放单元的基准电压输入端连接。
  2. 根据权利要求1所述的静电保护电路，其特征在于，所述第一电压基准单元包括：串联连接的第一分压模块和第二分压模块；
    所述第一分压模块的输入端与所述阵列基板行驱动信号线连接，所述第一分压模块的输出端和所述第二分压模块的输入端均与所述第一电压基准单元的电位中点连接，所述第二分压模块的输出端连接所述公共电极线。
  3. 根据权利要求2所述的电路，其特征在于，所述第一分压模块包括：第一薄膜场效应晶体管和第二薄膜场效应晶体管；所述第一薄膜场效应晶体管的栅极、所述第一薄膜场效应晶体管的第一电极和所述第二薄膜场效应晶体管的第二电极均与所述第一电压基准单元的电位中点连接；所述第一薄膜场效应晶体管的第二电极、所述第二薄膜场效应晶体管的栅极和所述第二薄膜场效应晶体管的第一电极均与所述阵列基板行驱动信号线连接。
  4. 根据权利要求2或3所述的电路，其特征在于，所述第二分压模块包括：第三薄膜场效应晶体管和第四薄膜场效应晶体管；所述第三薄膜场效应晶体管的栅极、所述第三薄膜场效应晶体管的第一电极和所述第四薄膜场效应晶体管的第二电极均与所述公共电极线连接；所述第三薄膜场效应晶体管的第二电极、所述第四薄膜场效应晶体管的栅极和所述第四薄膜场效应晶体管的第一电极均与所述第一电压基准单元的电位中点连接。
  5. 根据权利要求1所述的电路，其特征在于，所述第二电压基准单元包括：串联连接的第三分压模块和第四分压模块；
    所述第三分压模块的分压输入端与所述阵列基板行驱动信号线连接，所述第三分压模块的基准电压输出端与所述电荷释放单元的至少一个基准电压输入端连接，所述第三分压模块的分压输出端和所述第四分压模块的分压输入端均与所述第二电压基准单元的电位中点连接；
    所述第四分压模块的基准电压输出端与所述电荷释放单元的至少一个基准电压输入端连接，所述第四分压模块的分压输出端与所述公共电极线连接。
  6. 根据权利要求5所述的电路，其特征在于，所述第三分压模块包括：第五薄膜场效应晶体管和第六薄膜场效应晶体管；所述第五薄膜场效应晶体管的第一电极与所述阵列基板行驱动信号线连接；所述第五薄膜场效应晶体管的栅极、所述第五薄膜场效应晶体管的第二电极和所述第六薄膜场效应晶体管的第一电极均与所述第三分压模块的基准电压输出端连接；所述第六薄膜场效应晶体管的栅极和第六薄膜场效应晶体管的第二电极均与所述第二电压基准单元的电位中点连接。
  7. 根据权利要求5或6所述的电路，其特征在于，所述第四分压模块包括：第七薄膜场效应晶体管和第八薄膜场效应晶体管；所述第七薄膜场效应晶体管的栅极和所述第七薄膜场效应晶体管的第一电极均与所述第二电压基准单元的电位中点连接；所述第七薄膜场效应晶体管的第二电极、所述第八薄膜场效应晶体管的栅极和所述第八薄膜场效应晶体管的第一电极均与所述第四分压模块的基准电压输出端连接；所述第八薄膜场效应晶体管的第二电极与所述公共电极线连接。
  8. 根据权利要求7所述的电路，其特征在于，所述电荷释放单元包括：第九薄膜场效应晶体管；所述第九薄膜场效应晶体管的栅极与所述第三分压模块的基准电压输出端和所述第四分压模块的基准电压输出端连接；所述第九薄膜场效应晶体管的第一电极与所述阵列基板行驱动信号线连接，所述第九薄膜场效应晶体管的第二电极与所述公共电极线连接。
  9. 根据权利要求5所述的电路，其特征在于，所述第三分压模块包括：第五薄膜场效应晶体管、第六薄膜场效应晶体管和第七薄膜场效应晶体管；所述第五薄膜场效应晶体管的第一电极与所述阵列基板行驱动信号线连接；所述第五薄膜场效应晶体管的栅极、所述第五薄膜场效应晶体管的第二电极和所述第六薄膜场效应晶体管的第一电极均与所述第三分压模块的第一个基准电压输出端连接；所述第六薄膜场效应晶体管的栅极、所述第六薄膜场效应晶体管的第二电极和所述第七薄膜场效应晶体管的第一电极均与所述第三分压模块的第二个基准电压输出端连接；所述第七薄膜场效应晶体管的栅极和所述第七薄膜场效应晶体管的第二电极均与所述第二电压基准单元的电位中点连接。
  10. 根据权利要求5或9所述的电路，其特征在于，所述第四分压模块包括：第八薄膜场效应晶体管、第九薄膜场效应晶体管和第十薄膜场效应晶体管，所述第八薄膜场效应晶体管的第一电极和所述第八薄膜场效应晶体管的栅极与所述第二电压基准单元的电位中点连接；所述第八薄膜场效应晶体管的第二电极、所述第九薄膜场效应晶体管的栅极和所述第九薄膜场效应晶体管的第一电极均与所述第四分压模块的第一个基准电压输出端连接；所述第九薄膜场效应晶体管的第二电极、第十薄膜场效应晶体管的栅极和所述第十薄膜场效应晶体管的第一电极均与所述第四分压模块的第二个基准电压输出端连接；所述第十薄膜场效应晶体管的第二电极与所述公共电极线连接。
  11. 根据权利要求10所述的电路，其特征在于，所述电荷释放单元包括：第十一薄膜场效应晶体管和第十二薄膜场效应晶体管；
    所述第十一薄膜场效应晶体管的栅极与所述第三分压模块中的第一个基准电压输出端和所述第四分压模块中的第一个基准电压输出端连接；所述第十一薄膜场效应晶体管的第一电极与所述阵列基板行驱动信号线连接；所述第十一薄膜场效应晶体管的第二电极和所述第十二薄膜场效应晶体管的第一电极连接；
    所述第十二薄膜场效应晶体管的栅极与第三分压模块中的第二个基准电压输出端和第四分压模块中的第二个基准电压输出端连接；所述第十二薄膜场效应晶体管的第二电极与所述公共电极线连接。
  12. 一种显示面板，其特征在于，包括连接在阵列基板行驱动信号线和公共电极线之间的静电保护电路。
  13. 根据权利要求11所述的显示面板，所述静电保护电路包括：
    第一电压基准单元，用于对阵列基板行驱动信号线和公共电极线之间的电压进行一次分压；
    第二电压基准单元，用于对阵列基板行驱动信号线和公共电极线之间的电压进行二次分压；
    电荷释放单元，基于第一电压基准单元和第二电压基准单元提供的基准电压，调整阵列基板行驱动信号线和公共电极线之间电荷分布；
    所述第一电压基准单元、第二电压基准单元和电荷释放单元分别连接在阵列基板行驱动信号线和公共电极线之间；
    所述第一电压基准单元的电位中点与所述第二电压基准单元的电位中点连接；
    所述第二电压基准单元的至少两个基准电压输出端与所述电荷释放单元的基准电压输入端连接。
  14. 根据权利要求13所述的静电保护电路，其特征在于，所述第一电压基准单元包括：串联连接的第一分压模块和第二分压模块；
    所述第一分压模块的输入端与所述阵列基板行驱动信号线连接，所述第一分压模块的输出端和所述第二分压模块的输入端均与所述第一电压基准单元的电位中点连接，所述第二分压模块的输出端连接所述公共电极线。
  15. 根据权利要求14所述的电路，其特征在于，所述第一分压模块包括：第一薄膜场效应晶体管和第二薄膜场效应晶体管；所述第一薄膜场效应晶体管的栅极、所述第一薄膜场效应晶体管的第一电极和所述第二薄膜场效应晶体管的第二电极均与所述第一电压基准单元的电位中点连接；所述第一薄膜场效应晶体管的第二电极、所述第二薄膜场效应晶体管的栅极和所述第二薄膜场效应晶体管的第一电极均与所述阵列基板行驱动信号线连接；
    所述第二分压模块包括：第三薄膜场效应晶体管和第四薄膜场效应晶体管；所述第三薄膜场效应晶体管的栅极、所述第三薄膜场效应晶体管的第一电极和所述第四薄膜场效应晶体管的第二电极均与所述公共电极线连接；所述第三薄膜场效应晶体管的第二电极、所述第四薄膜场效应晶体管的栅极和所述第四薄膜场效应晶体管的第一电极均与所述第一电压基准单元的电位中点连接。
  16. 根据权利要求13所述的电路，其特征在于，所述第二电压基准单元包括：串联连接的第三分压模块和第四分压模块；
    所述第三分压模块的分压输入端与所述阵列基板行驱动信号线连接，所述第三分压模块的基准电压输出端与所述电荷释放单元的至少一个基准电压输入端连接，所述第三分压模块的分压输出端和所述第四分压模块的分压输入端均与所述第二电压基准单元的电位中点连接；
    所述第四分压模块的基准电压输出端与所述电荷释放单元的至少一个基准电压输入端连接，所述第四分压模块的分压输出端与所述公共电极线连接。
  17. 根据权利要求16所述的电路，其特征在于，所述第三分压模块包括：第五薄膜场效应晶体管和第六薄膜场效应晶体管；所述第五薄膜场效应晶体管的第一电极与所述阵列基板行驱动信号线连接；所述第五薄膜场效应晶体管的栅极、所述第五薄膜场效应晶体管的第二电极和所述第六薄膜场效应晶体管的第一电极均与所述第三分压模块的基准电压输出端连接；所述第六薄膜场效应晶体管的栅极和第六薄膜场效应晶体管的第二电极均与所述第二电压基准单元的电位中点连接；
    所述第四分压模块包括：第七薄膜场效应晶体管和第八薄膜场效应晶体管；所述第七薄膜场效应晶体管的栅极和所述第七薄膜场效应晶体管的第一电极均与所述第二电压基准单元的电位中点连接；所述第七薄膜场效应晶体管的第二电极、所述第八薄膜场效应晶体管的栅极和所述第八薄膜场效应晶体管的第一电极均与所述第四分压模块的基准电压输出端连接；所述第八薄膜场效应晶体管的第二电极与所述公共电极线连接。
  18. 根据权利要求17所述的电路，其特征在于，所述电荷释放单元包括：第九薄膜场效应晶体管；所述第九薄膜场效应晶体管的栅极与所述第三分压模块的基准电压输出端和所述第四分压模块的基准电压输出端连接；所述第九薄膜场效应晶体管的第一电极与所述阵列基板行驱动信号线连接，所述第九薄膜场效应晶体管的第二电极与所述公共电极线连接。
  19. 根据权利要求16所述的电路，其特征在于，所述第三分压模块包括：第五薄膜场效应晶体管、第六薄膜场效应晶体管和第七薄膜场效应晶体管；所述第五薄膜场效应晶体管的第一电极与所述阵列基板行驱动信号线连接；所述第五薄膜场效应晶体管的栅极、所述第五薄膜场效应晶体管的第二电极和所述第六薄膜场效应晶体管的第一电极均与所述第三分压模块的第一个基准电压输出端连接；所述第六薄膜场效应晶体管的栅极、所述第六薄膜场效应晶体管的第二电极和所述第七薄膜场效应晶体管的第一电极均与所述第三分压模块的第二个基准电压输出端连接；所述第七薄膜场效应晶体管的栅极和所述第七薄膜场效应晶体管的第二电极均与所述第二电压基准单元的电位中点连接；
    所述第四分压模块包括：第八薄膜场效应晶体管、第九薄膜场效应晶体管和第十薄膜场效应晶体管，所述第八薄膜场效应晶体管的第一电极和所述第八薄膜场效应晶体管的栅极与所述第二电压基准单元的电位中点连接；所述第八薄膜场效应晶体管的第二电极、所述第九薄膜场效应晶体管的栅极和所述第九薄膜场效应晶体管的第一电极均与所述第四分压模块的第一个基准电压输出端连接；所述第九薄膜场效应晶体管的第二电极、第十薄膜场效应晶体管的栅极和所述第十薄膜场效应晶体管的第一电极均与所述第四分压模块的第二个基准电压输出端连接；所述第十薄膜场效应晶体管的第二电极与所述公共电极线连接。
  20. 根据权利要求19所述的电路，其特征在于，所述电荷释放单元包括：第十一薄膜场效应晶体管和第十二薄膜场效应晶体管；
    所述第十一薄膜场效应晶体管的栅极与所述第三分压模块中的第一个基准电压输出端和所述第四分压模块中的第一个基准电压输出端连接；所述第十一薄膜场效应晶体管的第一电极与所述阵列基板行驱动信号线连接；所述第十一薄膜场效应晶体管的第二电极和所述第十二薄膜场效应晶体管的第一电极连接；
    所述第十二薄膜场效应晶体管的栅极与第三分压模块中的第二个基准电压输出端和第四分压模块中的第二个基准电压输出端连接；所述第十二薄膜场效应晶体管的第二电极与所述公共电极线连接。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
WO2024026634A1 (zh) * 2022-08-01 2024-02-08 京东方科技集团股份有限公司 显示基板、其制作方法、中板及电子纸显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040125308A1 (en) * 2002-12-31 2004-07-01 Lg.Philips Lcd Co., Ltd. Liquid crystal display device and method for removing residual charge
CN202720425U (zh) * 2012-07-05 2013-02-06 京东方科技集团股份有限公司 液晶面板及显示装置
CN103941908A (zh) * 2013-12-23 2014-07-23 上海天马微电子有限公司 一种触摸屏显示面板以及触摸屏显示装置
CN205374948U (zh) * 2015-12-18 2016-07-06 上海中航光电子有限公司 一种集成触摸显示装置
CN206040644U (zh) * 2016-08-31 2017-03-22 京东方科技集团股份有限公司 静电防护电路、显示面板和装置
CN107256687A (zh) * 2017-07-21 2017-10-17 京东方科技集团股份有限公司 静电保护电路、驱动方法、静电保护模组和显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005065368A2 (en) * 2003-12-29 2005-07-21 Sherwood Information Partners, Inc. System and method for reduced vibration interaction in a multiple-hard-disk-drive enclosure
JP4151688B2 (ja) * 2005-06-30 2008-09-17 セイコーエプソン株式会社 集積回路装置及び電子機器
EP1895545B1 (en) * 2006-08-31 2014-04-23 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
TW200847110A (en) * 2007-05-23 2008-12-01 Faraday Tech Corp Output stage and related logic control method applied to source driver/chip
TWI358872B (en) * 2008-01-09 2012-02-21 Chunghwa Picture Tubes Ltd Two-way electrostatic discharge protection circuit
JP5525224B2 (ja) * 2008-09-30 2014-06-18 株式会社半導体エネルギー研究所 表示装置
CN102783030B (zh) * 2010-03-02 2016-01-13 株式会社半导体能源研究所 脉冲信号输出电路和移位寄存器
TWI422008B (zh) * 2010-05-24 2014-01-01 Au Optronics Corp 靜電防護電路及採用此種靜電防護電路之顯示裝置
TWI548057B (zh) * 2011-04-22 2016-09-01 半導體能源研究所股份有限公司 半導體裝置
US8673426B2 (en) * 2011-06-29 2014-03-18 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, method of manufacturing the driver circuit, and display device including the driver circuit
CN102651547B (zh) * 2012-01-12 2013-06-05 京东方科技集团股份有限公司 一种静电放电保护电路及包括该保护电路的显示装置
US8988152B2 (en) * 2012-02-29 2015-03-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
TWI478139B (zh) * 2012-09-13 2015-03-21 Au Optronics Corp 靜電放電保護電路及其顯示裝置
US9772532B2 (en) * 2014-03-10 2017-09-26 Lg Display Co., Ltd. Electrostatic discharge circuit and liquid crystal display device including the same
CN104979814B (zh) * 2014-04-02 2017-12-29 中芯国际集成电路制造(上海)有限公司 一种静电放电保护电路
JP6537892B2 (ja) * 2014-05-30 2019-07-03 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
TWI541696B (zh) * 2014-11-28 2016-07-11 禾瑞亞科技股份有限公司 整合有靜電放電保護之信號傳送電路與觸控系統
CN107290908B (zh) * 2017-06-23 2020-05-29 武汉华星光电技术有限公司 静电保护电路及液晶显示面板
EP4170718A3 (en) * 2021-09-03 2023-08-23 LG Display Co., Ltd. Display panel and electronic device including same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040125308A1 (en) * 2002-12-31 2004-07-01 Lg.Philips Lcd Co., Ltd. Liquid crystal display device and method for removing residual charge
CN202720425U (zh) * 2012-07-05 2013-02-06 京东方科技集团股份有限公司 液晶面板及显示装置
CN103941908A (zh) * 2013-12-23 2014-07-23 上海天马微电子有限公司 一种触摸屏显示面板以及触摸屏显示装置
CN205374948U (zh) * 2015-12-18 2016-07-06 上海中航光电子有限公司 一种集成触摸显示装置
CN206040644U (zh) * 2016-08-31 2017-03-22 京东方科技集团股份有限公司 静电防护电路、显示面板和装置
CN107256687A (zh) * 2017-07-21 2017-10-17 京东方科技集团股份有限公司 静电保护电路、驱动方法、静电保护模组和显示装置

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US20220415243A1 (en) 2022-12-29
US11776457B2 (en) 2023-10-03

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